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1/*
2 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
3 *
4 * Copyright (c) 2010, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/delay.h>
27#include <linux/rtc.h>
28#include <linux/platform_device.h>
29
30/* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
31#define TEGRA_RTC_REG_BUSY 0x004
32#define TEGRA_RTC_REG_SECONDS 0x008
33/* when msec is read, the seconds are buffered into shadow seconds. */
34#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
35#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
36#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
37#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
38#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
39#define TEGRA_RTC_REG_INTR_MASK 0x028
40/* write 1 bits to clear status bits */
41#define TEGRA_RTC_REG_INTR_STATUS 0x02c
42
43/* bits in INTR_MASK */
44#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
45#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
46#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
47#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
48#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
49
50/* bits in INTR_STATUS */
51#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
52#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
53#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
54#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
55#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
56
57struct tegra_rtc_info {
58 struct platform_device *pdev;
59 struct rtc_device *rtc_dev;
60 void __iomem *rtc_base; /* NULL if not initialized. */
61 int tegra_rtc_irq; /* alarm and periodic irq */
62 spinlock_t tegra_rtc_lock;
63};
64
65/* RTC hardware is busy when it is updating its values over AHB once
66 * every eight 32kHz clocks (~250uS).
67 * outside of these updates the CPU is free to write.
68 * CPU is always free to read.
69 */
70static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
71{
72 return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
73}
74
75/* Wait for hardware to be ready for writing.
76 * This function tries to maximize the amount of time before the next update.
77 * It does this by waiting for the RTC to become busy with its periodic update,
78 * then returning once the RTC first becomes not busy.
79 * This periodic update (where the seconds and milliseconds are copied to the
80 * AHB side) occurs every eight 32kHz clocks (~250uS).
81 * The behavior of this function allows us to make some assumptions without
82 * introducing a race, because 250uS is plenty of time to read/write a value.
83 */
84static int tegra_rtc_wait_while_busy(struct device *dev)
85{
86 struct tegra_rtc_info *info = dev_get_drvdata(dev);
87
88 int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
89
90 /* first wait for the RTC to become busy. this is when it
91 * posts its updated seconds+msec registers to AHB side. */
92 while (tegra_rtc_check_busy(info)) {
93 if (!retries--)
94 goto retry_failed;
95 udelay(1);
96 }
97
98 /* now we have about 250 us to manipulate registers */
99 return 0;
100
101retry_failed:
102 dev_err(dev, "write failed:retry count exceeded.\n");
103 return -ETIMEDOUT;
104}
105
106static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
107{
108 struct tegra_rtc_info *info = dev_get_drvdata(dev);
109 unsigned long sec, msec;
110 unsigned long sl_irq_flags;
111
112 /* RTC hardware copies seconds to shadow seconds when a read
113 * of milliseconds occurs. use a lock to keep other threads out. */
114 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
115
116 msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
117 sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
118
119 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
120
121 rtc_time_to_tm(sec, tm);
122
123 dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
124 sec,
125 tm->tm_mon + 1,
126 tm->tm_mday,
127 tm->tm_year + 1900,
128 tm->tm_hour,
129 tm->tm_min,
130 tm->tm_sec
131 );
132
133 return 0;
134}
135
136static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
137{
138 struct tegra_rtc_info *info = dev_get_drvdata(dev);
139 unsigned long sec;
140 int ret;
141
142 /* convert tm to seconds. */
143 ret = rtc_valid_tm(tm);
144 if (ret)
145 return ret;
146
147 rtc_tm_to_time(tm, &sec);
148
149 dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
150 sec,
151 tm->tm_mon+1,
152 tm->tm_mday,
153 tm->tm_year+1900,
154 tm->tm_hour,
155 tm->tm_min,
156 tm->tm_sec
157 );
158
159 /* seconds only written if wait succeeded. */
160 ret = tegra_rtc_wait_while_busy(dev);
161 if (!ret)
162 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
163
164 dev_vdbg(dev, "time read back as %d\n",
165 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
166
167 return ret;
168}
169
170static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
171{
172 struct tegra_rtc_info *info = dev_get_drvdata(dev);
173 unsigned long sec;
174 unsigned tmp;
175
176 sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
177
178 if (sec == 0) {
179 /* alarm is disabled. */
180 alarm->enabled = 0;
181 alarm->time.tm_mon = -1;
182 alarm->time.tm_mday = -1;
183 alarm->time.tm_year = -1;
184 alarm->time.tm_hour = -1;
185 alarm->time.tm_min = -1;
186 alarm->time.tm_sec = -1;
187 } else {
188 /* alarm is enabled. */
189 alarm->enabled = 1;
190 rtc_time_to_tm(sec, &alarm->time);
191 }
192
193 tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
194 alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
195
196 return 0;
197}
198
199static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
200{
201 struct tegra_rtc_info *info = dev_get_drvdata(dev);
202 unsigned status;
203 unsigned long sl_irq_flags;
204
205 tegra_rtc_wait_while_busy(dev);
206 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
207
208 /* read the original value, and OR in the flag. */
209 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
210 if (enabled)
211 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
212 else
213 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
214
215 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
216
217 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
218
219 return 0;
220}
221
222static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
223{
224 struct tegra_rtc_info *info = dev_get_drvdata(dev);
225 unsigned long sec;
226
227 if (alarm->enabled)
228 rtc_tm_to_time(&alarm->time, &sec);
229 else
230 sec = 0;
231
232 tegra_rtc_wait_while_busy(dev);
233 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
234 dev_vdbg(dev, "alarm read back as %d\n",
235 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
236
237 /* if successfully written and alarm is enabled ... */
238 if (sec) {
239 tegra_rtc_alarm_irq_enable(dev, 1);
240
241 dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
242 sec,
243 alarm->time.tm_mon+1,
244 alarm->time.tm_mday,
245 alarm->time.tm_year+1900,
246 alarm->time.tm_hour,
247 alarm->time.tm_min,
248 alarm->time.tm_sec);
249 } else {
250 /* disable alarm if 0 or write error. */
251 dev_vdbg(dev, "alarm disabled\n");
252 tegra_rtc_alarm_irq_enable(dev, 0);
253 }
254
255 return 0;
256}
257
258static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
259{
260 if (!dev || !dev->driver)
261 return 0;
262
263 return seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
264}
265
266static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
267{
268 struct device *dev = data;
269 struct tegra_rtc_info *info = dev_get_drvdata(dev);
270 unsigned long events = 0;
271 unsigned status;
272 unsigned long sl_irq_flags;
273
274 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
275 if (status) {
276 /* clear the interrupt masks and status on any irq. */
277 tegra_rtc_wait_while_busy(dev);
278 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
279 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
280 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
281 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
282 }
283
284 /* check if Alarm */
285 if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
286 events |= RTC_IRQF | RTC_AF;
287
288 /* check if Periodic */
289 if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
290 events |= RTC_IRQF | RTC_PF;
291
292 rtc_update_irq(info->rtc_dev, 1, events);
293
294 return IRQ_HANDLED;
295}
296
297static struct rtc_class_ops tegra_rtc_ops = {
298 .read_time = tegra_rtc_read_time,
299 .set_time = tegra_rtc_set_time,
300 .read_alarm = tegra_rtc_read_alarm,
301 .set_alarm = tegra_rtc_set_alarm,
302 .proc = tegra_rtc_proc,
303 .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
304};
305
306static int __devinit tegra_rtc_probe(struct platform_device *pdev)
307{
308 struct tegra_rtc_info *info;
309 struct resource *res;
310 int ret;
311
312 info = kzalloc(sizeof(struct tegra_rtc_info), GFP_KERNEL);
313 if (!info)
314 return -ENOMEM;
315
316 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
317 if (!res) {
318 dev_err(&pdev->dev,
319 "Unable to allocate resources for device.\n");
320 ret = -EBUSY;
321 goto err_free_info;
322 }
323
324 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
325 dev_err(&pdev->dev,
326 "Unable to request mem region for device.\n");
327 ret = -EBUSY;
328 goto err_free_info;
329 }
330
331 info->tegra_rtc_irq = platform_get_irq(pdev, 0);
332 if (info->tegra_rtc_irq <= 0) {
333 ret = -EBUSY;
334 goto err_release_mem_region;
335 }
336
337 info->rtc_base = ioremap_nocache(res->start, resource_size(res));
338 if (!info->rtc_base) {
339 dev_err(&pdev->dev, "Unable to grab IOs for device.\n");
340 ret = -EBUSY;
341 goto err_release_mem_region;
342 }
343
344 /* set context info. */
345 info->pdev = pdev;
346 spin_lock_init(&info->tegra_rtc_lock);
347
348 platform_set_drvdata(pdev, info);
349
350 /* clear out the hardware. */
351 writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
352 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
353 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
354
355 device_init_wakeup(&pdev->dev, 1);
356
357 info->rtc_dev = rtc_device_register(
358 pdev->name, &pdev->dev, &tegra_rtc_ops, THIS_MODULE);
359 if (IS_ERR(info->rtc_dev)) {
360 ret = PTR_ERR(info->rtc_dev);
361 info->rtc_dev = NULL;
362 dev_err(&pdev->dev,
363 "Unable to register device (err=%d).\n",
364 ret);
365 goto err_iounmap;
366 }
367
368 ret = request_irq(info->tegra_rtc_irq, tegra_rtc_irq_handler,
369 IRQF_TRIGGER_HIGH, "rtc alarm", &pdev->dev);
370 if (ret) {
371 dev_err(&pdev->dev,
372 "Unable to request interrupt for device (err=%d).\n",
373 ret);
374 goto err_dev_unreg;
375 }
376
377 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
378
379 return 0;
380
381err_dev_unreg:
382 rtc_device_unregister(info->rtc_dev);
383err_iounmap:
384 iounmap(info->rtc_base);
385err_release_mem_region:
386 release_mem_region(res->start, resource_size(res));
387err_free_info:
388 kfree(info);
389
390 return ret;
391}
392
393static int __devexit tegra_rtc_remove(struct platform_device *pdev)
394{
395 struct tegra_rtc_info *info = platform_get_drvdata(pdev);
396 struct resource *res;
397
398 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
399 if (!res)
400 return -EBUSY;
401
402 free_irq(info->tegra_rtc_irq, &pdev->dev);
403 rtc_device_unregister(info->rtc_dev);
404 iounmap(info->rtc_base);
405 release_mem_region(res->start, resource_size(res));
406 kfree(info);
407
408 platform_set_drvdata(pdev, NULL);
409
410 return 0;
411}
412
413#ifdef CONFIG_PM
414static int tegra_rtc_suspend(struct platform_device *pdev, pm_message_t state)
415{
416 struct device *dev = &pdev->dev;
417 struct tegra_rtc_info *info = platform_get_drvdata(pdev);
418
419 tegra_rtc_wait_while_busy(dev);
420
421 /* only use ALARM0 as a wake source. */
422 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
423 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
424 info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
425
426 dev_vdbg(dev, "alarm sec = %d\n",
427 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
428
429 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
430 device_may_wakeup(dev), info->tegra_rtc_irq);
431
432 /* leave the alarms on as a wake source. */
433 if (device_may_wakeup(dev))
434 enable_irq_wake(info->tegra_rtc_irq);
435
436 return 0;
437}
438
439static int tegra_rtc_resume(struct platform_device *pdev)
440{
441 struct device *dev = &pdev->dev;
442 struct tegra_rtc_info *info = platform_get_drvdata(pdev);
443
444 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
445 device_may_wakeup(dev));
446 /* alarms were left on as a wake source, turn them off. */
447 if (device_may_wakeup(dev))
448 disable_irq_wake(info->tegra_rtc_irq);
449
450 return 0;
451}
452#endif
453
454static void tegra_rtc_shutdown(struct platform_device *pdev)
455{
456 dev_vdbg(&pdev->dev, "disabling interrupts.\n");
457 tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
458}
459
460MODULE_ALIAS("platform:tegra_rtc");
461static struct platform_driver tegra_rtc_driver = {
462 .remove = __devexit_p(tegra_rtc_remove),
463 .shutdown = tegra_rtc_shutdown,
464 .driver = {
465 .name = "tegra_rtc",
466 .owner = THIS_MODULE,
467 },
468#ifdef CONFIG_PM
469 .suspend = tegra_rtc_suspend,
470 .resume = tegra_rtc_resume,
471#endif
472};
473
474static int __init tegra_rtc_init(void)
475{
476 return platform_driver_probe(&tegra_rtc_driver, tegra_rtc_probe);
477}
478module_init(tegra_rtc_init);
479
480static void __exit tegra_rtc_exit(void)
481{
482 platform_driver_unregister(&tegra_rtc_driver);
483}
484module_exit(tegra_rtc_exit);
485
486MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
487MODULE_DESCRIPTION("driver for Tegra internal RTC");
488MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
4 *
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/irq.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/mod_devicetable.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/rtc.h>
19#include <linux/slab.h>
20
21/* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
22#define TEGRA_RTC_REG_BUSY 0x004
23#define TEGRA_RTC_REG_SECONDS 0x008
24/* When msec is read, the seconds are buffered into shadow seconds. */
25#define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
26#define TEGRA_RTC_REG_MILLI_SECONDS 0x010
27#define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
28#define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
29#define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
30#define TEGRA_RTC_REG_INTR_MASK 0x028
31/* write 1 bits to clear status bits */
32#define TEGRA_RTC_REG_INTR_STATUS 0x02c
33
34/* bits in INTR_MASK */
35#define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
36#define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
37#define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
38#define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
39#define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
40
41/* bits in INTR_STATUS */
42#define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
43#define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
44#define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
45#define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
46#define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
47
48struct tegra_rtc_info {
49 struct platform_device *pdev;
50 struct rtc_device *rtc;
51 void __iomem *base; /* NULL if not initialized */
52 struct clk *clk;
53 int irq; /* alarm and periodic IRQ */
54 spinlock_t lock;
55};
56
57/*
58 * RTC hardware is busy when it is updating its values over AHB once every
59 * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to
60 * write. CPU is always free to read.
61 */
62static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
63{
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1;
65}
66
67/*
68 * Wait for hardware to be ready for writing. This function tries to maximize
69 * the amount of time before the next update. It does this by waiting for the
70 * RTC to become busy with its periodic update, then returning once the RTC
71 * first becomes not busy.
72 *
73 * This periodic update (where the seconds and milliseconds are copied to the
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
75 * function allows us to make some assumptions without introducing a race,
76 * because 250 us is plenty of time to read/write a value.
77 */
78static int tegra_rtc_wait_while_busy(struct device *dev)
79{
80 struct tegra_rtc_info *info = dev_get_drvdata(dev);
81 int retries = 500; /* ~490 us is the worst case, ~250 us is best */
82
83 /*
84 * First wait for the RTC to become busy. This is when it posts its
85 * updated seconds+msec registers to AHB side.
86 */
87 while (tegra_rtc_check_busy(info)) {
88 if (!retries--)
89 goto retry_failed;
90
91 udelay(1);
92 }
93
94 /* now we have about 250 us to manipulate registers */
95 return 0;
96
97retry_failed:
98 dev_err(dev, "write failed: retry count exceeded\n");
99 return -ETIMEDOUT;
100}
101
102static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
103{
104 struct tegra_rtc_info *info = dev_get_drvdata(dev);
105 unsigned long flags;
106 u32 sec, msec;
107
108 /*
109 * RTC hardware copies seconds to shadow seconds when a read of
110 * milliseconds occurs. use a lock to keep other threads out.
111 */
112 spin_lock_irqsave(&info->lock, flags);
113
114 msec = readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS);
115 sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS);
116
117 spin_unlock_irqrestore(&info->lock, flags);
118
119 rtc_time64_to_tm(sec, tm);
120
121 dev_vdbg(dev, "time read as %u, %ptR\n", sec, tm);
122
123 return 0;
124}
125
126static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
127{
128 struct tegra_rtc_info *info = dev_get_drvdata(dev);
129 u32 sec;
130 int ret;
131
132 /* convert tm to seconds */
133 sec = rtc_tm_to_time64(tm);
134
135 dev_vdbg(dev, "time set to %u, %ptR\n", sec, tm);
136
137 /* seconds only written if wait succeeded */
138 ret = tegra_rtc_wait_while_busy(dev);
139 if (!ret)
140 writel(sec, info->base + TEGRA_RTC_REG_SECONDS);
141
142 dev_vdbg(dev, "time read back as %d\n",
143 readl(info->base + TEGRA_RTC_REG_SECONDS));
144
145 return ret;
146}
147
148static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
149{
150 struct tegra_rtc_info *info = dev_get_drvdata(dev);
151 u32 sec, value;
152
153 sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
154
155 if (sec == 0) {
156 /* alarm is disabled */
157 alarm->enabled = 0;
158 } else {
159 /* alarm is enabled */
160 alarm->enabled = 1;
161 rtc_time64_to_tm(sec, &alarm->time);
162 }
163
164 value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
165 alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
166
167 return 0;
168}
169
170static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
171{
172 struct tegra_rtc_info *info = dev_get_drvdata(dev);
173 unsigned long flags;
174 u32 status;
175
176 tegra_rtc_wait_while_busy(dev);
177 spin_lock_irqsave(&info->lock, flags);
178
179 /* read the original value, and OR in the flag */
180 status = readl(info->base + TEGRA_RTC_REG_INTR_MASK);
181 if (enabled)
182 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
183 else
184 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
185
186 writel(status, info->base + TEGRA_RTC_REG_INTR_MASK);
187
188 spin_unlock_irqrestore(&info->lock, flags);
189
190 return 0;
191}
192
193static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
194{
195 struct tegra_rtc_info *info = dev_get_drvdata(dev);
196 u32 sec;
197
198 if (alarm->enabled)
199 sec = rtc_tm_to_time64(&alarm->time);
200 else
201 sec = 0;
202
203 tegra_rtc_wait_while_busy(dev);
204 writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
205 dev_vdbg(dev, "alarm read back as %d\n",
206 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
207
208 /* if successfully written and alarm is enabled ... */
209 if (sec) {
210 tegra_rtc_alarm_irq_enable(dev, 1);
211 dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time);
212 } else {
213 /* disable alarm if 0 or write error */
214 dev_vdbg(dev, "alarm disabled\n");
215 tegra_rtc_alarm_irq_enable(dev, 0);
216 }
217
218 return 0;
219}
220
221static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
222{
223 if (!dev || !dev->driver)
224 return 0;
225
226 seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
227
228 return 0;
229}
230
231static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
232{
233 struct device *dev = data;
234 struct tegra_rtc_info *info = dev_get_drvdata(dev);
235 unsigned long events = 0, flags;
236 u32 status;
237
238 status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS);
239 if (status) {
240 /* clear the interrupt masks and status on any IRQ */
241 tegra_rtc_wait_while_busy(dev);
242
243 spin_lock_irqsave(&info->lock, flags);
244 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
245 writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS);
246 spin_unlock_irqrestore(&info->lock, flags);
247 }
248
249 /* check if alarm */
250 if (status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0)
251 events |= RTC_IRQF | RTC_AF;
252
253 /* check if periodic */
254 if (status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM)
255 events |= RTC_IRQF | RTC_PF;
256
257 rtc_update_irq(info->rtc, 1, events);
258
259 return IRQ_HANDLED;
260}
261
262static const struct rtc_class_ops tegra_rtc_ops = {
263 .read_time = tegra_rtc_read_time,
264 .set_time = tegra_rtc_set_time,
265 .read_alarm = tegra_rtc_read_alarm,
266 .set_alarm = tegra_rtc_set_alarm,
267 .proc = tegra_rtc_proc,
268 .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
269};
270
271static const struct of_device_id tegra_rtc_dt_match[] = {
272 { .compatible = "nvidia,tegra20-rtc", },
273 {}
274};
275MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
276
277static int tegra_rtc_probe(struct platform_device *pdev)
278{
279 struct tegra_rtc_info *info;
280 struct resource *res;
281 int ret;
282
283 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
284 if (!info)
285 return -ENOMEM;
286
287 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
288 info->base = devm_ioremap_resource(&pdev->dev, res);
289 if (IS_ERR(info->base))
290 return PTR_ERR(info->base);
291
292 ret = platform_get_irq(pdev, 0);
293 if (ret <= 0)
294 return ret;
295
296 info->irq = ret;
297
298 info->rtc = devm_rtc_allocate_device(&pdev->dev);
299 if (IS_ERR(info->rtc))
300 return PTR_ERR(info->rtc);
301
302 info->rtc->ops = &tegra_rtc_ops;
303 info->rtc->range_max = U32_MAX;
304
305 info->clk = devm_clk_get(&pdev->dev, NULL);
306 if (IS_ERR(info->clk))
307 return PTR_ERR(info->clk);
308
309 ret = clk_prepare_enable(info->clk);
310 if (ret < 0)
311 return ret;
312
313 /* set context info */
314 info->pdev = pdev;
315 spin_lock_init(&info->lock);
316
317 platform_set_drvdata(pdev, info);
318
319 /* clear out the hardware */
320 writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0);
321 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
322 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK);
323
324 device_init_wakeup(&pdev->dev, 1);
325
326 ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler,
327 IRQF_TRIGGER_HIGH, dev_name(&pdev->dev),
328 &pdev->dev);
329 if (ret) {
330 dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret);
331 goto disable_clk;
332 }
333
334 ret = rtc_register_device(info->rtc);
335 if (ret)
336 goto disable_clk;
337
338 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
339
340 return 0;
341
342disable_clk:
343 clk_disable_unprepare(info->clk);
344 return ret;
345}
346
347static int tegra_rtc_remove(struct platform_device *pdev)
348{
349 struct tegra_rtc_info *info = platform_get_drvdata(pdev);
350
351 clk_disable_unprepare(info->clk);
352
353 return 0;
354}
355
356#ifdef CONFIG_PM_SLEEP
357static int tegra_rtc_suspend(struct device *dev)
358{
359 struct tegra_rtc_info *info = dev_get_drvdata(dev);
360
361 tegra_rtc_wait_while_busy(dev);
362
363 /* only use ALARM0 as a wake source */
364 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS);
365 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
366 info->base + TEGRA_RTC_REG_INTR_MASK);
367
368 dev_vdbg(dev, "alarm sec = %d\n",
369 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0));
370
371 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) IRQ:%d\n",
372 device_may_wakeup(dev), info->irq);
373
374 /* leave the alarms on as a wake source */
375 if (device_may_wakeup(dev))
376 enable_irq_wake(info->irq);
377
378 return 0;
379}
380
381static int tegra_rtc_resume(struct device *dev)
382{
383 struct tegra_rtc_info *info = dev_get_drvdata(dev);
384
385 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
386 device_may_wakeup(dev));
387
388 /* alarms were left on as a wake source, turn them off */
389 if (device_may_wakeup(dev))
390 disable_irq_wake(info->irq);
391
392 return 0;
393}
394#endif
395
396static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
397
398static void tegra_rtc_shutdown(struct platform_device *pdev)
399{
400 dev_vdbg(&pdev->dev, "disabling interrupts\n");
401 tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
402}
403
404static struct platform_driver tegra_rtc_driver = {
405 .probe = tegra_rtc_probe,
406 .remove = tegra_rtc_remove,
407 .shutdown = tegra_rtc_shutdown,
408 .driver = {
409 .name = "tegra_rtc",
410 .of_match_table = tegra_rtc_dt_match,
411 .pm = &tegra_rtc_pm_ops,
412 },
413};
414module_platform_driver(tegra_rtc_driver);
415
416MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
417MODULE_DESCRIPTION("driver for Tegra internal RTC");
418MODULE_LICENSE("GPL");