Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
4 *
5 * Copyright (C) 2014-2017 Broadcom
6 */
7
8/*
9 * This module contains USB PHY initialization for power up and S3 resume
10 */
11
12#include <linux/delay.h>
13#include <linux/io.h>
14
15#include <linux/soc/brcmstb/brcmstb.h>
16#include "phy-brcm-usb-init.h"
17
18#define PHY_PORTS 2
19#define PHY_PORT_SELECT_0 0
20#define PHY_PORT_SELECT_1 0x1000
21
22/* Register definitions for the USB CTRL block */
23#define USB_CTRL_SETUP 0x00
24#define USB_CTRL_SETUP_IOC_MASK 0x00000010
25#define USB_CTRL_SETUP_IPP_MASK 0x00000020
26#define USB_CTRL_SETUP_BABO_MASK 0x00000001
27#define USB_CTRL_SETUP_FNHW_MASK 0x00000002
28#define USB_CTRL_SETUP_FNBO_MASK 0x00000004
29#define USB_CTRL_SETUP_WABO_MASK 0x00000008
30#define USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK 0x00002000 /* option */
31#define USB_CTRL_SETUP_SCB1_EN_MASK 0x00004000 /* option */
32#define USB_CTRL_SETUP_SCB2_EN_MASK 0x00008000 /* option */
33#define USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK 0X00020000 /* option */
34#define USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK 0x00010000 /* option */
35#define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK 0x02000000 /* option */
36#define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK 0x04000000 /* option */
37#define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK 0x08000000 /* opt */
38#define USB_CTRL_SETUP_OC3_DISABLE_MASK 0xc0000000 /* option */
39#define USB_CTRL_PLL_CTL 0x04
40#define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000
41#define USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000
42#define USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000 /* option */
43#define USB_CTRL_EBRIDGE 0x0c
44#define USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK 0x00020000 /* option */
45#define USB_CTRL_OBRIDGE 0x10
46#define USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK 0x08000000
47#define USB_CTRL_MDIO 0x14
48#define USB_CTRL_MDIO2 0x18
49#define USB_CTRL_UTMI_CTL_1 0x2c
50#define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800
51#define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK 0x08000000
52#define USB_CTRL_USB_PM 0x34
53#define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK 0x00800000 /* option */
54#define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK 0x00400000 /* option */
55#define USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK 0x40000000 /* option */
56#define USB_CTRL_USB_PM_USB_PWRDN_MASK 0x80000000 /* option */
57#define USB_CTRL_USB_PM_SOFT_RESET_MASK 0x40000000 /* option */
58#define USB_CTRL_USB_PM_USB20_HC_RESETB_MASK 0x30000000 /* option */
59#define USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK 0x00300000 /* option */
60#define USB_CTRL_USB30_CTL1 0x60
61#define USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK 0x00000010
62#define USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK 0x00010000
63#define USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK 0x00020000 /* option */
64#define USB_CTRL_USB30_CTL1_USB3_IOC_MASK 0x10000000 /* option */
65#define USB_CTRL_USB30_CTL1_USB3_IPP_MASK 0x20000000 /* option */
66#define USB_CTRL_USB30_PCTL 0x70
67#define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002
68#define USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK 0x00008000
69#define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000
70#define USB_CTRL_USB_DEVICE_CTL1 0x90
71#define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK 0x00000003 /* option */
72
73/* Register definitions for the XHCI EC block */
74#define USB_XHCI_EC_IRAADR 0x658
75#define USB_XHCI_EC_IRADAT 0x65c
76
77enum brcm_family_type {
78 BRCM_FAMILY_3390A0,
79 BRCM_FAMILY_7250B0,
80 BRCM_FAMILY_7271A0,
81 BRCM_FAMILY_7364A0,
82 BRCM_FAMILY_7366C0,
83 BRCM_FAMILY_74371A0,
84 BRCM_FAMILY_7439B0,
85 BRCM_FAMILY_7445D0,
86 BRCM_FAMILY_7260A0,
87 BRCM_FAMILY_7278A0,
88 BRCM_FAMILY_COUNT,
89};
90
91#define USB_BRCM_FAMILY(chip) \
92 [BRCM_FAMILY_##chip] = __stringify(chip)
93
94static const char *family_names[BRCM_FAMILY_COUNT] = {
95 USB_BRCM_FAMILY(3390A0),
96 USB_BRCM_FAMILY(7250B0),
97 USB_BRCM_FAMILY(7271A0),
98 USB_BRCM_FAMILY(7364A0),
99 USB_BRCM_FAMILY(7366C0),
100 USB_BRCM_FAMILY(74371A0),
101 USB_BRCM_FAMILY(7439B0),
102 USB_BRCM_FAMILY(7445D0),
103 USB_BRCM_FAMILY(7260A0),
104 USB_BRCM_FAMILY(7278A0),
105};
106
107enum {
108 USB_CTRL_SETUP_SCB1_EN_SELECTOR,
109 USB_CTRL_SETUP_SCB2_EN_SELECTOR,
110 USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR,
111 USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
112 USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
113 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
114 USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
115 USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR,
116 USB_CTRL_USB_PM_USB_PWRDN_SELECTOR,
117 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR,
118 USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR,
119 USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR,
120 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR,
121 USB_CTRL_USB_PM_SOFT_RESET_SELECTOR,
122 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR,
123 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR,
124 USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR,
125 USB_CTRL_SETUP_ENDIAN_SELECTOR,
126 USB_CTRL_SELECTOR_COUNT,
127};
128
129#define USB_CTRL_REG(base, reg) ((void *)base + USB_CTRL_##reg)
130#define USB_XHCI_EC_REG(base, reg) ((void *)base + USB_XHCI_EC_##reg)
131#define USB_CTRL_MASK(reg, field) \
132 USB_CTRL_##reg##_##field##_MASK
133#define USB_CTRL_MASK_FAMILY(params, reg, field) \
134 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
135
136#define USB_CTRL_SET_FAMILY(params, reg, field) \
137 usb_ctrl_set_family(params, USB_CTRL_##reg, \
138 USB_CTRL_##reg##_##field##_SELECTOR)
139#define USB_CTRL_UNSET_FAMILY(params, reg, field) \
140 usb_ctrl_unset_family(params, USB_CTRL_##reg, \
141 USB_CTRL_##reg##_##field##_SELECTOR)
142
143#define USB_CTRL_SET(base, reg, field) \
144 usb_ctrl_set(USB_CTRL_REG(base, reg), \
145 USB_CTRL_##reg##_##field##_MASK)
146#define USB_CTRL_UNSET(base, reg, field) \
147 usb_ctrl_unset(USB_CTRL_REG(base, reg), \
148 USB_CTRL_##reg##_##field##_MASK)
149
150#define MDIO_USB2 0
151#define MDIO_USB3 BIT(31)
152
153#define USB_CTRL_SETUP_ENDIAN_BITS ( \
154 USB_CTRL_MASK(SETUP, BABO) | \
155 USB_CTRL_MASK(SETUP, FNHW) | \
156 USB_CTRL_MASK(SETUP, FNBO) | \
157 USB_CTRL_MASK(SETUP, WABO))
158
159#ifdef __LITTLE_ENDIAN
160#define ENDIAN_SETTINGS ( \
161 USB_CTRL_MASK(SETUP, BABO) | \
162 USB_CTRL_MASK(SETUP, FNHW))
163#else
164#define ENDIAN_SETTINGS ( \
165 USB_CTRL_MASK(SETUP, FNHW) | \
166 USB_CTRL_MASK(SETUP, FNBO) | \
167 USB_CTRL_MASK(SETUP, WABO))
168#endif
169
170struct id_to_type {
171 u32 id;
172 int type;
173};
174
175static const struct id_to_type id_to_type_table[] = {
176 { 0x33900000, BRCM_FAMILY_3390A0 },
177 { 0x72500010, BRCM_FAMILY_7250B0 },
178 { 0x72600000, BRCM_FAMILY_7260A0 },
179 { 0x72680000, BRCM_FAMILY_7271A0 },
180 { 0x72710000, BRCM_FAMILY_7271A0 },
181 { 0x73640000, BRCM_FAMILY_7364A0 },
182 { 0x73660020, BRCM_FAMILY_7366C0 },
183 { 0x07437100, BRCM_FAMILY_74371A0 },
184 { 0x74390010, BRCM_FAMILY_7439B0 },
185 { 0x74450030, BRCM_FAMILY_7445D0 },
186 { 0x72780000, BRCM_FAMILY_7278A0 },
187 { 0, BRCM_FAMILY_7271A0 }, /* default */
188};
189
190static const u32
191usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
192 /* 3390B0 */
193 [BRCM_FAMILY_3390A0] = {
194 USB_CTRL_SETUP_SCB1_EN_MASK,
195 USB_CTRL_SETUP_SCB2_EN_MASK,
196 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
197 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
198 USB_CTRL_SETUP_OC3_DISABLE_MASK,
199 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
200 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
201 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
202 USB_CTRL_USB_PM_USB_PWRDN_MASK,
203 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
204 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
205 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
206 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
207 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
208 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
209 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
210 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
211 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
212 },
213 /* 7250b0 */
214 [BRCM_FAMILY_7250B0] = {
215 USB_CTRL_SETUP_SCB1_EN_MASK,
216 USB_CTRL_SETUP_SCB2_EN_MASK,
217 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
218 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
219 USB_CTRL_SETUP_OC3_DISABLE_MASK,
220 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
221 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
222 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
223 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
224 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
225 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
226 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
227 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
228 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
229 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
230 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
231 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
232 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
233 },
234 /* 7271a0 */
235 [BRCM_FAMILY_7271A0] = {
236 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
237 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
238 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
239 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
240 USB_CTRL_SETUP_OC3_DISABLE_MASK,
241 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
242 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
243 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
244 USB_CTRL_USB_PM_USB_PWRDN_MASK,
245 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
246 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
247 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
248 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
249 USB_CTRL_USB_PM_SOFT_RESET_MASK,
250 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
251 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
252 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
253 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
254 },
255 /* 7364a0 */
256 [BRCM_FAMILY_7364A0] = {
257 USB_CTRL_SETUP_SCB1_EN_MASK,
258 USB_CTRL_SETUP_SCB2_EN_MASK,
259 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
260 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
261 USB_CTRL_SETUP_OC3_DISABLE_MASK,
262 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
263 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
264 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
265 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
266 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
267 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
268 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
269 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
270 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
271 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
272 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
273 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
274 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
275 },
276 /* 7366c0 */
277 [BRCM_FAMILY_7366C0] = {
278 USB_CTRL_SETUP_SCB1_EN_MASK,
279 USB_CTRL_SETUP_SCB2_EN_MASK,
280 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
281 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
282 USB_CTRL_SETUP_OC3_DISABLE_MASK,
283 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
284 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
285 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
286 USB_CTRL_USB_PM_USB_PWRDN_MASK,
287 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
288 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
289 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
290 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
291 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
292 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
293 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
294 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
295 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
296 },
297 /* 74371A0 */
298 [BRCM_FAMILY_74371A0] = {
299 USB_CTRL_SETUP_SCB1_EN_MASK,
300 USB_CTRL_SETUP_SCB2_EN_MASK,
301 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
302 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
303 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
304 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
305 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
306 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
307 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
308 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
309 USB_CTRL_USB30_CTL1_USB3_IOC_MASK,
310 USB_CTRL_USB30_CTL1_USB3_IPP_MASK,
311 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
312 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
313 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
314 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
315 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
316 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
317 },
318 /* 7439B0 */
319 [BRCM_FAMILY_7439B0] = {
320 USB_CTRL_SETUP_SCB1_EN_MASK,
321 USB_CTRL_SETUP_SCB2_EN_MASK,
322 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
323 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
324 USB_CTRL_SETUP_OC3_DISABLE_MASK,
325 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
326 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
327 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
328 USB_CTRL_USB_PM_USB_PWRDN_MASK,
329 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
330 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
331 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
332 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
333 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
334 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
335 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
336 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
337 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
338 },
339 /* 7445d0 */
340 [BRCM_FAMILY_7445D0] = {
341 USB_CTRL_SETUP_SCB1_EN_MASK,
342 USB_CTRL_SETUP_SCB2_EN_MASK,
343 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
344 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
345 USB_CTRL_SETUP_OC3_DISABLE_MASK,
346 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
347 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
348 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
349 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
350 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
351 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
352 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
353 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
354 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
355 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
356 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
357 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
358 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
359 },
360 /* 7260a0 */
361 [BRCM_FAMILY_7260A0] = {
362 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
363 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
364 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
365 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
366 USB_CTRL_SETUP_OC3_DISABLE_MASK,
367 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
368 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
369 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
370 USB_CTRL_USB_PM_USB_PWRDN_MASK,
371 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
372 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
373 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
374 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
375 USB_CTRL_USB_PM_SOFT_RESET_MASK,
376 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
377 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
378 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
379 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
380 },
381 /* 7278a0 */
382 [BRCM_FAMILY_7278A0] = {
383 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
384 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
385 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
386 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
387 USB_CTRL_SETUP_OC3_DISABLE_MASK,
388 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
389 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
390 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
391 USB_CTRL_USB_PM_USB_PWRDN_MASK,
392 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
393 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
394 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
395 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
396 USB_CTRL_USB_PM_SOFT_RESET_MASK,
397 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
398 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
399 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
400 0, /* USB_CTRL_SETUP ENDIAN bits */
401 },
402};
403
404static inline u32 brcmusb_readl(void __iomem *addr)
405{
406 return readl(addr);
407}
408
409static inline void brcmusb_writel(u32 val, void __iomem *addr)
410{
411 writel(val, addr);
412}
413
414static inline
415void usb_ctrl_unset_family(struct brcm_usb_init_params *params,
416 u32 reg_offset, u32 field)
417{
418 u32 mask;
419 void *reg;
420
421 mask = params->usb_reg_bits_map[field];
422 reg = params->ctrl_regs + reg_offset;
423 brcmusb_writel(brcmusb_readl(reg) & ~mask, reg);
424};
425
426static inline
427void usb_ctrl_set_family(struct brcm_usb_init_params *params,
428 u32 reg_offset, u32 field)
429{
430 u32 mask;
431 void *reg;
432
433 mask = params->usb_reg_bits_map[field];
434 reg = params->ctrl_regs + reg_offset;
435 brcmusb_writel(brcmusb_readl(reg) | mask, reg);
436};
437
438static inline void usb_ctrl_set(void __iomem *reg, u32 field)
439{
440 u32 value;
441
442 value = brcmusb_readl(reg);
443 brcmusb_writel(value | field, reg);
444}
445
446static inline void usb_ctrl_unset(void __iomem *reg, u32 field)
447{
448 u32 value;
449
450 value = brcmusb_readl(reg);
451 brcmusb_writel(value & ~field, reg);
452}
453
454static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode)
455{
456 u32 data;
457
458 data = (reg << 16) | mode;
459 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
460 data |= (1 << 24);
461 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
462 data &= ~(1 << 24);
463 /* wait for the 60MHz parallel to serial shifter */
464 usleep_range(10, 20);
465 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
466 /* wait for the 60MHz parallel to serial shifter */
467 usleep_range(10, 20);
468
469 return brcmusb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff;
470}
471
472static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg,
473 u32 val, int mode)
474{
475 u32 data;
476
477 data = (reg << 16) | val | mode;
478 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
479 data |= (1 << 25);
480 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
481 data &= ~(1 << 25);
482
483 /* wait for the 60MHz parallel to serial shifter */
484 usleep_range(10, 20);
485 brcmusb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
486 /* wait for the 60MHz parallel to serial shifter */
487 usleep_range(10, 20);
488}
489
490static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base)
491{
492 /* first disable FSM but also leave it that way */
493 /* to allow normal suspend/resume */
494 USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN);
495 USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN_P1);
496
497 /* reset USB 2.0 PLL */
498 USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB);
499 /* PLL reset period */
500 udelay(1);
501 USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB);
502 /* Give PLL enough time to lock */
503 usleep_range(1000, 2000);
504}
505
506static void brcmusb_usb2_eye_fix(void __iomem *ctrl_base)
507{
508 /* Increase USB 2.0 TX level to meet spec requirement */
509 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2);
510 brcmusb_usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2);
511}
512
513static void brcmusb_usb3_pll_fix(void __iomem *ctrl_base)
514{
515 /* Set correct window for PLL lock detect */
516 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
517 brcmusb_usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3);
518}
519
520static void brcmusb_usb3_enable_pipe_reset(void __iomem *ctrl_base)
521{
522 u32 val;
523
524 /* Re-enable USB 3.0 pipe reset */
525 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
526 val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200;
527 brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3);
528}
529
530static void brcmusb_usb3_enable_sigdet(void __iomem *ctrl_base)
531{
532 u32 val, ofs;
533 int ii;
534
535 ofs = 0;
536 for (ii = 0; ii < PHY_PORTS; ++ii) {
537 /* Set correct default for sigdet */
538 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs),
539 MDIO_USB3);
540 val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3);
541 val = (val & ~0x800f) | 0x800d;
542 brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3);
543 ofs = PHY_PORT_SELECT_1;
544 }
545}
546
547static void brcmusb_usb3_enable_skip_align(void __iomem *ctrl_base)
548{
549 u32 val, ofs;
550 int ii;
551
552 ofs = 0;
553 for (ii = 0; ii < PHY_PORTS; ++ii) {
554 /* Set correct default for SKIP align */
555 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs),
556 MDIO_USB3);
557 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200;
558 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
559 ofs = PHY_PORT_SELECT_1;
560 }
561}
562
563static void brcmusb_usb3_unfreeze_aeq(void __iomem *ctrl_base)
564{
565 u32 val, ofs;
566 int ii;
567
568 ofs = 0;
569 for (ii = 0; ii < PHY_PORTS; ++ii) {
570 /* Let EQ freeze after TSEQ */
571 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs),
572 MDIO_USB3);
573 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3);
574 val &= ~0x0008;
575 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
576 ofs = PHY_PORT_SELECT_1;
577 }
578}
579
580static void brcmusb_usb3_pll_54mhz(struct brcm_usb_init_params *params)
581{
582 u32 ofs;
583 int ii;
584 void __iomem *ctrl_base = params->ctrl_regs;
585
586 /*
587 * On newer B53 based SoC's, the reference clock for the
588 * 3.0 PLL has been changed from 50MHz to 54MHz so the
589 * PLL needs to be reprogrammed.
590 * See SWLINUX-4006.
591 *
592 * On the 7364C0, the reference clock for the
593 * 3.0 PLL has been changed from 50MHz to 54MHz to
594 * work around a MOCA issue.
595 * See SWLINUX-4169.
596 */
597 switch (params->selected_family) {
598 case BRCM_FAMILY_3390A0:
599 case BRCM_FAMILY_7250B0:
600 case BRCM_FAMILY_7366C0:
601 case BRCM_FAMILY_74371A0:
602 case BRCM_FAMILY_7439B0:
603 case BRCM_FAMILY_7445D0:
604 case BRCM_FAMILY_7260A0:
605 return;
606 case BRCM_FAMILY_7364A0:
607 if (BRCM_REV(params->family_id) < 0x20)
608 return;
609 break;
610 }
611
612 /* set USB 3.0 PLL to accept 54Mhz reference clock */
613 USB_CTRL_UNSET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
614
615 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
616 brcmusb_usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3);
617 brcmusb_usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3);
618 brcmusb_usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3);
619 brcmusb_usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3);
620 brcmusb_usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3);
621 brcmusb_usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3);
622 brcmusb_usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3);
623 brcmusb_usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3);
624 brcmusb_usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3);
625
626 /* both ports */
627 ofs = 0;
628 for (ii = 0; ii < PHY_PORTS; ++ii) {
629 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs),
630 MDIO_USB3);
631 brcmusb_usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3);
632 brcmusb_usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3);
633 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs),
634 MDIO_USB3);
635 brcmusb_usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3);
636 ofs = PHY_PORT_SELECT_1;
637 }
638
639 /* restart PLL sequence */
640 USB_CTRL_SET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
641 /* Give PLL enough time to lock */
642 usleep_range(1000, 2000);
643}
644
645static void brcmusb_usb3_ssc_enable(void __iomem *ctrl_base)
646{
647 u32 val;
648
649 /* Enable USB 3.0 TX spread spectrum */
650 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3);
651 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
652 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
653
654 /* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers,
655 * which should have been adequate. However, due to a bug in the
656 * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26).
657 */
658 brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3);
659 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
660 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
661}
662
663static void brcmusb_usb3_phy_workarounds(struct brcm_usb_init_params *params)
664{
665 void __iomem *ctrl_base = params->ctrl_regs;
666
667 brcmusb_usb3_pll_fix(ctrl_base);
668 brcmusb_usb3_pll_54mhz(params);
669 brcmusb_usb3_ssc_enable(ctrl_base);
670 brcmusb_usb3_enable_pipe_reset(ctrl_base);
671 brcmusb_usb3_enable_sigdet(ctrl_base);
672 brcmusb_usb3_enable_skip_align(ctrl_base);
673 brcmusb_usb3_unfreeze_aeq(ctrl_base);
674}
675
676static void brcmusb_memc_fix(struct brcm_usb_init_params *params)
677{
678 u32 prid;
679
680 if (params->selected_family != BRCM_FAMILY_7445D0)
681 return;
682 /*
683 * This is a workaround for HW7445-1869 where a DMA write ends up
684 * doing a read pre-fetch after the end of the DMA buffer. This
685 * causes a problem when the DMA buffer is at the end of physical
686 * memory, causing the pre-fetch read to access non-existent memory,
687 * and the chip bondout has MEMC2 disabled. When the pre-fetch read
688 * tries to use the disabled MEMC2, it hangs the bus. The workaround
689 * is to disable MEMC2 access in the usb controller which avoids
690 * the hang.
691 */
692
693 prid = params->product_id & 0xfffff000;
694 switch (prid) {
695 case 0x72520000:
696 case 0x74480000:
697 case 0x74490000:
698 case 0x07252000:
699 case 0x07448000:
700 case 0x07449000:
701 USB_CTRL_UNSET_FAMILY(params, SETUP, SCB2_EN);
702 }
703}
704
705static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params)
706{
707 void __iomem *xhci_ec_base = params->xhci_ec_regs;
708 u32 val;
709
710 if (params->family_id != 0x74371000 || xhci_ec_base == 0)
711 return;
712 brcmusb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR));
713 val = brcmusb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
714
715 /* set cfg_pick_ss_lock */
716 val |= (1 << 27);
717 brcmusb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
718
719 /* Reset USB 3.0 PHY for workaround to take effect */
720 USB_CTRL_UNSET(params->ctrl_regs, USB30_CTL1, PHY3_RESETB);
721 USB_CTRL_SET(params->ctrl_regs, USB30_CTL1, PHY3_RESETB);
722}
723
724static void brcmusb_xhci_soft_reset(struct brcm_usb_init_params *params,
725 int on_off)
726{
727 /* Assert reset */
728 if (on_off) {
729 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
730 USB_CTRL_UNSET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
731 else
732 USB_CTRL_UNSET_FAMILY(params,
733 USB30_CTL1, XHC_SOFT_RESETB);
734 } else { /* De-assert reset */
735 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
736 USB_CTRL_SET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
737 else
738 USB_CTRL_SET_FAMILY(params, USB30_CTL1,
739 XHC_SOFT_RESETB);
740 }
741}
742
743/*
744 * Return the best map table family. The order is:
745 * - exact match of chip and major rev
746 * - exact match of chip and closest older major rev
747 * - default chip/rev.
748 * NOTE: The minor rev is always ignored.
749 */
750static enum brcm_family_type brcmusb_get_family_type(
751 struct brcm_usb_init_params *params)
752{
753 int last_type = -1;
754 u32 last_family = 0;
755 u32 family_no_major;
756 unsigned int x;
757 u32 family;
758
759 family = params->family_id & 0xfffffff0;
760 family_no_major = params->family_id & 0xffffff00;
761 for (x = 0; id_to_type_table[x].id; x++) {
762 if (family == id_to_type_table[x].id)
763 return id_to_type_table[x].type;
764 if (family_no_major == (id_to_type_table[x].id & 0xffffff00))
765 if (family > id_to_type_table[x].id &&
766 last_family < id_to_type_table[x].id) {
767 last_family = id_to_type_table[x].id;
768 last_type = id_to_type_table[x].type;
769 }
770 }
771
772 /* If no match, return the default family */
773 if (last_type == -1)
774 return id_to_type_table[x].type;
775 return last_type;
776}
777
778void brcm_usb_init_ipp(struct brcm_usb_init_params *params)
779{
780 void __iomem *ctrl = params->ctrl_regs;
781 u32 reg;
782 u32 orig_reg;
783
784 /* Starting with the 7445d0, there are no longer separate 3.0
785 * versions of IOC and IPP.
786 */
787 if (USB_CTRL_MASK_FAMILY(params, USB30_CTL1, USB3_IOC)) {
788 if (params->ioc)
789 USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IOC);
790 if (params->ipp == 1)
791 USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IPP);
792 }
793
794 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP));
795 orig_reg = reg;
796 if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_CC_DRD_MODE_ENABLE_SEL))
797 /* Never use the strap, it's going away. */
798 reg &= ~(USB_CTRL_MASK_FAMILY(params,
799 SETUP,
800 STRAP_CC_DRD_MODE_ENABLE_SEL));
801 if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_IPP_SEL))
802 if (params->ipp != 2)
803 /* override ipp strap pin (if it exits) */
804 reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP,
805 STRAP_IPP_SEL));
806
807 /* Override the default OC and PP polarity */
808 reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC));
809 if (params->ioc)
810 reg |= USB_CTRL_MASK(SETUP, IOC);
811 if (params->ipp == 1 && ((reg & USB_CTRL_MASK(SETUP, IPP)) == 0))
812 reg |= USB_CTRL_MASK(SETUP, IPP);
813 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
814
815 /*
816 * If we're changing IPP, make sure power is off long enough
817 * to turn off any connected devices.
818 */
819 if (reg != orig_reg)
820 msleep(50);
821}
822
823int brcm_usb_init_get_dual_select(struct brcm_usb_init_params *params)
824{
825 void __iomem *ctrl = params->ctrl_regs;
826 u32 reg = 0;
827
828 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
829 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
830 reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
831 PORT_MODE);
832 }
833 return reg;
834}
835
836void brcm_usb_init_set_dual_select(struct brcm_usb_init_params *params,
837 int mode)
838{
839 void __iomem *ctrl = params->ctrl_regs;
840 u32 reg;
841
842 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
843 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
844 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
845 PORT_MODE);
846 reg |= mode;
847 brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
848 }
849}
850
851void brcm_usb_init_common(struct brcm_usb_init_params *params)
852{
853 u32 reg;
854 void __iomem *ctrl = params->ctrl_regs;
855
856 /* Take USB out of power down */
857 if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) {
858 USB_CTRL_UNSET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
859 /* 1 millisecond - for USB clocks to settle down */
860 usleep_range(1000, 2000);
861 }
862
863 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) {
864 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB_PWRDN);
865 /* 1 millisecond - for USB clocks to settle down */
866 usleep_range(1000, 2000);
867 }
868
869 if (params->selected_family != BRCM_FAMILY_74371A0 &&
870 (BRCM_ID(params->family_id) != 0x7364))
871 /*
872 * HW7439-637: 7439a0 and its derivatives do not have large
873 * enough descriptor storage for this.
874 */
875 USB_CTRL_SET_FAMILY(params, SETUP, SS_EHCI64BIT_EN);
876
877 /* Block auto PLL suspend by USB2 PHY (Sasi) */
878 USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN);
879
880 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP));
881 if (params->selected_family == BRCM_FAMILY_7364A0)
882 /* Suppress overcurrent indication from USB30 ports for A0 */
883 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE);
884
885 brcmusb_usb_phy_ldo_fix(ctrl);
886 brcmusb_usb2_eye_fix(ctrl);
887
888 /*
889 * Make sure the the second and third memory controller
890 * interfaces are enabled if they exist.
891 */
892 if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN))
893 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN);
894 if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN))
895 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN);
896 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
897
898 brcmusb_memc_fix(params);
899
900 if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
901 reg = brcmusb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
902 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
903 PORT_MODE);
904 reg |= params->mode;
905 brcmusb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
906 }
907 if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) {
908 switch (params->mode) {
909 case USB_CTLR_MODE_HOST:
910 USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
911 break;
912 default:
913 USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
914 USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
915 break;
916 }
917 }
918 if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) {
919 if (params->mode == USB_CTLR_MODE_TYPEC_PD)
920 USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE);
921 else
922 USB_CTRL_UNSET_FAMILY(params, SETUP,
923 CC_DRD_MODE_ENABLE);
924 }
925}
926
927void brcm_usb_init_eohci(struct brcm_usb_init_params *params)
928{
929 u32 reg;
930 void __iomem *ctrl = params->ctrl_regs;
931
932 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB))
933 USB_CTRL_SET_FAMILY(params, USB_PM, USB20_HC_RESETB);
934
935 if (params->selected_family == BRCM_FAMILY_7366C0)
936 /*
937 * Don't enable this so the memory controller doesn't read
938 * into memory holes. NOTE: This bit is low true on 7366C0.
939 */
940 USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ);
941
942 /* Setup the endian bits */
943 reg = brcmusb_readl(USB_CTRL_REG(ctrl, SETUP));
944 reg &= ~USB_CTRL_SETUP_ENDIAN_BITS;
945 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN);
946 brcmusb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
947
948 if (params->selected_family == BRCM_FAMILY_7271A0)
949 /* Enable LS keep alive fix for certain keyboards */
950 USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE);
951}
952
953void brcm_usb_init_xhci(struct brcm_usb_init_params *params)
954{
955 void __iomem *ctrl = params->ctrl_regs;
956
957 USB_CTRL_UNSET(ctrl, USB30_PCTL, PHY3_IDDQ_OVERRIDE);
958 /* 1 millisecond - for USB clocks to settle down */
959 usleep_range(1000, 2000);
960
961 if (BRCM_ID(params->family_id) == 0x7366) {
962 /*
963 * The PHY3_SOFT_RESETB bits default to the wrong state.
964 */
965 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB);
966 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB_P1);
967 }
968
969 /*
970 * Kick start USB3 PHY
971 * Make sure it's low to insure a rising edge.
972 */
973 USB_CTRL_UNSET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
974 USB_CTRL_SET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
975
976 brcmusb_usb3_phy_workarounds(params);
977 brcmusb_xhci_soft_reset(params, 0);
978 brcmusb_usb3_otp_fix(params);
979}
980
981void brcm_usb_uninit_common(struct brcm_usb_init_params *params)
982{
983 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN))
984 USB_CTRL_SET_FAMILY(params, USB_PM, USB_PWRDN);
985
986 if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN))
987 USB_CTRL_SET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
988}
989
990void brcm_usb_uninit_eohci(struct brcm_usb_init_params *params)
991{
992 if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB))
993 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB20_HC_RESETB);
994}
995
996void brcm_usb_uninit_xhci(struct brcm_usb_init_params *params)
997{
998 brcmusb_xhci_soft_reset(params, 1);
999 USB_CTRL_SET(params->ctrl_regs, USB30_PCTL, PHY3_IDDQ_OVERRIDE);
1000}
1001
1002void brcm_usb_set_family_map(struct brcm_usb_init_params *params)
1003{
1004 int fam;
1005
1006 fam = brcmusb_get_family_type(params);
1007 params->selected_family = fam;
1008 params->usb_reg_bits_map =
1009 &usb_reg_bits_map_table[fam][0];
1010 params->family_name = family_names[fam];
1011}