Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014 Renesas Electronics Europe Ltd
5 *
6 * Based on:
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
10 *
11 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/msi.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/of_pci.h>
26#include <linux/of_platform.h>
27#include <linux/pci.h>
28#include <linux/phy/phy.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/slab.h>
32
33#include "../pci.h"
34
35#define PCIECAR 0x000010
36#define PCIECCTLR 0x000018
37#define CONFIG_SEND_ENABLE BIT(31)
38#define TYPE0 (0 << 8)
39#define TYPE1 BIT(8)
40#define PCIECDR 0x000020
41#define PCIEMSR 0x000028
42#define PCIEINTXR 0x000400
43#define PCIEPHYSR 0x0007f0
44#define PHYRDY BIT(0)
45#define PCIEMSITXR 0x000840
46
47/* Transfer control */
48#define PCIETCTLR 0x02000
49#define DL_DOWN BIT(3)
50#define CFINIT BIT(0)
51#define PCIETSTR 0x02004
52#define DATA_LINK_ACTIVE BIT(0)
53#define PCIEERRFR 0x02020
54#define UNSUPPORTED_REQUEST BIT(4)
55#define PCIEMSIFR 0x02044
56#define PCIEMSIALR 0x02048
57#define MSIFE BIT(0)
58#define PCIEMSIAUR 0x0204c
59#define PCIEMSIIER 0x02050
60
61/* root port address */
62#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
63
64/* local address reg & mask */
65#define PCIELAR(x) (0x02200 + ((x) * 0x20))
66#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
67#define LAM_PREFETCH BIT(3)
68#define LAM_64BIT BIT(2)
69#define LAR_ENABLE BIT(1)
70
71/* PCIe address reg & mask */
72#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
73#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
74#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
75#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
76#define PAR_ENABLE BIT(31)
77#define IO_SPACE BIT(8)
78
79/* Configuration */
80#define PCICONF(x) (0x010000 + ((x) * 0x4))
81#define PMCAP(x) (0x010040 + ((x) * 0x4))
82#define EXPCAP(x) (0x010070 + ((x) * 0x4))
83#define VCCAP(x) (0x010100 + ((x) * 0x4))
84
85/* link layer */
86#define IDSETR1 0x011004
87#define TLCTLR 0x011048
88#define MACSR 0x011054
89#define SPCHGFIN BIT(4)
90#define SPCHGFAIL BIT(6)
91#define SPCHGSUC BIT(7)
92#define LINK_SPEED (0xf << 16)
93#define LINK_SPEED_2_5GTS (1 << 16)
94#define LINK_SPEED_5_0GTS (2 << 16)
95#define MACCTLR 0x011058
96#define SPEED_CHANGE BIT(24)
97#define SCRAMBLE_DISABLE BIT(27)
98#define PMSR 0x01105c
99#define MACS2R 0x011078
100#define MACCGSPSETR 0x011084
101#define SPCNGRSN BIT(31)
102
103/* R-Car H1 PHY */
104#define H1_PCIEPHYADRR 0x04000c
105#define WRITE_CMD BIT(16)
106#define PHY_ACK BIT(24)
107#define RATE_POS 12
108#define LANE_POS 8
109#define ADR_POS 0
110#define H1_PCIEPHYDOUTR 0x040014
111
112/* R-Car Gen2 PHY */
113#define GEN2_PCIEPHYADDR 0x780
114#define GEN2_PCIEPHYDATA 0x784
115#define GEN2_PCIEPHYCTRL 0x78c
116
117#define INT_PCI_MSI_NR 32
118
119#define RCONF(x) (PCICONF(0) + (x))
120#define RPMCAP(x) (PMCAP(0) + (x))
121#define REXPCAP(x) (EXPCAP(0) + (x))
122#define RVCCAP(x) (VCCAP(0) + (x))
123
124#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
125#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
126#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
127
128#define RCAR_PCI_MAX_RESOURCES 4
129#define MAX_NR_INBOUND_MAPS 6
130
131struct rcar_msi {
132 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
133 struct irq_domain *domain;
134 struct msi_controller chip;
135 unsigned long pages;
136 struct mutex lock;
137 int irq1;
138 int irq2;
139};
140
141static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
142{
143 return container_of(chip, struct rcar_msi, chip);
144}
145
146/* Structure representing the PCIe interface */
147struct rcar_pcie {
148 struct device *dev;
149 struct phy *phy;
150 void __iomem *base;
151 struct list_head resources;
152 int root_bus_nr;
153 struct clk *bus_clk;
154 struct rcar_msi msi;
155};
156
157static void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val,
158 unsigned int reg)
159{
160 writel(val, pcie->base + reg);
161}
162
163static u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
164{
165 return readl(pcie->base + reg);
166}
167
168enum {
169 RCAR_PCI_ACCESS_READ,
170 RCAR_PCI_ACCESS_WRITE,
171};
172
173static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
174{
175 unsigned int shift = BITS_PER_BYTE * (where & 3);
176 u32 val = rcar_pci_read_reg(pcie, where & ~3);
177
178 val &= ~(mask << shift);
179 val |= data << shift;
180 rcar_pci_write_reg(pcie, val, where & ~3);
181}
182
183static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
184{
185 unsigned int shift = BITS_PER_BYTE * (where & 3);
186 u32 val = rcar_pci_read_reg(pcie, where & ~3);
187
188 return val >> shift;
189}
190
191/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
192static int rcar_pcie_config_access(struct rcar_pcie *pcie,
193 unsigned char access_type, struct pci_bus *bus,
194 unsigned int devfn, int where, u32 *data)
195{
196 unsigned int dev, func, reg, index;
197
198 dev = PCI_SLOT(devfn);
199 func = PCI_FUNC(devfn);
200 reg = where & ~3;
201 index = reg / 4;
202
203 /*
204 * While each channel has its own memory-mapped extended config
205 * space, it's generally only accessible when in endpoint mode.
206 * When in root complex mode, the controller is unable to target
207 * itself with either type 0 or type 1 accesses, and indeed, any
208 * controller initiated target transfer to its own config space
209 * result in a completer abort.
210 *
211 * Each channel effectively only supports a single device, but as
212 * the same channel <-> device access works for any PCI_SLOT()
213 * value, we cheat a bit here and bind the controller's config
214 * space to devfn 0 in order to enable self-enumeration. In this
215 * case the regular ECAR/ECDR path is sidelined and the mangled
216 * config access itself is initiated as an internal bus transaction.
217 */
218 if (pci_is_root_bus(bus)) {
219 if (dev != 0)
220 return PCIBIOS_DEVICE_NOT_FOUND;
221
222 if (access_type == RCAR_PCI_ACCESS_READ) {
223 *data = rcar_pci_read_reg(pcie, PCICONF(index));
224 } else {
225 /* Keep an eye out for changes to the root bus number */
226 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
227 pcie->root_bus_nr = *data & 0xff;
228
229 rcar_pci_write_reg(pcie, *data, PCICONF(index));
230 }
231
232 return PCIBIOS_SUCCESSFUL;
233 }
234
235 if (pcie->root_bus_nr < 0)
236 return PCIBIOS_DEVICE_NOT_FOUND;
237
238 /* Clear errors */
239 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
240
241 /* Set the PIO address */
242 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
243 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
244
245 /* Enable the configuration access */
246 if (bus->parent->number == pcie->root_bus_nr)
247 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
248 else
249 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
250
251 /* Check for errors */
252 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
253 return PCIBIOS_DEVICE_NOT_FOUND;
254
255 /* Check for master and target aborts */
256 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
257 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
258 return PCIBIOS_DEVICE_NOT_FOUND;
259
260 if (access_type == RCAR_PCI_ACCESS_READ)
261 *data = rcar_pci_read_reg(pcie, PCIECDR);
262 else
263 rcar_pci_write_reg(pcie, *data, PCIECDR);
264
265 /* Disable the configuration access */
266 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
267
268 return PCIBIOS_SUCCESSFUL;
269}
270
271static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
272 int where, int size, u32 *val)
273{
274 struct rcar_pcie *pcie = bus->sysdata;
275 int ret;
276
277 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
278 bus, devfn, where, val);
279 if (ret != PCIBIOS_SUCCESSFUL) {
280 *val = 0xffffffff;
281 return ret;
282 }
283
284 if (size == 1)
285 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff;
286 else if (size == 2)
287 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff;
288
289 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
290 bus->number, devfn, where, size, *val);
291
292 return ret;
293}
294
295/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
296static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
297 int where, int size, u32 val)
298{
299 struct rcar_pcie *pcie = bus->sysdata;
300 unsigned int shift;
301 u32 data;
302 int ret;
303
304 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
305 bus, devfn, where, &data);
306 if (ret != PCIBIOS_SUCCESSFUL)
307 return ret;
308
309 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n",
310 bus->number, devfn, where, size, val);
311
312 if (size == 1) {
313 shift = BITS_PER_BYTE * (where & 3);
314 data &= ~(0xff << shift);
315 data |= ((val & 0xff) << shift);
316 } else if (size == 2) {
317 shift = BITS_PER_BYTE * (where & 2);
318 data &= ~(0xffff << shift);
319 data |= ((val & 0xffff) << shift);
320 } else
321 data = val;
322
323 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
324 bus, devfn, where, &data);
325
326 return ret;
327}
328
329static struct pci_ops rcar_pcie_ops = {
330 .read = rcar_pcie_read_conf,
331 .write = rcar_pcie_write_conf,
332};
333
334static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
335 struct resource *res)
336{
337 /* Setup PCIe address space mappings for each resource */
338 resource_size_t size;
339 resource_size_t res_start;
340 u32 mask;
341
342 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
343
344 /*
345 * The PAMR mask is calculated in units of 128Bytes, which
346 * keeps things pretty simple.
347 */
348 size = resource_size(res);
349 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
350 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
351
352 if (res->flags & IORESOURCE_IO)
353 res_start = pci_pio_to_address(res->start);
354 else
355 res_start = res->start;
356
357 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
358 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
359 PCIEPALR(win));
360
361 /* First resource is for IO */
362 mask = PAR_ENABLE;
363 if (res->flags & IORESOURCE_IO)
364 mask |= IO_SPACE;
365
366 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
367}
368
369static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
370{
371 struct resource_entry *win;
372 int i = 0;
373
374 /* Setup PCI resources */
375 resource_list_for_each_entry(win, &pci->resources) {
376 struct resource *res = win->res;
377
378 if (!res->flags)
379 continue;
380
381 switch (resource_type(res)) {
382 case IORESOURCE_IO:
383 case IORESOURCE_MEM:
384 rcar_pcie_setup_window(i, pci, res);
385 i++;
386 break;
387 case IORESOURCE_BUS:
388 pci->root_bus_nr = res->start;
389 break;
390 default:
391 continue;
392 }
393
394 pci_add_resource(resource, res);
395 }
396
397 return 1;
398}
399
400static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
401{
402 struct device *dev = pcie->dev;
403 unsigned int timeout = 1000;
404 u32 macsr;
405
406 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
407 return;
408
409 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
410 dev_err(dev, "Speed change already in progress\n");
411 return;
412 }
413
414 macsr = rcar_pci_read_reg(pcie, MACSR);
415 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
416 goto done;
417
418 /* Set target link speed to 5.0 GT/s */
419 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
420 PCI_EXP_LNKSTA_CLS_5_0GB);
421
422 /* Set speed change reason as intentional factor */
423 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
424
425 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
426 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
427 rcar_pci_write_reg(pcie, macsr, MACSR);
428
429 /* Start link speed change */
430 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
431
432 while (timeout--) {
433 macsr = rcar_pci_read_reg(pcie, MACSR);
434 if (macsr & SPCHGFIN) {
435 /* Clear the interrupt bits */
436 rcar_pci_write_reg(pcie, macsr, MACSR);
437
438 if (macsr & SPCHGFAIL)
439 dev_err(dev, "Speed change failed\n");
440
441 goto done;
442 }
443
444 msleep(1);
445 }
446
447 dev_err(dev, "Speed change timed out\n");
448
449done:
450 dev_info(dev, "Current link speed is %s GT/s\n",
451 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
452}
453
454static int rcar_pcie_enable(struct rcar_pcie *pcie)
455{
456 struct device *dev = pcie->dev;
457 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
458 struct pci_bus *bus, *child;
459 int ret;
460
461 /* Try setting 5 GT/s link speed */
462 rcar_pcie_force_speedup(pcie);
463
464 rcar_pcie_setup(&bridge->windows, pcie);
465
466 pci_add_flags(PCI_REASSIGN_ALL_BUS);
467
468 bridge->dev.parent = dev;
469 bridge->sysdata = pcie;
470 bridge->busnr = pcie->root_bus_nr;
471 bridge->ops = &rcar_pcie_ops;
472 bridge->map_irq = of_irq_parse_and_map_pci;
473 bridge->swizzle_irq = pci_common_swizzle;
474 if (IS_ENABLED(CONFIG_PCI_MSI))
475 bridge->msi = &pcie->msi.chip;
476
477 ret = pci_scan_root_bus_bridge(bridge);
478 if (ret < 0)
479 return ret;
480
481 bus = bridge->bus;
482
483 pci_bus_size_bridges(bus);
484 pci_bus_assign_resources(bus);
485
486 list_for_each_entry(child, &bus->children, node)
487 pcie_bus_configure_settings(child);
488
489 pci_bus_add_devices(bus);
490
491 return 0;
492}
493
494static int phy_wait_for_ack(struct rcar_pcie *pcie)
495{
496 struct device *dev = pcie->dev;
497 unsigned int timeout = 100;
498
499 while (timeout--) {
500 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
501 return 0;
502
503 udelay(100);
504 }
505
506 dev_err(dev, "Access to PCIe phy timed out\n");
507
508 return -ETIMEDOUT;
509}
510
511static void phy_write_reg(struct rcar_pcie *pcie,
512 unsigned int rate, u32 addr,
513 unsigned int lane, u32 data)
514{
515 u32 phyaddr;
516
517 phyaddr = WRITE_CMD |
518 ((rate & 1) << RATE_POS) |
519 ((lane & 0xf) << LANE_POS) |
520 ((addr & 0xff) << ADR_POS);
521
522 /* Set write data */
523 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
524 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
525
526 /* Ignore errors as they will be dealt with if the data link is down */
527 phy_wait_for_ack(pcie);
528
529 /* Clear command */
530 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
531 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
532
533 /* Ignore errors as they will be dealt with if the data link is down */
534 phy_wait_for_ack(pcie);
535}
536
537static int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
538{
539 unsigned int timeout = 10;
540
541 while (timeout--) {
542 if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
543 return 0;
544
545 msleep(5);
546 }
547
548 return -ETIMEDOUT;
549}
550
551static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
552{
553 unsigned int timeout = 10000;
554
555 while (timeout--) {
556 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
557 return 0;
558
559 udelay(5);
560 cpu_relax();
561 }
562
563 return -ETIMEDOUT;
564}
565
566static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
567{
568 int err;
569
570 /* Begin initialization */
571 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
572
573 /* Set mode */
574 rcar_pci_write_reg(pcie, 1, PCIEMSR);
575
576 err = rcar_pcie_wait_for_phyrdy(pcie);
577 if (err)
578 return err;
579
580 /*
581 * Initial header for port config space is type 1, set the device
582 * class to match. Hardware takes care of propagating the IDSETR
583 * settings, so there is no need to bother with a quirk.
584 */
585 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
586
587 /*
588 * Setup Secondary Bus Number & Subordinate Bus Number, even though
589 * they aren't used, to avoid bridge being detected as broken.
590 */
591 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
592 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
593
594 /* Initialize default capabilities. */
595 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
596 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
597 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
598 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
599 PCI_HEADER_TYPE_BRIDGE);
600
601 /* Enable data link layer active state reporting */
602 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
603 PCI_EXP_LNKCAP_DLLLARC);
604
605 /* Write out the physical slot number = 0 */
606 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
607
608 /* Set the completion timer timeout to the maximum 50ms. */
609 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
610
611 /* Terminate list of capabilities (Next Capability Offset=0) */
612 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
613
614 /* Enable MSI */
615 if (IS_ENABLED(CONFIG_PCI_MSI))
616 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
617
618 /* Finish initialization - establish a PCI Express link */
619 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
620
621 /* This will timeout if we don't have a link. */
622 err = rcar_pcie_wait_for_dl(pcie);
623 if (err)
624 return err;
625
626 /* Enable INTx interrupts */
627 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
628
629 wmb();
630
631 return 0;
632}
633
634static int rcar_pcie_phy_init_h1(struct rcar_pcie *pcie)
635{
636 /* Initialize the phy */
637 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
638 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
639 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
640 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
641 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
642 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
643 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
644 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
645 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
646 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
647 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
648 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
649
650 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
651 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
652 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
653
654 return 0;
655}
656
657static int rcar_pcie_phy_init_gen2(struct rcar_pcie *pcie)
658{
659 /*
660 * These settings come from the R-Car Series, 2nd Generation User's
661 * Manual, section 50.3.1 (2) Initialization of the physical layer.
662 */
663 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
664 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
665 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
666 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
667
668 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
669 /* The following value is for DC connection, no termination resistor */
670 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
671 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
672 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
673
674 return 0;
675}
676
677static int rcar_pcie_phy_init_gen3(struct rcar_pcie *pcie)
678{
679 int err;
680
681 err = phy_init(pcie->phy);
682 if (err)
683 return err;
684
685 err = phy_power_on(pcie->phy);
686 if (err)
687 phy_exit(pcie->phy);
688
689 return err;
690}
691
692static int rcar_msi_alloc(struct rcar_msi *chip)
693{
694 int msi;
695
696 mutex_lock(&chip->lock);
697
698 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
699 if (msi < INT_PCI_MSI_NR)
700 set_bit(msi, chip->used);
701 else
702 msi = -ENOSPC;
703
704 mutex_unlock(&chip->lock);
705
706 return msi;
707}
708
709static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
710{
711 int msi;
712
713 mutex_lock(&chip->lock);
714 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
715 order_base_2(no_irqs));
716 mutex_unlock(&chip->lock);
717
718 return msi;
719}
720
721static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
722{
723 mutex_lock(&chip->lock);
724 clear_bit(irq, chip->used);
725 mutex_unlock(&chip->lock);
726}
727
728static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
729{
730 struct rcar_pcie *pcie = data;
731 struct rcar_msi *msi = &pcie->msi;
732 struct device *dev = pcie->dev;
733 unsigned long reg;
734
735 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
736
737 /* MSI & INTx share an interrupt - we only handle MSI here */
738 if (!reg)
739 return IRQ_NONE;
740
741 while (reg) {
742 unsigned int index = find_first_bit(®, 32);
743 unsigned int msi_irq;
744
745 /* clear the interrupt */
746 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
747
748 msi_irq = irq_find_mapping(msi->domain, index);
749 if (msi_irq) {
750 if (test_bit(index, msi->used))
751 generic_handle_irq(msi_irq);
752 else
753 dev_info(dev, "unhandled MSI\n");
754 } else {
755 /* Unknown MSI, just clear it */
756 dev_dbg(dev, "unexpected MSI\n");
757 }
758
759 /* see if there's any more pending in this vector */
760 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
761 }
762
763 return IRQ_HANDLED;
764}
765
766static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
767 struct msi_desc *desc)
768{
769 struct rcar_msi *msi = to_rcar_msi(chip);
770 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
771 struct msi_msg msg;
772 unsigned int irq;
773 int hwirq;
774
775 hwirq = rcar_msi_alloc(msi);
776 if (hwirq < 0)
777 return hwirq;
778
779 irq = irq_find_mapping(msi->domain, hwirq);
780 if (!irq) {
781 rcar_msi_free(msi, hwirq);
782 return -EINVAL;
783 }
784
785 irq_set_msi_desc(irq, desc);
786
787 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
788 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
789 msg.data = hwirq;
790
791 pci_write_msi_msg(irq, &msg);
792
793 return 0;
794}
795
796static int rcar_msi_setup_irqs(struct msi_controller *chip,
797 struct pci_dev *pdev, int nvec, int type)
798{
799 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
800 struct rcar_msi *msi = to_rcar_msi(chip);
801 struct msi_desc *desc;
802 struct msi_msg msg;
803 unsigned int irq;
804 int hwirq;
805 int i;
806
807 /* MSI-X interrupts are not supported */
808 if (type == PCI_CAP_ID_MSIX)
809 return -EINVAL;
810
811 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
812 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
813
814 hwirq = rcar_msi_alloc_region(msi, nvec);
815 if (hwirq < 0)
816 return -ENOSPC;
817
818 irq = irq_find_mapping(msi->domain, hwirq);
819 if (!irq)
820 return -ENOSPC;
821
822 for (i = 0; i < nvec; i++) {
823 /*
824 * irq_create_mapping() called from rcar_pcie_probe() pre-
825 * allocates descs, so there is no need to allocate descs here.
826 * We can therefore assume that if irq_find_mapping() above
827 * returns non-zero, then the descs are also successfully
828 * allocated.
829 */
830 if (irq_set_msi_desc_off(irq, i, desc)) {
831 /* TODO: clear */
832 return -EINVAL;
833 }
834 }
835
836 desc->nvec_used = nvec;
837 desc->msi_attrib.multiple = order_base_2(nvec);
838
839 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
840 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
841 msg.data = hwirq;
842
843 pci_write_msi_msg(irq, &msg);
844
845 return 0;
846}
847
848static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
849{
850 struct rcar_msi *msi = to_rcar_msi(chip);
851 struct irq_data *d = irq_get_irq_data(irq);
852
853 rcar_msi_free(msi, d->hwirq);
854}
855
856static struct irq_chip rcar_msi_irq_chip = {
857 .name = "R-Car PCIe MSI",
858 .irq_enable = pci_msi_unmask_irq,
859 .irq_disable = pci_msi_mask_irq,
860 .irq_mask = pci_msi_mask_irq,
861 .irq_unmask = pci_msi_unmask_irq,
862};
863
864static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
865 irq_hw_number_t hwirq)
866{
867 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
868 irq_set_chip_data(irq, domain->host_data);
869
870 return 0;
871}
872
873static const struct irq_domain_ops msi_domain_ops = {
874 .map = rcar_msi_map,
875};
876
877static void rcar_pcie_unmap_msi(struct rcar_pcie *pcie)
878{
879 struct rcar_msi *msi = &pcie->msi;
880 int i, irq;
881
882 for (i = 0; i < INT_PCI_MSI_NR; i++) {
883 irq = irq_find_mapping(msi->domain, i);
884 if (irq > 0)
885 irq_dispose_mapping(irq);
886 }
887
888 irq_domain_remove(msi->domain);
889}
890
891static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
892{
893 struct device *dev = pcie->dev;
894 struct rcar_msi *msi = &pcie->msi;
895 phys_addr_t base;
896 int err, i;
897
898 mutex_init(&msi->lock);
899
900 msi->chip.dev = dev;
901 msi->chip.setup_irq = rcar_msi_setup_irq;
902 msi->chip.setup_irqs = rcar_msi_setup_irqs;
903 msi->chip.teardown_irq = rcar_msi_teardown_irq;
904
905 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
906 &msi_domain_ops, &msi->chip);
907 if (!msi->domain) {
908 dev_err(dev, "failed to create IRQ domain\n");
909 return -ENOMEM;
910 }
911
912 for (i = 0; i < INT_PCI_MSI_NR; i++)
913 irq_create_mapping(msi->domain, i);
914
915 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
916 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
917 IRQF_SHARED | IRQF_NO_THREAD,
918 rcar_msi_irq_chip.name, pcie);
919 if (err < 0) {
920 dev_err(dev, "failed to request IRQ: %d\n", err);
921 goto err;
922 }
923
924 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
925 IRQF_SHARED | IRQF_NO_THREAD,
926 rcar_msi_irq_chip.name, pcie);
927 if (err < 0) {
928 dev_err(dev, "failed to request IRQ: %d\n", err);
929 goto err;
930 }
931
932 /* setup MSI data target */
933 msi->pages = __get_free_pages(GFP_KERNEL, 0);
934 if (!msi->pages) {
935 err = -ENOMEM;
936 goto err;
937 }
938 base = virt_to_phys((void *)msi->pages);
939
940 rcar_pci_write_reg(pcie, lower_32_bits(base) | MSIFE, PCIEMSIALR);
941 rcar_pci_write_reg(pcie, upper_32_bits(base), PCIEMSIAUR);
942
943 /* enable all MSI interrupts */
944 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
945
946 return 0;
947
948err:
949 rcar_pcie_unmap_msi(pcie);
950 return err;
951}
952
953static void rcar_pcie_teardown_msi(struct rcar_pcie *pcie)
954{
955 struct rcar_msi *msi = &pcie->msi;
956
957 /* Disable all MSI interrupts */
958 rcar_pci_write_reg(pcie, 0, PCIEMSIIER);
959
960 /* Disable address decoding of the MSI interrupt, MSIFE */
961 rcar_pci_write_reg(pcie, 0, PCIEMSIALR);
962
963 free_pages(msi->pages, 0);
964
965 rcar_pcie_unmap_msi(pcie);
966}
967
968static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
969{
970 struct device *dev = pcie->dev;
971 struct resource res;
972 int err, i;
973
974 pcie->phy = devm_phy_optional_get(dev, "pcie");
975 if (IS_ERR(pcie->phy))
976 return PTR_ERR(pcie->phy);
977
978 err = of_address_to_resource(dev->of_node, 0, &res);
979 if (err)
980 return err;
981
982 pcie->base = devm_ioremap_resource(dev, &res);
983 if (IS_ERR(pcie->base))
984 return PTR_ERR(pcie->base);
985
986 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
987 if (IS_ERR(pcie->bus_clk)) {
988 dev_err(dev, "cannot get pcie bus clock\n");
989 return PTR_ERR(pcie->bus_clk);
990 }
991
992 i = irq_of_parse_and_map(dev->of_node, 0);
993 if (!i) {
994 dev_err(dev, "cannot get platform resources for msi interrupt\n");
995 err = -ENOENT;
996 goto err_irq1;
997 }
998 pcie->msi.irq1 = i;
999
1000 i = irq_of_parse_and_map(dev->of_node, 1);
1001 if (!i) {
1002 dev_err(dev, "cannot get platform resources for msi interrupt\n");
1003 err = -ENOENT;
1004 goto err_irq2;
1005 }
1006 pcie->msi.irq2 = i;
1007
1008 return 0;
1009
1010err_irq2:
1011 irq_dispose_mapping(pcie->msi.irq1);
1012err_irq1:
1013 return err;
1014}
1015
1016static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
1017 struct of_pci_range *range,
1018 int *index)
1019{
1020 u64 restype = range->flags;
1021 u64 cpu_addr = range->cpu_addr;
1022 u64 cpu_end = range->cpu_addr + range->size;
1023 u64 pci_addr = range->pci_addr;
1024 u32 flags = LAM_64BIT | LAR_ENABLE;
1025 u64 mask;
1026 u64 size;
1027 int idx = *index;
1028
1029 if (restype & IORESOURCE_PREFETCH)
1030 flags |= LAM_PREFETCH;
1031
1032 /*
1033 * If the size of the range is larger than the alignment of the start
1034 * address, we have to use multiple entries to perform the mapping.
1035 */
1036 if (cpu_addr > 0) {
1037 unsigned long nr_zeros = __ffs64(cpu_addr);
1038 u64 alignment = 1ULL << nr_zeros;
1039
1040 size = min(range->size, alignment);
1041 } else {
1042 size = range->size;
1043 }
1044 /* Hardware supports max 4GiB inbound region */
1045 size = min(size, 1ULL << 32);
1046
1047 mask = roundup_pow_of_two(size) - 1;
1048 mask &= ~0xf;
1049
1050 while (cpu_addr < cpu_end) {
1051 /*
1052 * Set up 64-bit inbound regions as the range parser doesn't
1053 * distinguish between 32 and 64-bit types.
1054 */
1055 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1056 PCIEPRAR(idx));
1057 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1058 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1059 PCIELAMR(idx));
1060
1061 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1062 PCIEPRAR(idx + 1));
1063 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1064 PCIELAR(idx + 1));
1065 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1066
1067 pci_addr += size;
1068 cpu_addr += size;
1069 idx += 2;
1070
1071 if (idx > MAX_NR_INBOUND_MAPS) {
1072 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1073 return -EINVAL;
1074 }
1075 }
1076 *index = idx;
1077
1078 return 0;
1079}
1080
1081static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
1082 struct device_node *np)
1083{
1084 struct of_pci_range range;
1085 struct of_pci_range_parser parser;
1086 int index = 0;
1087 int err;
1088
1089 if (of_pci_dma_range_parser_init(&parser, np))
1090 return -EINVAL;
1091
1092 /* Get the dma-ranges from DT */
1093 for_each_of_pci_range(&parser, &range) {
1094 u64 end = range.cpu_addr + range.size - 1;
1095
1096 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1097 range.flags, range.cpu_addr, end, range.pci_addr);
1098
1099 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1100 if (err)
1101 return err;
1102 }
1103
1104 return 0;
1105}
1106
1107static const struct of_device_id rcar_pcie_of_match[] = {
1108 { .compatible = "renesas,pcie-r8a7779",
1109 .data = rcar_pcie_phy_init_h1 },
1110 { .compatible = "renesas,pcie-r8a7790",
1111 .data = rcar_pcie_phy_init_gen2 },
1112 { .compatible = "renesas,pcie-r8a7791",
1113 .data = rcar_pcie_phy_init_gen2 },
1114 { .compatible = "renesas,pcie-rcar-gen2",
1115 .data = rcar_pcie_phy_init_gen2 },
1116 { .compatible = "renesas,pcie-r8a7795",
1117 .data = rcar_pcie_phy_init_gen3 },
1118 { .compatible = "renesas,pcie-rcar-gen3",
1119 .data = rcar_pcie_phy_init_gen3 },
1120 {},
1121};
1122
1123static int rcar_pcie_probe(struct platform_device *pdev)
1124{
1125 struct device *dev = &pdev->dev;
1126 struct rcar_pcie *pcie;
1127 u32 data;
1128 int err;
1129 int (*phy_init_fn)(struct rcar_pcie *);
1130 struct pci_host_bridge *bridge;
1131
1132 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1133 if (!bridge)
1134 return -ENOMEM;
1135
1136 pcie = pci_host_bridge_priv(bridge);
1137
1138 pcie->dev = dev;
1139 platform_set_drvdata(pdev, pcie);
1140
1141 err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL);
1142 if (err)
1143 goto err_free_bridge;
1144
1145 pm_runtime_enable(pcie->dev);
1146 err = pm_runtime_get_sync(pcie->dev);
1147 if (err < 0) {
1148 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1149 goto err_pm_disable;
1150 }
1151
1152 err = rcar_pcie_get_resources(pcie);
1153 if (err < 0) {
1154 dev_err(dev, "failed to request resources: %d\n", err);
1155 goto err_pm_put;
1156 }
1157
1158 err = clk_prepare_enable(pcie->bus_clk);
1159 if (err) {
1160 dev_err(dev, "failed to enable bus clock: %d\n", err);
1161 goto err_unmap_msi_irqs;
1162 }
1163
1164 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
1165 if (err)
1166 goto err_clk_disable;
1167
1168 phy_init_fn = of_device_get_match_data(dev);
1169 err = phy_init_fn(pcie);
1170 if (err) {
1171 dev_err(dev, "failed to init PCIe PHY\n");
1172 goto err_clk_disable;
1173 }
1174
1175 /* Failure to get a link might just be that no cards are inserted */
1176 if (rcar_pcie_hw_init(pcie)) {
1177 dev_info(dev, "PCIe link down\n");
1178 err = -ENODEV;
1179 goto err_phy_shutdown;
1180 }
1181
1182 data = rcar_pci_read_reg(pcie, MACSR);
1183 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1184
1185 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1186 err = rcar_pcie_enable_msi(pcie);
1187 if (err < 0) {
1188 dev_err(dev,
1189 "failed to enable MSI support: %d\n",
1190 err);
1191 goto err_phy_shutdown;
1192 }
1193 }
1194
1195 err = rcar_pcie_enable(pcie);
1196 if (err)
1197 goto err_msi_teardown;
1198
1199 return 0;
1200
1201err_msi_teardown:
1202 if (IS_ENABLED(CONFIG_PCI_MSI))
1203 rcar_pcie_teardown_msi(pcie);
1204
1205err_phy_shutdown:
1206 if (pcie->phy) {
1207 phy_power_off(pcie->phy);
1208 phy_exit(pcie->phy);
1209 }
1210
1211err_clk_disable:
1212 clk_disable_unprepare(pcie->bus_clk);
1213
1214err_unmap_msi_irqs:
1215 irq_dispose_mapping(pcie->msi.irq2);
1216 irq_dispose_mapping(pcie->msi.irq1);
1217
1218err_pm_put:
1219 pm_runtime_put(dev);
1220
1221err_pm_disable:
1222 pm_runtime_disable(dev);
1223 pci_free_resource_list(&pcie->resources);
1224
1225err_free_bridge:
1226 pci_free_host_bridge(bridge);
1227
1228 return err;
1229}
1230
1231static int rcar_pcie_resume_noirq(struct device *dev)
1232{
1233 struct rcar_pcie *pcie = dev_get_drvdata(dev);
1234
1235 if (rcar_pci_read_reg(pcie, PMSR) &&
1236 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN))
1237 return 0;
1238
1239 /* Re-establish the PCIe link */
1240 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
1241 return rcar_pcie_wait_for_dl(pcie);
1242}
1243
1244static const struct dev_pm_ops rcar_pcie_pm_ops = {
1245 .resume_noirq = rcar_pcie_resume_noirq,
1246};
1247
1248static struct platform_driver rcar_pcie_driver = {
1249 .driver = {
1250 .name = "rcar-pcie",
1251 .of_match_table = rcar_pcie_of_match,
1252 .pm = &rcar_pcie_pm_ops,
1253 .suppress_bind_attrs = true,
1254 },
1255 .probe = rcar_pcie_probe,
1256};
1257builtin_platform_driver(rcar_pcie_driver);