1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
  4 *
  5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
  6 *
  7 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
  8 */
  9
 10#include <linux/delay.h>
 11#include <linux/device.h>
 12#include <linux/err.h>
 13#include <linux/interrupt.h>
 14#include <linux/irq.h>
 15#include <linux/irqdomain.h>
 16#include <linux/kernel.h>
 17#include <linux/init.h>
 18#include <linux/of_device.h>
 19#include <linux/of_gpio.h>
 20#include <linux/of_pci.h>
 21#include <linux/pci.h>
 22#include <linux/phy/phy.h>
 23#include <linux/platform_device.h>
 24#include <linux/pm_runtime.h>
 25#include <linux/resource.h>
 26#include <linux/types.h>
 27#include <linux/mfd/syscon.h>
 28#include <linux/regmap.h>
 29#include <linux/gpio/consumer.h>
 30
 31#include "../../pci.h"
 32#include "pcie-designware.h"
 33
 34/* PCIe controller wrapper DRA7XX configuration registers */
 35
 36#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN		0x0024
 37#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN		0x0028
 38#define	ERR_SYS						BIT(0)
 39#define	ERR_FATAL					BIT(1)
 40#define	ERR_NONFATAL					BIT(2)
 41#define	ERR_COR						BIT(3)
 42#define	ERR_AXI						BIT(4)
 43#define	ERR_ECRC					BIT(5)
 44#define	PME_TURN_OFF					BIT(8)
 45#define	PME_TO_ACK					BIT(9)
 46#define	PM_PME						BIT(10)
 47#define	LINK_REQ_RST					BIT(11)
 48#define	LINK_UP_EVT					BIT(12)
 49#define	CFG_BME_EVT					BIT(13)
 50#define	CFG_MSE_EVT					BIT(14)
 51#define	INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
 52			ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
 53			LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
 54
 55#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI		0x0034
 56#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI		0x0038
 57#define	INTA						BIT(0)
 58#define	INTB						BIT(1)
 59#define	INTC						BIT(2)
 60#define	INTD						BIT(3)
 61#define	MSI						BIT(4)
 62#define	LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
 63
 64#define	PCIECTRL_TI_CONF_DEVICE_TYPE			0x0100
 65#define	DEVICE_TYPE_EP					0x0
 66#define	DEVICE_TYPE_LEG_EP				0x1
 67#define	DEVICE_TYPE_RC					0x4
 68
 69#define	PCIECTRL_DRA7XX_CONF_DEVICE_CMD			0x0104
 70#define	LTSSM_EN					0x1
 71
 72#define	PCIECTRL_DRA7XX_CONF_PHY_CS			0x010C
 73#define	LINK_UP						BIT(16)
 74#define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF
 75
 76#define EXP_CAP_ID_OFFSET				0x70
 77
 78#define	PCIECTRL_TI_CONF_INTX_ASSERT			0x0124
 79#define	PCIECTRL_TI_CONF_INTX_DEASSERT			0x0128
 80
 81#define	PCIECTRL_TI_CONF_MSI_XMT			0x012c
 82#define MSI_REQ_GRANT					BIT(0)
 83#define MSI_VECTOR_SHIFT				7
 84
 85#define PCIE_1LANE_2LANE_SELECTION			BIT(13)
 86#define PCIE_B1C0_MODE_SEL				BIT(2)
 87#define PCIE_B0_B1_TSYNCEN				BIT(0)
 88
 89struct dra7xx_pcie {
 90	struct dw_pcie		*pci;
 91	void __iomem		*base;		/* DT ti_conf */
 92	int			phy_count;	/* DT phy-names count */
 93	struct phy		**phy;
 94	int			link_gen;
 95	struct irq_domain	*irq_domain;
 96	enum dw_pcie_device_mode mode;
 97};
 98
 99struct dra7xx_pcie_of_data {
100	enum dw_pcie_device_mode mode;
101	u32 b1co_mode_sel_mask;
102};
103
104#define to_dra7xx_pcie(x)	dev_get_drvdata((x)->dev)
105
106static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
107{
108	return readl(pcie->base + offset);
109}
110
111static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
112				      u32 value)
113{
114	writel(value, pcie->base + offset);
115}
116
117static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
118{
119	return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
120}
121
122static int dra7xx_pcie_link_up(struct dw_pcie *pci)
123{
124	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
125	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
126
127	return !!(reg & LINK_UP);
128}
129
130static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
131{
132	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
133	u32 reg;
134
135	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
136	reg &= ~LTSSM_EN;
137	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
138}
139
140static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
141{
142	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
143	struct device *dev = pci->dev;
144	u32 reg;
145	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
146
147	if (dw_pcie_link_up(pci)) {
148		dev_err(dev, "link is already up\n");
149		return 0;
150	}
151
152	if (dra7xx->link_gen == 1) {
153		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
154			     4, &reg);
155		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
156			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
157			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
158			dw_pcie_write(pci->dbi_base + exp_cap_off +
159				      PCI_EXP_LNKCAP, 4, reg);
160		}
161
162		dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
163			     2, &reg);
164		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
165			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
166			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
167			dw_pcie_write(pci->dbi_base + exp_cap_off +
168				      PCI_EXP_LNKCTL2, 2, reg);
169		}
170	}
171
172	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
173	reg |= LTSSM_EN;
174	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
175
176	return 0;
177}
178
179static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
180{
181	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
182			   LEG_EP_INTERRUPTS | MSI);
183
184	dra7xx_pcie_writel(dra7xx,
185			   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
186			   MSI | LEG_EP_INTERRUPTS);
187}
188
189static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
190{
191	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
192			   INTERRUPTS);
193	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
194			   INTERRUPTS);
195}
196
197static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
198{
199	dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
200	dra7xx_pcie_enable_msi_interrupts(dra7xx);
201}
202
203static int dra7xx_pcie_host_init(struct pcie_port *pp)
204{
205	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
206	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
207
208	dw_pcie_setup_rc(pp);
209
210	dra7xx_pcie_establish_link(pci);
211	dw_pcie_wait_for_link(pci);
212	dw_pcie_msi_init(pp);
213	dra7xx_pcie_enable_interrupts(dra7xx);
214
215	return 0;
216}
217
218static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
219	.host_init = dra7xx_pcie_host_init,
220};
221
222static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
223				irq_hw_number_t hwirq)
224{
225	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
226	irq_set_chip_data(irq, domain->host_data);
227
228	return 0;
229}
230
231static const struct irq_domain_ops intx_domain_ops = {
232	.map = dra7xx_pcie_intx_map,
233	.xlate = pci_irqd_intx_xlate,
234};
235
236static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
237{
238	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
239	struct device *dev = pci->dev;
240	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
241	struct device_node *node = dev->of_node;
242	struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
243
244	if (!pcie_intc_node) {
245		dev_err(dev, "No PCIe Intc node found\n");
246		return -ENODEV;
247	}
248
249	dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
250						   &intx_domain_ops, pp);
251	of_node_put(pcie_intc_node);
252	if (!dra7xx->irq_domain) {
253		dev_err(dev, "Failed to get a INTx IRQ domain\n");
254		return -ENODEV;
255	}
256
257	return 0;
258}
259
260static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
261{
262	struct dra7xx_pcie *dra7xx = arg;
263	struct dw_pcie *pci = dra7xx->pci;
264	struct pcie_port *pp = &pci->pp;
265	unsigned long reg;
266	u32 virq, bit;
267
268	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
269
270	switch (reg) {
271	case MSI:
272		dw_handle_msi_irq(pp);
273		break;
274	case INTA:
275	case INTB:
276	case INTC:
277	case INTD:
278		for_each_set_bit(bit, &reg, PCI_NUM_INTX) {
279			virq = irq_find_mapping(dra7xx->irq_domain, bit);
280			if (virq)
281				generic_handle_irq(virq);
282		}
283		break;
284	}
285
286	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
287
288	return IRQ_HANDLED;
289}
290
291static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
292{
293	struct dra7xx_pcie *dra7xx = arg;
294	struct dw_pcie *pci = dra7xx->pci;
295	struct device *dev = pci->dev;
296	struct dw_pcie_ep *ep = &pci->ep;
297	u32 reg;
298
299	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
300
301	if (reg & ERR_SYS)
302		dev_dbg(dev, "System Error\n");
303
304	if (reg & ERR_FATAL)
305		dev_dbg(dev, "Fatal Error\n");
306
307	if (reg & ERR_NONFATAL)
308		dev_dbg(dev, "Non Fatal Error\n");
309
310	if (reg & ERR_COR)
311		dev_dbg(dev, "Correctable Error\n");
312
313	if (reg & ERR_AXI)
314		dev_dbg(dev, "AXI tag lookup fatal Error\n");
315
316	if (reg & ERR_ECRC)
317		dev_dbg(dev, "ECRC Error\n");
318
319	if (reg & PME_TURN_OFF)
320		dev_dbg(dev,
321			"Power Management Event Turn-Off message received\n");
322
323	if (reg & PME_TO_ACK)
324		dev_dbg(dev,
325			"Power Management Turn-Off Ack message received\n");
326
327	if (reg & PM_PME)
328		dev_dbg(dev, "PM Power Management Event message received\n");
329
330	if (reg & LINK_REQ_RST)
331		dev_dbg(dev, "Link Request Reset\n");
332
333	if (reg & LINK_UP_EVT) {
334		if (dra7xx->mode == DW_PCIE_EP_TYPE)
335			dw_pcie_ep_linkup(ep);
336		dev_dbg(dev, "Link-up state change\n");
337	}
338
339	if (reg & CFG_BME_EVT)
340		dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
341
342	if (reg & CFG_MSE_EVT)
343		dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
344
345	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
346
347	return IRQ_HANDLED;
348}
349
350static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
351{
352	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
353	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
354	enum pci_barno bar;
355
356	for (bar = BAR_0; bar <= BAR_5; bar++)
357		dw_pcie_ep_reset_bar(pci, bar);
358
359	dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
360}
361
362static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
363{
364	dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
365	mdelay(1);
366	dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
367}
368
369static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
370				      u8 interrupt_num)
371{
372	u32 reg;
373
374	reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
375	reg |= MSI_REQ_GRANT;
376	dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
377}
378
379static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
380				 enum pci_epc_irq_type type, u16 interrupt_num)
381{
382	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
383	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
384
385	switch (type) {
386	case PCI_EPC_IRQ_LEGACY:
387		dra7xx_pcie_raise_legacy_irq(dra7xx);
388		break;
389	case PCI_EPC_IRQ_MSI:
390		dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
391		break;
392	default:
393		dev_err(pci->dev, "UNKNOWN IRQ type\n");
394	}
395
396	return 0;
397}
398
399static const struct pci_epc_features dra7xx_pcie_epc_features = {
400	.linkup_notifier = true,
401	.msi_capable = true,
402	.msix_capable = false,
403};
404
405static const struct pci_epc_features*
406dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
407{
408	return &dra7xx_pcie_epc_features;
409}
410
411static const struct dw_pcie_ep_ops pcie_ep_ops = {
412	.ep_init = dra7xx_pcie_ep_init,
413	.raise_irq = dra7xx_pcie_raise_irq,
414	.get_features = dra7xx_pcie_get_features,
415};
416
417static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
418				     struct platform_device *pdev)
419{
420	int ret;
421	struct dw_pcie_ep *ep;
422	struct resource *res;
423	struct device *dev = &pdev->dev;
424	struct dw_pcie *pci = dra7xx->pci;
425
426	ep = &pci->ep;
427	ep->ops = &pcie_ep_ops;
428
429	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
430	pci->dbi_base = devm_ioremap_resource(dev, res);
431	if (IS_ERR(pci->dbi_base))
432		return PTR_ERR(pci->dbi_base);
433
434	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
435	pci->dbi_base2 = devm_ioremap_resource(dev, res);
436	if (IS_ERR(pci->dbi_base2))
437		return PTR_ERR(pci->dbi_base2);
438
439	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
440	if (!res)
441		return -EINVAL;
442
443	ep->phys_base = res->start;
444	ep->addr_size = resource_size(res);
445
446	ret = dw_pcie_ep_init(ep);
447	if (ret) {
448		dev_err(dev, "failed to initialize endpoint\n");
449		return ret;
450	}
451
452	return 0;
453}
454
455static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
456				       struct platform_device *pdev)
457{
458	int ret;
459	struct dw_pcie *pci = dra7xx->pci;
460	struct pcie_port *pp = &pci->pp;
461	struct device *dev = pci->dev;
462	struct resource *res;
463
464	pp->irq = platform_get_irq(pdev, 1);
465	if (pp->irq < 0) {
466		dev_err(dev, "missing IRQ resource\n");
467		return pp->irq;
468	}
469
470	ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
471			       IRQF_SHARED | IRQF_NO_THREAD,
472			       "dra7-pcie-msi",	dra7xx);
473	if (ret) {
474		dev_err(dev, "failed to request irq\n");
475		return ret;
476	}
477
478	ret = dra7xx_pcie_init_irq_domain(pp);
479	if (ret < 0)
480		return ret;
481
482	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
483	pci->dbi_base = devm_ioremap_resource(dev, res);
484	if (IS_ERR(pci->dbi_base))
485		return PTR_ERR(pci->dbi_base);
486
487	pp->ops = &dra7xx_pcie_host_ops;
488
489	ret = dw_pcie_host_init(pp);
490	if (ret) {
491		dev_err(dev, "failed to initialize host\n");
492		return ret;
493	}
494
495	return 0;
496}
497
498static const struct dw_pcie_ops dw_pcie_ops = {
499	.cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
500	.start_link = dra7xx_pcie_establish_link,
501	.stop_link = dra7xx_pcie_stop_link,
502	.link_up = dra7xx_pcie_link_up,
503};
504
505static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
506{
507	int phy_count = dra7xx->phy_count;
508
509	while (phy_count--) {
510		phy_power_off(dra7xx->phy[phy_count]);
511		phy_exit(dra7xx->phy[phy_count]);
512	}
513}
514
515static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
516{
517	int phy_count = dra7xx->phy_count;
518	int ret;
519	int i;
520
521	for (i = 0; i < phy_count; i++) {
522		ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
523		if (ret < 0)
524			goto err_phy;
525
526		ret = phy_init(dra7xx->phy[i]);
527		if (ret < 0)
528			goto err_phy;
529
530		ret = phy_power_on(dra7xx->phy[i]);
531		if (ret < 0) {
532			phy_exit(dra7xx->phy[i]);
533			goto err_phy;
534		}
535	}
536
537	return 0;
538
539err_phy:
540	while (--i >= 0) {
541		phy_power_off(dra7xx->phy[i]);
542		phy_exit(dra7xx->phy[i]);
543	}
544
545	return ret;
546}
547
548static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
549	.mode = DW_PCIE_RC_TYPE,
550};
551
552static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
553	.mode = DW_PCIE_EP_TYPE,
554};
555
556static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
557	.b1co_mode_sel_mask = BIT(2),
558	.mode = DW_PCIE_RC_TYPE,
559};
560
561static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
562	.b1co_mode_sel_mask = GENMASK(3, 2),
563	.mode = DW_PCIE_RC_TYPE,
564};
565
566static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
567	.b1co_mode_sel_mask = BIT(2),
568	.mode = DW_PCIE_EP_TYPE,
569};
570
571static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
572	.b1co_mode_sel_mask = GENMASK(3, 2),
573	.mode = DW_PCIE_EP_TYPE,
574};
575
576static const struct of_device_id of_dra7xx_pcie_match[] = {
577	{
578		.compatible = "ti,dra7-pcie",
579		.data = &dra7xx_pcie_rc_of_data,
580	},
581	{
582		.compatible = "ti,dra7-pcie-ep",
583		.data = &dra7xx_pcie_ep_of_data,
584	},
585	{
586		.compatible = "ti,dra746-pcie-rc",
587		.data = &dra746_pcie_rc_of_data,
588	},
589	{
590		.compatible = "ti,dra726-pcie-rc",
591		.data = &dra726_pcie_rc_of_data,
592	},
593	{
594		.compatible = "ti,dra746-pcie-ep",
595		.data = &dra746_pcie_ep_of_data,
596	},
597	{
598		.compatible = "ti,dra726-pcie-ep",
599		.data = &dra726_pcie_ep_of_data,
600	},
601	{},
602};
603
604/*
605 * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
606 * @dra7xx: the dra7xx device where the workaround should be applied
607 *
608 * Access to the PCIe slave port that are not 32-bit aligned will result
609 * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
610 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
611 * 0x3.
612 *
613 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
614 */
615static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
616{
617	int ret;
618	struct device_node *np = dev->of_node;
619	struct of_phandle_args args;
620	struct regmap *regmap;
621
622	regmap = syscon_regmap_lookup_by_phandle(np,
623						 "ti,syscon-unaligned-access");
624	if (IS_ERR(regmap)) {
625		dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
626		return -EINVAL;
627	}
628
629	ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
630					       2, 0, &args);
631	if (ret) {
632		dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
633		return ret;
634	}
635
636	ret = regmap_update_bits(regmap, args.args[0], args.args[1],
637				 args.args[1]);
638	if (ret)
639		dev_err(dev, "failed to enable unaligned access\n");
640
641	of_node_put(args.np);
642
643	return ret;
644}
645
646static int dra7xx_pcie_configure_two_lane(struct device *dev,
647					  u32 b1co_mode_sel_mask)
648{
649	struct device_node *np = dev->of_node;
650	struct regmap *pcie_syscon;
651	unsigned int pcie_reg;
652	u32 mask;
653	u32 val;
654
655	pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
656	if (IS_ERR(pcie_syscon)) {
657		dev_err(dev, "unable to get ti,syscon-lane-sel\n");
658		return -EINVAL;
659	}
660
661	if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
662				       &pcie_reg)) {
663		dev_err(dev, "couldn't get lane selection reg offset\n");
664		return -EINVAL;
665	}
666
667	mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
668	val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
669	regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
670
671	return 0;
672}
673
674static int __init dra7xx_pcie_probe(struct platform_device *pdev)
675{
676	u32 reg;
677	int ret;
678	int irq;
679	int i;
680	int phy_count;
681	struct phy **phy;
682	struct device_link **link;
683	void __iomem *base;
684	struct resource *res;
685	struct dw_pcie *pci;
686	struct dra7xx_pcie *dra7xx;
687	struct device *dev = &pdev->dev;
688	struct device_node *np = dev->of_node;
689	char name[10];
690	struct gpio_desc *reset;
691	const struct of_device_id *match;
692	const struct dra7xx_pcie_of_data *data;
693	enum dw_pcie_device_mode mode;
694	u32 b1co_mode_sel_mask;
695
696	match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
697	if (!match)
698		return -EINVAL;
699
700	data = (struct dra7xx_pcie_of_data *)match->data;
701	mode = (enum dw_pcie_device_mode)data->mode;
702	b1co_mode_sel_mask = data->b1co_mode_sel_mask;
703
704	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
705	if (!dra7xx)
706		return -ENOMEM;
707
708	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
709	if (!pci)
710		return -ENOMEM;
711
712	pci->dev = dev;
713	pci->ops = &dw_pcie_ops;
714
715	irq = platform_get_irq(pdev, 0);
716	if (irq < 0) {
717		dev_err(dev, "missing IRQ resource: %d\n", irq);
718		return irq;
719	}
720
721	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
722	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
723	if (!base)
724		return -ENOMEM;
725
726	phy_count = of_property_count_strings(np, "phy-names");
727	if (phy_count < 0) {
728		dev_err(dev, "unable to find the strings\n");
729		return phy_count;
730	}
731
732	phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
733	if (!phy)
734		return -ENOMEM;
735
736	link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
737	if (!link)
738		return -ENOMEM;
739
740	for (i = 0; i < phy_count; i++) {
741		snprintf(name, sizeof(name), "pcie-phy%d", i);
742		phy[i] = devm_phy_get(dev, name);
743		if (IS_ERR(phy[i]))
744			return PTR_ERR(phy[i]);
745
746		link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
747		if (!link[i]) {
748			ret = -EINVAL;
749			goto err_link;
750		}
751	}
752
753	dra7xx->base = base;
754	dra7xx->phy = phy;
755	dra7xx->pci = pci;
756	dra7xx->phy_count = phy_count;
757
758	if (phy_count == 2) {
759		ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
760		if (ret < 0)
761			dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
762	}
763
764	ret = dra7xx_pcie_enable_phy(dra7xx);
765	if (ret) {
766		dev_err(dev, "failed to enable phy\n");
767		return ret;
768	}
769
770	platform_set_drvdata(pdev, dra7xx);
771
772	pm_runtime_enable(dev);
773	ret = pm_runtime_get_sync(dev);
774	if (ret < 0) {
775		dev_err(dev, "pm_runtime_get_sync failed\n");
776		goto err_get_sync;
777	}
778
779	reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
780	if (IS_ERR(reset)) {
781		ret = PTR_ERR(reset);
782		dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
783		goto err_gpio;
784	}
785
786	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
787	reg &= ~LTSSM_EN;
788	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
789
790	dra7xx->link_gen = of_pci_get_max_link_speed(np);
791	if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
792		dra7xx->link_gen = 2;
793
794	switch (mode) {
795	case DW_PCIE_RC_TYPE:
796		if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
797			ret = -ENODEV;
798			goto err_gpio;
799		}
800
801		dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
802				   DEVICE_TYPE_RC);
803
804		ret = dra7xx_pcie_unaligned_memaccess(dev);
805		if (ret)
806			dev_err(dev, "WA for Errata i870 not applied\n");
807
808		ret = dra7xx_add_pcie_port(dra7xx, pdev);
809		if (ret < 0)
810			goto err_gpio;
811		break;
812	case DW_PCIE_EP_TYPE:
813		if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
814			ret = -ENODEV;
815			goto err_gpio;
816		}
817
818		dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
819				   DEVICE_TYPE_EP);
820
821		ret = dra7xx_pcie_unaligned_memaccess(dev);
822		if (ret)
823			goto err_gpio;
824
825		ret = dra7xx_add_pcie_ep(dra7xx, pdev);
826		if (ret < 0)
827			goto err_gpio;
828		break;
829	default:
830		dev_err(dev, "INVALID device type %d\n", mode);
831	}
832	dra7xx->mode = mode;
833
834	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
835			       IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
836	if (ret) {
837		dev_err(dev, "failed to request irq\n");
838		goto err_gpio;
839	}
840
841	return 0;
842
843err_gpio:
844	pm_runtime_put(dev);
845
846err_get_sync:
847	pm_runtime_disable(dev);
848	dra7xx_pcie_disable_phy(dra7xx);
849
850err_link:
851	while (--i >= 0)
852		device_link_del(link[i]);
853
854	return ret;
855}
856
857#ifdef CONFIG_PM_SLEEP
858static int dra7xx_pcie_suspend(struct device *dev)
859{
860	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
861	struct dw_pcie *pci = dra7xx->pci;
862	u32 val;
863
864	if (dra7xx->mode != DW_PCIE_RC_TYPE)
865		return 0;
866
867	/* clear MSE */
868	val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
869	val &= ~PCI_COMMAND_MEMORY;
870	dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
871
872	return 0;
873}
874
875static int dra7xx_pcie_resume(struct device *dev)
876{
877	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
878	struct dw_pcie *pci = dra7xx->pci;
879	u32 val;
880
881	if (dra7xx->mode != DW_PCIE_RC_TYPE)
882		return 0;
883
884	/* set MSE */
885	val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
886	val |= PCI_COMMAND_MEMORY;
887	dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
888
889	return 0;
890}
891
892static int dra7xx_pcie_suspend_noirq(struct device *dev)
893{
894	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
895
896	dra7xx_pcie_disable_phy(dra7xx);
897
898	return 0;
899}
900
901static int dra7xx_pcie_resume_noirq(struct device *dev)
902{
903	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
904	int ret;
905
906	ret = dra7xx_pcie_enable_phy(dra7xx);
907	if (ret) {
908		dev_err(dev, "failed to enable phy\n");
909		return ret;
910	}
911
912	return 0;
913}
914#endif
915
916static void dra7xx_pcie_shutdown(struct platform_device *pdev)
917{
918	struct device *dev = &pdev->dev;
919	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
920	int ret;
921
922	dra7xx_pcie_stop_link(dra7xx->pci);
923
924	ret = pm_runtime_put_sync(dev);
925	if (ret < 0)
926		dev_dbg(dev, "pm_runtime_put_sync failed\n");
927
928	pm_runtime_disable(dev);
929	dra7xx_pcie_disable_phy(dra7xx);
930}
931
932static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
933	SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
934	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
935				      dra7xx_pcie_resume_noirq)
936};
937
938static struct platform_driver dra7xx_pcie_driver = {
939	.driver = {
940		.name	= "dra7-pcie",
941		.of_match_table = of_dra7xx_pcie_match,
942		.suppress_bind_attrs = true,
943		.pm	= &dra7xx_pcie_pm_ops,
944	},
945	.shutdown = dra7xx_pcie_shutdown,
946};
947builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);