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1/* linux/drivers/mfd/sm501.c
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * SM501 MFD driver
12*/
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/list.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/pci.h>
22#include <linux/i2c-gpio.h>
23#include <linux/slab.h>
24
25#include <linux/sm501.h>
26#include <linux/sm501-regs.h>
27#include <linux/serial_8250.h>
28
29#include <linux/io.h>
30
31struct sm501_device {
32 struct list_head list;
33 struct platform_device pdev;
34};
35
36struct sm501_gpio;
37
38#ifdef CONFIG_MFD_SM501_GPIO
39#include <linux/gpio.h>
40
41struct sm501_gpio_chip {
42 struct gpio_chip gpio;
43 struct sm501_gpio *ourgpio; /* to get back to parent. */
44 void __iomem *regbase;
45 void __iomem *control; /* address of control reg. */
46};
47
48struct sm501_gpio {
49 struct sm501_gpio_chip low;
50 struct sm501_gpio_chip high;
51 spinlock_t lock;
52
53 unsigned int registered : 1;
54 void __iomem *regs;
55 struct resource *regs_res;
56};
57#else
58struct sm501_gpio {
59 /* no gpio support, empty definition for sm501_devdata. */
60};
61#endif
62
63struct sm501_devdata {
64 spinlock_t reg_lock;
65 struct mutex clock_lock;
66 struct list_head devices;
67 struct sm501_gpio gpio;
68
69 struct device *dev;
70 struct resource *io_res;
71 struct resource *mem_res;
72 struct resource *regs_claim;
73 struct sm501_platdata *platdata;
74
75
76 unsigned int in_suspend;
77 unsigned long pm_misc;
78
79 int unit_power[20];
80 unsigned int pdev_id;
81 unsigned int irq;
82 void __iomem *regs;
83 unsigned int rev;
84};
85
86
87#define MHZ (1000 * 1000)
88
89#ifdef DEBUG
90static const unsigned int div_tab[] = {
91 [0] = 1,
92 [1] = 2,
93 [2] = 4,
94 [3] = 8,
95 [4] = 16,
96 [5] = 32,
97 [6] = 64,
98 [7] = 128,
99 [8] = 3,
100 [9] = 6,
101 [10] = 12,
102 [11] = 24,
103 [12] = 48,
104 [13] = 96,
105 [14] = 192,
106 [15] = 384,
107 [16] = 5,
108 [17] = 10,
109 [18] = 20,
110 [19] = 40,
111 [20] = 80,
112 [21] = 160,
113 [22] = 320,
114 [23] = 604,
115};
116
117static unsigned long decode_div(unsigned long pll2, unsigned long val,
118 unsigned int lshft, unsigned int selbit,
119 unsigned long mask)
120{
121 if (val & selbit)
122 pll2 = 288 * MHZ;
123
124 return pll2 / div_tab[(val >> lshft) & mask];
125}
126
127#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
128
129/* sm501_dump_clk
130 *
131 * Print out the current clock configuration for the device
132*/
133
134static void sm501_dump_clk(struct sm501_devdata *sm)
135{
136 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
137 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
138 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
139 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
140 unsigned long sdclk0, sdclk1;
141 unsigned long pll2 = 0;
142
143 switch (misct & 0x30) {
144 case 0x00:
145 pll2 = 336 * MHZ;
146 break;
147 case 0x10:
148 pll2 = 288 * MHZ;
149 break;
150 case 0x20:
151 pll2 = 240 * MHZ;
152 break;
153 case 0x30:
154 pll2 = 192 * MHZ;
155 break;
156 }
157
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
159 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
160
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
162 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
163
164 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
165 misct, pm0, pm1);
166
167 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
168 fmt_freq(pll2), sdclk0, sdclk1);
169
170 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
171
172 dev_dbg(sm->dev, "PM0[%c]: "
173 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
174 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
175 (pmc & 3 ) == 0 ? '*' : '-',
176 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
177 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
178 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
179 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
180
181 dev_dbg(sm->dev, "PM1[%c]: "
182 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
183 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
184 (pmc & 3 ) == 1 ? '*' : '-',
185 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
186 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
187 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
188 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
189}
190
191static void sm501_dump_regs(struct sm501_devdata *sm)
192{
193 void __iomem *regs = sm->regs;
194
195 dev_info(sm->dev, "System Control %08x\n",
196 smc501_readl(regs + SM501_SYSTEM_CONTROL));
197 dev_info(sm->dev, "Misc Control %08x\n",
198 smc501_readl(regs + SM501_MISC_CONTROL));
199 dev_info(sm->dev, "GPIO Control Low %08x\n",
200 smc501_readl(regs + SM501_GPIO31_0_CONTROL));
201 dev_info(sm->dev, "GPIO Control Hi %08x\n",
202 smc501_readl(regs + SM501_GPIO63_32_CONTROL));
203 dev_info(sm->dev, "DRAM Control %08x\n",
204 smc501_readl(regs + SM501_DRAM_CONTROL));
205 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
206 smc501_readl(regs + SM501_ARBTRTN_CONTROL));
207 dev_info(sm->dev, "Misc Timing %08x\n",
208 smc501_readl(regs + SM501_MISC_TIMING));
209}
210
211static void sm501_dump_gate(struct sm501_devdata *sm)
212{
213 dev_info(sm->dev, "CurrentGate %08x\n",
214 smc501_readl(sm->regs + SM501_CURRENT_GATE));
215 dev_info(sm->dev, "CurrentClock %08x\n",
216 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
217 dev_info(sm->dev, "PowerModeControl %08x\n",
218 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
219}
220
221#else
222static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
223static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
224static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
225#endif
226
227/* sm501_sync_regs
228 *
229 * ensure the
230*/
231
232static void sm501_sync_regs(struct sm501_devdata *sm)
233{
234 smc501_readl(sm->regs);
235}
236
237static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
238{
239 /* during suspend/resume, we are currently not allowed to sleep,
240 * so change to using mdelay() instead of msleep() if we
241 * are in one of these paths */
242
243 if (sm->in_suspend)
244 mdelay(delay);
245 else
246 msleep(delay);
247}
248
249/* sm501_misc_control
250 *
251 * alters the miscellaneous control parameters
252*/
253
254int sm501_misc_control(struct device *dev,
255 unsigned long set, unsigned long clear)
256{
257 struct sm501_devdata *sm = dev_get_drvdata(dev);
258 unsigned long misc;
259 unsigned long save;
260 unsigned long to;
261
262 spin_lock_irqsave(&sm->reg_lock, save);
263
264 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
265 to = (misc & ~clear) | set;
266
267 if (to != misc) {
268 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
269 sm501_sync_regs(sm);
270
271 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
272 }
273
274 spin_unlock_irqrestore(&sm->reg_lock, save);
275 return to;
276}
277
278EXPORT_SYMBOL_GPL(sm501_misc_control);
279
280/* sm501_modify_reg
281 *
282 * Modify a register in the SM501 which may be shared with other
283 * drivers.
284*/
285
286unsigned long sm501_modify_reg(struct device *dev,
287 unsigned long reg,
288 unsigned long set,
289 unsigned long clear)
290{
291 struct sm501_devdata *sm = dev_get_drvdata(dev);
292 unsigned long data;
293 unsigned long save;
294
295 spin_lock_irqsave(&sm->reg_lock, save);
296
297 data = smc501_readl(sm->regs + reg);
298 data |= set;
299 data &= ~clear;
300
301 smc501_writel(data, sm->regs + reg);
302 sm501_sync_regs(sm);
303
304 spin_unlock_irqrestore(&sm->reg_lock, save);
305
306 return data;
307}
308
309EXPORT_SYMBOL_GPL(sm501_modify_reg);
310
311/* sm501_unit_power
312 *
313 * alters the power active gate to set specific units on or off
314 */
315
316int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
317{
318 struct sm501_devdata *sm = dev_get_drvdata(dev);
319 unsigned long mode;
320 unsigned long gate;
321 unsigned long clock;
322
323 mutex_lock(&sm->clock_lock);
324
325 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
326 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
327 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
328
329 mode &= 3; /* get current power mode */
330
331 if (unit >= ARRAY_SIZE(sm->unit_power)) {
332 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
333 goto already;
334 }
335
336 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
337 sm->unit_power[unit], to);
338
339 if (to == 0 && sm->unit_power[unit] == 0) {
340 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
341 goto already;
342 }
343
344 sm->unit_power[unit] += to ? 1 : -1;
345 to = sm->unit_power[unit] ? 1 : 0;
346
347 if (to) {
348 if (gate & (1 << unit))
349 goto already;
350 gate |= (1 << unit);
351 } else {
352 if (!(gate & (1 << unit)))
353 goto already;
354 gate &= ~(1 << unit);
355 }
356
357 switch (mode) {
358 case 1:
359 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
360 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
361 mode = 0;
362 break;
363 case 2:
364 case 0:
365 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
366 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
367 mode = 1;
368 break;
369
370 default:
371 gate = -1;
372 goto already;
373 }
374
375 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
376 sm501_sync_regs(sm);
377
378 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
379 gate, clock, mode);
380
381 sm501_mdelay(sm, 16);
382
383 already:
384 mutex_unlock(&sm->clock_lock);
385 return gate;
386}
387
388EXPORT_SYMBOL_GPL(sm501_unit_power);
389
390
391/* Perform a rounded division. */
392static long sm501fb_round_div(long num, long denom)
393{
394 /* n / d + 1 / 2 = (2n + d) / 2d */
395 return (2 * num + denom) / (2 * denom);
396}
397
398/* clock value structure. */
399struct sm501_clock {
400 unsigned long mclk;
401 int divider;
402 int shift;
403 unsigned int m, n, k;
404};
405
406/* sm501_calc_clock
407 *
408 * Calculates the nearest discrete clock frequency that
409 * can be achieved with the specified input clock.
410 * the maximum divisor is 3 or 5
411 */
412
413static int sm501_calc_clock(unsigned long freq,
414 struct sm501_clock *clock,
415 int max_div,
416 unsigned long mclk,
417 long *best_diff)
418{
419 int ret = 0;
420 int divider;
421 int shift;
422 long diff;
423
424 /* try dividers 1 and 3 for CRT and for panel,
425 try divider 5 for panel only.*/
426
427 for (divider = 1; divider <= max_div; divider += 2) {
428 /* try all 8 shift values.*/
429 for (shift = 0; shift < 8; shift++) {
430 /* Calculate difference to requested clock */
431 diff = sm501fb_round_div(mclk, divider << shift) - freq;
432 if (diff < 0)
433 diff = -diff;
434
435 /* If it is less than the current, use it */
436 if (diff < *best_diff) {
437 *best_diff = diff;
438
439 clock->mclk = mclk;
440 clock->divider = divider;
441 clock->shift = shift;
442 ret = 1;
443 }
444 }
445 }
446
447 return ret;
448}
449
450/* sm501_calc_pll
451 *
452 * Calculates the nearest discrete clock frequency that can be
453 * achieved using the programmable PLL.
454 * the maximum divisor is 3 or 5
455 */
456
457static unsigned long sm501_calc_pll(unsigned long freq,
458 struct sm501_clock *clock,
459 int max_div)
460{
461 unsigned long mclk;
462 unsigned int m, n, k;
463 long best_diff = 999999999;
464
465 /*
466 * The SM502 datasheet doesn't specify the min/max values for M and N.
467 * N = 1 at least doesn't work in practice.
468 */
469 for (m = 2; m <= 255; m++) {
470 for (n = 2; n <= 127; n++) {
471 for (k = 0; k <= 1; k++) {
472 mclk = (24000000UL * m / n) >> k;
473
474 if (sm501_calc_clock(freq, clock, max_div,
475 mclk, &best_diff)) {
476 clock->m = m;
477 clock->n = n;
478 clock->k = k;
479 }
480 }
481 }
482 }
483
484 /* Return best clock. */
485 return clock->mclk / (clock->divider << clock->shift);
486}
487
488/* sm501_select_clock
489 *
490 * Calculates the nearest discrete clock frequency that can be
491 * achieved using the 288MHz and 336MHz PLLs.
492 * the maximum divisor is 3 or 5
493 */
494
495static unsigned long sm501_select_clock(unsigned long freq,
496 struct sm501_clock *clock,
497 int max_div)
498{
499 unsigned long mclk;
500 long best_diff = 999999999;
501
502 /* Try 288MHz and 336MHz clocks. */
503 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
504 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
505 }
506
507 /* Return best clock. */
508 return clock->mclk / (clock->divider << clock->shift);
509}
510
511/* sm501_set_clock
512 *
513 * set one of the four clock sources to the closest available frequency to
514 * the one specified
515*/
516
517unsigned long sm501_set_clock(struct device *dev,
518 int clksrc,
519 unsigned long req_freq)
520{
521 struct sm501_devdata *sm = dev_get_drvdata(dev);
522 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
523 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
524 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
525 unsigned char reg;
526 unsigned int pll_reg = 0;
527 unsigned long sm501_freq; /* the actual frequency achieved */
528
529 struct sm501_clock to;
530
531 /* find achivable discrete frequency and setup register value
532 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
533 * has an extra bit for the divider */
534
535 switch (clksrc) {
536 case SM501_CLOCK_P2XCLK:
537 /* This clock is divided in half so to achieve the
538 * requested frequency the value must be multiplied by
539 * 2. This clock also has an additional pre divisor */
540
541 if (sm->rev >= 0xC0) {
542 /* SM502 -> use the programmable PLL */
543 sm501_freq = (sm501_calc_pll(2 * req_freq,
544 &to, 5) / 2);
545 reg = to.shift & 0x07;/* bottom 3 bits are shift */
546 if (to.divider == 3)
547 reg |= 0x08; /* /3 divider required */
548 else if (to.divider == 5)
549 reg |= 0x10; /* /5 divider required */
550 reg |= 0x40; /* select the programmable PLL */
551 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
552 } else {
553 sm501_freq = (sm501_select_clock(2 * req_freq,
554 &to, 5) / 2);
555 reg = to.shift & 0x07;/* bottom 3 bits are shift */
556 if (to.divider == 3)
557 reg |= 0x08; /* /3 divider required */
558 else if (to.divider == 5)
559 reg |= 0x10; /* /5 divider required */
560 if (to.mclk != 288000000)
561 reg |= 0x20; /* which mclk pll is source */
562 }
563 break;
564
565 case SM501_CLOCK_V2XCLK:
566 /* This clock is divided in half so to achieve the
567 * requested frequency the value must be multiplied by 2. */
568
569 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
570 reg=to.shift & 0x07; /* bottom 3 bits are shift */
571 if (to.divider == 3)
572 reg |= 0x08; /* /3 divider required */
573 if (to.mclk != 288000000)
574 reg |= 0x10; /* which mclk pll is source */
575 break;
576
577 case SM501_CLOCK_MCLK:
578 case SM501_CLOCK_M1XCLK:
579 /* These clocks are the same and not further divided */
580
581 sm501_freq = sm501_select_clock( req_freq, &to, 3);
582 reg=to.shift & 0x07; /* bottom 3 bits are shift */
583 if (to.divider == 3)
584 reg |= 0x08; /* /3 divider required */
585 if (to.mclk != 288000000)
586 reg |= 0x10; /* which mclk pll is source */
587 break;
588
589 default:
590 return 0; /* this is bad */
591 }
592
593 mutex_lock(&sm->clock_lock);
594
595 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
596 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
597 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
598
599 clock = clock & ~(0xFF << clksrc);
600 clock |= reg<<clksrc;
601
602 mode &= 3; /* find current mode */
603
604 switch (mode) {
605 case 1:
606 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
607 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
608 mode = 0;
609 break;
610 case 2:
611 case 0:
612 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
613 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
614 mode = 1;
615 break;
616
617 default:
618 mutex_unlock(&sm->clock_lock);
619 return -1;
620 }
621
622 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
623
624 if (pll_reg)
625 smc501_writel(pll_reg,
626 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
627
628 sm501_sync_regs(sm);
629
630 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
631 gate, clock, mode);
632
633 sm501_mdelay(sm, 16);
634 mutex_unlock(&sm->clock_lock);
635
636 sm501_dump_clk(sm);
637
638 return sm501_freq;
639}
640
641EXPORT_SYMBOL_GPL(sm501_set_clock);
642
643/* sm501_find_clock
644 *
645 * finds the closest available frequency for a given clock
646*/
647
648unsigned long sm501_find_clock(struct device *dev,
649 int clksrc,
650 unsigned long req_freq)
651{
652 struct sm501_devdata *sm = dev_get_drvdata(dev);
653 unsigned long sm501_freq; /* the frequency achieveable by the 501 */
654 struct sm501_clock to;
655
656 switch (clksrc) {
657 case SM501_CLOCK_P2XCLK:
658 if (sm->rev >= 0xC0) {
659 /* SM502 -> use the programmable PLL */
660 sm501_freq = (sm501_calc_pll(2 * req_freq,
661 &to, 5) / 2);
662 } else {
663 sm501_freq = (sm501_select_clock(2 * req_freq,
664 &to, 5) / 2);
665 }
666 break;
667
668 case SM501_CLOCK_V2XCLK:
669 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
670 break;
671
672 case SM501_CLOCK_MCLK:
673 case SM501_CLOCK_M1XCLK:
674 sm501_freq = sm501_select_clock(req_freq, &to, 3);
675 break;
676
677 default:
678 sm501_freq = 0; /* error */
679 }
680
681 return sm501_freq;
682}
683
684EXPORT_SYMBOL_GPL(sm501_find_clock);
685
686static struct sm501_device *to_sm_device(struct platform_device *pdev)
687{
688 return container_of(pdev, struct sm501_device, pdev);
689}
690
691/* sm501_device_release
692 *
693 * A release function for the platform devices we create to allow us to
694 * free any items we allocated
695*/
696
697static void sm501_device_release(struct device *dev)
698{
699 kfree(to_sm_device(to_platform_device(dev)));
700}
701
702/* sm501_create_subdev
703 *
704 * Create a skeleton platform device with resources for passing to a
705 * sub-driver
706*/
707
708static struct platform_device *
709sm501_create_subdev(struct sm501_devdata *sm, char *name,
710 unsigned int res_count, unsigned int platform_data_size)
711{
712 struct sm501_device *smdev;
713
714 smdev = kzalloc(sizeof(struct sm501_device) +
715 (sizeof(struct resource) * res_count) +
716 platform_data_size, GFP_KERNEL);
717 if (!smdev)
718 return NULL;
719
720 smdev->pdev.dev.release = sm501_device_release;
721
722 smdev->pdev.name = name;
723 smdev->pdev.id = sm->pdev_id;
724 smdev->pdev.dev.parent = sm->dev;
725
726 if (res_count) {
727 smdev->pdev.resource = (struct resource *)(smdev+1);
728 smdev->pdev.num_resources = res_count;
729 }
730 if (platform_data_size)
731 smdev->pdev.dev.platform_data = (void *)(smdev+1);
732
733 return &smdev->pdev;
734}
735
736/* sm501_register_device
737 *
738 * Register a platform device created with sm501_create_subdev()
739*/
740
741static int sm501_register_device(struct sm501_devdata *sm,
742 struct platform_device *pdev)
743{
744 struct sm501_device *smdev = to_sm_device(pdev);
745 int ptr;
746 int ret;
747
748 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
749 printk(KERN_DEBUG "%s[%d] %pR\n",
750 pdev->name, ptr, &pdev->resource[ptr]);
751 }
752
753 ret = platform_device_register(pdev);
754
755 if (ret >= 0) {
756 dev_dbg(sm->dev, "registered %s\n", pdev->name);
757 list_add_tail(&smdev->list, &sm->devices);
758 } else
759 dev_err(sm->dev, "error registering %s (%d)\n",
760 pdev->name, ret);
761
762 return ret;
763}
764
765/* sm501_create_subio
766 *
767 * Fill in an IO resource for a sub device
768*/
769
770static void sm501_create_subio(struct sm501_devdata *sm,
771 struct resource *res,
772 resource_size_t offs,
773 resource_size_t size)
774{
775 res->flags = IORESOURCE_MEM;
776 res->parent = sm->io_res;
777 res->start = sm->io_res->start + offs;
778 res->end = res->start + size - 1;
779}
780
781/* sm501_create_mem
782 *
783 * Fill in an MEM resource for a sub device
784*/
785
786static void sm501_create_mem(struct sm501_devdata *sm,
787 struct resource *res,
788 resource_size_t *offs,
789 resource_size_t size)
790{
791 *offs -= size; /* adjust memory size */
792
793 res->flags = IORESOURCE_MEM;
794 res->parent = sm->mem_res;
795 res->start = sm->mem_res->start + *offs;
796 res->end = res->start + size - 1;
797}
798
799/* sm501_create_irq
800 *
801 * Fill in an IRQ resource for a sub device
802*/
803
804static void sm501_create_irq(struct sm501_devdata *sm,
805 struct resource *res)
806{
807 res->flags = IORESOURCE_IRQ;
808 res->parent = NULL;
809 res->start = res->end = sm->irq;
810}
811
812static int sm501_register_usbhost(struct sm501_devdata *sm,
813 resource_size_t *mem_avail)
814{
815 struct platform_device *pdev;
816
817 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
818 if (!pdev)
819 return -ENOMEM;
820
821 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
822 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
823 sm501_create_irq(sm, &pdev->resource[2]);
824
825 return sm501_register_device(sm, pdev);
826}
827
828static void sm501_setup_uart_data(struct sm501_devdata *sm,
829 struct plat_serial8250_port *uart_data,
830 unsigned int offset)
831{
832 uart_data->membase = sm->regs + offset;
833 uart_data->mapbase = sm->io_res->start + offset;
834 uart_data->iotype = UPIO_MEM;
835 uart_data->irq = sm->irq;
836 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
837 uart_data->regshift = 2;
838 uart_data->uartclk = (9600 * 16);
839}
840
841static int sm501_register_uart(struct sm501_devdata *sm, int devices)
842{
843 struct platform_device *pdev;
844 struct plat_serial8250_port *uart_data;
845
846 pdev = sm501_create_subdev(sm, "serial8250", 0,
847 sizeof(struct plat_serial8250_port) * 3);
848 if (!pdev)
849 return -ENOMEM;
850
851 uart_data = pdev->dev.platform_data;
852
853 if (devices & SM501_USE_UART0) {
854 sm501_setup_uart_data(sm, uart_data++, 0x30000);
855 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
856 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
857 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
858 }
859 if (devices & SM501_USE_UART1) {
860 sm501_setup_uart_data(sm, uart_data++, 0x30020);
861 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
862 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
863 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
864 }
865
866 pdev->id = PLAT8250_DEV_SM501;
867
868 return sm501_register_device(sm, pdev);
869}
870
871static int sm501_register_display(struct sm501_devdata *sm,
872 resource_size_t *mem_avail)
873{
874 struct platform_device *pdev;
875
876 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
877 if (!pdev)
878 return -ENOMEM;
879
880 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
881 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
882 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
883 sm501_create_irq(sm, &pdev->resource[3]);
884
885 return sm501_register_device(sm, pdev);
886}
887
888#ifdef CONFIG_MFD_SM501_GPIO
889
890static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
891{
892 return container_of(gc, struct sm501_gpio_chip, gpio);
893}
894
895static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
896{
897 return container_of(gpio, struct sm501_devdata, gpio);
898}
899
900static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
901
902{
903 struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
904 unsigned long result;
905
906 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
907 result >>= offset;
908
909 return result & 1UL;
910}
911
912static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
913 unsigned long bit)
914{
915 unsigned long ctrl;
916
917 /* check and modify if this pin is not set as gpio. */
918
919 if (smc501_readl(smchip->control) & bit) {
920 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
921 "changing mode of gpio, bit %08lx\n", bit);
922
923 ctrl = smc501_readl(smchip->control);
924 ctrl &= ~bit;
925 smc501_writel(ctrl, smchip->control);
926
927 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
928 }
929}
930
931static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
932
933{
934 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
935 struct sm501_gpio *smgpio = smchip->ourgpio;
936 unsigned long bit = 1 << offset;
937 void __iomem *regs = smchip->regbase;
938 unsigned long save;
939 unsigned long val;
940
941 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
942 __func__, chip, offset);
943
944 spin_lock_irqsave(&smgpio->lock, save);
945
946 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
947 if (value)
948 val |= bit;
949 smc501_writel(val, regs);
950
951 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
952 sm501_gpio_ensure_gpio(smchip, bit);
953
954 spin_unlock_irqrestore(&smgpio->lock, save);
955}
956
957static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
958{
959 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
960 struct sm501_gpio *smgpio = smchip->ourgpio;
961 void __iomem *regs = smchip->regbase;
962 unsigned long bit = 1 << offset;
963 unsigned long save;
964 unsigned long ddr;
965
966 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
967 __func__, chip, offset);
968
969 spin_lock_irqsave(&smgpio->lock, save);
970
971 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
972 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
973
974 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
975 sm501_gpio_ensure_gpio(smchip, bit);
976
977 spin_unlock_irqrestore(&smgpio->lock, save);
978
979 return 0;
980}
981
982static int sm501_gpio_output(struct gpio_chip *chip,
983 unsigned offset, int value)
984{
985 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
986 struct sm501_gpio *smgpio = smchip->ourgpio;
987 unsigned long bit = 1 << offset;
988 void __iomem *regs = smchip->regbase;
989 unsigned long save;
990 unsigned long val;
991 unsigned long ddr;
992
993 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
994 __func__, chip, offset, value);
995
996 spin_lock_irqsave(&smgpio->lock, save);
997
998 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
999 if (value)
1000 val |= bit;
1001 else
1002 val &= ~bit;
1003 smc501_writel(val, regs);
1004
1005 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
1006 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
1007
1008 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1009 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
1010
1011 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1012 spin_unlock_irqrestore(&smgpio->lock, save);
1013
1014 return 0;
1015}
1016
1017static struct gpio_chip gpio_chip_template = {
1018 .ngpio = 32,
1019 .direction_input = sm501_gpio_input,
1020 .direction_output = sm501_gpio_output,
1021 .set = sm501_gpio_set,
1022 .get = sm501_gpio_get,
1023};
1024
1025static int __devinit sm501_gpio_register_chip(struct sm501_devdata *sm,
1026 struct sm501_gpio *gpio,
1027 struct sm501_gpio_chip *chip)
1028{
1029 struct sm501_platdata *pdata = sm->platdata;
1030 struct gpio_chip *gchip = &chip->gpio;
1031 int base = pdata->gpio_base;
1032
1033 chip->gpio = gpio_chip_template;
1034
1035 if (chip == &gpio->high) {
1036 if (base > 0)
1037 base += 32;
1038 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1039 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1040 gchip->label = "SM501-HIGH";
1041 } else {
1042 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1043 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1044 gchip->label = "SM501-LOW";
1045 }
1046
1047 gchip->base = base;
1048 chip->ourgpio = gpio;
1049
1050 return gpiochip_add(gchip);
1051}
1052
1053static int __devinit sm501_register_gpio(struct sm501_devdata *sm)
1054{
1055 struct sm501_gpio *gpio = &sm->gpio;
1056 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1057 int ret;
1058 int tmp;
1059
1060 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1061 (unsigned long long)iobase);
1062
1063 spin_lock_init(&gpio->lock);
1064
1065 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1066 if (gpio->regs_res == NULL) {
1067 dev_err(sm->dev, "gpio: failed to request region\n");
1068 return -ENXIO;
1069 }
1070
1071 gpio->regs = ioremap(iobase, 0x20);
1072 if (gpio->regs == NULL) {
1073 dev_err(sm->dev, "gpio: failed to remap registers\n");
1074 ret = -ENXIO;
1075 goto err_claimed;
1076 }
1077
1078 /* Register both our chips. */
1079
1080 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1081 if (ret) {
1082 dev_err(sm->dev, "failed to add low chip\n");
1083 goto err_mapped;
1084 }
1085
1086 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1087 if (ret) {
1088 dev_err(sm->dev, "failed to add high chip\n");
1089 goto err_low_chip;
1090 }
1091
1092 gpio->registered = 1;
1093
1094 return 0;
1095
1096 err_low_chip:
1097 tmp = gpiochip_remove(&gpio->low.gpio);
1098 if (tmp) {
1099 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1100 return ret;
1101 }
1102
1103 err_mapped:
1104 iounmap(gpio->regs);
1105
1106 err_claimed:
1107 release_resource(gpio->regs_res);
1108 kfree(gpio->regs_res);
1109
1110 return ret;
1111}
1112
1113static void sm501_gpio_remove(struct sm501_devdata *sm)
1114{
1115 struct sm501_gpio *gpio = &sm->gpio;
1116 int ret;
1117
1118 if (!sm->gpio.registered)
1119 return;
1120
1121 ret = gpiochip_remove(&gpio->low.gpio);
1122 if (ret)
1123 dev_err(sm->dev, "cannot remove low chip, cannot tidy up\n");
1124
1125 ret = gpiochip_remove(&gpio->high.gpio);
1126 if (ret)
1127 dev_err(sm->dev, "cannot remove high chip, cannot tidy up\n");
1128
1129 iounmap(gpio->regs);
1130 release_resource(gpio->regs_res);
1131 kfree(gpio->regs_res);
1132}
1133
1134static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1135{
1136 struct sm501_gpio *gpio = &sm->gpio;
1137 int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1138
1139 return (pin % 32) + base;
1140}
1141
1142static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1143{
1144 return sm->gpio.registered;
1145}
1146#else
1147static inline int sm501_register_gpio(struct sm501_devdata *sm)
1148{
1149 return 0;
1150}
1151
1152static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1153{
1154}
1155
1156static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1157{
1158 return -1;
1159}
1160
1161static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1162{
1163 return 0;
1164}
1165#endif
1166
1167static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1168 struct sm501_platdata_gpio_i2c *iic)
1169{
1170 struct i2c_gpio_platform_data *icd;
1171 struct platform_device *pdev;
1172
1173 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1174 sizeof(struct i2c_gpio_platform_data));
1175 if (!pdev)
1176 return -ENOMEM;
1177
1178 icd = pdev->dev.platform_data;
1179
1180 /* We keep the pin_sda and pin_scl fields relative in case the
1181 * same platform data is passed to >1 SM501.
1182 */
1183
1184 icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1185 icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1186 icd->timeout = iic->timeout;
1187 icd->udelay = iic->udelay;
1188
1189 /* note, we can't use either of the pin numbers, as the i2c-gpio
1190 * driver uses the platform.id field to generate the bus number
1191 * to register with the i2c core; The i2c core doesn't have enough
1192 * entries to deal with anything we currently use.
1193 */
1194
1195 pdev->id = iic->bus_num;
1196
1197 dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1198 iic->bus_num,
1199 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1200
1201 return sm501_register_device(sm, pdev);
1202}
1203
1204static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1205 struct sm501_platdata *pdata)
1206{
1207 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1208 int index;
1209 int ret;
1210
1211 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1212 ret = sm501_register_gpio_i2c_instance(sm, iic);
1213 if (ret < 0)
1214 return ret;
1215 }
1216
1217 return 0;
1218}
1219
1220/* sm501_dbg_regs
1221 *
1222 * Debug attribute to attach to parent device to show core registers
1223*/
1224
1225static ssize_t sm501_dbg_regs(struct device *dev,
1226 struct device_attribute *attr, char *buff)
1227{
1228 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1229 unsigned int reg;
1230 char *ptr = buff;
1231 int ret;
1232
1233 for (reg = 0x00; reg < 0x70; reg += 4) {
1234 ret = sprintf(ptr, "%08x = %08x\n",
1235 reg, smc501_readl(sm->regs + reg));
1236 ptr += ret;
1237 }
1238
1239 return ptr - buff;
1240}
1241
1242
1243static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
1244
1245/* sm501_init_reg
1246 *
1247 * Helper function for the init code to setup a register
1248 *
1249 * clear the bits which are set in r->mask, and then set
1250 * the bits set in r->set.
1251*/
1252
1253static inline void sm501_init_reg(struct sm501_devdata *sm,
1254 unsigned long reg,
1255 struct sm501_reg_init *r)
1256{
1257 unsigned long tmp;
1258
1259 tmp = smc501_readl(sm->regs + reg);
1260 tmp &= ~r->mask;
1261 tmp |= r->set;
1262 smc501_writel(tmp, sm->regs + reg);
1263}
1264
1265/* sm501_init_regs
1266 *
1267 * Setup core register values
1268*/
1269
1270static void sm501_init_regs(struct sm501_devdata *sm,
1271 struct sm501_initdata *init)
1272{
1273 sm501_misc_control(sm->dev,
1274 init->misc_control.set,
1275 init->misc_control.mask);
1276
1277 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1278 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1279 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1280
1281 if (init->m1xclk) {
1282 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1283 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1284 }
1285
1286 if (init->mclk) {
1287 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1288 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1289 }
1290
1291}
1292
1293/* Check the PLL sources for the M1CLK and M1XCLK
1294 *
1295 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1296 * there is a risk (see errata AB-5) that the SM501 will cease proper
1297 * function. If this happens, then it is likely the SM501 will
1298 * hang the system.
1299*/
1300
1301static int sm501_check_clocks(struct sm501_devdata *sm)
1302{
1303 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1304 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1305 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1306
1307 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1308}
1309
1310static unsigned int sm501_mem_local[] = {
1311 [0] = 4*1024*1024,
1312 [1] = 8*1024*1024,
1313 [2] = 16*1024*1024,
1314 [3] = 32*1024*1024,
1315 [4] = 64*1024*1024,
1316 [5] = 2*1024*1024,
1317};
1318
1319/* sm501_init_dev
1320 *
1321 * Common init code for an SM501
1322*/
1323
1324static int __devinit sm501_init_dev(struct sm501_devdata *sm)
1325{
1326 struct sm501_initdata *idata;
1327 struct sm501_platdata *pdata;
1328 resource_size_t mem_avail;
1329 unsigned long dramctrl;
1330 unsigned long devid;
1331 int ret;
1332
1333 mutex_init(&sm->clock_lock);
1334 spin_lock_init(&sm->reg_lock);
1335
1336 INIT_LIST_HEAD(&sm->devices);
1337
1338 devid = smc501_readl(sm->regs + SM501_DEVICEID);
1339
1340 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1341 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1342 return -EINVAL;
1343 }
1344
1345 /* disable irqs */
1346 smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1347
1348 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1349 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1350
1351 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1352 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1353
1354 sm->rev = devid & SM501_DEVICEID_REVMASK;
1355
1356 sm501_dump_gate(sm);
1357
1358 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1359 if (ret)
1360 dev_err(sm->dev, "failed to create debug regs file\n");
1361
1362 sm501_dump_clk(sm);
1363
1364 /* check to see if we have some device initialisation */
1365
1366 pdata = sm->platdata;
1367 idata = pdata ? pdata->init : NULL;
1368
1369 if (idata) {
1370 sm501_init_regs(sm, idata);
1371
1372 if (idata->devices & SM501_USE_USB_HOST)
1373 sm501_register_usbhost(sm, &mem_avail);
1374 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1375 sm501_register_uart(sm, idata->devices);
1376 if (idata->devices & SM501_USE_GPIO)
1377 sm501_register_gpio(sm);
1378 }
1379
1380 if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
1381 if (!sm501_gpio_isregistered(sm))
1382 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1383 else
1384 sm501_register_gpio_i2c(sm, pdata);
1385 }
1386
1387 ret = sm501_check_clocks(sm);
1388 if (ret) {
1389 dev_err(sm->dev, "M1X and M clocks sourced from different "
1390 "PLLs\n");
1391 return -EINVAL;
1392 }
1393
1394 /* always create a framebuffer */
1395 sm501_register_display(sm, &mem_avail);
1396
1397 return 0;
1398}
1399
1400static int __devinit sm501_plat_probe(struct platform_device *dev)
1401{
1402 struct sm501_devdata *sm;
1403 int ret;
1404
1405 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1406 if (sm == NULL) {
1407 dev_err(&dev->dev, "no memory for device data\n");
1408 ret = -ENOMEM;
1409 goto err1;
1410 }
1411
1412 sm->dev = &dev->dev;
1413 sm->pdev_id = dev->id;
1414 sm->platdata = dev->dev.platform_data;
1415
1416 ret = platform_get_irq(dev, 0);
1417 if (ret < 0) {
1418 dev_err(&dev->dev, "failed to get irq resource\n");
1419 goto err_res;
1420 }
1421 sm->irq = ret;
1422
1423 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1424 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1425
1426 if (sm->io_res == NULL || sm->mem_res == NULL) {
1427 dev_err(&dev->dev, "failed to get IO resource\n");
1428 ret = -ENOENT;
1429 goto err_res;
1430 }
1431
1432 sm->regs_claim = request_mem_region(sm->io_res->start,
1433 0x100, "sm501");
1434
1435 if (sm->regs_claim == NULL) {
1436 dev_err(&dev->dev, "cannot claim registers\n");
1437 ret = -EBUSY;
1438 goto err_res;
1439 }
1440
1441 platform_set_drvdata(dev, sm);
1442
1443 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1444
1445 if (sm->regs == NULL) {
1446 dev_err(&dev->dev, "cannot remap registers\n");
1447 ret = -EIO;
1448 goto err_claim;
1449 }
1450
1451 return sm501_init_dev(sm);
1452
1453 err_claim:
1454 release_resource(sm->regs_claim);
1455 kfree(sm->regs_claim);
1456 err_res:
1457 kfree(sm);
1458 err1:
1459 return ret;
1460
1461}
1462
1463#ifdef CONFIG_PM
1464
1465/* power management support */
1466
1467static void sm501_set_power(struct sm501_devdata *sm, int on)
1468{
1469 struct sm501_platdata *pd = sm->platdata;
1470
1471 if (pd == NULL)
1472 return;
1473
1474 if (pd->get_power) {
1475 if (pd->get_power(sm->dev) == on) {
1476 dev_dbg(sm->dev, "is already %d\n", on);
1477 return;
1478 }
1479 }
1480
1481 if (pd->set_power) {
1482 dev_dbg(sm->dev, "setting power to %d\n", on);
1483
1484 pd->set_power(sm->dev, on);
1485 sm501_mdelay(sm, 10);
1486 }
1487}
1488
1489static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1490{
1491 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1492
1493 sm->in_suspend = 1;
1494 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1495
1496 sm501_dump_regs(sm);
1497
1498 if (sm->platdata) {
1499 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1500 sm501_set_power(sm, 0);
1501 }
1502
1503 return 0;
1504}
1505
1506static int sm501_plat_resume(struct platform_device *pdev)
1507{
1508 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1509
1510 sm501_set_power(sm, 1);
1511
1512 sm501_dump_regs(sm);
1513 sm501_dump_gate(sm);
1514 sm501_dump_clk(sm);
1515
1516 /* check to see if we are in the same state as when suspended */
1517
1518 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1519 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1520 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1521
1522 /* our suspend causes the controller state to change,
1523 * either by something attempting setup, power loss,
1524 * or an external reset event on power change */
1525
1526 if (sm->platdata && sm->platdata->init) {
1527 sm501_init_regs(sm, sm->platdata->init);
1528 }
1529 }
1530
1531 /* dump our state from resume */
1532
1533 sm501_dump_regs(sm);
1534 sm501_dump_clk(sm);
1535
1536 sm->in_suspend = 0;
1537
1538 return 0;
1539}
1540#else
1541#define sm501_plat_suspend NULL
1542#define sm501_plat_resume NULL
1543#endif
1544
1545/* Initialisation data for PCI devices */
1546
1547static struct sm501_initdata sm501_pci_initdata = {
1548 .gpio_high = {
1549 .set = 0x3F000000, /* 24bit panel */
1550 .mask = 0x0,
1551 },
1552 .misc_timing = {
1553 .set = 0x010100, /* SDRAM timing */
1554 .mask = 0x1F1F00,
1555 },
1556 .misc_control = {
1557 .set = SM501_MISC_PNL_24BIT,
1558 .mask = 0,
1559 },
1560
1561 .devices = SM501_USE_ALL,
1562
1563 /* Errata AB-3 says that 72MHz is the fastest available
1564 * for 33MHZ PCI with proper bus-mastering operation */
1565
1566 .mclk = 72 * MHZ,
1567 .m1xclk = 144 * MHZ,
1568};
1569
1570static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1571 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1572 SM501FB_FLAG_USE_HWCURSOR |
1573 SM501FB_FLAG_USE_HWACCEL |
1574 SM501FB_FLAG_DISABLE_AT_EXIT),
1575};
1576
1577static struct sm501_platdata_fb sm501_fb_pdata = {
1578 .fb_route = SM501_FB_OWN,
1579 .fb_crt = &sm501_pdata_fbsub,
1580 .fb_pnl = &sm501_pdata_fbsub,
1581};
1582
1583static struct sm501_platdata sm501_pci_platdata = {
1584 .init = &sm501_pci_initdata,
1585 .fb = &sm501_fb_pdata,
1586 .gpio_base = -1,
1587};
1588
1589static int __devinit sm501_pci_probe(struct pci_dev *dev,
1590 const struct pci_device_id *id)
1591{
1592 struct sm501_devdata *sm;
1593 int err;
1594
1595 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1596 if (sm == NULL) {
1597 dev_err(&dev->dev, "no memory for device data\n");
1598 err = -ENOMEM;
1599 goto err1;
1600 }
1601
1602 /* set a default set of platform data */
1603 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1604
1605 /* set a hopefully unique id for our child platform devices */
1606 sm->pdev_id = 32 + dev->devfn;
1607
1608 pci_set_drvdata(dev, sm);
1609
1610 err = pci_enable_device(dev);
1611 if (err) {
1612 dev_err(&dev->dev, "cannot enable device\n");
1613 goto err2;
1614 }
1615
1616 sm->dev = &dev->dev;
1617 sm->irq = dev->irq;
1618
1619#ifdef __BIG_ENDIAN
1620 /* if the system is big-endian, we most probably have a
1621 * translation in the IO layer making the PCI bus little endian
1622 * so make the framebuffer swapped pixels */
1623
1624 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1625#endif
1626
1627 /* check our resources */
1628
1629 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1630 dev_err(&dev->dev, "region #0 is not memory?\n");
1631 err = -EINVAL;
1632 goto err3;
1633 }
1634
1635 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1636 dev_err(&dev->dev, "region #1 is not memory?\n");
1637 err = -EINVAL;
1638 goto err3;
1639 }
1640
1641 /* make our resources ready for sharing */
1642
1643 sm->io_res = &dev->resource[1];
1644 sm->mem_res = &dev->resource[0];
1645
1646 sm->regs_claim = request_mem_region(sm->io_res->start,
1647 0x100, "sm501");
1648 if (sm->regs_claim == NULL) {
1649 dev_err(&dev->dev, "cannot claim registers\n");
1650 err= -EBUSY;
1651 goto err3;
1652 }
1653
1654 sm->regs = pci_ioremap_bar(dev, 1);
1655
1656 if (sm->regs == NULL) {
1657 dev_err(&dev->dev, "cannot remap registers\n");
1658 err = -EIO;
1659 goto err4;
1660 }
1661
1662 sm501_init_dev(sm);
1663 return 0;
1664
1665 err4:
1666 release_resource(sm->regs_claim);
1667 kfree(sm->regs_claim);
1668 err3:
1669 pci_disable_device(dev);
1670 err2:
1671 pci_set_drvdata(dev, NULL);
1672 kfree(sm);
1673 err1:
1674 return err;
1675}
1676
1677static void sm501_remove_sub(struct sm501_devdata *sm,
1678 struct sm501_device *smdev)
1679{
1680 list_del(&smdev->list);
1681 platform_device_unregister(&smdev->pdev);
1682}
1683
1684static void sm501_dev_remove(struct sm501_devdata *sm)
1685{
1686 struct sm501_device *smdev, *tmp;
1687
1688 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1689 sm501_remove_sub(sm, smdev);
1690
1691 device_remove_file(sm->dev, &dev_attr_dbg_regs);
1692
1693 sm501_gpio_remove(sm);
1694}
1695
1696static void __devexit sm501_pci_remove(struct pci_dev *dev)
1697{
1698 struct sm501_devdata *sm = pci_get_drvdata(dev);
1699
1700 sm501_dev_remove(sm);
1701 iounmap(sm->regs);
1702
1703 release_resource(sm->regs_claim);
1704 kfree(sm->regs_claim);
1705
1706 pci_set_drvdata(dev, NULL);
1707 pci_disable_device(dev);
1708}
1709
1710static int sm501_plat_remove(struct platform_device *dev)
1711{
1712 struct sm501_devdata *sm = platform_get_drvdata(dev);
1713
1714 sm501_dev_remove(sm);
1715 iounmap(sm->regs);
1716
1717 release_resource(sm->regs_claim);
1718 kfree(sm->regs_claim);
1719
1720 return 0;
1721}
1722
1723static struct pci_device_id sm501_pci_tbl[] = {
1724 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1725 { 0, },
1726};
1727
1728MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1729
1730static struct pci_driver sm501_pci_driver = {
1731 .name = "sm501",
1732 .id_table = sm501_pci_tbl,
1733 .probe = sm501_pci_probe,
1734 .remove = __devexit_p(sm501_pci_remove),
1735};
1736
1737MODULE_ALIAS("platform:sm501");
1738
1739static struct of_device_id __devinitdata of_sm501_match_tbl[] = {
1740 { .compatible = "smi,sm501", },
1741 { /* end */ }
1742};
1743
1744static struct platform_driver sm501_plat_driver = {
1745 .driver = {
1746 .name = "sm501",
1747 .owner = THIS_MODULE,
1748 .of_match_table = of_sm501_match_tbl,
1749 },
1750 .probe = sm501_plat_probe,
1751 .remove = sm501_plat_remove,
1752 .suspend = sm501_plat_suspend,
1753 .resume = sm501_plat_resume,
1754};
1755
1756static int __init sm501_base_init(void)
1757{
1758 platform_driver_register(&sm501_plat_driver);
1759 return pci_register_driver(&sm501_pci_driver);
1760}
1761
1762static void __exit sm501_base_exit(void)
1763{
1764 platform_driver_unregister(&sm501_plat_driver);
1765 pci_unregister_driver(&sm501_pci_driver);
1766}
1767
1768module_init(sm501_base_init);
1769module_exit(sm501_base_exit);
1770
1771MODULE_DESCRIPTION("SM501 Core Driver");
1772MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1773MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/* linux/drivers/mfd/sm501.c
3 *
4 * Copyright (C) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@simtec.co.uk>
7 *
8 * SM501 MFD driver
9*/
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/list.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/pci.h>
19#include <linux/platform_data/i2c-gpio.h>
20#include <linux/gpio/driver.h>
21#include <linux/gpio/machine.h>
22#include <linux/slab.h>
23
24#include <linux/sm501.h>
25#include <linux/sm501-regs.h>
26#include <linux/serial_8250.h>
27
28#include <linux/io.h>
29
30struct sm501_device {
31 struct list_head list;
32 struct platform_device pdev;
33};
34
35struct sm501_gpio;
36
37#ifdef CONFIG_MFD_SM501_GPIO
38#include <linux/gpio.h>
39
40struct sm501_gpio_chip {
41 struct gpio_chip gpio;
42 struct sm501_gpio *ourgpio; /* to get back to parent. */
43 void __iomem *regbase;
44 void __iomem *control; /* address of control reg. */
45};
46
47struct sm501_gpio {
48 struct sm501_gpio_chip low;
49 struct sm501_gpio_chip high;
50 spinlock_t lock;
51
52 unsigned int registered : 1;
53 void __iomem *regs;
54 struct resource *regs_res;
55};
56#else
57struct sm501_gpio {
58 /* no gpio support, empty definition for sm501_devdata. */
59};
60#endif
61
62struct sm501_devdata {
63 spinlock_t reg_lock;
64 struct mutex clock_lock;
65 struct list_head devices;
66 struct sm501_gpio gpio;
67
68 struct device *dev;
69 struct resource *io_res;
70 struct resource *mem_res;
71 struct resource *regs_claim;
72 struct sm501_platdata *platdata;
73
74
75 unsigned int in_suspend;
76 unsigned long pm_misc;
77
78 int unit_power[20];
79 unsigned int pdev_id;
80 unsigned int irq;
81 void __iomem *regs;
82 unsigned int rev;
83};
84
85
86#define MHZ (1000 * 1000)
87
88#ifdef DEBUG
89static const unsigned int div_tab[] = {
90 [0] = 1,
91 [1] = 2,
92 [2] = 4,
93 [3] = 8,
94 [4] = 16,
95 [5] = 32,
96 [6] = 64,
97 [7] = 128,
98 [8] = 3,
99 [9] = 6,
100 [10] = 12,
101 [11] = 24,
102 [12] = 48,
103 [13] = 96,
104 [14] = 192,
105 [15] = 384,
106 [16] = 5,
107 [17] = 10,
108 [18] = 20,
109 [19] = 40,
110 [20] = 80,
111 [21] = 160,
112 [22] = 320,
113 [23] = 604,
114};
115
116static unsigned long decode_div(unsigned long pll2, unsigned long val,
117 unsigned int lshft, unsigned int selbit,
118 unsigned long mask)
119{
120 if (val & selbit)
121 pll2 = 288 * MHZ;
122
123 return pll2 / div_tab[(val >> lshft) & mask];
124}
125
126#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
127
128/* sm501_dump_clk
129 *
130 * Print out the current clock configuration for the device
131*/
132
133static void sm501_dump_clk(struct sm501_devdata *sm)
134{
135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
139 unsigned long sdclk0, sdclk1;
140 unsigned long pll2 = 0;
141
142 switch (misct & 0x30) {
143 case 0x00:
144 pll2 = 336 * MHZ;
145 break;
146 case 0x10:
147 pll2 = 288 * MHZ;
148 break;
149 case 0x20:
150 pll2 = 240 * MHZ;
151 break;
152 case 0x30:
153 pll2 = 192 * MHZ;
154 break;
155 }
156
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
158 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
159
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
161 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
162
163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
164 misct, pm0, pm1);
165
166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
167 fmt_freq(pll2), sdclk0, sdclk1);
168
169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
170
171 dev_dbg(sm->dev, "PM0[%c]: "
172 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
174 (pmc & 3 ) == 0 ? '*' : '-',
175 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
176 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
177 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
178 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
179
180 dev_dbg(sm->dev, "PM1[%c]: "
181 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
183 (pmc & 3 ) == 1 ? '*' : '-',
184 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
185 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
186 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
187 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
188}
189
190static void sm501_dump_regs(struct sm501_devdata *sm)
191{
192 void __iomem *regs = sm->regs;
193
194 dev_info(sm->dev, "System Control %08x\n",
195 smc501_readl(regs + SM501_SYSTEM_CONTROL));
196 dev_info(sm->dev, "Misc Control %08x\n",
197 smc501_readl(regs + SM501_MISC_CONTROL));
198 dev_info(sm->dev, "GPIO Control Low %08x\n",
199 smc501_readl(regs + SM501_GPIO31_0_CONTROL));
200 dev_info(sm->dev, "GPIO Control Hi %08x\n",
201 smc501_readl(regs + SM501_GPIO63_32_CONTROL));
202 dev_info(sm->dev, "DRAM Control %08x\n",
203 smc501_readl(regs + SM501_DRAM_CONTROL));
204 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
205 smc501_readl(regs + SM501_ARBTRTN_CONTROL));
206 dev_info(sm->dev, "Misc Timing %08x\n",
207 smc501_readl(regs + SM501_MISC_TIMING));
208}
209
210static void sm501_dump_gate(struct sm501_devdata *sm)
211{
212 dev_info(sm->dev, "CurrentGate %08x\n",
213 smc501_readl(sm->regs + SM501_CURRENT_GATE));
214 dev_info(sm->dev, "CurrentClock %08x\n",
215 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
216 dev_info(sm->dev, "PowerModeControl %08x\n",
217 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
218}
219
220#else
221static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
222static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
223static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
224#endif
225
226/* sm501_sync_regs
227 *
228 * ensure the
229*/
230
231static void sm501_sync_regs(struct sm501_devdata *sm)
232{
233 smc501_readl(sm->regs);
234}
235
236static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
237{
238 /* during suspend/resume, we are currently not allowed to sleep,
239 * so change to using mdelay() instead of msleep() if we
240 * are in one of these paths */
241
242 if (sm->in_suspend)
243 mdelay(delay);
244 else
245 msleep(delay);
246}
247
248/* sm501_misc_control
249 *
250 * alters the miscellaneous control parameters
251*/
252
253int sm501_misc_control(struct device *dev,
254 unsigned long set, unsigned long clear)
255{
256 struct sm501_devdata *sm = dev_get_drvdata(dev);
257 unsigned long misc;
258 unsigned long save;
259 unsigned long to;
260
261 spin_lock_irqsave(&sm->reg_lock, save);
262
263 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
264 to = (misc & ~clear) | set;
265
266 if (to != misc) {
267 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
268 sm501_sync_regs(sm);
269
270 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
271 }
272
273 spin_unlock_irqrestore(&sm->reg_lock, save);
274 return to;
275}
276
277EXPORT_SYMBOL_GPL(sm501_misc_control);
278
279/* sm501_modify_reg
280 *
281 * Modify a register in the SM501 which may be shared with other
282 * drivers.
283*/
284
285unsigned long sm501_modify_reg(struct device *dev,
286 unsigned long reg,
287 unsigned long set,
288 unsigned long clear)
289{
290 struct sm501_devdata *sm = dev_get_drvdata(dev);
291 unsigned long data;
292 unsigned long save;
293
294 spin_lock_irqsave(&sm->reg_lock, save);
295
296 data = smc501_readl(sm->regs + reg);
297 data |= set;
298 data &= ~clear;
299
300 smc501_writel(data, sm->regs + reg);
301 sm501_sync_regs(sm);
302
303 spin_unlock_irqrestore(&sm->reg_lock, save);
304
305 return data;
306}
307
308EXPORT_SYMBOL_GPL(sm501_modify_reg);
309
310/* sm501_unit_power
311 *
312 * alters the power active gate to set specific units on or off
313 */
314
315int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
316{
317 struct sm501_devdata *sm = dev_get_drvdata(dev);
318 unsigned long mode;
319 unsigned long gate;
320 unsigned long clock;
321
322 mutex_lock(&sm->clock_lock);
323
324 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
325 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
326 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
327
328 mode &= 3; /* get current power mode */
329
330 if (unit >= ARRAY_SIZE(sm->unit_power)) {
331 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
332 goto already;
333 }
334
335 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
336 sm->unit_power[unit], to);
337
338 if (to == 0 && sm->unit_power[unit] == 0) {
339 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
340 goto already;
341 }
342
343 sm->unit_power[unit] += to ? 1 : -1;
344 to = sm->unit_power[unit] ? 1 : 0;
345
346 if (to) {
347 if (gate & (1 << unit))
348 goto already;
349 gate |= (1 << unit);
350 } else {
351 if (!(gate & (1 << unit)))
352 goto already;
353 gate &= ~(1 << unit);
354 }
355
356 switch (mode) {
357 case 1:
358 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
359 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
360 mode = 0;
361 break;
362 case 2:
363 case 0:
364 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
365 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
366 mode = 1;
367 break;
368
369 default:
370 gate = -1;
371 goto already;
372 }
373
374 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
375 sm501_sync_regs(sm);
376
377 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
378 gate, clock, mode);
379
380 sm501_mdelay(sm, 16);
381
382 already:
383 mutex_unlock(&sm->clock_lock);
384 return gate;
385}
386
387EXPORT_SYMBOL_GPL(sm501_unit_power);
388
389/* clock value structure. */
390struct sm501_clock {
391 unsigned long mclk;
392 int divider;
393 int shift;
394 unsigned int m, n, k;
395};
396
397/* sm501_calc_clock
398 *
399 * Calculates the nearest discrete clock frequency that
400 * can be achieved with the specified input clock.
401 * the maximum divisor is 3 or 5
402 */
403
404static int sm501_calc_clock(unsigned long freq,
405 struct sm501_clock *clock,
406 int max_div,
407 unsigned long mclk,
408 long *best_diff)
409{
410 int ret = 0;
411 int divider;
412 int shift;
413 long diff;
414
415 /* try dividers 1 and 3 for CRT and for panel,
416 try divider 5 for panel only.*/
417
418 for (divider = 1; divider <= max_div; divider += 2) {
419 /* try all 8 shift values.*/
420 for (shift = 0; shift < 8; shift++) {
421 /* Calculate difference to requested clock */
422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
423 if (diff < 0)
424 diff = -diff;
425
426 /* If it is less than the current, use it */
427 if (diff < *best_diff) {
428 *best_diff = diff;
429
430 clock->mclk = mclk;
431 clock->divider = divider;
432 clock->shift = shift;
433 ret = 1;
434 }
435 }
436 }
437
438 return ret;
439}
440
441/* sm501_calc_pll
442 *
443 * Calculates the nearest discrete clock frequency that can be
444 * achieved using the programmable PLL.
445 * the maximum divisor is 3 or 5
446 */
447
448static unsigned long sm501_calc_pll(unsigned long freq,
449 struct sm501_clock *clock,
450 int max_div)
451{
452 unsigned long mclk;
453 unsigned int m, n, k;
454 long best_diff = 999999999;
455
456 /*
457 * The SM502 datasheet doesn't specify the min/max values for M and N.
458 * N = 1 at least doesn't work in practice.
459 */
460 for (m = 2; m <= 255; m++) {
461 for (n = 2; n <= 127; n++) {
462 for (k = 0; k <= 1; k++) {
463 mclk = (24000000UL * m / n) >> k;
464
465 if (sm501_calc_clock(freq, clock, max_div,
466 mclk, &best_diff)) {
467 clock->m = m;
468 clock->n = n;
469 clock->k = k;
470 }
471 }
472 }
473 }
474
475 /* Return best clock. */
476 return clock->mclk / (clock->divider << clock->shift);
477}
478
479/* sm501_select_clock
480 *
481 * Calculates the nearest discrete clock frequency that can be
482 * achieved using the 288MHz and 336MHz PLLs.
483 * the maximum divisor is 3 or 5
484 */
485
486static unsigned long sm501_select_clock(unsigned long freq,
487 struct sm501_clock *clock,
488 int max_div)
489{
490 unsigned long mclk;
491 long best_diff = 999999999;
492
493 /* Try 288MHz and 336MHz clocks. */
494 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
495 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
496 }
497
498 /* Return best clock. */
499 return clock->mclk / (clock->divider << clock->shift);
500}
501
502/* sm501_set_clock
503 *
504 * set one of the four clock sources to the closest available frequency to
505 * the one specified
506*/
507
508unsigned long sm501_set_clock(struct device *dev,
509 int clksrc,
510 unsigned long req_freq)
511{
512 struct sm501_devdata *sm = dev_get_drvdata(dev);
513 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
514 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
515 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
516 unsigned int pll_reg = 0;
517 unsigned long sm501_freq; /* the actual frequency achieved */
518 u64 reg;
519
520 struct sm501_clock to;
521
522 /* find achivable discrete frequency and setup register value
523 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
524 * has an extra bit for the divider */
525
526 switch (clksrc) {
527 case SM501_CLOCK_P2XCLK:
528 /* This clock is divided in half so to achieve the
529 * requested frequency the value must be multiplied by
530 * 2. This clock also has an additional pre divisor */
531
532 if (sm->rev >= 0xC0) {
533 /* SM502 -> use the programmable PLL */
534 sm501_freq = (sm501_calc_pll(2 * req_freq,
535 &to, 5) / 2);
536 reg = to.shift & 0x07;/* bottom 3 bits are shift */
537 if (to.divider == 3)
538 reg |= 0x08; /* /3 divider required */
539 else if (to.divider == 5)
540 reg |= 0x10; /* /5 divider required */
541 reg |= 0x40; /* select the programmable PLL */
542 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
543 } else {
544 sm501_freq = (sm501_select_clock(2 * req_freq,
545 &to, 5) / 2);
546 reg = to.shift & 0x07;/* bottom 3 bits are shift */
547 if (to.divider == 3)
548 reg |= 0x08; /* /3 divider required */
549 else if (to.divider == 5)
550 reg |= 0x10; /* /5 divider required */
551 if (to.mclk != 288000000)
552 reg |= 0x20; /* which mclk pll is source */
553 }
554 break;
555
556 case SM501_CLOCK_V2XCLK:
557 /* This clock is divided in half so to achieve the
558 * requested frequency the value must be multiplied by 2. */
559
560 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
561 reg=to.shift & 0x07; /* bottom 3 bits are shift */
562 if (to.divider == 3)
563 reg |= 0x08; /* /3 divider required */
564 if (to.mclk != 288000000)
565 reg |= 0x10; /* which mclk pll is source */
566 break;
567
568 case SM501_CLOCK_MCLK:
569 case SM501_CLOCK_M1XCLK:
570 /* These clocks are the same and not further divided */
571
572 sm501_freq = sm501_select_clock( req_freq, &to, 3);
573 reg=to.shift & 0x07; /* bottom 3 bits are shift */
574 if (to.divider == 3)
575 reg |= 0x08; /* /3 divider required */
576 if (to.mclk != 288000000)
577 reg |= 0x10; /* which mclk pll is source */
578 break;
579
580 default:
581 return 0; /* this is bad */
582 }
583
584 mutex_lock(&sm->clock_lock);
585
586 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
587 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
588 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
589
590 clock = clock & ~(0xFF << clksrc);
591 clock |= reg<<clksrc;
592
593 mode &= 3; /* find current mode */
594
595 switch (mode) {
596 case 1:
597 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
598 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
599 mode = 0;
600 break;
601 case 2:
602 case 0:
603 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
604 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
605 mode = 1;
606 break;
607
608 default:
609 mutex_unlock(&sm->clock_lock);
610 return -1;
611 }
612
613 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
614
615 if (pll_reg)
616 smc501_writel(pll_reg,
617 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
618
619 sm501_sync_regs(sm);
620
621 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
622 gate, clock, mode);
623
624 sm501_mdelay(sm, 16);
625 mutex_unlock(&sm->clock_lock);
626
627 sm501_dump_clk(sm);
628
629 return sm501_freq;
630}
631
632EXPORT_SYMBOL_GPL(sm501_set_clock);
633
634/* sm501_find_clock
635 *
636 * finds the closest available frequency for a given clock
637*/
638
639unsigned long sm501_find_clock(struct device *dev,
640 int clksrc,
641 unsigned long req_freq)
642{
643 struct sm501_devdata *sm = dev_get_drvdata(dev);
644 unsigned long sm501_freq; /* the frequency achieveable by the 501 */
645 struct sm501_clock to;
646
647 switch (clksrc) {
648 case SM501_CLOCK_P2XCLK:
649 if (sm->rev >= 0xC0) {
650 /* SM502 -> use the programmable PLL */
651 sm501_freq = (sm501_calc_pll(2 * req_freq,
652 &to, 5) / 2);
653 } else {
654 sm501_freq = (sm501_select_clock(2 * req_freq,
655 &to, 5) / 2);
656 }
657 break;
658
659 case SM501_CLOCK_V2XCLK:
660 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
661 break;
662
663 case SM501_CLOCK_MCLK:
664 case SM501_CLOCK_M1XCLK:
665 sm501_freq = sm501_select_clock(req_freq, &to, 3);
666 break;
667
668 default:
669 sm501_freq = 0; /* error */
670 }
671
672 return sm501_freq;
673}
674
675EXPORT_SYMBOL_GPL(sm501_find_clock);
676
677static struct sm501_device *to_sm_device(struct platform_device *pdev)
678{
679 return container_of(pdev, struct sm501_device, pdev);
680}
681
682/* sm501_device_release
683 *
684 * A release function for the platform devices we create to allow us to
685 * free any items we allocated
686*/
687
688static void sm501_device_release(struct device *dev)
689{
690 kfree(to_sm_device(to_platform_device(dev)));
691}
692
693/* sm501_create_subdev
694 *
695 * Create a skeleton platform device with resources for passing to a
696 * sub-driver
697*/
698
699static struct platform_device *
700sm501_create_subdev(struct sm501_devdata *sm, char *name,
701 unsigned int res_count, unsigned int platform_data_size)
702{
703 struct sm501_device *smdev;
704
705 smdev = kzalloc(sizeof(struct sm501_device) +
706 (sizeof(struct resource) * res_count) +
707 platform_data_size, GFP_KERNEL);
708 if (!smdev)
709 return NULL;
710
711 smdev->pdev.dev.release = sm501_device_release;
712
713 smdev->pdev.name = name;
714 smdev->pdev.id = sm->pdev_id;
715 smdev->pdev.dev.parent = sm->dev;
716 smdev->pdev.dev.coherent_dma_mask = 0xffffffff;
717
718 if (res_count) {
719 smdev->pdev.resource = (struct resource *)(smdev+1);
720 smdev->pdev.num_resources = res_count;
721 }
722 if (platform_data_size)
723 smdev->pdev.dev.platform_data = (void *)(smdev+1);
724
725 return &smdev->pdev;
726}
727
728/* sm501_register_device
729 *
730 * Register a platform device created with sm501_create_subdev()
731*/
732
733static int sm501_register_device(struct sm501_devdata *sm,
734 struct platform_device *pdev)
735{
736 struct sm501_device *smdev = to_sm_device(pdev);
737 int ptr;
738 int ret;
739
740 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
741 printk(KERN_DEBUG "%s[%d] %pR\n",
742 pdev->name, ptr, &pdev->resource[ptr]);
743 }
744
745 ret = platform_device_register(pdev);
746
747 if (ret >= 0) {
748 dev_dbg(sm->dev, "registered %s\n", pdev->name);
749 list_add_tail(&smdev->list, &sm->devices);
750 } else
751 dev_err(sm->dev, "error registering %s (%d)\n",
752 pdev->name, ret);
753
754 return ret;
755}
756
757/* sm501_create_subio
758 *
759 * Fill in an IO resource for a sub device
760*/
761
762static void sm501_create_subio(struct sm501_devdata *sm,
763 struct resource *res,
764 resource_size_t offs,
765 resource_size_t size)
766{
767 res->flags = IORESOURCE_MEM;
768 res->parent = sm->io_res;
769 res->start = sm->io_res->start + offs;
770 res->end = res->start + size - 1;
771}
772
773/* sm501_create_mem
774 *
775 * Fill in an MEM resource for a sub device
776*/
777
778static void sm501_create_mem(struct sm501_devdata *sm,
779 struct resource *res,
780 resource_size_t *offs,
781 resource_size_t size)
782{
783 *offs -= size; /* adjust memory size */
784
785 res->flags = IORESOURCE_MEM;
786 res->parent = sm->mem_res;
787 res->start = sm->mem_res->start + *offs;
788 res->end = res->start + size - 1;
789}
790
791/* sm501_create_irq
792 *
793 * Fill in an IRQ resource for a sub device
794*/
795
796static void sm501_create_irq(struct sm501_devdata *sm,
797 struct resource *res)
798{
799 res->flags = IORESOURCE_IRQ;
800 res->parent = NULL;
801 res->start = res->end = sm->irq;
802}
803
804static int sm501_register_usbhost(struct sm501_devdata *sm,
805 resource_size_t *mem_avail)
806{
807 struct platform_device *pdev;
808
809 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
810 if (!pdev)
811 return -ENOMEM;
812
813 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
814 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
815 sm501_create_irq(sm, &pdev->resource[2]);
816
817 return sm501_register_device(sm, pdev);
818}
819
820static void sm501_setup_uart_data(struct sm501_devdata *sm,
821 struct plat_serial8250_port *uart_data,
822 unsigned int offset)
823{
824 uart_data->membase = sm->regs + offset;
825 uart_data->mapbase = sm->io_res->start + offset;
826 uart_data->iotype = UPIO_MEM;
827 uart_data->irq = sm->irq;
828 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
829 uart_data->regshift = 2;
830 uart_data->uartclk = (9600 * 16);
831}
832
833static int sm501_register_uart(struct sm501_devdata *sm, int devices)
834{
835 struct platform_device *pdev;
836 struct plat_serial8250_port *uart_data;
837
838 pdev = sm501_create_subdev(sm, "serial8250", 0,
839 sizeof(struct plat_serial8250_port) * 3);
840 if (!pdev)
841 return -ENOMEM;
842
843 uart_data = dev_get_platdata(&pdev->dev);
844
845 if (devices & SM501_USE_UART0) {
846 sm501_setup_uart_data(sm, uart_data++, 0x30000);
847 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
848 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
849 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
850 }
851 if (devices & SM501_USE_UART1) {
852 sm501_setup_uart_data(sm, uart_data++, 0x30020);
853 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
854 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
855 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
856 }
857
858 pdev->id = PLAT8250_DEV_SM501;
859
860 return sm501_register_device(sm, pdev);
861}
862
863static int sm501_register_display(struct sm501_devdata *sm,
864 resource_size_t *mem_avail)
865{
866 struct platform_device *pdev;
867
868 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
869 if (!pdev)
870 return -ENOMEM;
871
872 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
873 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
874 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
875 sm501_create_irq(sm, &pdev->resource[3]);
876
877 return sm501_register_device(sm, pdev);
878}
879
880#ifdef CONFIG_MFD_SM501_GPIO
881
882static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
883{
884 return container_of(gpio, struct sm501_devdata, gpio);
885}
886
887static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
888
889{
890 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
891 unsigned long result;
892
893 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
894 result >>= offset;
895
896 return result & 1UL;
897}
898
899static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
900 unsigned long bit)
901{
902 unsigned long ctrl;
903
904 /* check and modify if this pin is not set as gpio. */
905
906 if (smc501_readl(smchip->control) & bit) {
907 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
908 "changing mode of gpio, bit %08lx\n", bit);
909
910 ctrl = smc501_readl(smchip->control);
911 ctrl &= ~bit;
912 smc501_writel(ctrl, smchip->control);
913
914 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
915 }
916}
917
918static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
919
920{
921 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
922 struct sm501_gpio *smgpio = smchip->ourgpio;
923 unsigned long bit = 1 << offset;
924 void __iomem *regs = smchip->regbase;
925 unsigned long save;
926 unsigned long val;
927
928 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
929 __func__, chip, offset);
930
931 spin_lock_irqsave(&smgpio->lock, save);
932
933 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
934 if (value)
935 val |= bit;
936 smc501_writel(val, regs);
937
938 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
939 sm501_gpio_ensure_gpio(smchip, bit);
940
941 spin_unlock_irqrestore(&smgpio->lock, save);
942}
943
944static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
945{
946 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
947 struct sm501_gpio *smgpio = smchip->ourgpio;
948 void __iomem *regs = smchip->regbase;
949 unsigned long bit = 1 << offset;
950 unsigned long save;
951 unsigned long ddr;
952
953 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
954 __func__, chip, offset);
955
956 spin_lock_irqsave(&smgpio->lock, save);
957
958 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
959 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
960
961 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
962 sm501_gpio_ensure_gpio(smchip, bit);
963
964 spin_unlock_irqrestore(&smgpio->lock, save);
965
966 return 0;
967}
968
969static int sm501_gpio_output(struct gpio_chip *chip,
970 unsigned offset, int value)
971{
972 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
973 struct sm501_gpio *smgpio = smchip->ourgpio;
974 unsigned long bit = 1 << offset;
975 void __iomem *regs = smchip->regbase;
976 unsigned long save;
977 unsigned long val;
978 unsigned long ddr;
979
980 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
981 __func__, chip, offset, value);
982
983 spin_lock_irqsave(&smgpio->lock, save);
984
985 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
986 if (value)
987 val |= bit;
988 else
989 val &= ~bit;
990 smc501_writel(val, regs);
991
992 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
993 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
994
995 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
996 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
997
998 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
999 spin_unlock_irqrestore(&smgpio->lock, save);
1000
1001 return 0;
1002}
1003
1004static const struct gpio_chip gpio_chip_template = {
1005 .ngpio = 32,
1006 .direction_input = sm501_gpio_input,
1007 .direction_output = sm501_gpio_output,
1008 .set = sm501_gpio_set,
1009 .get = sm501_gpio_get,
1010};
1011
1012static int sm501_gpio_register_chip(struct sm501_devdata *sm,
1013 struct sm501_gpio *gpio,
1014 struct sm501_gpio_chip *chip)
1015{
1016 struct sm501_platdata *pdata = sm->platdata;
1017 struct gpio_chip *gchip = &chip->gpio;
1018 int base = pdata->gpio_base;
1019
1020 chip->gpio = gpio_chip_template;
1021
1022 if (chip == &gpio->high) {
1023 if (base > 0)
1024 base += 32;
1025 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1026 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1027 gchip->label = "SM501-HIGH";
1028 } else {
1029 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1030 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1031 gchip->label = "SM501-LOW";
1032 }
1033
1034 gchip->base = base;
1035 chip->ourgpio = gpio;
1036
1037 return gpiochip_add_data(gchip, chip);
1038}
1039
1040static int sm501_register_gpio(struct sm501_devdata *sm)
1041{
1042 struct sm501_gpio *gpio = &sm->gpio;
1043 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1044 int ret;
1045
1046 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1047 (unsigned long long)iobase);
1048
1049 spin_lock_init(&gpio->lock);
1050
1051 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1052 if (!gpio->regs_res) {
1053 dev_err(sm->dev, "gpio: failed to request region\n");
1054 return -ENXIO;
1055 }
1056
1057 gpio->regs = ioremap(iobase, 0x20);
1058 if (!gpio->regs) {
1059 dev_err(sm->dev, "gpio: failed to remap registers\n");
1060 ret = -ENXIO;
1061 goto err_claimed;
1062 }
1063
1064 /* Register both our chips. */
1065
1066 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1067 if (ret) {
1068 dev_err(sm->dev, "failed to add low chip\n");
1069 goto err_mapped;
1070 }
1071
1072 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1073 if (ret) {
1074 dev_err(sm->dev, "failed to add high chip\n");
1075 goto err_low_chip;
1076 }
1077
1078 gpio->registered = 1;
1079
1080 return 0;
1081
1082 err_low_chip:
1083 gpiochip_remove(&gpio->low.gpio);
1084
1085 err_mapped:
1086 iounmap(gpio->regs);
1087
1088 err_claimed:
1089 release_resource(gpio->regs_res);
1090 kfree(gpio->regs_res);
1091
1092 return ret;
1093}
1094
1095static void sm501_gpio_remove(struct sm501_devdata *sm)
1096{
1097 struct sm501_gpio *gpio = &sm->gpio;
1098
1099 if (!sm->gpio.registered)
1100 return;
1101
1102 gpiochip_remove(&gpio->low.gpio);
1103 gpiochip_remove(&gpio->high.gpio);
1104
1105 iounmap(gpio->regs);
1106 release_resource(gpio->regs_res);
1107 kfree(gpio->regs_res);
1108}
1109
1110static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1111{
1112 return sm->gpio.registered;
1113}
1114#else
1115static inline int sm501_register_gpio(struct sm501_devdata *sm)
1116{
1117 return 0;
1118}
1119
1120static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1121{
1122}
1123
1124static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1125{
1126 return 0;
1127}
1128#endif
1129
1130static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1131 struct sm501_platdata_gpio_i2c *iic)
1132{
1133 struct i2c_gpio_platform_data *icd;
1134 struct platform_device *pdev;
1135 struct gpiod_lookup_table *lookup;
1136
1137 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1138 sizeof(struct i2c_gpio_platform_data));
1139 if (!pdev)
1140 return -ENOMEM;
1141
1142 /* Create a gpiod lookup using gpiochip-local offsets */
1143 lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3),
1144 GFP_KERNEL);
1145 if (!lookup)
1146 return -ENOMEM;
1147
1148 lookup->dev_id = "i2c-gpio";
1149 if (iic->pin_sda < 32)
1150 lookup->table[0].chip_label = "SM501-LOW";
1151 else
1152 lookup->table[0].chip_label = "SM501-HIGH";
1153 lookup->table[0].chip_hwnum = iic->pin_sda % 32;
1154 lookup->table[0].con_id = NULL;
1155 lookup->table[0].idx = 0;
1156 lookup->table[0].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN;
1157 if (iic->pin_scl < 32)
1158 lookup->table[1].chip_label = "SM501-LOW";
1159 else
1160 lookup->table[1].chip_label = "SM501-HIGH";
1161 lookup->table[1].chip_hwnum = iic->pin_scl % 32;
1162 lookup->table[1].con_id = NULL;
1163 lookup->table[1].idx = 1;
1164 lookup->table[1].flags = GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN;
1165 gpiod_add_lookup_table(lookup);
1166
1167 icd = dev_get_platdata(&pdev->dev);
1168 icd->timeout = iic->timeout;
1169 icd->udelay = iic->udelay;
1170
1171 /* note, we can't use either of the pin numbers, as the i2c-gpio
1172 * driver uses the platform.id field to generate the bus number
1173 * to register with the i2c core; The i2c core doesn't have enough
1174 * entries to deal with anything we currently use.
1175 */
1176
1177 pdev->id = iic->bus_num;
1178
1179 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",
1180 iic->bus_num,
1181 iic->pin_sda, iic->pin_scl);
1182
1183 return sm501_register_device(sm, pdev);
1184}
1185
1186static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1187 struct sm501_platdata *pdata)
1188{
1189 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1190 int index;
1191 int ret;
1192
1193 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1194 ret = sm501_register_gpio_i2c_instance(sm, iic);
1195 if (ret < 0)
1196 return ret;
1197 }
1198
1199 return 0;
1200}
1201
1202/* sm501_dbg_regs
1203 *
1204 * Debug attribute to attach to parent device to show core registers
1205*/
1206
1207static ssize_t sm501_dbg_regs(struct device *dev,
1208 struct device_attribute *attr, char *buff)
1209{
1210 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1211 unsigned int reg;
1212 char *ptr = buff;
1213 int ret;
1214
1215 for (reg = 0x00; reg < 0x70; reg += 4) {
1216 ret = sprintf(ptr, "%08x = %08x\n",
1217 reg, smc501_readl(sm->regs + reg));
1218 ptr += ret;
1219 }
1220
1221 return ptr - buff;
1222}
1223
1224
1225static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL);
1226
1227/* sm501_init_reg
1228 *
1229 * Helper function for the init code to setup a register
1230 *
1231 * clear the bits which are set in r->mask, and then set
1232 * the bits set in r->set.
1233*/
1234
1235static inline void sm501_init_reg(struct sm501_devdata *sm,
1236 unsigned long reg,
1237 struct sm501_reg_init *r)
1238{
1239 unsigned long tmp;
1240
1241 tmp = smc501_readl(sm->regs + reg);
1242 tmp &= ~r->mask;
1243 tmp |= r->set;
1244 smc501_writel(tmp, sm->regs + reg);
1245}
1246
1247/* sm501_init_regs
1248 *
1249 * Setup core register values
1250*/
1251
1252static void sm501_init_regs(struct sm501_devdata *sm,
1253 struct sm501_initdata *init)
1254{
1255 sm501_misc_control(sm->dev,
1256 init->misc_control.set,
1257 init->misc_control.mask);
1258
1259 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1260 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1261 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1262
1263 if (init->m1xclk) {
1264 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1265 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1266 }
1267
1268 if (init->mclk) {
1269 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1270 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1271 }
1272
1273}
1274
1275/* Check the PLL sources for the M1CLK and M1XCLK
1276 *
1277 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1278 * there is a risk (see errata AB-5) that the SM501 will cease proper
1279 * function. If this happens, then it is likely the SM501 will
1280 * hang the system.
1281*/
1282
1283static int sm501_check_clocks(struct sm501_devdata *sm)
1284{
1285 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1286 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1287 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1288
1289 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1290}
1291
1292static unsigned int sm501_mem_local[] = {
1293 [0] = 4*1024*1024,
1294 [1] = 8*1024*1024,
1295 [2] = 16*1024*1024,
1296 [3] = 32*1024*1024,
1297 [4] = 64*1024*1024,
1298 [5] = 2*1024*1024,
1299};
1300
1301/* sm501_init_dev
1302 *
1303 * Common init code for an SM501
1304*/
1305
1306static int sm501_init_dev(struct sm501_devdata *sm)
1307{
1308 struct sm501_initdata *idata;
1309 struct sm501_platdata *pdata;
1310 resource_size_t mem_avail;
1311 unsigned long dramctrl;
1312 unsigned long devid;
1313 int ret;
1314
1315 mutex_init(&sm->clock_lock);
1316 spin_lock_init(&sm->reg_lock);
1317
1318 INIT_LIST_HEAD(&sm->devices);
1319
1320 devid = smc501_readl(sm->regs + SM501_DEVICEID);
1321
1322 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1323 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1324 return -EINVAL;
1325 }
1326
1327 /* disable irqs */
1328 smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1329
1330 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1331 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1332
1333 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1334 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1335
1336 sm->rev = devid & SM501_DEVICEID_REVMASK;
1337
1338 sm501_dump_gate(sm);
1339
1340 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1341 if (ret)
1342 dev_err(sm->dev, "failed to create debug regs file\n");
1343
1344 sm501_dump_clk(sm);
1345
1346 /* check to see if we have some device initialisation */
1347
1348 pdata = sm->platdata;
1349 idata = pdata ? pdata->init : NULL;
1350
1351 if (idata) {
1352 sm501_init_regs(sm, idata);
1353
1354 if (idata->devices & SM501_USE_USB_HOST)
1355 sm501_register_usbhost(sm, &mem_avail);
1356 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1357 sm501_register_uart(sm, idata->devices);
1358 if (idata->devices & SM501_USE_GPIO)
1359 sm501_register_gpio(sm);
1360 }
1361
1362 if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) {
1363 if (!sm501_gpio_isregistered(sm))
1364 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1365 else
1366 sm501_register_gpio_i2c(sm, pdata);
1367 }
1368
1369 ret = sm501_check_clocks(sm);
1370 if (ret) {
1371 dev_err(sm->dev, "M1X and M clocks sourced from different "
1372 "PLLs\n");
1373 return -EINVAL;
1374 }
1375
1376 /* always create a framebuffer */
1377 sm501_register_display(sm, &mem_avail);
1378
1379 return 0;
1380}
1381
1382static int sm501_plat_probe(struct platform_device *dev)
1383{
1384 struct sm501_devdata *sm;
1385 int ret;
1386
1387 sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1388 if (!sm) {
1389 ret = -ENOMEM;
1390 goto err1;
1391 }
1392
1393 sm->dev = &dev->dev;
1394 sm->pdev_id = dev->id;
1395 sm->platdata = dev_get_platdata(&dev->dev);
1396
1397 ret = platform_get_irq(dev, 0);
1398 if (ret < 0)
1399 goto err_res;
1400 sm->irq = ret;
1401
1402 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1403 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1404 if (!sm->io_res || !sm->mem_res) {
1405 dev_err(&dev->dev, "failed to get IO resource\n");
1406 ret = -ENOENT;
1407 goto err_res;
1408 }
1409
1410 sm->regs_claim = request_mem_region(sm->io_res->start,
1411 0x100, "sm501");
1412 if (!sm->regs_claim) {
1413 dev_err(&dev->dev, "cannot claim registers\n");
1414 ret = -EBUSY;
1415 goto err_res;
1416 }
1417
1418 platform_set_drvdata(dev, sm);
1419
1420 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1421 if (!sm->regs) {
1422 dev_err(&dev->dev, "cannot remap registers\n");
1423 ret = -EIO;
1424 goto err_claim;
1425 }
1426
1427 return sm501_init_dev(sm);
1428
1429 err_claim:
1430 release_resource(sm->regs_claim);
1431 kfree(sm->regs_claim);
1432 err_res:
1433 kfree(sm);
1434 err1:
1435 return ret;
1436
1437}
1438
1439#ifdef CONFIG_PM
1440
1441/* power management support */
1442
1443static void sm501_set_power(struct sm501_devdata *sm, int on)
1444{
1445 struct sm501_platdata *pd = sm->platdata;
1446
1447 if (!pd)
1448 return;
1449
1450 if (pd->get_power) {
1451 if (pd->get_power(sm->dev) == on) {
1452 dev_dbg(sm->dev, "is already %d\n", on);
1453 return;
1454 }
1455 }
1456
1457 if (pd->set_power) {
1458 dev_dbg(sm->dev, "setting power to %d\n", on);
1459
1460 pd->set_power(sm->dev, on);
1461 sm501_mdelay(sm, 10);
1462 }
1463}
1464
1465static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1466{
1467 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1468
1469 sm->in_suspend = 1;
1470 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1471
1472 sm501_dump_regs(sm);
1473
1474 if (sm->platdata) {
1475 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1476 sm501_set_power(sm, 0);
1477 }
1478
1479 return 0;
1480}
1481
1482static int sm501_plat_resume(struct platform_device *pdev)
1483{
1484 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1485
1486 sm501_set_power(sm, 1);
1487
1488 sm501_dump_regs(sm);
1489 sm501_dump_gate(sm);
1490 sm501_dump_clk(sm);
1491
1492 /* check to see if we are in the same state as when suspended */
1493
1494 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1495 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1496 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1497
1498 /* our suspend causes the controller state to change,
1499 * either by something attempting setup, power loss,
1500 * or an external reset event on power change */
1501
1502 if (sm->platdata && sm->platdata->init) {
1503 sm501_init_regs(sm, sm->platdata->init);
1504 }
1505 }
1506
1507 /* dump our state from resume */
1508
1509 sm501_dump_regs(sm);
1510 sm501_dump_clk(sm);
1511
1512 sm->in_suspend = 0;
1513
1514 return 0;
1515}
1516#else
1517#define sm501_plat_suspend NULL
1518#define sm501_plat_resume NULL
1519#endif
1520
1521/* Initialisation data for PCI devices */
1522
1523static struct sm501_initdata sm501_pci_initdata = {
1524 .gpio_high = {
1525 .set = 0x3F000000, /* 24bit panel */
1526 .mask = 0x0,
1527 },
1528 .misc_timing = {
1529 .set = 0x010100, /* SDRAM timing */
1530 .mask = 0x1F1F00,
1531 },
1532 .misc_control = {
1533 .set = SM501_MISC_PNL_24BIT,
1534 .mask = 0,
1535 },
1536
1537 .devices = SM501_USE_ALL,
1538
1539 /* Errata AB-3 says that 72MHz is the fastest available
1540 * for 33MHZ PCI with proper bus-mastering operation */
1541
1542 .mclk = 72 * MHZ,
1543 .m1xclk = 144 * MHZ,
1544};
1545
1546static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1547 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1548 SM501FB_FLAG_USE_HWCURSOR |
1549 SM501FB_FLAG_USE_HWACCEL |
1550 SM501FB_FLAG_DISABLE_AT_EXIT),
1551};
1552
1553static struct sm501_platdata_fb sm501_fb_pdata = {
1554 .fb_route = SM501_FB_OWN,
1555 .fb_crt = &sm501_pdata_fbsub,
1556 .fb_pnl = &sm501_pdata_fbsub,
1557};
1558
1559static struct sm501_platdata sm501_pci_platdata = {
1560 .init = &sm501_pci_initdata,
1561 .fb = &sm501_fb_pdata,
1562 .gpio_base = -1,
1563};
1564
1565static int sm501_pci_probe(struct pci_dev *dev,
1566 const struct pci_device_id *id)
1567{
1568 struct sm501_devdata *sm;
1569 int err;
1570
1571 sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1572 if (!sm) {
1573 err = -ENOMEM;
1574 goto err1;
1575 }
1576
1577 /* set a default set of platform data */
1578 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1579
1580 /* set a hopefully unique id for our child platform devices */
1581 sm->pdev_id = 32 + dev->devfn;
1582
1583 pci_set_drvdata(dev, sm);
1584
1585 err = pci_enable_device(dev);
1586 if (err) {
1587 dev_err(&dev->dev, "cannot enable device\n");
1588 goto err2;
1589 }
1590
1591 sm->dev = &dev->dev;
1592 sm->irq = dev->irq;
1593
1594#ifdef __BIG_ENDIAN
1595 /* if the system is big-endian, we most probably have a
1596 * translation in the IO layer making the PCI bus little endian
1597 * so make the framebuffer swapped pixels */
1598
1599 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1600#endif
1601
1602 /* check our resources */
1603
1604 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1605 dev_err(&dev->dev, "region #0 is not memory?\n");
1606 err = -EINVAL;
1607 goto err3;
1608 }
1609
1610 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1611 dev_err(&dev->dev, "region #1 is not memory?\n");
1612 err = -EINVAL;
1613 goto err3;
1614 }
1615
1616 /* make our resources ready for sharing */
1617
1618 sm->io_res = &dev->resource[1];
1619 sm->mem_res = &dev->resource[0];
1620
1621 sm->regs_claim = request_mem_region(sm->io_res->start,
1622 0x100, "sm501");
1623 if (!sm->regs_claim) {
1624 dev_err(&dev->dev, "cannot claim registers\n");
1625 err= -EBUSY;
1626 goto err3;
1627 }
1628
1629 sm->regs = pci_ioremap_bar(dev, 1);
1630 if (!sm->regs) {
1631 dev_err(&dev->dev, "cannot remap registers\n");
1632 err = -EIO;
1633 goto err4;
1634 }
1635
1636 sm501_init_dev(sm);
1637 return 0;
1638
1639 err4:
1640 release_resource(sm->regs_claim);
1641 kfree(sm->regs_claim);
1642 err3:
1643 pci_disable_device(dev);
1644 err2:
1645 kfree(sm);
1646 err1:
1647 return err;
1648}
1649
1650static void sm501_remove_sub(struct sm501_devdata *sm,
1651 struct sm501_device *smdev)
1652{
1653 list_del(&smdev->list);
1654 platform_device_unregister(&smdev->pdev);
1655}
1656
1657static void sm501_dev_remove(struct sm501_devdata *sm)
1658{
1659 struct sm501_device *smdev, *tmp;
1660
1661 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1662 sm501_remove_sub(sm, smdev);
1663
1664 device_remove_file(sm->dev, &dev_attr_dbg_regs);
1665
1666 sm501_gpio_remove(sm);
1667}
1668
1669static void sm501_pci_remove(struct pci_dev *dev)
1670{
1671 struct sm501_devdata *sm = pci_get_drvdata(dev);
1672
1673 sm501_dev_remove(sm);
1674 iounmap(sm->regs);
1675
1676 release_resource(sm->regs_claim);
1677 kfree(sm->regs_claim);
1678
1679 pci_disable_device(dev);
1680}
1681
1682static int sm501_plat_remove(struct platform_device *dev)
1683{
1684 struct sm501_devdata *sm = platform_get_drvdata(dev);
1685
1686 sm501_dev_remove(sm);
1687 iounmap(sm->regs);
1688
1689 release_resource(sm->regs_claim);
1690 kfree(sm->regs_claim);
1691
1692 return 0;
1693}
1694
1695static const struct pci_device_id sm501_pci_tbl[] = {
1696 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1697 { 0, },
1698};
1699
1700MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1701
1702static struct pci_driver sm501_pci_driver = {
1703 .name = "sm501",
1704 .id_table = sm501_pci_tbl,
1705 .probe = sm501_pci_probe,
1706 .remove = sm501_pci_remove,
1707};
1708
1709MODULE_ALIAS("platform:sm501");
1710
1711static const struct of_device_id of_sm501_match_tbl[] = {
1712 { .compatible = "smi,sm501", },
1713 { /* end */ }
1714};
1715MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
1716
1717static struct platform_driver sm501_plat_driver = {
1718 .driver = {
1719 .name = "sm501",
1720 .of_match_table = of_sm501_match_tbl,
1721 },
1722 .probe = sm501_plat_probe,
1723 .remove = sm501_plat_remove,
1724 .suspend = sm501_plat_suspend,
1725 .resume = sm501_plat_resume,
1726};
1727
1728static int __init sm501_base_init(void)
1729{
1730 platform_driver_register(&sm501_plat_driver);
1731 return pci_register_driver(&sm501_pci_driver);
1732}
1733
1734static void __exit sm501_base_exit(void)
1735{
1736 platform_driver_unregister(&sm501_plat_driver);
1737 pci_unregister_driver(&sm501_pci_driver);
1738}
1739
1740module_init(sm501_base_init);
1741module_exit(sm501_base_exit);
1742
1743MODULE_DESCRIPTION("SM501 Core Driver");
1744MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1745MODULE_LICENSE("GPL v2");