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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
4 *
5 * Copyright (C) 2014 Broadcom Corporation
6 * Author: Kevin Cernekee
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/bitops.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/smp.h>
27#include <linux/types.h>
28#include <linux/irqchip.h>
29#include <linux/irqchip/chained_irq.h>
30
31#define IRQS_PER_WORD 32
32#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
33#define MAX_WORDS 8
34
35struct bcm7038_l1_cpu;
36
37struct bcm7038_l1_chip {
38 raw_spinlock_t lock;
39 unsigned int n_words;
40 struct irq_domain *domain;
41 struct bcm7038_l1_cpu *cpus[NR_CPUS];
42 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
43};
44
45struct bcm7038_l1_cpu {
46 void __iomem *map_base;
47 u32 mask_cache[0];
48};
49
50/*
51 * STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
52 *
53 * 7038:
54 * 0x1000_1400: W0_STATUS
55 * 0x1000_1404: W1_STATUS
56 * 0x1000_1408: W0_MASK_STATUS
57 * 0x1000_140c: W1_MASK_STATUS
58 * 0x1000_1410: W0_MASK_SET
59 * 0x1000_1414: W1_MASK_SET
60 * 0x1000_1418: W0_MASK_CLEAR
61 * 0x1000_141c: W1_MASK_CLEAR
62 *
63 * 7445:
64 * 0xf03e_1500: W0_STATUS
65 * 0xf03e_1504: W1_STATUS
66 * 0xf03e_1508: W2_STATUS
67 * 0xf03e_150c: W3_STATUS
68 * 0xf03e_1510: W4_STATUS
69 * 0xf03e_1514: W0_MASK_STATUS
70 * 0xf03e_1518: W1_MASK_STATUS
71 * [...]
72 */
73
74static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
75 unsigned int word)
76{
77 return (0 * intc->n_words + word) * sizeof(u32);
78}
79
80static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
81 unsigned int word)
82{
83 return (1 * intc->n_words + word) * sizeof(u32);
84}
85
86static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
87 unsigned int word)
88{
89 return (2 * intc->n_words + word) * sizeof(u32);
90}
91
92static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
93 unsigned int word)
94{
95 return (3 * intc->n_words + word) * sizeof(u32);
96}
97
98static inline u32 l1_readl(void __iomem *reg)
99{
100 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
101 return ioread32be(reg);
102 else
103 return readl(reg);
104}
105
106static inline void l1_writel(u32 val, void __iomem *reg)
107{
108 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
109 iowrite32be(val, reg);
110 else
111 writel(val, reg);
112}
113
114static void bcm7038_l1_irq_handle(struct irq_desc *desc)
115{
116 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
117 struct bcm7038_l1_cpu *cpu;
118 struct irq_chip *chip = irq_desc_get_chip(desc);
119 unsigned int idx;
120
121#ifdef CONFIG_SMP
122 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
123#else
124 cpu = intc->cpus[0];
125#endif
126
127 chained_irq_enter(chip, desc);
128
129 for (idx = 0; idx < intc->n_words; idx++) {
130 int base = idx * IRQS_PER_WORD;
131 unsigned long pending, flags;
132 int hwirq;
133
134 raw_spin_lock_irqsave(&intc->lock, flags);
135 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
136 ~cpu->mask_cache[idx];
137 raw_spin_unlock_irqrestore(&intc->lock, flags);
138
139 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
140 generic_handle_irq(irq_find_mapping(intc->domain,
141 base + hwirq));
142 }
143 }
144
145 chained_irq_exit(chip, desc);
146}
147
148static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
149{
150 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
151 u32 word = d->hwirq / IRQS_PER_WORD;
152 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
153
154 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
155 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
156 reg_mask_clr(intc, word));
157}
158
159static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
160{
161 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
162 u32 word = d->hwirq / IRQS_PER_WORD;
163 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
164
165 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
166 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
167 reg_mask_set(intc, word));
168}
169
170static void bcm7038_l1_unmask(struct irq_data *d)
171{
172 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
173 unsigned long flags;
174
175 raw_spin_lock_irqsave(&intc->lock, flags);
176 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
177 raw_spin_unlock_irqrestore(&intc->lock, flags);
178}
179
180static void bcm7038_l1_mask(struct irq_data *d)
181{
182 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
183 unsigned long flags;
184
185 raw_spin_lock_irqsave(&intc->lock, flags);
186 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
187 raw_spin_unlock_irqrestore(&intc->lock, flags);
188}
189
190static int bcm7038_l1_set_affinity(struct irq_data *d,
191 const struct cpumask *dest,
192 bool force)
193{
194 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
195 unsigned long flags;
196 irq_hw_number_t hw = d->hwirq;
197 u32 word = hw / IRQS_PER_WORD;
198 u32 mask = BIT(hw % IRQS_PER_WORD);
199 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
200 bool was_disabled;
201
202 raw_spin_lock_irqsave(&intc->lock, flags);
203
204 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
205 mask);
206 __bcm7038_l1_mask(d, intc->affinity[hw]);
207 intc->affinity[hw] = first_cpu;
208 if (!was_disabled)
209 __bcm7038_l1_unmask(d, first_cpu);
210
211 raw_spin_unlock_irqrestore(&intc->lock, flags);
212 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
213
214 return 0;
215}
216
217#ifdef CONFIG_SMP
218static void bcm7038_l1_cpu_offline(struct irq_data *d)
219{
220 struct cpumask *mask = irq_data_get_affinity_mask(d);
221 int cpu = smp_processor_id();
222 cpumask_t new_affinity;
223
224 /* This CPU was not on the affinity mask */
225 if (!cpumask_test_cpu(cpu, mask))
226 return;
227
228 if (cpumask_weight(mask) > 1) {
229 /*
230 * Multiple CPU affinity, remove this CPU from the affinity
231 * mask
232 */
233 cpumask_copy(&new_affinity, mask);
234 cpumask_clear_cpu(cpu, &new_affinity);
235 } else {
236 /* Only CPU, put on the lowest online CPU */
237 cpumask_clear(&new_affinity);
238 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
239 }
240 irq_set_affinity_locked(d, &new_affinity, false);
241}
242#endif
243
244static int __init bcm7038_l1_init_one(struct device_node *dn,
245 unsigned int idx,
246 struct bcm7038_l1_chip *intc)
247{
248 struct resource res;
249 resource_size_t sz;
250 struct bcm7038_l1_cpu *cpu;
251 unsigned int i, n_words, parent_irq;
252
253 if (of_address_to_resource(dn, idx, &res))
254 return -EINVAL;
255 sz = resource_size(&res);
256 n_words = sz / REG_BYTES_PER_IRQ_WORD;
257
258 if (n_words > MAX_WORDS)
259 return -EINVAL;
260 else if (!intc->n_words)
261 intc->n_words = n_words;
262 else if (intc->n_words != n_words)
263 return -EINVAL;
264
265 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
266 GFP_KERNEL);
267 if (!cpu)
268 return -ENOMEM;
269
270 cpu->map_base = ioremap(res.start, sz);
271 if (!cpu->map_base)
272 return -ENOMEM;
273
274 for (i = 0; i < n_words; i++) {
275 l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
276 cpu->mask_cache[i] = 0xffffffff;
277 }
278
279 parent_irq = irq_of_parse_and_map(dn, idx);
280 if (!parent_irq) {
281 pr_err("failed to map parent interrupt %d\n", parent_irq);
282 return -EINVAL;
283 }
284 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
285 intc);
286
287 return 0;
288}
289
290static struct irq_chip bcm7038_l1_irq_chip = {
291 .name = "bcm7038-l1",
292 .irq_mask = bcm7038_l1_mask,
293 .irq_unmask = bcm7038_l1_unmask,
294 .irq_set_affinity = bcm7038_l1_set_affinity,
295#ifdef CONFIG_SMP
296 .irq_cpu_offline = bcm7038_l1_cpu_offline,
297#endif
298};
299
300static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
301 irq_hw_number_t hw_irq)
302{
303 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
304 irq_set_chip_data(virq, d->host_data);
305 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
306 return 0;
307}
308
309static const struct irq_domain_ops bcm7038_l1_domain_ops = {
310 .xlate = irq_domain_xlate_onecell,
311 .map = bcm7038_l1_map,
312};
313
314int __init bcm7038_l1_of_init(struct device_node *dn,
315 struct device_node *parent)
316{
317 struct bcm7038_l1_chip *intc;
318 int idx, ret;
319
320 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
321 if (!intc)
322 return -ENOMEM;
323
324 raw_spin_lock_init(&intc->lock);
325 for_each_possible_cpu(idx) {
326 ret = bcm7038_l1_init_one(dn, idx, intc);
327 if (ret < 0) {
328 if (idx)
329 break;
330 pr_err("failed to remap intc L1 registers\n");
331 goto out_free;
332 }
333 }
334
335 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
336 &bcm7038_l1_domain_ops,
337 intc);
338 if (!intc->domain) {
339 ret = -ENOMEM;
340 goto out_unmap;
341 }
342
343 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
344 dn, IRQS_PER_WORD * intc->n_words);
345
346 return 0;
347
348out_unmap:
349 for_each_possible_cpu(idx) {
350 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
351
352 if (cpu) {
353 if (cpu->map_base)
354 iounmap(cpu->map_base);
355 kfree(cpu);
356 }
357 }
358out_free:
359 kfree(intc);
360 return ret;
361}
362
363IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);