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1/*
2 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
3 * (http://www.opencores.org/projects.cgi/web/i2c/overview).
4 *
5 * Peter Korsgaard <jacmet@sunsite.dk>
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/*
13 * Device tree configuration:
14 *
15 * Required properties:
16 * - compatible : "opencores,i2c-ocores"
17 * - reg : bus address start and address range size of device
18 * - interrupts : interrupt number
19 * - regstep : size of device registers in bytes
20 * - clock-frequency : frequency of bus clock in Hz
21 *
22 * Example:
23 *
24 * i2c0: ocores@a0000000 {
25 * compatible = "opencores,i2c-ocores";
26 * reg = <0xa0000000 0x8>;
27 * interrupts = <10>;
28 *
29 * regstep = <1>;
30 * clock-frequency = <20000000>;
31 *
32 * -- Devices connected on this I2C bus get
33 * -- defined here; address- and size-cells
34 * -- apply to these child devices
35 *
36 * #address-cells = <1>;
37 * #size-cells = <0>;
38 *
39 * dummy@60 {
40 * compatible = "dummy";
41 * reg = <60>;
42 * };
43 * };
44 *
45 */
46
47#include <linux/kernel.h>
48#include <linux/module.h>
49#include <linux/init.h>
50#include <linux/errno.h>
51#include <linux/platform_device.h>
52#include <linux/i2c.h>
53#include <linux/interrupt.h>
54#include <linux/wait.h>
55#include <linux/i2c-ocores.h>
56#include <linux/slab.h>
57#include <linux/io.h>
58
59struct ocores_i2c {
60 void __iomem *base;
61 int regstep;
62 wait_queue_head_t wait;
63 struct i2c_adapter adap;
64 struct i2c_msg *msg;
65 int pos;
66 int nmsgs;
67 int state; /* see STATE_ */
68 int clock_khz;
69};
70
71/* registers */
72#define OCI2C_PRELOW 0
73#define OCI2C_PREHIGH 1
74#define OCI2C_CONTROL 2
75#define OCI2C_DATA 3
76#define OCI2C_CMD 4 /* write only */
77#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
78
79#define OCI2C_CTRL_IEN 0x40
80#define OCI2C_CTRL_EN 0x80
81
82#define OCI2C_CMD_START 0x91
83#define OCI2C_CMD_STOP 0x41
84#define OCI2C_CMD_READ 0x21
85#define OCI2C_CMD_WRITE 0x11
86#define OCI2C_CMD_READ_ACK 0x21
87#define OCI2C_CMD_READ_NACK 0x29
88#define OCI2C_CMD_IACK 0x01
89
90#define OCI2C_STAT_IF 0x01
91#define OCI2C_STAT_TIP 0x02
92#define OCI2C_STAT_ARBLOST 0x20
93#define OCI2C_STAT_BUSY 0x40
94#define OCI2C_STAT_NACK 0x80
95
96#define STATE_DONE 0
97#define STATE_START 1
98#define STATE_WRITE 2
99#define STATE_READ 3
100#define STATE_ERROR 4
101
102static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
103{
104 iowrite8(value, i2c->base + reg * i2c->regstep);
105}
106
107static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
108{
109 return ioread8(i2c->base + reg * i2c->regstep);
110}
111
112static void ocores_process(struct ocores_i2c *i2c)
113{
114 struct i2c_msg *msg = i2c->msg;
115 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
116
117 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
118 /* stop has been sent */
119 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
120 wake_up(&i2c->wait);
121 return;
122 }
123
124 /* error? */
125 if (stat & OCI2C_STAT_ARBLOST) {
126 i2c->state = STATE_ERROR;
127 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
128 return;
129 }
130
131 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
132 i2c->state =
133 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
134
135 if (stat & OCI2C_STAT_NACK) {
136 i2c->state = STATE_ERROR;
137 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
138 return;
139 }
140 } else
141 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
142
143 /* end of msg? */
144 if (i2c->pos == msg->len) {
145 i2c->nmsgs--;
146 i2c->msg++;
147 i2c->pos = 0;
148 msg = i2c->msg;
149
150 if (i2c->nmsgs) { /* end? */
151 /* send start? */
152 if (!(msg->flags & I2C_M_NOSTART)) {
153 u8 addr = (msg->addr << 1);
154
155 if (msg->flags & I2C_M_RD)
156 addr |= 1;
157
158 i2c->state = STATE_START;
159
160 oc_setreg(i2c, OCI2C_DATA, addr);
161 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
162 return;
163 } else
164 i2c->state = (msg->flags & I2C_M_RD)
165 ? STATE_READ : STATE_WRITE;
166 } else {
167 i2c->state = STATE_DONE;
168 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
169 return;
170 }
171 }
172
173 if (i2c->state == STATE_READ) {
174 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
175 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
176 } else {
177 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
178 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
179 }
180}
181
182static irqreturn_t ocores_isr(int irq, void *dev_id)
183{
184 struct ocores_i2c *i2c = dev_id;
185
186 ocores_process(i2c);
187
188 return IRQ_HANDLED;
189}
190
191static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
192{
193 struct ocores_i2c *i2c = i2c_get_adapdata(adap);
194
195 i2c->msg = msgs;
196 i2c->pos = 0;
197 i2c->nmsgs = num;
198 i2c->state = STATE_START;
199
200 oc_setreg(i2c, OCI2C_DATA,
201 (i2c->msg->addr << 1) |
202 ((i2c->msg->flags & I2C_M_RD) ? 1:0));
203
204 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
205
206 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
207 (i2c->state == STATE_DONE), HZ))
208 return (i2c->state == STATE_DONE) ? num : -EIO;
209 else
210 return -ETIMEDOUT;
211}
212
213static void ocores_init(struct ocores_i2c *i2c)
214{
215 int prescale;
216 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
217
218 /* make sure the device is disabled */
219 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
220
221 prescale = (i2c->clock_khz / (5*100)) - 1;
222 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
223 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
224
225 /* Init the device */
226 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
227 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
228}
229
230
231static u32 ocores_func(struct i2c_adapter *adap)
232{
233 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
234}
235
236static const struct i2c_algorithm ocores_algorithm = {
237 .master_xfer = ocores_xfer,
238 .functionality = ocores_func,
239};
240
241static struct i2c_adapter ocores_adapter = {
242 .owner = THIS_MODULE,
243 .name = "i2c-ocores",
244 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
245 .algo = &ocores_algorithm,
246};
247
248#ifdef CONFIG_OF
249static int ocores_i2c_of_probe(struct platform_device* pdev,
250 struct ocores_i2c* i2c)
251{
252 const __be32* val;
253
254 val = of_get_property(pdev->dev.of_node, "regstep", NULL);
255 if (!val) {
256 dev_err(&pdev->dev, "Missing required parameter 'regstep'");
257 return -ENODEV;
258 }
259 i2c->regstep = be32_to_cpup(val);
260
261 val = of_get_property(pdev->dev.of_node, "clock-frequency", NULL);
262 if (!val) {
263 dev_err(&pdev->dev,
264 "Missing required parameter 'clock-frequency'");
265 return -ENODEV;
266 }
267 i2c->clock_khz = be32_to_cpup(val) / 1000;
268
269 return 0;
270}
271#else
272#define ocores_i2c_of_probe(pdev,i2c) -ENODEV
273#endif
274
275static int __devinit ocores_i2c_probe(struct platform_device *pdev)
276{
277 struct ocores_i2c *i2c;
278 struct ocores_i2c_platform_data *pdata;
279 struct resource *res, *res2;
280 int ret;
281 int i;
282
283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
284 if (!res)
285 return -ENODEV;
286
287 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
288 if (!res2)
289 return -ENODEV;
290
291 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
292 if (!i2c)
293 return -ENOMEM;
294
295 if (!devm_request_mem_region(&pdev->dev, res->start,
296 resource_size(res), pdev->name)) {
297 dev_err(&pdev->dev, "Memory region busy\n");
298 return -EBUSY;
299 }
300
301 i2c->base = devm_ioremap_nocache(&pdev->dev, res->start,
302 resource_size(res));
303 if (!i2c->base) {
304 dev_err(&pdev->dev, "Unable to map registers\n");
305 return -EIO;
306 }
307
308 pdata = pdev->dev.platform_data;
309 if (pdata) {
310 i2c->regstep = pdata->regstep;
311 i2c->clock_khz = pdata->clock_khz;
312 } else {
313 ret = ocores_i2c_of_probe(pdev, i2c);
314 if (ret)
315 return ret;
316 }
317
318 ocores_init(i2c);
319
320 init_waitqueue_head(&i2c->wait);
321 ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0,
322 pdev->name, i2c);
323 if (ret) {
324 dev_err(&pdev->dev, "Cannot claim IRQ\n");
325 return ret;
326 }
327
328 /* hook up driver to tree */
329 platform_set_drvdata(pdev, i2c);
330 i2c->adap = ocores_adapter;
331 i2c_set_adapdata(&i2c->adap, i2c);
332 i2c->adap.dev.parent = &pdev->dev;
333 i2c->adap.dev.of_node = pdev->dev.of_node;
334
335 /* add i2c adapter to i2c tree */
336 ret = i2c_add_adapter(&i2c->adap);
337 if (ret) {
338 dev_err(&pdev->dev, "Failed to add adapter\n");
339 return ret;
340 }
341
342 /* add in known devices to the bus */
343 if (pdata) {
344 for (i = 0; i < pdata->num_devices; i++)
345 i2c_new_device(&i2c->adap, pdata->devices + i);
346 }
347
348 return 0;
349}
350
351static int __devexit ocores_i2c_remove(struct platform_device* pdev)
352{
353 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
354
355 /* disable i2c logic */
356 oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
357 & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
358
359 /* remove adapter & data */
360 i2c_del_adapter(&i2c->adap);
361 platform_set_drvdata(pdev, NULL);
362
363 return 0;
364}
365
366#ifdef CONFIG_PM
367static int ocores_i2c_suspend(struct platform_device *pdev, pm_message_t state)
368{
369 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
370 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
371
372 /* make sure the device is disabled */
373 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
374
375 return 0;
376}
377
378static int ocores_i2c_resume(struct platform_device *pdev)
379{
380 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
381
382 ocores_init(i2c);
383
384 return 0;
385}
386#else
387#define ocores_i2c_suspend NULL
388#define ocores_i2c_resume NULL
389#endif
390
391static struct of_device_id ocores_i2c_match[] = {
392 { .compatible = "opencores,i2c-ocores", },
393 {},
394};
395MODULE_DEVICE_TABLE(of, ocores_i2c_match);
396
397/* work with hotplug and coldplug */
398MODULE_ALIAS("platform:ocores-i2c");
399
400static struct platform_driver ocores_i2c_driver = {
401 .probe = ocores_i2c_probe,
402 .remove = __devexit_p(ocores_i2c_remove),
403 .suspend = ocores_i2c_suspend,
404 .resume = ocores_i2c_resume,
405 .driver = {
406 .owner = THIS_MODULE,
407 .name = "ocores-i2c",
408 .of_match_table = ocores_i2c_match,
409 },
410};
411
412static int __init ocores_i2c_init(void)
413{
414 return platform_driver_register(&ocores_i2c_driver);
415}
416
417static void __exit ocores_i2c_exit(void)
418{
419 platform_driver_unregister(&ocores_i2c_driver);
420}
421
422module_init(ocores_i2c_init);
423module_exit(ocores_i2c_exit);
424
425MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
426MODULE_DESCRIPTION("OpenCores I2C bus driver");
427MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/project/i2c/overview)
5 *
6 * Peter Korsgaard <peter@korsgaard.com>
7 *
8 * Support for the GRLIB port of the controller by
9 * Andreas Larsson <andreas@gaisler.com>
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/errno.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/interrupt.h>
21#include <linux/wait.h>
22#include <linux/platform_data/i2c-ocores.h>
23#include <linux/slab.h>
24#include <linux/io.h>
25#include <linux/log2.h>
26#include <linux/spinlock.h>
27#include <linux/jiffies.h>
28
29/*
30 * 'process_lock' exists because ocores_process() and ocores_process_timeout()
31 * can't run in parallel.
32 */
33struct ocores_i2c {
34 void __iomem *base;
35 int iobase;
36 u32 reg_shift;
37 u32 reg_io_width;
38 unsigned long flags;
39 wait_queue_head_t wait;
40 struct i2c_adapter adap;
41 struct i2c_msg *msg;
42 int pos;
43 int nmsgs;
44 int state; /* see STATE_ */
45 spinlock_t process_lock;
46 struct clk *clk;
47 int ip_clock_khz;
48 int bus_clock_khz;
49 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
50 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
51};
52
53/* registers */
54#define OCI2C_PRELOW 0
55#define OCI2C_PREHIGH 1
56#define OCI2C_CONTROL 2
57#define OCI2C_DATA 3
58#define OCI2C_CMD 4 /* write only */
59#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
60
61#define OCI2C_CTRL_IEN 0x40
62#define OCI2C_CTRL_EN 0x80
63
64#define OCI2C_CMD_START 0x91
65#define OCI2C_CMD_STOP 0x41
66#define OCI2C_CMD_READ 0x21
67#define OCI2C_CMD_WRITE 0x11
68#define OCI2C_CMD_READ_ACK 0x21
69#define OCI2C_CMD_READ_NACK 0x29
70#define OCI2C_CMD_IACK 0x01
71
72#define OCI2C_STAT_IF 0x01
73#define OCI2C_STAT_TIP 0x02
74#define OCI2C_STAT_ARBLOST 0x20
75#define OCI2C_STAT_BUSY 0x40
76#define OCI2C_STAT_NACK 0x80
77
78#define STATE_DONE 0
79#define STATE_START 1
80#define STATE_WRITE 2
81#define STATE_READ 3
82#define STATE_ERROR 4
83
84#define TYPE_OCORES 0
85#define TYPE_GRLIB 1
86#define TYPE_SIFIVE_REV0 2
87
88#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
89
90static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
91{
92 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
93}
94
95static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
96{
97 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
98}
99
100static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
101{
102 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
103}
104
105static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
106{
107 iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
108}
109
110static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
111{
112 iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
113}
114
115static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
116{
117 return ioread8(i2c->base + (reg << i2c->reg_shift));
118}
119
120static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
121{
122 return ioread16(i2c->base + (reg << i2c->reg_shift));
123}
124
125static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
126{
127 return ioread32(i2c->base + (reg << i2c->reg_shift));
128}
129
130static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
131{
132 return ioread16be(i2c->base + (reg << i2c->reg_shift));
133}
134
135static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
136{
137 return ioread32be(i2c->base + (reg << i2c->reg_shift));
138}
139
140static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
141{
142 outb(value, i2c->iobase + reg);
143}
144
145static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
146{
147 return inb(i2c->iobase + reg);
148}
149
150static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
151{
152 i2c->setreg(i2c, reg, value);
153}
154
155static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
156{
157 return i2c->getreg(i2c, reg);
158}
159
160static void ocores_process(struct ocores_i2c *i2c, u8 stat)
161{
162 struct i2c_msg *msg = i2c->msg;
163 unsigned long flags;
164
165 /*
166 * If we spin here is because we are in timeout, so we are going
167 * to be in STATE_ERROR. See ocores_process_timeout()
168 */
169 spin_lock_irqsave(&i2c->process_lock, flags);
170
171 if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
172 /* stop has been sent */
173 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
174 wake_up(&i2c->wait);
175 goto out;
176 }
177
178 /* error? */
179 if (stat & OCI2C_STAT_ARBLOST) {
180 i2c->state = STATE_ERROR;
181 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
182 goto out;
183 }
184
185 if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
186 i2c->state =
187 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
188
189 if (stat & OCI2C_STAT_NACK) {
190 i2c->state = STATE_ERROR;
191 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
192 goto out;
193 }
194 } else {
195 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
196 }
197
198 /* end of msg? */
199 if (i2c->pos == msg->len) {
200 i2c->nmsgs--;
201 i2c->msg++;
202 i2c->pos = 0;
203 msg = i2c->msg;
204
205 if (i2c->nmsgs) { /* end? */
206 /* send start? */
207 if (!(msg->flags & I2C_M_NOSTART)) {
208 u8 addr = i2c_8bit_addr_from_msg(msg);
209
210 i2c->state = STATE_START;
211
212 oc_setreg(i2c, OCI2C_DATA, addr);
213 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
214 goto out;
215 }
216 i2c->state = (msg->flags & I2C_M_RD)
217 ? STATE_READ : STATE_WRITE;
218 } else {
219 i2c->state = STATE_DONE;
220 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
221 goto out;
222 }
223 }
224
225 if (i2c->state == STATE_READ) {
226 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
227 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
228 } else {
229 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
230 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
231 }
232
233out:
234 spin_unlock_irqrestore(&i2c->process_lock, flags);
235}
236
237static irqreturn_t ocores_isr(int irq, void *dev_id)
238{
239 struct ocores_i2c *i2c = dev_id;
240 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
241
242 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
243 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
244 return IRQ_NONE;
245 } else if (!(stat & OCI2C_STAT_IF)) {
246 return IRQ_NONE;
247 }
248 ocores_process(i2c, stat);
249
250 return IRQ_HANDLED;
251}
252
253/**
254 * Process timeout event
255 * @i2c: ocores I2C device instance
256 */
257static void ocores_process_timeout(struct ocores_i2c *i2c)
258{
259 unsigned long flags;
260
261 spin_lock_irqsave(&i2c->process_lock, flags);
262 i2c->state = STATE_ERROR;
263 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
264 spin_unlock_irqrestore(&i2c->process_lock, flags);
265}
266
267/**
268 * Wait until something change in a given register
269 * @i2c: ocores I2C device instance
270 * @reg: register to query
271 * @mask: bitmask to apply on register value
272 * @val: expected result
273 * @timeout: timeout in jiffies
274 *
275 * Timeout is necessary to avoid to stay here forever when the chip
276 * does not answer correctly.
277 *
278 * Return: 0 on success, -ETIMEDOUT on timeout
279 */
280static int ocores_wait(struct ocores_i2c *i2c,
281 int reg, u8 mask, u8 val,
282 const unsigned long timeout)
283{
284 unsigned long j;
285
286 j = jiffies + timeout;
287 while (1) {
288 u8 status = oc_getreg(i2c, reg);
289
290 if ((status & mask) == val)
291 break;
292
293 if (time_after(jiffies, j))
294 return -ETIMEDOUT;
295 }
296 return 0;
297}
298
299/**
300 * Wait until is possible to process some data
301 * @i2c: ocores I2C device instance
302 *
303 * Used when the device is in polling mode (interrupts disabled).
304 *
305 * Return: 0 on success, -ETIMEDOUT on timeout
306 */
307static int ocores_poll_wait(struct ocores_i2c *i2c)
308{
309 u8 mask;
310 int err;
311
312 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
313 /* transfer is over */
314 mask = OCI2C_STAT_BUSY;
315 } else {
316 /* on going transfer */
317 mask = OCI2C_STAT_TIP;
318 /*
319 * We wait for the data to be transferred (8bit),
320 * then we start polling on the ACK/NACK bit
321 */
322 udelay((8 * 1000) / i2c->bus_clock_khz);
323 }
324
325 /*
326 * once we are here we expect to get the expected result immediately
327 * so if after 1ms we timeout then something is broken.
328 */
329 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
330 if (err)
331 dev_warn(i2c->adap.dev.parent,
332 "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
333 __func__, mask);
334 return err;
335}
336
337/**
338 * It handles an IRQ-less transfer
339 * @i2c: ocores I2C device instance
340 *
341 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
342 * (only that IRQ are not produced). This means that we can re-use entirely
343 * ocores_isr(), we just add our polling code around it.
344 *
345 * It can run in atomic context
346 */
347static void ocores_process_polling(struct ocores_i2c *i2c)
348{
349 while (1) {
350 irqreturn_t ret;
351 int err;
352
353 err = ocores_poll_wait(i2c);
354 if (err) {
355 i2c->state = STATE_ERROR;
356 break; /* timeout */
357 }
358
359 ret = ocores_isr(-1, i2c);
360 if (ret == IRQ_NONE)
361 break; /* all messages have been transferred */
362 else {
363 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
364 if (i2c->state == STATE_DONE)
365 break;
366 }
367 }
368}
369
370static int ocores_xfer_core(struct ocores_i2c *i2c,
371 struct i2c_msg *msgs, int num,
372 bool polling)
373{
374 int ret;
375 u8 ctrl;
376
377 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
378 if (polling)
379 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
380 else
381 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
382
383 i2c->msg = msgs;
384 i2c->pos = 0;
385 i2c->nmsgs = num;
386 i2c->state = STATE_START;
387
388 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
389 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
390
391 if (polling) {
392 ocores_process_polling(i2c);
393 } else {
394 ret = wait_event_timeout(i2c->wait,
395 (i2c->state == STATE_ERROR) ||
396 (i2c->state == STATE_DONE), HZ);
397 if (ret == 0) {
398 ocores_process_timeout(i2c);
399 return -ETIMEDOUT;
400 }
401 }
402
403 return (i2c->state == STATE_DONE) ? num : -EIO;
404}
405
406static int ocores_xfer_polling(struct i2c_adapter *adap,
407 struct i2c_msg *msgs, int num)
408{
409 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
410}
411
412static int ocores_xfer(struct i2c_adapter *adap,
413 struct i2c_msg *msgs, int num)
414{
415 return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
416}
417
418static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
419{
420 int prescale;
421 int diff;
422 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
423
424 /* make sure the device is disabled */
425 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
426 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
427
428 prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
429 prescale = clamp(prescale, 0, 0xffff);
430
431 diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
432 if (abs(diff) > i2c->bus_clock_khz / 10) {
433 dev_err(dev,
434 "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
435 i2c->ip_clock_khz, i2c->bus_clock_khz);
436 return -EINVAL;
437 }
438
439 oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
440 oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
441
442 /* Init the device */
443 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
444 oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
445
446 return 0;
447}
448
449
450static u32 ocores_func(struct i2c_adapter *adap)
451{
452 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
453}
454
455static struct i2c_algorithm ocores_algorithm = {
456 .master_xfer = ocores_xfer,
457 .master_xfer_atomic = ocores_xfer_polling,
458 .functionality = ocores_func,
459};
460
461static const struct i2c_adapter ocores_adapter = {
462 .owner = THIS_MODULE,
463 .name = "i2c-ocores",
464 .class = I2C_CLASS_DEPRECATED,
465 .algo = &ocores_algorithm,
466};
467
468static const struct of_device_id ocores_i2c_match[] = {
469 {
470 .compatible = "opencores,i2c-ocores",
471 .data = (void *)TYPE_OCORES,
472 },
473 {
474 .compatible = "aeroflexgaisler,i2cmst",
475 .data = (void *)TYPE_GRLIB,
476 },
477 {
478 .compatible = "sifive,fu540-c000-i2c",
479 .data = (void *)TYPE_SIFIVE_REV0,
480 },
481 {
482 .compatible = "sifive,i2c0",
483 .data = (void *)TYPE_SIFIVE_REV0,
484 },
485 {},
486};
487MODULE_DEVICE_TABLE(of, ocores_i2c_match);
488
489#ifdef CONFIG_OF
490/*
491 * Read and write functions for the GRLIB port of the controller. Registers are
492 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
493 * register. The subsequent registers have their offsets decreased accordingly.
494 */
495static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
496{
497 u32 rd;
498 int rreg = reg;
499
500 if (reg != OCI2C_PRELOW)
501 rreg--;
502 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
503 if (reg == OCI2C_PREHIGH)
504 return (u8)(rd >> 8);
505 else
506 return (u8)rd;
507}
508
509static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
510{
511 u32 curr, wr;
512 int rreg = reg;
513
514 if (reg != OCI2C_PRELOW)
515 rreg--;
516 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
517 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
518 if (reg == OCI2C_PRELOW)
519 wr = (curr & 0xff00) | value;
520 else
521 wr = (((u32)value) << 8) | (curr & 0xff);
522 } else {
523 wr = value;
524 }
525 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
526}
527
528static int ocores_i2c_of_probe(struct platform_device *pdev,
529 struct ocores_i2c *i2c)
530{
531 struct device_node *np = pdev->dev.of_node;
532 const struct of_device_id *match;
533 u32 val;
534 u32 clock_frequency;
535 bool clock_frequency_present;
536
537 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
538 /* no 'reg-shift', check for deprecated 'regstep' */
539 if (!of_property_read_u32(np, "regstep", &val)) {
540 if (!is_power_of_2(val)) {
541 dev_err(&pdev->dev, "invalid regstep %d\n",
542 val);
543 return -EINVAL;
544 }
545 i2c->reg_shift = ilog2(val);
546 dev_warn(&pdev->dev,
547 "regstep property deprecated, use reg-shift\n");
548 }
549 }
550
551 clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
552 &clock_frequency);
553 i2c->bus_clock_khz = 100;
554
555 i2c->clk = devm_clk_get(&pdev->dev, NULL);
556
557 if (!IS_ERR(i2c->clk)) {
558 int ret = clk_prepare_enable(i2c->clk);
559
560 if (ret) {
561 dev_err(&pdev->dev,
562 "clk_prepare_enable failed: %d\n", ret);
563 return ret;
564 }
565 i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
566 if (clock_frequency_present)
567 i2c->bus_clock_khz = clock_frequency / 1000;
568 }
569
570 if (i2c->ip_clock_khz == 0) {
571 if (of_property_read_u32(np, "opencores,ip-clock-frequency",
572 &val)) {
573 if (!clock_frequency_present) {
574 dev_err(&pdev->dev,
575 "Missing required parameter 'opencores,ip-clock-frequency'\n");
576 clk_disable_unprepare(i2c->clk);
577 return -ENODEV;
578 }
579 i2c->ip_clock_khz = clock_frequency / 1000;
580 dev_warn(&pdev->dev,
581 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
582 } else {
583 i2c->ip_clock_khz = val / 1000;
584 if (clock_frequency_present)
585 i2c->bus_clock_khz = clock_frequency / 1000;
586 }
587 }
588
589 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
590 &i2c->reg_io_width);
591
592 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
593 if (match && (long)match->data == TYPE_GRLIB) {
594 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
595 i2c->setreg = oc_setreg_grlib;
596 i2c->getreg = oc_getreg_grlib;
597 }
598
599 return 0;
600}
601#else
602#define ocores_i2c_of_probe(pdev, i2c) -ENODEV
603#endif
604
605static int ocores_i2c_probe(struct platform_device *pdev)
606{
607 struct ocores_i2c *i2c;
608 struct ocores_i2c_platform_data *pdata;
609 const struct of_device_id *match;
610 struct resource *res;
611 int irq;
612 int ret;
613 int i;
614
615 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
616 if (!i2c)
617 return -ENOMEM;
618
619 spin_lock_init(&i2c->process_lock);
620
621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
622 if (res) {
623 i2c->base = devm_ioremap_resource(&pdev->dev, res);
624 if (IS_ERR(i2c->base))
625 return PTR_ERR(i2c->base);
626 } else {
627 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
628 if (!res)
629 return -EINVAL;
630 i2c->iobase = res->start;
631 if (!devm_request_region(&pdev->dev, res->start,
632 resource_size(res),
633 pdev->name)) {
634 dev_err(&pdev->dev, "Can't get I/O resource.\n");
635 return -EBUSY;
636 }
637 i2c->setreg = oc_setreg_io_8;
638 i2c->getreg = oc_getreg_io_8;
639 }
640
641 pdata = dev_get_platdata(&pdev->dev);
642 if (pdata) {
643 i2c->reg_shift = pdata->reg_shift;
644 i2c->reg_io_width = pdata->reg_io_width;
645 i2c->ip_clock_khz = pdata->clock_khz;
646 if (pdata->bus_khz)
647 i2c->bus_clock_khz = pdata->bus_khz;
648 else
649 i2c->bus_clock_khz = 100;
650 } else {
651 ret = ocores_i2c_of_probe(pdev, i2c);
652 if (ret)
653 return ret;
654 }
655
656 if (i2c->reg_io_width == 0)
657 i2c->reg_io_width = 1; /* Set to default value */
658
659 if (!i2c->setreg || !i2c->getreg) {
660 bool be = pdata ? pdata->big_endian :
661 of_device_is_big_endian(pdev->dev.of_node);
662
663 switch (i2c->reg_io_width) {
664 case 1:
665 i2c->setreg = oc_setreg_8;
666 i2c->getreg = oc_getreg_8;
667 break;
668
669 case 2:
670 i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
671 i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
672 break;
673
674 case 4:
675 i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
676 i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
677 break;
678
679 default:
680 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
681 i2c->reg_io_width);
682 ret = -EINVAL;
683 goto err_clk;
684 }
685 }
686
687 init_waitqueue_head(&i2c->wait);
688
689 irq = platform_get_irq(pdev, 0);
690 if (irq == -ENXIO) {
691 ocores_algorithm.master_xfer = ocores_xfer_polling;
692
693 /*
694 * Set in OCORES_FLAG_BROKEN_IRQ to enable workaround for
695 * FU540-C000 SoC in polling mode.
696 */
697 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
698 if (match && (long)match->data == TYPE_SIFIVE_REV0)
699 i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
700 } else {
701 if (irq < 0)
702 return irq;
703 }
704
705 if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
706 ret = devm_request_any_context_irq(&pdev->dev, irq,
707 ocores_isr, 0,
708 pdev->name, i2c);
709 if (ret) {
710 dev_err(&pdev->dev, "Cannot claim IRQ\n");
711 goto err_clk;
712 }
713 }
714
715 ret = ocores_init(&pdev->dev, i2c);
716 if (ret)
717 goto err_clk;
718
719 /* hook up driver to tree */
720 platform_set_drvdata(pdev, i2c);
721 i2c->adap = ocores_adapter;
722 i2c_set_adapdata(&i2c->adap, i2c);
723 i2c->adap.dev.parent = &pdev->dev;
724 i2c->adap.dev.of_node = pdev->dev.of_node;
725
726 /* add i2c adapter to i2c tree */
727 ret = i2c_add_adapter(&i2c->adap);
728 if (ret)
729 goto err_clk;
730
731 /* add in known devices to the bus */
732 if (pdata) {
733 for (i = 0; i < pdata->num_devices; i++)
734 i2c_new_device(&i2c->adap, pdata->devices + i);
735 }
736
737 return 0;
738
739err_clk:
740 clk_disable_unprepare(i2c->clk);
741 return ret;
742}
743
744static int ocores_i2c_remove(struct platform_device *pdev)
745{
746 struct ocores_i2c *i2c = platform_get_drvdata(pdev);
747 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
748
749 /* disable i2c logic */
750 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
751 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
752
753 /* remove adapter & data */
754 i2c_del_adapter(&i2c->adap);
755
756 if (!IS_ERR(i2c->clk))
757 clk_disable_unprepare(i2c->clk);
758
759 return 0;
760}
761
762#ifdef CONFIG_PM_SLEEP
763static int ocores_i2c_suspend(struct device *dev)
764{
765 struct ocores_i2c *i2c = dev_get_drvdata(dev);
766 u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
767
768 /* make sure the device is disabled */
769 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
770 oc_setreg(i2c, OCI2C_CONTROL, ctrl);
771
772 if (!IS_ERR(i2c->clk))
773 clk_disable_unprepare(i2c->clk);
774 return 0;
775}
776
777static int ocores_i2c_resume(struct device *dev)
778{
779 struct ocores_i2c *i2c = dev_get_drvdata(dev);
780
781 if (!IS_ERR(i2c->clk)) {
782 unsigned long rate;
783 int ret = clk_prepare_enable(i2c->clk);
784
785 if (ret) {
786 dev_err(dev,
787 "clk_prepare_enable failed: %d\n", ret);
788 return ret;
789 }
790 rate = clk_get_rate(i2c->clk) / 1000;
791 if (rate)
792 i2c->ip_clock_khz = rate;
793 }
794 return ocores_init(dev, i2c);
795}
796
797static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
798#define OCORES_I2C_PM (&ocores_i2c_pm)
799#else
800#define OCORES_I2C_PM NULL
801#endif
802
803static struct platform_driver ocores_i2c_driver = {
804 .probe = ocores_i2c_probe,
805 .remove = ocores_i2c_remove,
806 .driver = {
807 .name = "ocores-i2c",
808 .of_match_table = ocores_i2c_match,
809 .pm = OCORES_I2C_PM,
810 },
811};
812
813module_platform_driver(ocores_i2c_driver);
814
815MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
816MODULE_DESCRIPTION("OpenCores I2C bus driver");
817MODULE_LICENSE("GPL");
818MODULE_ALIAS("platform:ocores-i2c");