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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 */
5
6/**
7 * DOC: VC4 plane module
8 *
9 * Each DRM plane is a layer of pixels being scanned out by the HVS.
10 *
11 * At atomic modeset check time, we compute the HVS display element
12 * state that would be necessary for displaying the plane (giving us a
13 * chance to figure out if a plane configuration is invalid), then at
14 * atomic flush time the CRTC will ask us to write our element state
15 * into the region of the HVS that it has allocated for us.
16 */
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_atomic_uapi.h>
21#include <drm/drm_fb_cma_helper.h>
22#include <drm/drm_fourcc.h>
23#include <drm/drm_gem_framebuffer_helper.h>
24#include <drm/drm_plane_helper.h>
25
26#include "uapi/drm/vc4_drm.h"
27
28#include "vc4_drv.h"
29#include "vc4_regs.h"
30
31static const struct hvs_format {
32 u32 drm; /* DRM_FORMAT_* */
33 u32 hvs; /* HVS_FORMAT_* */
34 u32 pixel_order;
35} hvs_formats[] = {
36 {
37 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
38 .pixel_order = HVS_PIXEL_ORDER_ABGR,
39 },
40 {
41 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
42 .pixel_order = HVS_PIXEL_ORDER_ABGR,
43 },
44 {
45 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
46 .pixel_order = HVS_PIXEL_ORDER_ARGB,
47 },
48 {
49 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
50 .pixel_order = HVS_PIXEL_ORDER_ARGB,
51 },
52 {
53 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
54 .pixel_order = HVS_PIXEL_ORDER_XRGB,
55 },
56 {
57 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
58 .pixel_order = HVS_PIXEL_ORDER_XBGR,
59 },
60 {
61 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
62 .pixel_order = HVS_PIXEL_ORDER_ABGR,
63 },
64 {
65 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
66 .pixel_order = HVS_PIXEL_ORDER_ABGR,
67 },
68 {
69 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
70 .pixel_order = HVS_PIXEL_ORDER_XRGB,
71 },
72 {
73 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
74 .pixel_order = HVS_PIXEL_ORDER_XBGR,
75 },
76 {
77 .drm = DRM_FORMAT_YUV422,
78 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
79 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
80 },
81 {
82 .drm = DRM_FORMAT_YVU422,
83 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
84 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
85 },
86 {
87 .drm = DRM_FORMAT_YUV420,
88 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
89 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
90 },
91 {
92 .drm = DRM_FORMAT_YVU420,
93 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
94 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
95 },
96 {
97 .drm = DRM_FORMAT_NV12,
98 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
99 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
100 },
101 {
102 .drm = DRM_FORMAT_NV21,
103 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
104 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
105 },
106 {
107 .drm = DRM_FORMAT_NV16,
108 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
109 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
110 },
111 {
112 .drm = DRM_FORMAT_NV61,
113 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
114 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
115 },
116};
117
118static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
119{
120 unsigned i;
121
122 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
123 if (hvs_formats[i].drm == drm_format)
124 return &hvs_formats[i];
125 }
126
127 return NULL;
128}
129
130static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
131{
132 if (dst == src)
133 return VC4_SCALING_NONE;
134 if (3 * dst >= 2 * src)
135 return VC4_SCALING_PPF;
136 else
137 return VC4_SCALING_TPZ;
138}
139
140static bool plane_enabled(struct drm_plane_state *state)
141{
142 return state->fb && state->crtc;
143}
144
145static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
146{
147 struct vc4_plane_state *vc4_state;
148
149 if (WARN_ON(!plane->state))
150 return NULL;
151
152 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
153 if (!vc4_state)
154 return NULL;
155
156 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
157 vc4_state->dlist_initialized = 0;
158
159 __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
160
161 if (vc4_state->dlist) {
162 vc4_state->dlist = kmemdup(vc4_state->dlist,
163 vc4_state->dlist_count * 4,
164 GFP_KERNEL);
165 if (!vc4_state->dlist) {
166 kfree(vc4_state);
167 return NULL;
168 }
169 vc4_state->dlist_size = vc4_state->dlist_count;
170 }
171
172 return &vc4_state->base;
173}
174
175static void vc4_plane_destroy_state(struct drm_plane *plane,
176 struct drm_plane_state *state)
177{
178 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
179 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
180
181 if (vc4_state->lbm.allocated) {
182 unsigned long irqflags;
183
184 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
185 drm_mm_remove_node(&vc4_state->lbm);
186 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
187 }
188
189 kfree(vc4_state->dlist);
190 __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
191 kfree(state);
192}
193
194/* Called during init to allocate the plane's atomic state. */
195static void vc4_plane_reset(struct drm_plane *plane)
196{
197 struct vc4_plane_state *vc4_state;
198
199 WARN_ON(plane->state);
200
201 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
202 if (!vc4_state)
203 return;
204
205 __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
206}
207
208static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
209{
210 if (vc4_state->dlist_count == vc4_state->dlist_size) {
211 u32 new_size = max(4u, vc4_state->dlist_count * 2);
212 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
213
214 if (!new_dlist)
215 return;
216 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
217
218 kfree(vc4_state->dlist);
219 vc4_state->dlist = new_dlist;
220 vc4_state->dlist_size = new_size;
221 }
222
223 vc4_state->dlist[vc4_state->dlist_count++] = val;
224}
225
226/* Returns the scl0/scl1 field based on whether the dimensions need to
227 * be up/down/non-scaled.
228 *
229 * This is a replication of a table from the spec.
230 */
231static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
232{
233 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
234
235 switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
236 case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
237 return SCALER_CTL0_SCL_H_PPF_V_PPF;
238 case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
239 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
240 case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
241 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
242 case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
243 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
244 case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
245 return SCALER_CTL0_SCL_H_PPF_V_NONE;
246 case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
247 return SCALER_CTL0_SCL_H_NONE_V_PPF;
248 case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
249 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
250 case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
251 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
252 default:
253 case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
254 /* The unity case is independently handled by
255 * SCALER_CTL0_UNITY.
256 */
257 return 0;
258 }
259}
260
261static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
262{
263 struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
264 unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay;
265 struct drm_crtc_state *crtc_state;
266
267 crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
268 pstate->crtc);
269
270 vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);
271 if (!left && !right && !top && !bottom)
272 return 0;
273
274 if (left + right >= crtc_state->mode.hdisplay ||
275 top + bottom >= crtc_state->mode.vdisplay)
276 return -EINVAL;
277
278 adjhdisplay = crtc_state->mode.hdisplay - (left + right);
279 vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x *
280 adjhdisplay,
281 crtc_state->mode.hdisplay);
282 vc4_pstate->crtc_x += left;
283 if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - left)
284 vc4_pstate->crtc_x = crtc_state->mode.hdisplay - left;
285
286 adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);
287 vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *
288 adjvdisplay,
289 crtc_state->mode.vdisplay);
290 vc4_pstate->crtc_y += top;
291 if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - top)
292 vc4_pstate->crtc_y = crtc_state->mode.vdisplay - top;
293
294 vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *
295 adjhdisplay,
296 crtc_state->mode.hdisplay);
297 vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h *
298 adjvdisplay,
299 crtc_state->mode.vdisplay);
300
301 if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h)
302 return -EINVAL;
303
304 return 0;
305}
306
307static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
308{
309 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
310 struct drm_framebuffer *fb = state->fb;
311 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
312 u32 subpixel_src_mask = (1 << 16) - 1;
313 int num_planes = fb->format->num_planes;
314 struct drm_crtc_state *crtc_state;
315 u32 h_subsample = fb->format->hsub;
316 u32 v_subsample = fb->format->vsub;
317 int i, ret;
318
319 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
320 state->crtc);
321 if (!crtc_state) {
322 DRM_DEBUG_KMS("Invalid crtc state\n");
323 return -EINVAL;
324 }
325
326 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1,
327 INT_MAX, true, true);
328 if (ret)
329 return ret;
330
331 for (i = 0; i < num_planes; i++)
332 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
333
334 /* We don't support subpixel source positioning for scaling. */
335 if ((state->src.x1 & subpixel_src_mask) ||
336 (state->src.x2 & subpixel_src_mask) ||
337 (state->src.y1 & subpixel_src_mask) ||
338 (state->src.y2 & subpixel_src_mask)) {
339 return -EINVAL;
340 }
341
342 vc4_state->src_x = state->src.x1 >> 16;
343 vc4_state->src_y = state->src.y1 >> 16;
344 vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;
345 vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;
346
347 vc4_state->crtc_x = state->dst.x1;
348 vc4_state->crtc_y = state->dst.y1;
349 vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
350 vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
351
352 ret = vc4_plane_margins_adj(state);
353 if (ret)
354 return ret;
355
356 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
357 vc4_state->crtc_w);
358 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
359 vc4_state->crtc_h);
360
361 vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
362 vc4_state->y_scaling[0] == VC4_SCALING_NONE);
363
364 if (num_planes > 1) {
365 vc4_state->is_yuv = true;
366
367 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
368 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
369
370 vc4_state->x_scaling[1] =
371 vc4_get_scaling_mode(vc4_state->src_w[1],
372 vc4_state->crtc_w);
373 vc4_state->y_scaling[1] =
374 vc4_get_scaling_mode(vc4_state->src_h[1],
375 vc4_state->crtc_h);
376
377 /* YUV conversion requires that horizontal scaling be enabled
378 * on the UV plane even if vc4_get_scaling_mode() returned
379 * VC4_SCALING_NONE (which can happen when the down-scaling
380 * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
381 * case.
382 */
383 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
384 vc4_state->x_scaling[1] = VC4_SCALING_PPF;
385 } else {
386 vc4_state->is_yuv = false;
387 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
388 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
389 }
390
391 return 0;
392}
393
394static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
395{
396 u32 scale, recip;
397
398 scale = (1 << 16) * src / dst;
399
400 /* The specs note that while the reciprocal would be defined
401 * as (1<<32)/scale, ~0 is close enough.
402 */
403 recip = ~0 / scale;
404
405 vc4_dlist_write(vc4_state,
406 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
407 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
408 vc4_dlist_write(vc4_state,
409 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
410}
411
412static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
413{
414 u32 scale = (1 << 16) * src / dst;
415
416 vc4_dlist_write(vc4_state,
417 SCALER_PPF_AGC |
418 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
419 VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
420}
421
422static u32 vc4_lbm_size(struct drm_plane_state *state)
423{
424 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
425 /* This is the worst case number. One of the two sizes will
426 * be used depending on the scaling configuration.
427 */
428 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
429 u32 lbm;
430
431 /* LBM is not needed when there's no vertical scaling. */
432 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
433 vc4_state->y_scaling[1] == VC4_SCALING_NONE)
434 return 0;
435
436 if (!vc4_state->is_yuv) {
437 if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
438 lbm = pix_per_line * 8;
439 else {
440 /* In special cases, this multiplier might be 12. */
441 lbm = pix_per_line * 16;
442 }
443 } else {
444 /* There are cases for this going down to a multiplier
445 * of 2, but according to the firmware source, the
446 * table in the docs is somewhat wrong.
447 */
448 lbm = pix_per_line * 16;
449 }
450
451 lbm = roundup(lbm, 32);
452
453 return lbm;
454}
455
456static void vc4_write_scaling_parameters(struct drm_plane_state *state,
457 int channel)
458{
459 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
460
461 /* Ch0 H-PPF Word 0: Scaling Parameters */
462 if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
463 vc4_write_ppf(vc4_state,
464 vc4_state->src_w[channel], vc4_state->crtc_w);
465 }
466
467 /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
468 if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
469 vc4_write_ppf(vc4_state,
470 vc4_state->src_h[channel], vc4_state->crtc_h);
471 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
472 }
473
474 /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
475 if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
476 vc4_write_tpz(vc4_state,
477 vc4_state->src_w[channel], vc4_state->crtc_w);
478 }
479
480 /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
481 if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
482 vc4_write_tpz(vc4_state,
483 vc4_state->src_h[channel], vc4_state->crtc_h);
484 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
485 }
486}
487
488static void vc4_plane_calc_load(struct drm_plane_state *state)
489{
490 unsigned int hvs_load_shift, vrefresh, i;
491 struct drm_framebuffer *fb = state->fb;
492 struct vc4_plane_state *vc4_state;
493 struct drm_crtc_state *crtc_state;
494 unsigned int vscale_factor;
495
496 vc4_state = to_vc4_plane_state(state);
497 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
498 state->crtc);
499 vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode);
500
501 /* The HVS is able to process 2 pixels/cycle when scaling the source,
502 * 4 pixels/cycle otherwise.
503 * Alpha blending step seems to be pipelined and it's always operating
504 * at 4 pixels/cycle, so the limiting aspect here seems to be the
505 * scaler block.
506 * HVS load is expressed in clk-cycles/sec (AKA Hz).
507 */
508 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
509 vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
510 vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
511 vc4_state->y_scaling[1] != VC4_SCALING_NONE)
512 hvs_load_shift = 1;
513 else
514 hvs_load_shift = 2;
515
516 vc4_state->membus_load = 0;
517 vc4_state->hvs_load = 0;
518 for (i = 0; i < fb->format->num_planes; i++) {
519 /* Even if the bandwidth/plane required for a single frame is
520 *
521 * vc4_state->src_w[i] * vc4_state->src_h[i] * cpp * vrefresh
522 *
523 * when downscaling, we have to read more pixels per line in
524 * the time frame reserved for a single line, so the bandwidth
525 * demand can be punctually higher. To account for that, we
526 * calculate the down-scaling factor and multiply the plane
527 * load by this number. We're likely over-estimating the read
528 * demand, but that's better than under-estimating it.
529 */
530 vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i],
531 vc4_state->crtc_h);
532 vc4_state->membus_load += vc4_state->src_w[i] *
533 vc4_state->src_h[i] * vscale_factor *
534 fb->format->cpp[i];
535 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w;
536 }
537
538 vc4_state->hvs_load *= vrefresh;
539 vc4_state->hvs_load >>= hvs_load_shift;
540 vc4_state->membus_load *= vrefresh;
541}
542
543static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
544{
545 struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
546 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
547 unsigned long irqflags;
548 u32 lbm_size;
549
550 lbm_size = vc4_lbm_size(state);
551 if (!lbm_size)
552 return 0;
553
554 if (WARN_ON(!vc4_state->lbm_offset))
555 return -EINVAL;
556
557 /* Allocate the LBM memory that the HVS will use for temporary
558 * storage due to our scaling/format conversion.
559 */
560 if (!vc4_state->lbm.allocated) {
561 int ret;
562
563 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
564 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
565 &vc4_state->lbm,
566 lbm_size, 32, 0, 0);
567 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
568
569 if (ret)
570 return ret;
571 } else {
572 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
573 }
574
575 vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start;
576
577 return 0;
578}
579
580/* Writes out a full display list for an active plane to the plane's
581 * private dlist state.
582 */
583static int vc4_plane_mode_set(struct drm_plane *plane,
584 struct drm_plane_state *state)
585{
586 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
587 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
588 struct drm_framebuffer *fb = state->fb;
589 u32 ctl0_offset = vc4_state->dlist_count;
590 const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
591 u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
592 int num_planes = fb->format->num_planes;
593 u32 h_subsample = fb->format->hsub;
594 u32 v_subsample = fb->format->vsub;
595 bool mix_plane_alpha;
596 bool covers_screen;
597 u32 scl0, scl1, pitch0;
598 u32 tiling, src_y;
599 u32 hvs_format = format->hvs;
600 unsigned int rotation;
601 int ret, i;
602
603 if (vc4_state->dlist_initialized)
604 return 0;
605
606 ret = vc4_plane_setup_clipping_and_scaling(state);
607 if (ret)
608 return ret;
609
610 /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB
611 * and 4:4:4, scl1 should be set to scl0 so both channels of
612 * the scaler do the same thing. For YUV, the Y plane needs
613 * to be put in channel 1 and Cb/Cr in channel 0, so we swap
614 * the scl fields here.
615 */
616 if (num_planes == 1) {
617 scl0 = vc4_get_scl_field(state, 0);
618 scl1 = scl0;
619 } else {
620 scl0 = vc4_get_scl_field(state, 1);
621 scl1 = vc4_get_scl_field(state, 0);
622 }
623
624 rotation = drm_rotation_simplify(state->rotation,
625 DRM_MODE_ROTATE_0 |
626 DRM_MODE_REFLECT_X |
627 DRM_MODE_REFLECT_Y);
628
629 /* We must point to the last line when Y reflection is enabled. */
630 src_y = vc4_state->src_y;
631 if (rotation & DRM_MODE_REFLECT_Y)
632 src_y += vc4_state->src_h[0] - 1;
633
634 switch (base_format_mod) {
635 case DRM_FORMAT_MOD_LINEAR:
636 tiling = SCALER_CTL0_TILING_LINEAR;
637 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
638
639 /* Adjust the base pointer to the first pixel to be scanned
640 * out.
641 */
642 for (i = 0; i < num_planes; i++) {
643 vc4_state->offsets[i] += src_y /
644 (i ? v_subsample : 1) *
645 fb->pitches[i];
646
647 vc4_state->offsets[i] += vc4_state->src_x /
648 (i ? h_subsample : 1) *
649 fb->format->cpp[i];
650 }
651
652 break;
653
654 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
655 u32 tile_size_shift = 12; /* T tiles are 4kb */
656 /* Whole-tile offsets, mostly for setting the pitch. */
657 u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
658 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
659 u32 tile_w_mask = (1 << tile_w_shift) - 1;
660 /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
661 * the height (in pixels) of a 4k tile.
662 */
663 u32 tile_h_mask = (2 << tile_h_shift) - 1;
664 /* For T-tiled, the FB pitch is "how many bytes from one row to
665 * the next, such that
666 *
667 * pitch * tile_h == tile_size * tiles_per_row
668 */
669 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
670 u32 tiles_l = vc4_state->src_x >> tile_w_shift;
671 u32 tiles_r = tiles_w - tiles_l;
672 u32 tiles_t = src_y >> tile_h_shift;
673 /* Intra-tile offsets, which modify the base address (the
674 * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
675 * base address).
676 */
677 u32 tile_y = (src_y >> 4) & 1;
678 u32 subtile_y = (src_y >> 2) & 3;
679 u32 utile_y = src_y & 3;
680 u32 x_off = vc4_state->src_x & tile_w_mask;
681 u32 y_off = src_y & tile_h_mask;
682
683 /* When Y reflection is requested we must set the
684 * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
685 * after the initial one should be fetched in descending order,
686 * which makes sense since we start from the last line and go
687 * backward.
688 * Don't know why we need y_off = max_y_off - y_off, but it's
689 * definitely required (I guess it's also related to the "going
690 * backward" situation).
691 */
692 if (rotation & DRM_MODE_REFLECT_Y) {
693 y_off = tile_h_mask - y_off;
694 pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
695 } else {
696 pitch0 = 0;
697 }
698
699 tiling = SCALER_CTL0_TILING_256B_OR_T;
700 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
701 VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
702 VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
703 VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
704 vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
705 vc4_state->offsets[0] += subtile_y << 8;
706 vc4_state->offsets[0] += utile_y << 4;
707
708 /* Rows of tiles alternate left-to-right and right-to-left. */
709 if (tiles_t & 1) {
710 pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
711 vc4_state->offsets[0] += (tiles_w - tiles_l) <<
712 tile_size_shift;
713 vc4_state->offsets[0] -= (1 + !tile_y) << 10;
714 } else {
715 vc4_state->offsets[0] += tiles_l << tile_size_shift;
716 vc4_state->offsets[0] += tile_y << 10;
717 }
718
719 break;
720 }
721
722 case DRM_FORMAT_MOD_BROADCOM_SAND64:
723 case DRM_FORMAT_MOD_BROADCOM_SAND128:
724 case DRM_FORMAT_MOD_BROADCOM_SAND256: {
725 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
726 u32 tile_w, tile, x_off, pix_per_tile;
727
728 hvs_format = HVS_PIXEL_FORMAT_H264;
729
730 switch (base_format_mod) {
731 case DRM_FORMAT_MOD_BROADCOM_SAND64:
732 tiling = SCALER_CTL0_TILING_64B;
733 tile_w = 64;
734 break;
735 case DRM_FORMAT_MOD_BROADCOM_SAND128:
736 tiling = SCALER_CTL0_TILING_128B;
737 tile_w = 128;
738 break;
739 case DRM_FORMAT_MOD_BROADCOM_SAND256:
740 tiling = SCALER_CTL0_TILING_256B_OR_T;
741 tile_w = 256;
742 break;
743 default:
744 break;
745 }
746
747 if (param > SCALER_TILE_HEIGHT_MASK) {
748 DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
749 return -EINVAL;
750 }
751
752 pix_per_tile = tile_w / fb->format->cpp[0];
753 tile = vc4_state->src_x / pix_per_tile;
754 x_off = vc4_state->src_x % pix_per_tile;
755
756 /* Adjust the base pointer to the first pixel to be scanned
757 * out.
758 */
759 for (i = 0; i < num_planes; i++) {
760 vc4_state->offsets[i] += param * tile_w * tile;
761 vc4_state->offsets[i] += src_y /
762 (i ? v_subsample : 1) *
763 tile_w;
764 vc4_state->offsets[i] += x_off /
765 (i ? h_subsample : 1) *
766 fb->format->cpp[i];
767 }
768
769 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
770 break;
771 }
772
773 default:
774 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
775 (long long)fb->modifier);
776 return -EINVAL;
777 }
778
779 /* Control word */
780 vc4_dlist_write(vc4_state,
781 SCALER_CTL0_VALID |
782 (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
783 (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
784 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
785 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
786 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
787 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
788 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
789 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
790 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
791
792 /* Position Word 0: Image Positions and Alpha Value */
793 vc4_state->pos0_offset = vc4_state->dlist_count;
794 vc4_dlist_write(vc4_state,
795 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
796 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
797 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
798
799 /* Position Word 1: Scaled Image Dimensions. */
800 if (!vc4_state->is_unity) {
801 vc4_dlist_write(vc4_state,
802 VC4_SET_FIELD(vc4_state->crtc_w,
803 SCALER_POS1_SCL_WIDTH) |
804 VC4_SET_FIELD(vc4_state->crtc_h,
805 SCALER_POS1_SCL_HEIGHT));
806 }
807
808 /* Don't waste cycles mixing with plane alpha if the set alpha
809 * is opaque or there is no per-pixel alpha information.
810 * In any case we use the alpha property value as the fixed alpha.
811 */
812 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
813 fb->format->has_alpha;
814
815 /* Position Word 2: Source Image Size, Alpha */
816 vc4_state->pos2_offset = vc4_state->dlist_count;
817 vc4_dlist_write(vc4_state,
818 VC4_SET_FIELD(fb->format->has_alpha ?
819 SCALER_POS2_ALPHA_MODE_PIPELINE :
820 SCALER_POS2_ALPHA_MODE_FIXED,
821 SCALER_POS2_ALPHA_MODE) |
822 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
823 (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
824 VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
825 VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
826
827 /* Position Word 3: Context. Written by the HVS. */
828 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
829
830
831 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
832 *
833 * The pointers may be any byte address.
834 */
835 vc4_state->ptr0_offset = vc4_state->dlist_count;
836 for (i = 0; i < num_planes; i++)
837 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
838
839 /* Pointer Context Word 0/1/2: Written by the HVS */
840 for (i = 0; i < num_planes; i++)
841 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
842
843 /* Pitch word 0 */
844 vc4_dlist_write(vc4_state, pitch0);
845
846 /* Pitch word 1/2 */
847 for (i = 1; i < num_planes; i++) {
848 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
849 vc4_dlist_write(vc4_state,
850 VC4_SET_FIELD(fb->pitches[i],
851 SCALER_SRC_PITCH));
852 } else {
853 vc4_dlist_write(vc4_state, pitch0);
854 }
855 }
856
857 /* Colorspace conversion words */
858 if (vc4_state->is_yuv) {
859 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
860 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
861 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
862 }
863
864 vc4_state->lbm_offset = 0;
865
866 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
867 vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
868 vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
869 vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
870 /* Reserve a slot for the LBM Base Address. The real value will
871 * be set when calling vc4_plane_allocate_lbm().
872 */
873 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
874 vc4_state->y_scaling[1] != VC4_SCALING_NONE)
875 vc4_state->lbm_offset = vc4_state->dlist_count++;
876
877 if (num_planes > 1) {
878 /* Emit Cb/Cr as channel 0 and Y as channel
879 * 1. This matches how we set up scl0/scl1
880 * above.
881 */
882 vc4_write_scaling_parameters(state, 1);
883 }
884 vc4_write_scaling_parameters(state, 0);
885
886 /* If any PPF setup was done, then all the kernel
887 * pointers get uploaded.
888 */
889 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
890 vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
891 vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
892 vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
893 u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
894 SCALER_PPF_KERNEL_OFFSET);
895
896 /* HPPF plane 0 */
897 vc4_dlist_write(vc4_state, kernel);
898 /* VPPF plane 0 */
899 vc4_dlist_write(vc4_state, kernel);
900 /* HPPF plane 1 */
901 vc4_dlist_write(vc4_state, kernel);
902 /* VPPF plane 1 */
903 vc4_dlist_write(vc4_state, kernel);
904 }
905 }
906
907 vc4_state->dlist[ctl0_offset] |=
908 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
909
910 /* crtc_* are already clipped coordinates. */
911 covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
912 vc4_state->crtc_w == state->crtc->mode.hdisplay &&
913 vc4_state->crtc_h == state->crtc->mode.vdisplay;
914 /* Background fill might be necessary when the plane has per-pixel
915 * alpha content or a non-opaque plane alpha and could blend from the
916 * background or does not cover the entire screen.
917 */
918 vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
919 state->alpha != DRM_BLEND_ALPHA_OPAQUE;
920
921 /* Flag the dlist as initialized to avoid checking it twice in case
922 * the async update check already called vc4_plane_mode_set() and
923 * decided to fallback to sync update because async update was not
924 * possible.
925 */
926 vc4_state->dlist_initialized = 1;
927
928 vc4_plane_calc_load(state);
929
930 return 0;
931}
932
933/* If a modeset involves changing the setup of a plane, the atomic
934 * infrastructure will call this to validate a proposed plane setup.
935 * However, if a plane isn't getting updated, this (and the
936 * corresponding vc4_plane_atomic_update) won't get called. Thus, we
937 * compute the dlist here and have all active plane dlists get updated
938 * in the CRTC's flush.
939 */
940static int vc4_plane_atomic_check(struct drm_plane *plane,
941 struct drm_plane_state *state)
942{
943 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
944 int ret;
945
946 vc4_state->dlist_count = 0;
947
948 if (!plane_enabled(state))
949 return 0;
950
951 ret = vc4_plane_mode_set(plane, state);
952 if (ret)
953 return ret;
954
955 return vc4_plane_allocate_lbm(state);
956}
957
958static void vc4_plane_atomic_update(struct drm_plane *plane,
959 struct drm_plane_state *old_state)
960{
961 /* No contents here. Since we don't know where in the CRTC's
962 * dlist we should be stored, our dlist is uploaded to the
963 * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
964 * time.
965 */
966}
967
968u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
969{
970 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
971 int i;
972
973 vc4_state->hw_dlist = dlist;
974
975 /* Can't memcpy_toio() because it needs to be 32-bit writes. */
976 for (i = 0; i < vc4_state->dlist_count; i++)
977 writel(vc4_state->dlist[i], &dlist[i]);
978
979 return vc4_state->dlist_count;
980}
981
982u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
983{
984 const struct vc4_plane_state *vc4_state =
985 container_of(state, typeof(*vc4_state), base);
986
987 return vc4_state->dlist_count;
988}
989
990/* Updates the plane to immediately (well, once the FIFO needs
991 * refilling) scan out from at a new framebuffer.
992 */
993void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
994{
995 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
996 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
997 uint32_t addr;
998
999 /* We're skipping the address adjustment for negative origin,
1000 * because this is only called on the primary plane.
1001 */
1002 WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
1003 addr = bo->paddr + fb->offsets[0];
1004
1005 /* Write the new address into the hardware immediately. The
1006 * scanout will start from this address as soon as the FIFO
1007 * needs to refill with pixels.
1008 */
1009 writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1010
1011 /* Also update the CPU-side dlist copy, so that any later
1012 * atomic updates that don't do a new modeset on our plane
1013 * also use our updated address.
1014 */
1015 vc4_state->dlist[vc4_state->ptr0_offset] = addr;
1016}
1017
1018static void vc4_plane_atomic_async_update(struct drm_plane *plane,
1019 struct drm_plane_state *state)
1020{
1021 struct vc4_plane_state *vc4_state, *new_vc4_state;
1022
1023 swap(plane->state->fb, state->fb);
1024 plane->state->crtc_x = state->crtc_x;
1025 plane->state->crtc_y = state->crtc_y;
1026 plane->state->crtc_w = state->crtc_w;
1027 plane->state->crtc_h = state->crtc_h;
1028 plane->state->src_x = state->src_x;
1029 plane->state->src_y = state->src_y;
1030 plane->state->src_w = state->src_w;
1031 plane->state->src_h = state->src_h;
1032 plane->state->src_h = state->src_h;
1033 plane->state->alpha = state->alpha;
1034 plane->state->pixel_blend_mode = state->pixel_blend_mode;
1035 plane->state->rotation = state->rotation;
1036 plane->state->zpos = state->zpos;
1037 plane->state->normalized_zpos = state->normalized_zpos;
1038 plane->state->color_encoding = state->color_encoding;
1039 plane->state->color_range = state->color_range;
1040 plane->state->src = state->src;
1041 plane->state->dst = state->dst;
1042 plane->state->visible = state->visible;
1043
1044 new_vc4_state = to_vc4_plane_state(state);
1045 vc4_state = to_vc4_plane_state(plane->state);
1046
1047 vc4_state->crtc_x = new_vc4_state->crtc_x;
1048 vc4_state->crtc_y = new_vc4_state->crtc_y;
1049 vc4_state->crtc_h = new_vc4_state->crtc_h;
1050 vc4_state->crtc_w = new_vc4_state->crtc_w;
1051 vc4_state->src_x = new_vc4_state->src_x;
1052 vc4_state->src_y = new_vc4_state->src_y;
1053 memcpy(vc4_state->src_w, new_vc4_state->src_w,
1054 sizeof(vc4_state->src_w));
1055 memcpy(vc4_state->src_h, new_vc4_state->src_h,
1056 sizeof(vc4_state->src_h));
1057 memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling,
1058 sizeof(vc4_state->x_scaling));
1059 memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling,
1060 sizeof(vc4_state->y_scaling));
1061 vc4_state->is_unity = new_vc4_state->is_unity;
1062 vc4_state->is_yuv = new_vc4_state->is_yuv;
1063 memcpy(vc4_state->offsets, new_vc4_state->offsets,
1064 sizeof(vc4_state->offsets));
1065 vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
1066
1067 /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
1068 vc4_state->dlist[vc4_state->pos0_offset] =
1069 new_vc4_state->dlist[vc4_state->pos0_offset];
1070 vc4_state->dlist[vc4_state->pos2_offset] =
1071 new_vc4_state->dlist[vc4_state->pos2_offset];
1072 vc4_state->dlist[vc4_state->ptr0_offset] =
1073 new_vc4_state->dlist[vc4_state->ptr0_offset];
1074
1075 /* Note that we can't just call vc4_plane_write_dlist()
1076 * because that would smash the context data that the HVS is
1077 * currently using.
1078 */
1079 writel(vc4_state->dlist[vc4_state->pos0_offset],
1080 &vc4_state->hw_dlist[vc4_state->pos0_offset]);
1081 writel(vc4_state->dlist[vc4_state->pos2_offset],
1082 &vc4_state->hw_dlist[vc4_state->pos2_offset]);
1083 writel(vc4_state->dlist[vc4_state->ptr0_offset],
1084 &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1085}
1086
1087static int vc4_plane_atomic_async_check(struct drm_plane *plane,
1088 struct drm_plane_state *state)
1089{
1090 struct vc4_plane_state *old_vc4_state, *new_vc4_state;
1091 int ret;
1092 u32 i;
1093
1094 ret = vc4_plane_mode_set(plane, state);
1095 if (ret)
1096 return ret;
1097
1098 old_vc4_state = to_vc4_plane_state(plane->state);
1099 new_vc4_state = to_vc4_plane_state(state);
1100 if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
1101 old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
1102 old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
1103 old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset ||
1104 vc4_lbm_size(plane->state) != vc4_lbm_size(state))
1105 return -EINVAL;
1106
1107 /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update
1108 * if anything else has changed, fallback to a sync update.
1109 */
1110 for (i = 0; i < new_vc4_state->dlist_count; i++) {
1111 if (i == new_vc4_state->pos0_offset ||
1112 i == new_vc4_state->pos2_offset ||
1113 i == new_vc4_state->ptr0_offset ||
1114 (new_vc4_state->lbm_offset &&
1115 i == new_vc4_state->lbm_offset))
1116 continue;
1117
1118 if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i])
1119 return -EINVAL;
1120 }
1121
1122 return 0;
1123}
1124
1125static int vc4_prepare_fb(struct drm_plane *plane,
1126 struct drm_plane_state *state)
1127{
1128 struct vc4_bo *bo;
1129 int ret;
1130
1131 if (!state->fb)
1132 return 0;
1133
1134 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1135
1136 drm_gem_fb_prepare_fb(plane, state);
1137
1138 if (plane->state->fb == state->fb)
1139 return 0;
1140
1141 ret = vc4_bo_inc_usecnt(bo);
1142 if (ret)
1143 return ret;
1144
1145 return 0;
1146}
1147
1148static void vc4_cleanup_fb(struct drm_plane *plane,
1149 struct drm_plane_state *state)
1150{
1151 struct vc4_bo *bo;
1152
1153 if (plane->state->fb == state->fb || !state->fb)
1154 return;
1155
1156 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1157 vc4_bo_dec_usecnt(bo);
1158}
1159
1160static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
1161 .atomic_check = vc4_plane_atomic_check,
1162 .atomic_update = vc4_plane_atomic_update,
1163 .prepare_fb = vc4_prepare_fb,
1164 .cleanup_fb = vc4_cleanup_fb,
1165 .atomic_async_check = vc4_plane_atomic_async_check,
1166 .atomic_async_update = vc4_plane_atomic_async_update,
1167};
1168
1169static void vc4_plane_destroy(struct drm_plane *plane)
1170{
1171 drm_plane_cleanup(plane);
1172}
1173
1174static bool vc4_format_mod_supported(struct drm_plane *plane,
1175 uint32_t format,
1176 uint64_t modifier)
1177{
1178 /* Support T_TILING for RGB formats only. */
1179 switch (format) {
1180 case DRM_FORMAT_XRGB8888:
1181 case DRM_FORMAT_ARGB8888:
1182 case DRM_FORMAT_ABGR8888:
1183 case DRM_FORMAT_XBGR8888:
1184 case DRM_FORMAT_RGB565:
1185 case DRM_FORMAT_BGR565:
1186 case DRM_FORMAT_ARGB1555:
1187 case DRM_FORMAT_XRGB1555:
1188 switch (fourcc_mod_broadcom_mod(modifier)) {
1189 case DRM_FORMAT_MOD_LINEAR:
1190 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
1191 return true;
1192 default:
1193 return false;
1194 }
1195 case DRM_FORMAT_NV12:
1196 case DRM_FORMAT_NV21:
1197 switch (fourcc_mod_broadcom_mod(modifier)) {
1198 case DRM_FORMAT_MOD_LINEAR:
1199 case DRM_FORMAT_MOD_BROADCOM_SAND64:
1200 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1201 case DRM_FORMAT_MOD_BROADCOM_SAND256:
1202 return true;
1203 default:
1204 return false;
1205 }
1206 case DRM_FORMAT_YUV422:
1207 case DRM_FORMAT_YVU422:
1208 case DRM_FORMAT_YUV420:
1209 case DRM_FORMAT_YVU420:
1210 case DRM_FORMAT_NV16:
1211 case DRM_FORMAT_NV61:
1212 default:
1213 return (modifier == DRM_FORMAT_MOD_LINEAR);
1214 }
1215}
1216
1217static const struct drm_plane_funcs vc4_plane_funcs = {
1218 .update_plane = drm_atomic_helper_update_plane,
1219 .disable_plane = drm_atomic_helper_disable_plane,
1220 .destroy = vc4_plane_destroy,
1221 .set_property = NULL,
1222 .reset = vc4_plane_reset,
1223 .atomic_duplicate_state = vc4_plane_duplicate_state,
1224 .atomic_destroy_state = vc4_plane_destroy_state,
1225 .format_mod_supported = vc4_format_mod_supported,
1226};
1227
1228struct drm_plane *vc4_plane_init(struct drm_device *dev,
1229 enum drm_plane_type type)
1230{
1231 struct drm_plane *plane = NULL;
1232 struct vc4_plane *vc4_plane;
1233 u32 formats[ARRAY_SIZE(hvs_formats)];
1234 int ret = 0;
1235 unsigned i;
1236 static const uint64_t modifiers[] = {
1237 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
1238 DRM_FORMAT_MOD_BROADCOM_SAND128,
1239 DRM_FORMAT_MOD_BROADCOM_SAND64,
1240 DRM_FORMAT_MOD_BROADCOM_SAND256,
1241 DRM_FORMAT_MOD_LINEAR,
1242 DRM_FORMAT_MOD_INVALID
1243 };
1244
1245 vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
1246 GFP_KERNEL);
1247 if (!vc4_plane)
1248 return ERR_PTR(-ENOMEM);
1249
1250 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
1251 formats[i] = hvs_formats[i].drm;
1252
1253 plane = &vc4_plane->base;
1254 ret = drm_universal_plane_init(dev, plane, 0,
1255 &vc4_plane_funcs,
1256 formats, ARRAY_SIZE(formats),
1257 modifiers, type, NULL);
1258
1259 drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1260
1261 drm_plane_create_alpha_property(plane);
1262 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1263 DRM_MODE_ROTATE_0 |
1264 DRM_MODE_ROTATE_180 |
1265 DRM_MODE_REFLECT_X |
1266 DRM_MODE_REFLECT_Y);
1267
1268 return plane;
1269}