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1/*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/console.h>
26#include <linux/vgaarb.h>
27#include <linux/vga_switcheroo.h>
28
29#include <drm/drm_drv.h>
30
31#include "display/intel_fbdev.h"
32
33#include "i915_drv.h"
34#include "i915_globals.h"
35#include "i915_selftest.h"
36
37#define PLATFORM(x) .platform = (x)
38#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
39
40#define I845_PIPE_OFFSETS \
41 .pipe_offsets = { \
42 [TRANSCODER_A] = PIPE_A_OFFSET, \
43 }, \
44 .trans_offsets = { \
45 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
46 }
47
48#define I9XX_PIPE_OFFSETS \
49 .pipe_offsets = { \
50 [TRANSCODER_A] = PIPE_A_OFFSET, \
51 [TRANSCODER_B] = PIPE_B_OFFSET, \
52 }, \
53 .trans_offsets = { \
54 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
55 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
56 }
57
58#define IVB_PIPE_OFFSETS \
59 .pipe_offsets = { \
60 [TRANSCODER_A] = PIPE_A_OFFSET, \
61 [TRANSCODER_B] = PIPE_B_OFFSET, \
62 [TRANSCODER_C] = PIPE_C_OFFSET, \
63 }, \
64 .trans_offsets = { \
65 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
66 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
67 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
68 }
69
70#define HSW_PIPE_OFFSETS \
71 .pipe_offsets = { \
72 [TRANSCODER_A] = PIPE_A_OFFSET, \
73 [TRANSCODER_B] = PIPE_B_OFFSET, \
74 [TRANSCODER_C] = PIPE_C_OFFSET, \
75 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
76 }, \
77 .trans_offsets = { \
78 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
79 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
80 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
81 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
82 }
83
84#define CHV_PIPE_OFFSETS \
85 .pipe_offsets = { \
86 [TRANSCODER_A] = PIPE_A_OFFSET, \
87 [TRANSCODER_B] = PIPE_B_OFFSET, \
88 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
89 }, \
90 .trans_offsets = { \
91 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
92 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
93 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
94 }
95
96#define I845_CURSOR_OFFSETS \
97 .cursor_offsets = { \
98 [PIPE_A] = CURSOR_A_OFFSET, \
99 }
100
101#define I9XX_CURSOR_OFFSETS \
102 .cursor_offsets = { \
103 [PIPE_A] = CURSOR_A_OFFSET, \
104 [PIPE_B] = CURSOR_B_OFFSET, \
105 }
106
107#define CHV_CURSOR_OFFSETS \
108 .cursor_offsets = { \
109 [PIPE_A] = CURSOR_A_OFFSET, \
110 [PIPE_B] = CURSOR_B_OFFSET, \
111 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
112 }
113
114#define IVB_CURSOR_OFFSETS \
115 .cursor_offsets = { \
116 [PIPE_A] = CURSOR_A_OFFSET, \
117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
118 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
119 }
120
121#define I9XX_COLORS \
122 .color = { .gamma_lut_size = 256 }
123#define I965_COLORS \
124 .color = { .gamma_lut_size = 129, \
125 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
126 }
127#define ILK_COLORS \
128 .color = { .gamma_lut_size = 1024 }
129#define IVB_COLORS \
130 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
131#define CHV_COLORS \
132 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
133 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
134 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
135 }
136#define GLK_COLORS \
137 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
138 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
139 DRM_COLOR_LUT_EQUAL_CHANNELS, \
140 }
141
142/* Keep in gen based order, and chronological order within a gen */
143
144#define GEN_DEFAULT_PAGE_SIZES \
145 .page_sizes = I915_GTT_PAGE_SIZE_4K
146
147#define I830_FEATURES \
148 GEN(2), \
149 .is_mobile = 1, \
150 .num_pipes = 2, \
151 .display.has_overlay = 1, \
152 .display.cursor_needs_physical = 1, \
153 .display.overlay_needs_physical = 1, \
154 .display.has_gmch = 1, \
155 .gpu_reset_clobbers_display = true, \
156 .hws_needs_physical = 1, \
157 .unfenced_needs_alignment = 1, \
158 .engine_mask = BIT(RCS0), \
159 .has_snoop = true, \
160 .has_coherent_ggtt = false, \
161 I9XX_PIPE_OFFSETS, \
162 I9XX_CURSOR_OFFSETS, \
163 I9XX_COLORS, \
164 GEN_DEFAULT_PAGE_SIZES
165
166#define I845_FEATURES \
167 GEN(2), \
168 .num_pipes = 1, \
169 .display.has_overlay = 1, \
170 .display.overlay_needs_physical = 1, \
171 .display.has_gmch = 1, \
172 .gpu_reset_clobbers_display = true, \
173 .hws_needs_physical = 1, \
174 .unfenced_needs_alignment = 1, \
175 .engine_mask = BIT(RCS0), \
176 .has_snoop = true, \
177 .has_coherent_ggtt = false, \
178 I845_PIPE_OFFSETS, \
179 I845_CURSOR_OFFSETS, \
180 I9XX_COLORS, \
181 GEN_DEFAULT_PAGE_SIZES
182
183static const struct intel_device_info intel_i830_info = {
184 I830_FEATURES,
185 PLATFORM(INTEL_I830),
186};
187
188static const struct intel_device_info intel_i845g_info = {
189 I845_FEATURES,
190 PLATFORM(INTEL_I845G),
191};
192
193static const struct intel_device_info intel_i85x_info = {
194 I830_FEATURES,
195 PLATFORM(INTEL_I85X),
196 .display.has_fbc = 1,
197};
198
199static const struct intel_device_info intel_i865g_info = {
200 I845_FEATURES,
201 PLATFORM(INTEL_I865G),
202};
203
204#define GEN3_FEATURES \
205 GEN(3), \
206 .num_pipes = 2, \
207 .display.has_gmch = 1, \
208 .gpu_reset_clobbers_display = true, \
209 .engine_mask = BIT(RCS0), \
210 .has_snoop = true, \
211 .has_coherent_ggtt = true, \
212 I9XX_PIPE_OFFSETS, \
213 I9XX_CURSOR_OFFSETS, \
214 I9XX_COLORS, \
215 GEN_DEFAULT_PAGE_SIZES
216
217static const struct intel_device_info intel_i915g_info = {
218 GEN3_FEATURES,
219 PLATFORM(INTEL_I915G),
220 .has_coherent_ggtt = false,
221 .display.cursor_needs_physical = 1,
222 .display.has_overlay = 1,
223 .display.overlay_needs_physical = 1,
224 .hws_needs_physical = 1,
225 .unfenced_needs_alignment = 1,
226};
227
228static const struct intel_device_info intel_i915gm_info = {
229 GEN3_FEATURES,
230 PLATFORM(INTEL_I915GM),
231 .is_mobile = 1,
232 .display.cursor_needs_physical = 1,
233 .display.has_overlay = 1,
234 .display.overlay_needs_physical = 1,
235 .display.supports_tv = 1,
236 .display.has_fbc = 1,
237 .hws_needs_physical = 1,
238 .unfenced_needs_alignment = 1,
239};
240
241static const struct intel_device_info intel_i945g_info = {
242 GEN3_FEATURES,
243 PLATFORM(INTEL_I945G),
244 .display.has_hotplug = 1,
245 .display.cursor_needs_physical = 1,
246 .display.has_overlay = 1,
247 .display.overlay_needs_physical = 1,
248 .hws_needs_physical = 1,
249 .unfenced_needs_alignment = 1,
250};
251
252static const struct intel_device_info intel_i945gm_info = {
253 GEN3_FEATURES,
254 PLATFORM(INTEL_I945GM),
255 .is_mobile = 1,
256 .display.has_hotplug = 1,
257 .display.cursor_needs_physical = 1,
258 .display.has_overlay = 1,
259 .display.overlay_needs_physical = 1,
260 .display.supports_tv = 1,
261 .display.has_fbc = 1,
262 .hws_needs_physical = 1,
263 .unfenced_needs_alignment = 1,
264};
265
266static const struct intel_device_info intel_g33_info = {
267 GEN3_FEATURES,
268 PLATFORM(INTEL_G33),
269 .display.has_hotplug = 1,
270 .display.has_overlay = 1,
271};
272
273static const struct intel_device_info intel_pineview_g_info = {
274 GEN3_FEATURES,
275 PLATFORM(INTEL_PINEVIEW),
276 .display.has_hotplug = 1,
277 .display.has_overlay = 1,
278};
279
280static const struct intel_device_info intel_pineview_m_info = {
281 GEN3_FEATURES,
282 PLATFORM(INTEL_PINEVIEW),
283 .is_mobile = 1,
284 .display.has_hotplug = 1,
285 .display.has_overlay = 1,
286};
287
288#define GEN4_FEATURES \
289 GEN(4), \
290 .num_pipes = 2, \
291 .display.has_hotplug = 1, \
292 .display.has_gmch = 1, \
293 .gpu_reset_clobbers_display = true, \
294 .engine_mask = BIT(RCS0), \
295 .has_snoop = true, \
296 .has_coherent_ggtt = true, \
297 I9XX_PIPE_OFFSETS, \
298 I9XX_CURSOR_OFFSETS, \
299 I965_COLORS, \
300 GEN_DEFAULT_PAGE_SIZES
301
302static const struct intel_device_info intel_i965g_info = {
303 GEN4_FEATURES,
304 PLATFORM(INTEL_I965G),
305 .display.has_overlay = 1,
306 .hws_needs_physical = 1,
307 .has_snoop = false,
308};
309
310static const struct intel_device_info intel_i965gm_info = {
311 GEN4_FEATURES,
312 PLATFORM(INTEL_I965GM),
313 .is_mobile = 1,
314 .display.has_fbc = 1,
315 .display.has_overlay = 1,
316 .display.supports_tv = 1,
317 .hws_needs_physical = 1,
318 .has_snoop = false,
319};
320
321static const struct intel_device_info intel_g45_info = {
322 GEN4_FEATURES,
323 PLATFORM(INTEL_G45),
324 .engine_mask = BIT(RCS0) | BIT(VCS0),
325 .gpu_reset_clobbers_display = false,
326};
327
328static const struct intel_device_info intel_gm45_info = {
329 GEN4_FEATURES,
330 PLATFORM(INTEL_GM45),
331 .is_mobile = 1,
332 .display.has_fbc = 1,
333 .display.supports_tv = 1,
334 .engine_mask = BIT(RCS0) | BIT(VCS0),
335 .gpu_reset_clobbers_display = false,
336};
337
338#define GEN5_FEATURES \
339 GEN(5), \
340 .num_pipes = 2, \
341 .display.has_hotplug = 1, \
342 .engine_mask = BIT(RCS0) | BIT(VCS0), \
343 .has_snoop = true, \
344 .has_coherent_ggtt = true, \
345 /* ilk does support rc6, but we do not implement [power] contexts */ \
346 .has_rc6 = 0, \
347 I9XX_PIPE_OFFSETS, \
348 I9XX_CURSOR_OFFSETS, \
349 ILK_COLORS, \
350 GEN_DEFAULT_PAGE_SIZES
351
352static const struct intel_device_info intel_ironlake_d_info = {
353 GEN5_FEATURES,
354 PLATFORM(INTEL_IRONLAKE),
355};
356
357static const struct intel_device_info intel_ironlake_m_info = {
358 GEN5_FEATURES,
359 PLATFORM(INTEL_IRONLAKE),
360 .is_mobile = 1,
361 .display.has_fbc = 1,
362};
363
364#define GEN6_FEATURES \
365 GEN(6), \
366 .num_pipes = 2, \
367 .display.has_hotplug = 1, \
368 .display.has_fbc = 1, \
369 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
370 .has_coherent_ggtt = true, \
371 .has_llc = 1, \
372 .has_rc6 = 1, \
373 .has_rc6p = 1, \
374 .has_rps = true, \
375 .ppgtt_type = INTEL_PPGTT_ALIASING, \
376 .ppgtt_size = 31, \
377 I9XX_PIPE_OFFSETS, \
378 I9XX_CURSOR_OFFSETS, \
379 ILK_COLORS, \
380 GEN_DEFAULT_PAGE_SIZES
381
382#define SNB_D_PLATFORM \
383 GEN6_FEATURES, \
384 PLATFORM(INTEL_SANDYBRIDGE)
385
386static const struct intel_device_info intel_sandybridge_d_gt1_info = {
387 SNB_D_PLATFORM,
388 .gt = 1,
389};
390
391static const struct intel_device_info intel_sandybridge_d_gt2_info = {
392 SNB_D_PLATFORM,
393 .gt = 2,
394};
395
396#define SNB_M_PLATFORM \
397 GEN6_FEATURES, \
398 PLATFORM(INTEL_SANDYBRIDGE), \
399 .is_mobile = 1
400
401
402static const struct intel_device_info intel_sandybridge_m_gt1_info = {
403 SNB_M_PLATFORM,
404 .gt = 1,
405};
406
407static const struct intel_device_info intel_sandybridge_m_gt2_info = {
408 SNB_M_PLATFORM,
409 .gt = 2,
410};
411
412#define GEN7_FEATURES \
413 GEN(7), \
414 .num_pipes = 3, \
415 .display.has_hotplug = 1, \
416 .display.has_fbc = 1, \
417 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
418 .has_coherent_ggtt = true, \
419 .has_llc = 1, \
420 .has_rc6 = 1, \
421 .has_rc6p = 1, \
422 .has_rps = true, \
423 .ppgtt_type = INTEL_PPGTT_FULL, \
424 .ppgtt_size = 31, \
425 IVB_PIPE_OFFSETS, \
426 IVB_CURSOR_OFFSETS, \
427 IVB_COLORS, \
428 GEN_DEFAULT_PAGE_SIZES
429
430#define IVB_D_PLATFORM \
431 GEN7_FEATURES, \
432 PLATFORM(INTEL_IVYBRIDGE), \
433 .has_l3_dpf = 1
434
435static const struct intel_device_info intel_ivybridge_d_gt1_info = {
436 IVB_D_PLATFORM,
437 .gt = 1,
438};
439
440static const struct intel_device_info intel_ivybridge_d_gt2_info = {
441 IVB_D_PLATFORM,
442 .gt = 2,
443};
444
445#define IVB_M_PLATFORM \
446 GEN7_FEATURES, \
447 PLATFORM(INTEL_IVYBRIDGE), \
448 .is_mobile = 1, \
449 .has_l3_dpf = 1
450
451static const struct intel_device_info intel_ivybridge_m_gt1_info = {
452 IVB_M_PLATFORM,
453 .gt = 1,
454};
455
456static const struct intel_device_info intel_ivybridge_m_gt2_info = {
457 IVB_M_PLATFORM,
458 .gt = 2,
459};
460
461static const struct intel_device_info intel_ivybridge_q_info = {
462 GEN7_FEATURES,
463 PLATFORM(INTEL_IVYBRIDGE),
464 .gt = 2,
465 .num_pipes = 0, /* legal, last one wins */
466 .has_l3_dpf = 1,
467};
468
469static const struct intel_device_info intel_valleyview_info = {
470 PLATFORM(INTEL_VALLEYVIEW),
471 GEN(7),
472 .is_lp = 1,
473 .num_pipes = 2,
474 .has_runtime_pm = 1,
475 .has_rc6 = 1,
476 .has_rps = true,
477 .display.has_gmch = 1,
478 .display.has_hotplug = 1,
479 .ppgtt_type = INTEL_PPGTT_FULL,
480 .ppgtt_size = 31,
481 .has_snoop = true,
482 .has_coherent_ggtt = false,
483 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
484 .display_mmio_offset = VLV_DISPLAY_BASE,
485 I9XX_PIPE_OFFSETS,
486 I9XX_CURSOR_OFFSETS,
487 I965_COLORS,
488 GEN_DEFAULT_PAGE_SIZES,
489};
490
491#define G75_FEATURES \
492 GEN7_FEATURES, \
493 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
494 .display.has_ddi = 1, \
495 .has_fpga_dbg = 1, \
496 .display.has_psr = 1, \
497 .display.has_dp_mst = 1, \
498 .has_rc6p = 0 /* RC6p removed-by HSW */, \
499 HSW_PIPE_OFFSETS, \
500 .has_runtime_pm = 1
501
502#define HSW_PLATFORM \
503 G75_FEATURES, \
504 PLATFORM(INTEL_HASWELL), \
505 .has_l3_dpf = 1
506
507static const struct intel_device_info intel_haswell_gt1_info = {
508 HSW_PLATFORM,
509 .gt = 1,
510};
511
512static const struct intel_device_info intel_haswell_gt2_info = {
513 HSW_PLATFORM,
514 .gt = 2,
515};
516
517static const struct intel_device_info intel_haswell_gt3_info = {
518 HSW_PLATFORM,
519 .gt = 3,
520};
521
522#define GEN8_FEATURES \
523 G75_FEATURES, \
524 GEN(8), \
525 .has_logical_ring_contexts = 1, \
526 .ppgtt_type = INTEL_PPGTT_FULL, \
527 .ppgtt_size = 48, \
528 .has_64bit_reloc = 1, \
529 .has_reset_engine = 1
530
531#define BDW_PLATFORM \
532 GEN8_FEATURES, \
533 PLATFORM(INTEL_BROADWELL)
534
535static const struct intel_device_info intel_broadwell_gt1_info = {
536 BDW_PLATFORM,
537 .gt = 1,
538};
539
540static const struct intel_device_info intel_broadwell_gt2_info = {
541 BDW_PLATFORM,
542 .gt = 2,
543};
544
545static const struct intel_device_info intel_broadwell_rsvd_info = {
546 BDW_PLATFORM,
547 .gt = 3,
548 /* According to the device ID those devices are GT3, they were
549 * previously treated as not GT3, keep it like that.
550 */
551};
552
553static const struct intel_device_info intel_broadwell_gt3_info = {
554 BDW_PLATFORM,
555 .gt = 3,
556 .engine_mask =
557 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
558};
559
560static const struct intel_device_info intel_cherryview_info = {
561 PLATFORM(INTEL_CHERRYVIEW),
562 GEN(8),
563 .num_pipes = 3,
564 .display.has_hotplug = 1,
565 .is_lp = 1,
566 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
567 .has_64bit_reloc = 1,
568 .has_runtime_pm = 1,
569 .has_rc6 = 1,
570 .has_rps = true,
571 .has_logical_ring_contexts = 1,
572 .display.has_gmch = 1,
573 .ppgtt_type = INTEL_PPGTT_FULL,
574 .ppgtt_size = 32,
575 .has_reset_engine = 1,
576 .has_snoop = true,
577 .has_coherent_ggtt = false,
578 .display_mmio_offset = VLV_DISPLAY_BASE,
579 CHV_PIPE_OFFSETS,
580 CHV_CURSOR_OFFSETS,
581 CHV_COLORS,
582 GEN_DEFAULT_PAGE_SIZES,
583};
584
585#define GEN9_DEFAULT_PAGE_SIZES \
586 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
587 I915_GTT_PAGE_SIZE_64K
588
589#define GEN9_FEATURES \
590 GEN8_FEATURES, \
591 GEN(9), \
592 GEN9_DEFAULT_PAGE_SIZES, \
593 .has_logical_ring_preemption = 1, \
594 .display.has_csr = 1, \
595 .has_gt_uc = 1, \
596 .display.has_ipc = 1, \
597 .ddb_size = 896
598
599#define SKL_PLATFORM \
600 GEN9_FEATURES, \
601 PLATFORM(INTEL_SKYLAKE)
602
603static const struct intel_device_info intel_skylake_gt1_info = {
604 SKL_PLATFORM,
605 .gt = 1,
606};
607
608static const struct intel_device_info intel_skylake_gt2_info = {
609 SKL_PLATFORM,
610 .gt = 2,
611};
612
613#define SKL_GT3_PLUS_PLATFORM \
614 SKL_PLATFORM, \
615 .engine_mask = \
616 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
617
618
619static const struct intel_device_info intel_skylake_gt3_info = {
620 SKL_GT3_PLUS_PLATFORM,
621 .gt = 3,
622};
623
624static const struct intel_device_info intel_skylake_gt4_info = {
625 SKL_GT3_PLUS_PLATFORM,
626 .gt = 4,
627};
628
629#define GEN9_LP_FEATURES \
630 GEN(9), \
631 .is_lp = 1, \
632 .display.has_hotplug = 1, \
633 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
634 .num_pipes = 3, \
635 .has_64bit_reloc = 1, \
636 .display.has_ddi = 1, \
637 .has_fpga_dbg = 1, \
638 .display.has_fbc = 1, \
639 .display.has_psr = 1, \
640 .has_runtime_pm = 1, \
641 .display.has_csr = 1, \
642 .has_rc6 = 1, \
643 .has_rps = true, \
644 .display.has_dp_mst = 1, \
645 .has_logical_ring_contexts = 1, \
646 .has_logical_ring_preemption = 1, \
647 .has_gt_uc = 1, \
648 .ppgtt_type = INTEL_PPGTT_FULL, \
649 .ppgtt_size = 48, \
650 .has_reset_engine = 1, \
651 .has_snoop = true, \
652 .has_coherent_ggtt = false, \
653 .display.has_ipc = 1, \
654 HSW_PIPE_OFFSETS, \
655 IVB_CURSOR_OFFSETS, \
656 IVB_COLORS, \
657 GEN9_DEFAULT_PAGE_SIZES
658
659static const struct intel_device_info intel_broxton_info = {
660 GEN9_LP_FEATURES,
661 PLATFORM(INTEL_BROXTON),
662 .ddb_size = 512,
663};
664
665static const struct intel_device_info intel_geminilake_info = {
666 GEN9_LP_FEATURES,
667 PLATFORM(INTEL_GEMINILAKE),
668 .ddb_size = 1024,
669 GLK_COLORS,
670};
671
672#define KBL_PLATFORM \
673 GEN9_FEATURES, \
674 PLATFORM(INTEL_KABYLAKE)
675
676static const struct intel_device_info intel_kabylake_gt1_info = {
677 KBL_PLATFORM,
678 .gt = 1,
679};
680
681static const struct intel_device_info intel_kabylake_gt2_info = {
682 KBL_PLATFORM,
683 .gt = 2,
684};
685
686static const struct intel_device_info intel_kabylake_gt3_info = {
687 KBL_PLATFORM,
688 .gt = 3,
689 .engine_mask =
690 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
691};
692
693#define CFL_PLATFORM \
694 GEN9_FEATURES, \
695 PLATFORM(INTEL_COFFEELAKE)
696
697static const struct intel_device_info intel_coffeelake_gt1_info = {
698 CFL_PLATFORM,
699 .gt = 1,
700};
701
702static const struct intel_device_info intel_coffeelake_gt2_info = {
703 CFL_PLATFORM,
704 .gt = 2,
705};
706
707static const struct intel_device_info intel_coffeelake_gt3_info = {
708 CFL_PLATFORM,
709 .gt = 3,
710 .engine_mask =
711 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
712};
713
714#define GEN10_FEATURES \
715 GEN9_FEATURES, \
716 GEN(10), \
717 .ddb_size = 1024, \
718 .has_coherent_ggtt = false, \
719 GLK_COLORS
720
721static const struct intel_device_info intel_cannonlake_info = {
722 GEN10_FEATURES,
723 PLATFORM(INTEL_CANNONLAKE),
724 .gt = 2,
725};
726
727#define GEN11_DEFAULT_PAGE_SIZES \
728 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
729 I915_GTT_PAGE_SIZE_64K | \
730 I915_GTT_PAGE_SIZE_2M
731
732#define GEN11_FEATURES \
733 GEN10_FEATURES, \
734 GEN11_DEFAULT_PAGE_SIZES, \
735 .pipe_offsets = { \
736 [TRANSCODER_A] = PIPE_A_OFFSET, \
737 [TRANSCODER_B] = PIPE_B_OFFSET, \
738 [TRANSCODER_C] = PIPE_C_OFFSET, \
739 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
740 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
741 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
742 }, \
743 .trans_offsets = { \
744 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
745 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
746 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
747 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
748 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
749 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
750 }, \
751 GEN(11), \
752 .ddb_size = 2048, \
753 .has_logical_ring_elsq = 1, \
754 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
755
756static const struct intel_device_info intel_icelake_11_info = {
757 GEN11_FEATURES,
758 PLATFORM(INTEL_ICELAKE),
759 .engine_mask =
760 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
761};
762
763static const struct intel_device_info intel_elkhartlake_info = {
764 GEN11_FEATURES,
765 PLATFORM(INTEL_ELKHARTLAKE),
766 .require_force_probe = 1,
767 .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
768 .ppgtt_size = 36,
769};
770
771#define GEN12_FEATURES \
772 GEN11_FEATURES, \
773 GEN(12), \
774 .pipe_offsets = { \
775 [TRANSCODER_A] = PIPE_A_OFFSET, \
776 [TRANSCODER_B] = PIPE_B_OFFSET, \
777 [TRANSCODER_C] = PIPE_C_OFFSET, \
778 [TRANSCODER_D] = PIPE_D_OFFSET, \
779 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
780 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
781 }, \
782 .trans_offsets = { \
783 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
784 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
785 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
786 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
787 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
788 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
789 }, \
790 .has_global_mocs = 1
791
792static const struct intel_device_info intel_tigerlake_12_info = {
793 GEN12_FEATURES,
794 PLATFORM(INTEL_TIGERLAKE),
795 .num_pipes = 4,
796 .require_force_probe = 1,
797 .display.has_modular_fia = 1,
798 .engine_mask =
799 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
800};
801
802#undef GEN
803#undef PLATFORM
804
805/*
806 * Make sure any device matches here are from most specific to most
807 * general. For example, since the Quanta match is based on the subsystem
808 * and subvendor IDs, we need it to come before the more general IVB
809 * PCI ID matches, otherwise we'll use the wrong info struct above.
810 */
811static const struct pci_device_id pciidlist[] = {
812 INTEL_I830_IDS(&intel_i830_info),
813 INTEL_I845G_IDS(&intel_i845g_info),
814 INTEL_I85X_IDS(&intel_i85x_info),
815 INTEL_I865G_IDS(&intel_i865g_info),
816 INTEL_I915G_IDS(&intel_i915g_info),
817 INTEL_I915GM_IDS(&intel_i915gm_info),
818 INTEL_I945G_IDS(&intel_i945g_info),
819 INTEL_I945GM_IDS(&intel_i945gm_info),
820 INTEL_I965G_IDS(&intel_i965g_info),
821 INTEL_G33_IDS(&intel_g33_info),
822 INTEL_I965GM_IDS(&intel_i965gm_info),
823 INTEL_GM45_IDS(&intel_gm45_info),
824 INTEL_G45_IDS(&intel_g45_info),
825 INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
826 INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
827 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
828 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
829 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
830 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
831 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
832 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
833 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
834 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
835 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
836 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
837 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
838 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
839 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
840 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
841 INTEL_VLV_IDS(&intel_valleyview_info),
842 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
843 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
844 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
845 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
846 INTEL_CHV_IDS(&intel_cherryview_info),
847 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
848 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
849 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
850 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
851 INTEL_BXT_IDS(&intel_broxton_info),
852 INTEL_GLK_IDS(&intel_geminilake_info),
853 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
854 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
855 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
856 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
857 INTEL_AML_KBL_GT2_IDS(&intel_kabylake_gt2_info),
858 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
859 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
860 INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
861 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
862 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
863 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
864 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),
865 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
866 INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
867 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
868 INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
869 INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
870 INTEL_CNL_IDS(&intel_cannonlake_info),
871 INTEL_ICL_11_IDS(&intel_icelake_11_info),
872 INTEL_EHL_IDS(&intel_elkhartlake_info),
873 INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
874 {0, 0, 0}
875};
876MODULE_DEVICE_TABLE(pci, pciidlist);
877
878static void i915_pci_remove(struct pci_dev *pdev)
879{
880 struct drm_i915_private *i915;
881
882 i915 = pci_get_drvdata(pdev);
883 if (!i915) /* driver load aborted, nothing to cleanup */
884 return;
885
886 i915_driver_remove(i915);
887 pci_set_drvdata(pdev, NULL);
888
889 drm_dev_put(&i915->drm);
890}
891
892/* is device_id present in comma separated list of ids */
893static bool force_probe(u16 device_id, const char *devices)
894{
895 char *s, *p, *tok;
896 bool ret;
897
898 /* FIXME: transitional */
899 if (i915_modparams.alpha_support) {
900 DRM_INFO("i915.alpha_support is deprecated, use i915.force_probe=%04x instead\n",
901 device_id);
902 return true;
903 }
904
905 if (!devices || !*devices)
906 return false;
907
908 /* match everything */
909 if (strcmp(devices, "*") == 0)
910 return true;
911
912 s = kstrdup(devices, GFP_KERNEL);
913 if (!s)
914 return false;
915
916 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
917 u16 val;
918
919 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
920 ret = true;
921 break;
922 }
923 }
924
925 kfree(s);
926
927 return ret;
928}
929
930static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
931{
932 struct intel_device_info *intel_info =
933 (struct intel_device_info *) ent->driver_data;
934 int err;
935
936 if (intel_info->require_force_probe &&
937 !force_probe(pdev->device, i915_modparams.force_probe)) {
938 DRM_INFO("Your graphics device %04x is not properly supported by the driver in this\n"
939 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
940 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
941 "or (recommended) check for kernel updates.\n",
942 pdev->device, pdev->device, pdev->device);
943 return -ENODEV;
944 }
945
946 /* Only bind to function 0 of the device. Early generations
947 * used function 1 as a placeholder for multi-head. This causes
948 * us confusion instead, especially on the systems where both
949 * functions have the same PCI-ID!
950 */
951 if (PCI_FUNC(pdev->devfn))
952 return -ENODEV;
953
954 /*
955 * apple-gmux is needed on dual GPU MacBook Pro
956 * to probe the panel if we're the inactive GPU.
957 */
958 if (vga_switcheroo_client_probe_defer(pdev))
959 return -EPROBE_DEFER;
960
961 err = i915_driver_probe(pdev, ent);
962 if (err)
963 return err;
964
965 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
966 i915_pci_remove(pdev);
967 return -ENODEV;
968 }
969
970 err = i915_live_selftests(pdev);
971 if (err) {
972 i915_pci_remove(pdev);
973 return err > 0 ? -ENOTTY : err;
974 }
975
976 return 0;
977}
978
979static struct pci_driver i915_pci_driver = {
980 .name = DRIVER_NAME,
981 .id_table = pciidlist,
982 .probe = i915_pci_probe,
983 .remove = i915_pci_remove,
984 .driver.pm = &i915_pm_ops,
985};
986
987static int __init i915_init(void)
988{
989 bool use_kms = true;
990 int err;
991
992 err = i915_globals_init();
993 if (err)
994 return err;
995
996 err = i915_mock_selftests();
997 if (err)
998 return err > 0 ? 0 : err;
999
1000 /*
1001 * Enable KMS by default, unless explicitly overriden by
1002 * either the i915.modeset prarameter or by the
1003 * vga_text_mode_force boot option.
1004 */
1005
1006 if (i915_modparams.modeset == 0)
1007 use_kms = false;
1008
1009 if (vgacon_text_force() && i915_modparams.modeset == -1)
1010 use_kms = false;
1011
1012 if (!use_kms) {
1013 /* Silently fail loading to not upset userspace. */
1014 DRM_DEBUG_DRIVER("KMS disabled.\n");
1015 return 0;
1016 }
1017
1018 return pci_register_driver(&i915_pci_driver);
1019}
1020
1021static void __exit i915_exit(void)
1022{
1023 if (!i915_pci_driver.driver.owner)
1024 return;
1025
1026 pci_unregister_driver(&i915_pci_driver);
1027 i915_globals_exit();
1028}
1029
1030module_init(i915_init);
1031module_exit(i915_exit);
1032
1033MODULE_AUTHOR("Tungsten Graphics, Inc.");
1034MODULE_AUTHOR("Intel Corporation");
1035
1036MODULE_DESCRIPTION(DRIVER_DESC);
1037MODULE_LICENSE("GPL and additional rights");