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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "dc.h"
28#include "dcn_calcs.h"
29#include "dcn_calc_auto.h"
30#include "dal_asic_id.h"
31#include "resource.h"
32#include "dcn10/dcn10_resource.h"
33#include "dcn10/dcn10_hubbub.h"
34#include "dml/dml1_display_rq_dlg_calc.h"
35
36#include "dcn_calc_math.h"
37
38#define DC_LOGGER \
39 dc->ctx->logger
40
41#define WM_SET_COUNT 4
42#define WM_A 0
43#define WM_B 1
44#define WM_C 2
45#define WM_D 3
46
47/*
48 * NOTE:
49 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
50 *
51 * It doesn't adhere to Linux kernel style and sometimes will do things in odd
52 * ways. Unless there is something clearly wrong with it the code should
53 * remain as-is as it provides us with a guarantee from HW that it is correct.
54 */
55
56#ifdef CONFIG_DRM_AMD_DC_DCN2_0
57/* Defaults from spreadsheet rev#247.
58 * RV2 delta: dram_clock_change_latency, max_num_dpp
59 */
60#else
61/* Defaults from spreadsheet rev#247 */
62#endif
63const struct dcn_soc_bounding_box dcn10_soc_defaults = {
64 /* latencies */
65 .sr_exit_time = 17, /*us*/
66 .sr_enter_plus_exit_time = 19, /*us*/
67 .urgent_latency = 4, /*us*/
68 .dram_clock_change_latency = 17, /*us*/
69 .write_back_latency = 12, /*us*/
70 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
71
72 /* below default clocks derived from STA target base on
73 * slow-slow corner + 10% margin with voltages aligned to FCLK.
74 *
75 * Use these value if fused value doesn't make sense as earlier
76 * part don't have correct value fused */
77 /* default DCF CLK DPM on RV*/
78 .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */
79 .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */
80 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
81 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
82
83 /* default DISP CLK voltage state on RV */
84 .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */
85 .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */
86 .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */
87 .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */
88
89 /* default DPP CLK voltage state on RV */
90 .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */
91 .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */
92 .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */
93 .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */
94
95 /* default PHY CLK voltage state on RV */
96 .phyclkv_max0p9 = 900, /*MHz*/
97 .phyclkv_nom0p8 = 847, /*MHz*/
98 .phyclkv_mid0p72 = 800, /*MHz*/
99 .phyclkv_min0p65 = 600, /*MHz*/
100
101 /* BW depend on FCLK, MCLK, # of channels */
102 /* dual channel BW */
103 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
104 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
105 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
106 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
107 /* single channel BW
108 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
109 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
110 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
111 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
112 */
113
114 .number_of_channels = 2,
115
116 .socclk = 208, /*MHz*/
117 .downspreading = 0.5f, /*%*/
118 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
119 .urgent_out_of_order_return_per_channel = 256, /*bytes*/
120 .vmm_page_size = 4096, /*bytes*/
121 .return_bus_width = 64, /*bytes*/
122 .max_request_size = 256, /*bytes*/
123
124 /* Depends on user class (client vs embedded, workstation, etc) */
125 .percent_disp_bw_limit = 0.3f /*%*/
126};
127
128const struct dcn_ip_params dcn10_ip_defaults = {
129 .rob_buffer_size_in_kbyte = 64,
130 .det_buffer_size_in_kbyte = 164,
131 .dpp_output_buffer_pixels = 2560,
132 .opp_output_buffer_lines = 1,
133 .pixel_chunk_size_in_kbyte = 8,
134 .pte_enable = dcn_bw_yes,
135 .pte_chunk_size = 2, /*kbytes*/
136 .meta_chunk_size = 2, /*kbytes*/
137 .writeback_chunk_size = 2, /*kbytes*/
138 .odm_capability = dcn_bw_no,
139 .dsc_capability = dcn_bw_no,
140 .line_buffer_size = 589824, /*bit*/
141 .max_line_buffer_lines = 12,
142 .is_line_buffer_bpp_fixed = dcn_bw_no,
143 .line_buffer_fixed_bpp = dcn_bw_na,
144 .writeback_luma_buffer_size = 12, /*kbytes*/
145 .writeback_chroma_buffer_size = 8, /*kbytes*/
146 .max_num_dpp = 4,
147 .max_num_writeback = 2,
148 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
149 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
150 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
151 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
152 .max_hscl_ratio = 4,
153 .max_vscl_ratio = 4,
154 .max_hscl_taps = 8,
155 .max_vscl_taps = 8,
156 .pte_buffer_size_in_requests = 42,
157 .dispclk_ramping_margin = 1, /*%*/
158 .under_scan_factor = 1.11f,
159 .max_inter_dcn_tile_repeaters = 8,
160 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
161 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
162 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
163};
164
165static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
166{
167 switch (sw_mode) {
168 case DC_SW_LINEAR:
169 return dcn_bw_sw_linear;
170 case DC_SW_4KB_S:
171 return dcn_bw_sw_4_kb_s;
172 case DC_SW_4KB_D:
173 return dcn_bw_sw_4_kb_d;
174 case DC_SW_64KB_S:
175 return dcn_bw_sw_64_kb_s;
176 case DC_SW_64KB_D:
177 return dcn_bw_sw_64_kb_d;
178 case DC_SW_VAR_S:
179 return dcn_bw_sw_var_s;
180 case DC_SW_VAR_D:
181 return dcn_bw_sw_var_d;
182 case DC_SW_64KB_S_T:
183 return dcn_bw_sw_64_kb_s_t;
184 case DC_SW_64KB_D_T:
185 return dcn_bw_sw_64_kb_d_t;
186 case DC_SW_4KB_S_X:
187 return dcn_bw_sw_4_kb_s_x;
188 case DC_SW_4KB_D_X:
189 return dcn_bw_sw_4_kb_d_x;
190 case DC_SW_64KB_S_X:
191 return dcn_bw_sw_64_kb_s_x;
192 case DC_SW_64KB_D_X:
193 return dcn_bw_sw_64_kb_d_x;
194 case DC_SW_VAR_S_X:
195 return dcn_bw_sw_var_s_x;
196 case DC_SW_VAR_D_X:
197 return dcn_bw_sw_var_d_x;
198 case DC_SW_256B_S:
199 case DC_SW_256_D:
200 case DC_SW_256_R:
201 case DC_SW_4KB_R:
202 case DC_SW_64KB_R:
203 case DC_SW_VAR_R:
204 case DC_SW_4KB_R_X:
205 case DC_SW_64KB_R_X:
206 case DC_SW_VAR_R_X:
207 default:
208 BREAK_TO_DEBUGGER(); /*not in formula*/
209 return dcn_bw_sw_4_kb_s;
210 }
211}
212
213static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
214{
215 switch (depth) {
216 case LB_PIXEL_DEPTH_18BPP:
217 return 18;
218 case LB_PIXEL_DEPTH_24BPP:
219 return 24;
220 case LB_PIXEL_DEPTH_30BPP:
221 return 30;
222 case LB_PIXEL_DEPTH_36BPP:
223 return 36;
224 default:
225 return 30;
226 }
227}
228
229static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
230{
231 switch (format) {
232 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
233 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
234 return dcn_bw_rgb_sub_16;
235 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
236 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
237 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
238 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
239 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
240 return dcn_bw_rgb_sub_32;
241 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
242 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
243 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
244 return dcn_bw_rgb_sub_64;
245 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
246 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
247 return dcn_bw_yuv420_sub_8;
248 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
249 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
250 return dcn_bw_yuv420_sub_10;
251 default:
252 return dcn_bw_rgb_sub_32;
253 }
254}
255
256enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
257{
258 switch (sw_mode) {
259 /* for 4/8/16 high tiles */
260 case DC_SW_LINEAR:
261 return dm_4k_tile;
262 case DC_SW_4KB_S:
263 case DC_SW_4KB_S_X:
264 return dm_4k_tile;
265 case DC_SW_64KB_S:
266 case DC_SW_64KB_S_X:
267 case DC_SW_64KB_S_T:
268 return dm_64k_tile;
269 case DC_SW_VAR_S:
270 case DC_SW_VAR_S_X:
271 return dm_256k_tile;
272
273 /* For 64bpp 2 high tiles */
274 case DC_SW_4KB_D:
275 case DC_SW_4KB_D_X:
276 return dm_4k_tile;
277 case DC_SW_64KB_D:
278 case DC_SW_64KB_D_X:
279 case DC_SW_64KB_D_T:
280 return dm_64k_tile;
281 case DC_SW_VAR_D:
282 case DC_SW_VAR_D_X:
283 return dm_256k_tile;
284
285 case DC_SW_4KB_R:
286 case DC_SW_4KB_R_X:
287 return dm_4k_tile;
288 case DC_SW_64KB_R:
289 case DC_SW_64KB_R_X:
290 return dm_64k_tile;
291 case DC_SW_VAR_R:
292 case DC_SW_VAR_R_X:
293 return dm_256k_tile;
294
295 /* Unsupported swizzle modes for dcn */
296 case DC_SW_256B_S:
297 default:
298 ASSERT(0); /* Not supported */
299 return 0;
300 }
301}
302
303static void pipe_ctx_to_e2e_pipe_params (
304 const struct pipe_ctx *pipe,
305 struct _vcs_dpi_display_pipe_params_st *input)
306{
307 input->src.is_hsplit = false;
308 if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state)
309 input->src.is_hsplit = true;
310 else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state)
311 input->src.is_hsplit = true;
312
313 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
314 /*
315 * this method requires us to always re-calculate watermark when dcc change
316 * between flip.
317 */
318 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
319 } else {
320 /*
321 * allow us to disable dcc on the fly without re-calculating WM
322 *
323 * extra overhead for DCC is quite small. for 1080p WM without
324 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
325 */
326 unsigned int bpe;
327
328 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
329 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
330 }
331 input->src.dcc_rate = 1;
332 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;
333 input->src.source_scan = dm_horz;
334 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
335
336 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;
337 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;
338 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;
339 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;
340 input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */
341 input->src.cur0_bpp = 32;
342
343 input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
344
345 switch (pipe->plane_state->rotation) {
346 case ROTATION_ANGLE_0:
347 case ROTATION_ANGLE_180:
348 input->src.source_scan = dm_horz;
349 break;
350 case ROTATION_ANGLE_90:
351 case ROTATION_ANGLE_270:
352 input->src.source_scan = dm_vert;
353 break;
354 default:
355 ASSERT(0); /* Not supported */
356 break;
357 }
358
359 /* TODO: Fix pixel format mappings */
360 switch (pipe->plane_state->format) {
361 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
362 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
363 input->src.source_format = dm_420_8;
364 input->src.viewport_width_c = input->src.viewport_width / 2;
365 input->src.viewport_height_c = input->src.viewport_height / 2;
366 break;
367 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
368 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
369 input->src.source_format = dm_420_10;
370 input->src.viewport_width_c = input->src.viewport_width / 2;
371 input->src.viewport_height_c = input->src.viewport_height / 2;
372 break;
373 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
374 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
375 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
376 input->src.source_format = dm_444_64;
377 input->src.viewport_width_c = input->src.viewport_width;
378 input->src.viewport_height_c = input->src.viewport_height;
379 break;
380 default:
381 input->src.source_format = dm_444_32;
382 input->src.viewport_width_c = input->src.viewport_width;
383 input->src.viewport_height_c = input->src.viewport_height;
384 break;
385 }
386
387 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
388 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
389 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
390 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;
391 if (input->scale_ratio_depth.vinit < 1.0)
392 input->scale_ratio_depth.vinit = 1;
393 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
394 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
395 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;
396 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
397 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
398 input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
399 if (input->scale_ratio_depth.vinit_c < 1.0)
400 input->scale_ratio_depth.vinit_c = 1;
401 switch (pipe->plane_res.scl_data.lb_params.depth) {
402 case LB_PIXEL_DEPTH_30BPP:
403 input->scale_ratio_depth.lb_depth = 30; break;
404 case LB_PIXEL_DEPTH_36BPP:
405 input->scale_ratio_depth.lb_depth = 36; break;
406 default:
407 input->scale_ratio_depth.lb_depth = 24; break;
408 }
409
410
411 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
412 + pipe->stream->timing.v_border_bottom;
413
414 input->dest.recout_width = pipe->plane_res.scl_data.recout.width;
415 input->dest.recout_height = pipe->plane_res.scl_data.recout.height;
416
417 input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width;
418 input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height;
419
420 input->dest.htotal = pipe->stream->timing.h_total;
421 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;
422 input->dest.hblank_end = input->dest.hblank_start
423 - pipe->stream->timing.h_addressable
424 - pipe->stream->timing.h_border_left
425 - pipe->stream->timing.h_border_right;
426
427 input->dest.vtotal = pipe->stream->timing.v_total;
428 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;
429 input->dest.vblank_end = input->dest.vblank_start
430 - pipe->stream->timing.v_addressable
431 - pipe->stream->timing.v_border_bottom
432 - pipe->stream->timing.v_border_top;
433 input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
434 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
435 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
436 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
437 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
438
439}
440
441static void dcn_bw_calc_rq_dlg_ttu(
442 const struct dc *dc,
443 const struct dcn_bw_internal_vars *v,
444 struct pipe_ctx *pipe,
445 int in_idx)
446{
447 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
448 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
449 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
450 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
451 struct _vcs_dpi_display_rq_params_st rq_param = {0};
452 struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
453 struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
454 float total_active_bw = 0;
455 float total_prefetch_bw = 0;
456 int total_flip_bytes = 0;
457 int i;
458
459 memset(dlg_regs, 0, sizeof(*dlg_regs));
460 memset(ttu_regs, 0, sizeof(*ttu_regs));
461 memset(rq_regs, 0, sizeof(*rq_regs));
462
463 for (i = 0; i < number_of_planes; i++) {
464 total_active_bw += v->read_bandwidth[i];
465 total_prefetch_bw += v->prefetch_bandwidth[i];
466 total_flip_bytes += v->total_immediate_flip_bytes[i];
467 }
468 dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
469 if (dlg_sys_param.total_flip_bw < 0.0)
470 dlg_sys_param.total_flip_bw = 0;
471
472 dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
473 dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
474 dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
475 dlg_sys_param.t_extra_us = v->urgent_extra_latency;
476 dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
477 dlg_sys_param.total_flip_bytes = total_flip_bytes;
478
479 pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
480 input.clks_cfg.dcfclk_mhz = v->dcfclk;
481 input.clks_cfg.dispclk_mhz = v->dispclk;
482 input.clks_cfg.dppclk_mhz = v->dppclk;
483 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
484 input.clks_cfg.socclk_mhz = v->socclk;
485 input.clks_cfg.voltage = v->voltage_level;
486// dc->dml.logger = pool->base.logger;
487 input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
488 input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
489 //input[in_idx].dout.output_standard;
490
491 /*todo: soc->sr_enter_plus_exit_time??*/
492 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
493
494 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
495 dml1_extract_rq_regs(dml, rq_regs, rq_param);
496 dml1_rq_dlg_get_dlg_params(
497 dml,
498 dlg_regs,
499 ttu_regs,
500 rq_param.dlg,
501 dlg_sys_param,
502 input,
503 true,
504 true,
505 v->pte_enable == dcn_bw_yes,
506 pipe->plane_state->flip_immediate);
507}
508
509static void split_stream_across_pipes(
510 struct resource_context *res_ctx,
511 const struct resource_pool *pool,
512 struct pipe_ctx *primary_pipe,
513 struct pipe_ctx *secondary_pipe)
514{
515 int pipe_idx = secondary_pipe->pipe_idx;
516
517 if (!primary_pipe->plane_state)
518 return;
519
520 *secondary_pipe = *primary_pipe;
521
522 secondary_pipe->pipe_idx = pipe_idx;
523 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
524 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
525 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
526 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
527 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
528 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
529 if (primary_pipe->bottom_pipe) {
530 ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
531 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
532 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
533 }
534 primary_pipe->bottom_pipe = secondary_pipe;
535 secondary_pipe->top_pipe = primary_pipe;
536
537 resource_build_scaling_params(primary_pipe);
538 resource_build_scaling_params(secondary_pipe);
539}
540
541#if 0
542static void calc_wm_sets_and_perf_params(
543 struct dc_state *context,
544 struct dcn_bw_internal_vars *v)
545{
546 /* Calculate set A last to keep internal var state consistent for required config */
547 if (v->voltage_level < 2) {
548 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
549 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
550 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
551 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
552
553 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
554 v->stutter_exit_watermark * 1000;
555 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
556 v->stutter_enter_plus_exit_watermark * 1000;
557 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
558 v->dram_clock_change_watermark * 1000;
559 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
560 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
561
562 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
563 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
564 v->dcfclk = v->dcfclkv_nom0p8;
565 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
566
567 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
568 v->stutter_exit_watermark * 1000;
569 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
570 v->stutter_enter_plus_exit_watermark * 1000;
571 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
572 v->dram_clock_change_watermark * 1000;
573 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
574 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
575 }
576
577 if (v->voltage_level < 3) {
578 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
579 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
580 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
581 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
582 v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
583 v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
584 v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
585 v->dcfclk = v->dcfclkv_max0p9;
586 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
587
588 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
589 v->stutter_exit_watermark * 1000;
590 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
591 v->stutter_enter_plus_exit_watermark * 1000;
592 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
593 v->dram_clock_change_watermark * 1000;
594 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
595 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
596 }
597
598 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
599 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
600 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
601 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
602 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
603 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
604 v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
605 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
606 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
607
608 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
609 v->stutter_exit_watermark * 1000;
610 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
611 v->stutter_enter_plus_exit_watermark * 1000;
612 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
613 v->dram_clock_change_watermark * 1000;
614 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
615 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
616 if (v->voltage_level >= 2) {
617 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
618 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
619 }
620 if (v->voltage_level >= 3)
621 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
622}
623#endif
624
625static bool dcn_bw_apply_registry_override(struct dc *dc)
626{
627 bool updated = false;
628
629 kernel_fpu_begin();
630 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
631 && dc->debug.sr_exit_time_ns) {
632 updated = true;
633 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
634 }
635
636 if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
637 != dc->debug.sr_enter_plus_exit_time_ns
638 && dc->debug.sr_enter_plus_exit_time_ns) {
639 updated = true;
640 dc->dcn_soc->sr_enter_plus_exit_time =
641 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
642 }
643
644 if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
645 && dc->debug.urgent_latency_ns) {
646 updated = true;
647 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
648 }
649
650 if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
651 != dc->debug.percent_of_ideal_drambw
652 && dc->debug.percent_of_ideal_drambw) {
653 updated = true;
654 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
655 dc->debug.percent_of_ideal_drambw;
656 }
657
658 if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
659 != dc->debug.dram_clock_change_latency_ns
660 && dc->debug.dram_clock_change_latency_ns) {
661 updated = true;
662 dc->dcn_soc->dram_clock_change_latency =
663 dc->debug.dram_clock_change_latency_ns / 1000.0;
664 }
665 kernel_fpu_end();
666
667 return updated;
668}
669
670static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
671{
672 /*
673 * disable optional pipe split by lower dispclk bounding box
674 * at DPM0
675 */
676 v->max_dispclk[0] = v->max_dppclk_vmin0p65;
677}
678
679static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
680 unsigned int pixel_rate_100hz)
681{
682 float pixel_rate_mhz = pixel_rate_100hz / 10000;
683
684 /*
685 * force enabling pipe split by lower dpp clock for DPM0 to just
686 * below the specify pixel_rate, so bw calc would split pipe.
687 */
688 if (pixel_rate_mhz < v->max_dppclk[0])
689 v->max_dppclk[0] = pixel_rate_mhz;
690}
691
692static void hack_bounding_box(struct dcn_bw_internal_vars *v,
693 struct dc_debug_options *dbg,
694 struct dc_state *context)
695{
696 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
697 hack_disable_optional_pipe_split(v);
698
699 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
700 context->stream_count >= 2)
701 hack_disable_optional_pipe_split(v);
702
703 if (context->stream_count == 1 &&
704 dbg->force_single_disp_pipe_split)
705 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
706}
707
708
709unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
710{
711 /* for dali, the highest voltage level we want is 0 */
712 if (ASICREV_IS_DALI(hw_internal_rev))
713 return 0;
714
715 /* we are ok with all levels */
716 return 4;
717}
718
719bool dcn_validate_bandwidth(
720 struct dc *dc,
721 struct dc_state *context,
722 bool fast_validate)
723{
724 /*
725 * we want a breakdown of the various stages of validation, which the
726 * perf_trace macro doesn't support
727 */
728 BW_VAL_TRACE_SETUP();
729
730 const struct resource_pool *pool = dc->res_pool;
731 struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
732 int i, input_idx, k;
733 int vesa_sync_start, asic_blank_end, asic_blank_start;
734 bool bw_limit_pass;
735 float bw_limit;
736
737 PERFORMANCE_TRACE_START();
738
739 BW_VAL_TRACE_COUNT();
740
741 if (dcn_bw_apply_registry_override(dc))
742 dcn_bw_sync_calcs_and_dml(dc);
743
744 memset(v, 0, sizeof(*v));
745 kernel_fpu_begin();
746
747 v->sr_exit_time = dc->dcn_soc->sr_exit_time;
748 v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
749 v->urgent_latency = dc->dcn_soc->urgent_latency;
750 v->write_back_latency = dc->dcn_soc->write_back_latency;
751 v->percent_of_ideal_drambw_received_after_urg_latency =
752 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
753
754 v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
755 v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
756 v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
757 v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
758
759 v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
760 v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
761 v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
762 v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
763
764 v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
765 v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
766 v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
767 v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
768
769 v->socclk = dc->dcn_soc->socclk;
770
771 v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
772 v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
773 v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
774 v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
775
776 v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
777 v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
778 v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
779 v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
780
781 v->downspreading = dc->dcn_soc->downspreading;
782 v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
783 v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
784 v->number_of_channels = dc->dcn_soc->number_of_channels;
785 v->vmm_page_size = dc->dcn_soc->vmm_page_size;
786 v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
787 v->return_bus_width = dc->dcn_soc->return_bus_width;
788
789 v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
790 v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
791 v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
792 v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
793 v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
794 v->pte_enable = dc->dcn_ip->pte_enable;
795 v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
796 v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
797 v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
798 v->odm_capability = dc->dcn_ip->odm_capability;
799 v->dsc_capability = dc->dcn_ip->dsc_capability;
800 v->line_buffer_size = dc->dcn_ip->line_buffer_size;
801 v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
802 v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
803 v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
804 v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
805 v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
806 v->max_num_dpp = dc->dcn_ip->max_num_dpp;
807 v->max_num_writeback = dc->dcn_ip->max_num_writeback;
808 v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
809 v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
810 v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
811 v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
812 v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
813 v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
814 v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
815 v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
816 v->under_scan_factor = dc->dcn_ip->under_scan_factor;
817 v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
818 v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
819 v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
820 v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
821 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
822 v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
823 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
824
825 v->voltage[5] = dcn_bw_no_support;
826 v->voltage[4] = dcn_bw_v_max0p9;
827 v->voltage[3] = dcn_bw_v_max0p9;
828 v->voltage[2] = dcn_bw_v_nom0p8;
829 v->voltage[1] = dcn_bw_v_mid0p72;
830 v->voltage[0] = dcn_bw_v_min0p65;
831 v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
832 v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
833 v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
834 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
835 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
836 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
837 v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
838 v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
839 v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
840 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
841 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
842 v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
843 v->max_dispclk[5] = v->max_dispclk_vmax0p9;
844 v->max_dispclk[4] = v->max_dispclk_vmax0p9;
845 v->max_dispclk[3] = v->max_dispclk_vmax0p9;
846 v->max_dispclk[2] = v->max_dispclk_vnom0p8;
847 v->max_dispclk[1] = v->max_dispclk_vmid0p72;
848 v->max_dispclk[0] = v->max_dispclk_vmin0p65;
849 v->max_dppclk[5] = v->max_dppclk_vmax0p9;
850 v->max_dppclk[4] = v->max_dppclk_vmax0p9;
851 v->max_dppclk[3] = v->max_dppclk_vmax0p9;
852 v->max_dppclk[2] = v->max_dppclk_vnom0p8;
853 v->max_dppclk[1] = v->max_dppclk_vmid0p72;
854 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
855 v->phyclk_per_state[5] = v->phyclkv_max0p9;
856 v->phyclk_per_state[4] = v->phyclkv_max0p9;
857 v->phyclk_per_state[3] = v->phyclkv_max0p9;
858 v->phyclk_per_state[2] = v->phyclkv_nom0p8;
859 v->phyclk_per_state[1] = v->phyclkv_mid0p72;
860 v->phyclk_per_state[0] = v->phyclkv_min0p65;
861 v->synchronized_vblank = dcn_bw_no;
862 v->ta_pscalculation = dcn_bw_override;
863 v->allow_different_hratio_vratio = dcn_bw_yes;
864
865 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
866 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
867
868 if (!pipe->stream)
869 continue;
870 /* skip all but first of split pipes */
871 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
872 continue;
873
874 v->underscan_output[input_idx] = false; /* taken care of in recout already*/
875 v->interlace_output[input_idx] = false;
876
877 v->htotal[input_idx] = pipe->stream->timing.h_total;
878 v->vtotal[input_idx] = pipe->stream->timing.v_total;
879 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
880 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
881 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
882 - v->vactive[input_idx]
883 - pipe->stream->timing.v_front_porch;
884 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
885 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
886 v->pixel_clock[input_idx] *= 2;
887 if (!pipe->plane_state) {
888 v->dcc_enable[input_idx] = dcn_bw_yes;
889 v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
890 v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
891 v->lb_bit_per_pixel[input_idx] = 30;
892 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
893 v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
894 /*
895 * for cases where we have no plane, we want to validate up to 1080p
896 * source size because here we are only interested in if the output
897 * timing is supported or not. if we cannot support native resolution
898 * of the high res display, we still want to support lower res up scale
899 * to native
900 */
901 if (v->viewport_width[input_idx] > 1920)
902 v->viewport_width[input_idx] = 1920;
903 if (v->viewport_height[input_idx] > 1080)
904 v->viewport_height[input_idx] = 1080;
905 v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
906 v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
907 v->override_hta_ps[input_idx] = 1;
908 v->override_vta_ps[input_idx] = 1;
909 v->override_hta_pschroma[input_idx] = 1;
910 v->override_vta_pschroma[input_idx] = 1;
911 v->source_scan[input_idx] = dcn_bw_hor;
912
913 } else {
914 v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height;
915 v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
916 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
917 v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
918 if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
919 if (pipe->plane_state->rotation % 2 == 0) {
920 int viewport_end = pipe->plane_res.scl_data.viewport.width
921 + pipe->plane_res.scl_data.viewport.x;
922 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
923 + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
924
925 if (viewport_end > viewport_b_end)
926 v->viewport_width[input_idx] = viewport_end
927 - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
928 else
929 v->viewport_width[input_idx] = viewport_b_end
930 - pipe->plane_res.scl_data.viewport.x;
931 } else {
932 int viewport_end = pipe->plane_res.scl_data.viewport.height
933 + pipe->plane_res.scl_data.viewport.y;
934 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
935 + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
936
937 if (viewport_end > viewport_b_end)
938 v->viewport_height[input_idx] = viewport_end
939 - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
940 else
941 v->viewport_height[input_idx] = viewport_b_end
942 - pipe->plane_res.scl_data.viewport.y;
943 }
944 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
945 + pipe->bottom_pipe->plane_res.scl_data.recout.width;
946 }
947
948 if (pipe->plane_state->rotation % 2 == 0) {
949 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
950 || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
951 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
952 || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
953 } else {
954 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
955 || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
956 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
957 || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
958 }
959
960 if (dc->debug.optimized_watermark) {
961 /*
962 * this method requires us to always re-calculate watermark when dcc change
963 * between flip.
964 */
965 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
966 } else {
967 /*
968 * allow us to disable dcc on the fly without re-calculating WM
969 *
970 * extra overhead for DCC is quite small. for 1080p WM without
971 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
972 */
973 unsigned int bpe;
974
975 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
976 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
977 }
978
979 v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
980 pipe->plane_state->format);
981 v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
982 pipe->plane_state->tiling_info.gfx9.swizzle);
983 v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
984 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
985 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
986 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
987 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
988 /*
989 * Spreadsheet doesn't handle taps_c is one properly,
990 * need to force Chroma to always be scaled to pass
991 * bandwidth validation.
992 */
993 if (v->override_hta_pschroma[input_idx] == 1)
994 v->override_hta_pschroma[input_idx] = 2;
995 if (v->override_vta_pschroma[input_idx] == 1)
996 v->override_vta_pschroma[input_idx] = 2;
997 v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
998 }
999 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
1000 v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
1001 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
1002 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
1003 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
1004 v->output[input_idx] = pipe->stream->signal ==
1005 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
1006 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
1007 if (v->output[input_idx] == dcn_bw_hdmi) {
1008 switch (pipe->stream->timing.display_color_depth) {
1009 case COLOR_DEPTH_101010:
1010 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
1011 break;
1012 case COLOR_DEPTH_121212:
1013 v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc;
1014 break;
1015 case COLOR_DEPTH_161616:
1016 v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc;
1017 break;
1018 default:
1019 break;
1020 }
1021 }
1022
1023 input_idx++;
1024 }
1025 v->number_of_active_planes = input_idx;
1026
1027 scaler_settings_calculation(v);
1028
1029 hack_bounding_box(v, &dc->debug, context);
1030
1031 mode_support_and_system_configuration(v);
1032
1033 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
1034 if (v->voltage_level != 0
1035 && context->stream_count == 1
1036 && dc->debug.force_single_disp_pipe_split) {
1037 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
1038 mode_support_and_system_configuration(v);
1039 }
1040
1041 if (v->voltage_level == 0 &&
1042 (dc->debug.sr_exit_time_dpm0_ns
1043 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
1044
1045 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
1046 v->sr_enter_plus_exit_time =
1047 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1048 if (dc->debug.sr_exit_time_dpm0_ns)
1049 v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1050 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1051 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1052 mode_support_and_system_configuration(v);
1053 }
1054
1055 display_pipe_configuration(v);
1056
1057 for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1058 if (v->source_scan[k] == dcn_bw_hor)
1059 v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
1060 else
1061 v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
1062 }
1063 for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1064 if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
1065 v->byte_per_pixel_dety[k] = 8.0;
1066 v->byte_per_pixel_detc[k] = 0.0;
1067 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
1068 v->byte_per_pixel_dety[k] = 4.0;
1069 v->byte_per_pixel_detc[k] = 0.0;
1070 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
1071 v->byte_per_pixel_dety[k] = 2.0;
1072 v->byte_per_pixel_detc[k] = 0.0;
1073 } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
1074 v->byte_per_pixel_dety[k] = 1.0;
1075 v->byte_per_pixel_detc[k] = 2.0;
1076 } else {
1077 v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
1078 v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
1079 }
1080 }
1081
1082 v->total_data_read_bandwidth = 0.0;
1083 for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1084 v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
1085 dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
1086 v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
1087 dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
1088 v->total_data_read_bandwidth = v->total_data_read_bandwidth +
1089 v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
1090 }
1091
1092 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1093
1094 if (v->voltage_level != number_of_states_plus_one && !fast_validate) {
1095 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1096
1097 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1098 bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1099 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
1100 bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
1101 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
1102 bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
1103 else
1104 bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
1105
1106 if (bw_consumed < v->fabric_and_dram_bandwidth)
1107 if (dc->debug.voltage_align_fclk)
1108 bw_consumed = v->fabric_and_dram_bandwidth;
1109
1110 display_pipe_configuration(v);
1111 /*calc_wm_sets_and_perf_params(context, v);*/
1112 /* Only 1 set is used by dcn since no noticeable
1113 * performance improvement was measured and due to hw bug DEGVIDCN10-254
1114 */
1115 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1116
1117 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1118 v->stutter_exit_watermark * 1000;
1119 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1120 v->stutter_enter_plus_exit_watermark * 1000;
1121 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1122 v->dram_clock_change_watermark * 1000;
1123 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1124 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1125 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1126 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1127 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1128
1129 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1130 (ddr4_dram_factor_single_Channel * v->number_of_channels));
1131 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
1132 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1133
1134 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1135 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1136
1137 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1138 if (dc->debug.max_disp_clk == true)
1139 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1140
1141 if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
1142 dc->debug.min_disp_clk_khz) {
1143 context->bw_ctx.bw.dcn.clk.dispclk_khz =
1144 dc->debug.min_disp_clk_khz;
1145 }
1146
1147 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1148 v->dispclk_dppclk_ratio;
1149 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1150 switch (v->voltage_level) {
1151 case 0:
1152 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1153 (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1154 break;
1155 case 1:
1156 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1157 (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1158 break;
1159 case 2:
1160 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1161 (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1162 break;
1163 default:
1164 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1165 (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1166 break;
1167 }
1168
1169 BW_VAL_TRACE_END_WATERMARKS();
1170
1171 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1172 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1173
1174 /* skip inactive pipe */
1175 if (!pipe->stream)
1176 continue;
1177 /* skip all but first of split pipes */
1178 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1179 continue;
1180
1181 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1182 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1183 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1184 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1185
1186 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1187 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1188 vesa_sync_start = pipe->stream->timing.v_addressable +
1189 pipe->stream->timing.v_border_bottom +
1190 pipe->stream->timing.v_front_porch;
1191
1192 asic_blank_end = (pipe->stream->timing.v_total -
1193 vesa_sync_start -
1194 pipe->stream->timing.v_border_top)
1195 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1196
1197 asic_blank_start = asic_blank_end +
1198 (pipe->stream->timing.v_border_top +
1199 pipe->stream->timing.v_addressable +
1200 pipe->stream->timing.v_border_bottom)
1201 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1202
1203 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1204 pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1205
1206 if (pipe->plane_state) {
1207 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1208
1209 pipe->plane_state->update_flags.bits.full_update = 1;
1210
1211 if (v->dpp_per_plane[input_idx] == 2 ||
1212 ((pipe->stream->view_format ==
1213 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1214 pipe->stream->view_format ==
1215 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1216 (pipe->stream->timing.timing_3d_format ==
1217 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1218 pipe->stream->timing.timing_3d_format ==
1219 TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1220 if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1221 /* update previously split pipe */
1222 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1223 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1224 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1225 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1226
1227 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1228 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1229 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1230 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1231 } else {
1232 /* pipe not split previously needs split */
1233 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
1234 ASSERT(hsplit_pipe);
1235 split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
1236 }
1237
1238 dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1239 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1240 /* merge previously split pipe */
1241 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1242 if (hsplit_pipe->bottom_pipe)
1243 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1244 hsplit_pipe->plane_state = NULL;
1245 hsplit_pipe->stream = NULL;
1246 hsplit_pipe->top_pipe = NULL;
1247 hsplit_pipe->bottom_pipe = NULL;
1248 /* Clear plane_res and stream_res */
1249 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1250 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1251 resource_build_scaling_params(pipe);
1252 }
1253 /* for now important to do this after pipe split for building e2e params */
1254 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1255 }
1256
1257 input_idx++;
1258 }
1259 } else if (v->voltage_level == number_of_states_plus_one) {
1260 BW_VAL_TRACE_SKIP(fail);
1261 } else if (fast_validate) {
1262 BW_VAL_TRACE_SKIP(fast);
1263 }
1264
1265 if (v->voltage_level == 0) {
1266 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
1267 dc->dcn_soc->sr_enter_plus_exit_time;
1268 context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1269 }
1270
1271 /*
1272 * BW limit is set to prevent display from impacting other system functions
1273 */
1274
1275 bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1276 bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1277
1278 kernel_fpu_end();
1279
1280 PERFORMANCE_TRACE_END();
1281 BW_VAL_TRACE_FINISH();
1282
1283 if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
1284 return true;
1285 else
1286 return false;
1287}
1288
1289static unsigned int dcn_find_normalized_clock_vdd_Level(
1290 const struct dc *dc,
1291 enum dm_pp_clock_type clocks_type,
1292 int clocks_in_khz)
1293{
1294 int vdd_level = dcn_bw_v_min0p65;
1295
1296 if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1297 return vdd_level;
1298
1299 switch (clocks_type) {
1300 case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1301 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1302 vdd_level = dcn_bw_v_max0p91;
1303 BREAK_TO_DEBUGGER();
1304 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1305 vdd_level = dcn_bw_v_max0p9;
1306 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1307 vdd_level = dcn_bw_v_nom0p8;
1308 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1309 vdd_level = dcn_bw_v_mid0p72;
1310 } else
1311 vdd_level = dcn_bw_v_min0p65;
1312 break;
1313 case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1314 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1315 vdd_level = dcn_bw_v_max0p91;
1316 BREAK_TO_DEBUGGER();
1317 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1318 vdd_level = dcn_bw_v_max0p9;
1319 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1320 vdd_level = dcn_bw_v_nom0p8;
1321 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1322 vdd_level = dcn_bw_v_mid0p72;
1323 } else
1324 vdd_level = dcn_bw_v_min0p65;
1325 break;
1326
1327 case DM_PP_CLOCK_TYPE_DPPCLK:
1328 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1329 vdd_level = dcn_bw_v_max0p91;
1330 BREAK_TO_DEBUGGER();
1331 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1332 vdd_level = dcn_bw_v_max0p9;
1333 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1334 vdd_level = dcn_bw_v_nom0p8;
1335 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1336 vdd_level = dcn_bw_v_mid0p72;
1337 } else
1338 vdd_level = dcn_bw_v_min0p65;
1339 break;
1340
1341 case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1342 {
1343 unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1344
1345 if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1346 vdd_level = dcn_bw_v_max0p91;
1347 BREAK_TO_DEBUGGER();
1348 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1349 vdd_level = dcn_bw_v_max0p9;
1350 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1351 vdd_level = dcn_bw_v_nom0p8;
1352 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1353 vdd_level = dcn_bw_v_mid0p72;
1354 } else
1355 vdd_level = dcn_bw_v_min0p65;
1356 }
1357 break;
1358
1359 case DM_PP_CLOCK_TYPE_DCFCLK:
1360 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1361 vdd_level = dcn_bw_v_max0p91;
1362 BREAK_TO_DEBUGGER();
1363 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1364 vdd_level = dcn_bw_v_max0p9;
1365 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1366 vdd_level = dcn_bw_v_nom0p8;
1367 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1368 vdd_level = dcn_bw_v_mid0p72;
1369 } else
1370 vdd_level = dcn_bw_v_min0p65;
1371 break;
1372
1373 default:
1374 break;
1375 }
1376 return vdd_level;
1377}
1378
1379unsigned int dcn_find_dcfclk_suits_all(
1380 const struct dc *dc,
1381 struct dc_clocks *clocks)
1382{
1383 unsigned vdd_level, vdd_level_temp;
1384 unsigned dcf_clk;
1385
1386 /*find a common supported voltage level*/
1387 vdd_level = dcn_find_normalized_clock_vdd_Level(
1388 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
1389 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1390 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
1391
1392 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1393 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1394 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
1395 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1396
1397 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1398 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
1399 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1400 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1401 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
1402
1403 /*find that level conresponding dcfclk*/
1404 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1405 if (vdd_level == dcn_bw_v_max0p91) {
1406 BREAK_TO_DEBUGGER();
1407 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1408 } else if (vdd_level == dcn_bw_v_max0p9)
1409 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1410 else if (vdd_level == dcn_bw_v_nom0p8)
1411 dcf_clk = dc->dcn_soc->dcfclkv_nom0p8*1000;
1412 else if (vdd_level == dcn_bw_v_mid0p72)
1413 dcf_clk = dc->dcn_soc->dcfclkv_mid0p72*1000;
1414 else
1415 dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000;
1416
1417 DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1418 return dcf_clk;
1419}
1420
1421static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1422{
1423 int i;
1424
1425 if (clks->num_levels == 0)
1426 return false;
1427
1428 for (i = 0; i < clks->num_levels; i++)
1429 /* Ensure that the result is sane */
1430 if (clks->data[i].clocks_in_khz == 0)
1431 return false;
1432
1433 return true;
1434}
1435
1436void dcn_bw_update_from_pplib(struct dc *dc)
1437{
1438 struct dc_context *ctx = dc->ctx;
1439 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1440 bool res;
1441
1442 /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1443 res = dm_pp_get_clock_levels_by_type_with_voltage(
1444 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1445
1446 kernel_fpu_begin();
1447
1448 if (res)
1449 res = verify_clock_values(&fclks);
1450
1451 if (res) {
1452 ASSERT(fclks.num_levels >= 3);
1453 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0;
1454 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels *
1455 (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0)
1456 * ddr4_dram_factor_single_Channel / 1000.0;
1457 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels *
1458 (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0)
1459 * ddr4_dram_factor_single_Channel / 1000.0;
1460 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels *
1461 (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0)
1462 * ddr4_dram_factor_single_Channel / 1000.0;
1463 } else
1464 BREAK_TO_DEBUGGER();
1465
1466 kernel_fpu_end();
1467
1468 res = dm_pp_get_clock_levels_by_type_with_voltage(
1469 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1470
1471 kernel_fpu_begin();
1472
1473 if (res)
1474 res = verify_clock_values(&dcfclks);
1475
1476 if (res && dcfclks.num_levels >= 3) {
1477 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1478 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1479 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1480 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1481 } else
1482 BREAK_TO_DEBUGGER();
1483
1484 kernel_fpu_end();
1485}
1486
1487void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1488{
1489 struct pp_smu_funcs_rv *pp = NULL;
1490 struct pp_smu_wm_range_sets ranges = {0};
1491 int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1492 const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1493
1494 if (dc->res_pool->pp_smu)
1495 pp = &dc->res_pool->pp_smu->rv_funcs;
1496 if (!pp || !pp->set_wm_ranges)
1497 return;
1498
1499 kernel_fpu_begin();
1500 min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1501 min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1502 socclk_khz = dc->dcn_soc->socclk * 1000;
1503 kernel_fpu_end();
1504
1505 /* Now notify PPLib/SMU about which Watermarks sets they should select
1506 * depending on DPM state they are in. And update BW MGR GFX Engine and
1507 * Memory clock member variables for Watermarks calculations for each
1508 * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
1509 */
1510 /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1511 * care what the value is, hence min to overdrive level
1512 */
1513 ranges.num_reader_wm_sets = WM_SET_COUNT;
1514 ranges.num_writer_wm_sets = WM_SET_COUNT;
1515 ranges.reader_wm_sets[0].wm_inst = WM_A;
1516 ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1517 ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1518 ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1519 ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1520 ranges.writer_wm_sets[0].wm_inst = WM_A;
1521 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1522 ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1523 ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1524 ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1525
1526 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1527 ranges.reader_wm_sets[0].wm_inst = WM_A;
1528 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1529 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1530 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1531 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1532 ranges.writer_wm_sets[0].wm_inst = WM_A;
1533 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1534 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1535 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1536 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1537 }
1538
1539 ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
1540 ranges.reader_wm_sets[1].wm_inst = WM_B;
1541
1542 ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
1543 ranges.reader_wm_sets[2].wm_inst = WM_C;
1544
1545 ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
1546 ranges.reader_wm_sets[3].wm_inst = WM_D;
1547
1548 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1549 pp->set_wm_ranges(&pp->pp_smu, &ranges);
1550}
1551
1552void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1553{
1554 kernel_fpu_begin();
1555 DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1556 "sr_enter_plus_exit_time: %f ns\n"
1557 "urgent_latency: %f ns\n"
1558 "write_back_latency: %f ns\n"
1559 "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1560 "max_request_size: %d bytes\n"
1561 "dcfclkv_max0p9: %f kHz\n"
1562 "dcfclkv_nom0p8: %f kHz\n"
1563 "dcfclkv_mid0p72: %f kHz\n"
1564 "dcfclkv_min0p65: %f kHz\n"
1565 "max_dispclk_vmax0p9: %f kHz\n"
1566 "max_dispclk_vnom0p8: %f kHz\n"
1567 "max_dispclk_vmid0p72: %f kHz\n"
1568 "max_dispclk_vmin0p65: %f kHz\n"
1569 "max_dppclk_vmax0p9: %f kHz\n"
1570 "max_dppclk_vnom0p8: %f kHz\n"
1571 "max_dppclk_vmid0p72: %f kHz\n"
1572 "max_dppclk_vmin0p65: %f kHz\n"
1573 "socclk: %f kHz\n"
1574 "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1575 "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1576 "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1577 "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1578 "phyclkv_max0p9: %f kHz\n"
1579 "phyclkv_nom0p8: %f kHz\n"
1580 "phyclkv_mid0p72: %f kHz\n"
1581 "phyclkv_min0p65: %f kHz\n"
1582 "downspreading: %f %%\n"
1583 "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1584 "urgent_out_of_order_return_per_channel: %d Bytes\n"
1585 "number_of_channels: %d\n"
1586 "vmm_page_size: %d Bytes\n"
1587 "dram_clock_change_latency: %f ns\n"
1588 "return_bus_width: %d Bytes\n",
1589 dc->dcn_soc->sr_exit_time * 1000,
1590 dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1591 dc->dcn_soc->urgent_latency * 1000,
1592 dc->dcn_soc->write_back_latency * 1000,
1593 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1594 dc->dcn_soc->max_request_size,
1595 dc->dcn_soc->dcfclkv_max0p9 * 1000,
1596 dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1597 dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1598 dc->dcn_soc->dcfclkv_min0p65 * 1000,
1599 dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1600 dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1601 dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1602 dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1603 dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1604 dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1605 dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1606 dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1607 dc->dcn_soc->socclk * 1000,
1608 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1609 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1610 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1611 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1612 dc->dcn_soc->phyclkv_max0p9 * 1000,
1613 dc->dcn_soc->phyclkv_nom0p8 * 1000,
1614 dc->dcn_soc->phyclkv_mid0p72 * 1000,
1615 dc->dcn_soc->phyclkv_min0p65 * 1000,
1616 dc->dcn_soc->downspreading * 100,
1617 dc->dcn_soc->round_trip_ping_latency_cycles,
1618 dc->dcn_soc->urgent_out_of_order_return_per_channel,
1619 dc->dcn_soc->number_of_channels,
1620 dc->dcn_soc->vmm_page_size,
1621 dc->dcn_soc->dram_clock_change_latency * 1000,
1622 dc->dcn_soc->return_bus_width);
1623 DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1624 "det_buffer_size_in_kbyte: %f\n"
1625 "dpp_output_buffer_pixels: %f\n"
1626 "opp_output_buffer_lines: %f\n"
1627 "pixel_chunk_size_in_kbyte: %f\n"
1628 "pte_enable: %d\n"
1629 "pte_chunk_size: %d kbytes\n"
1630 "meta_chunk_size: %d kbytes\n"
1631 "writeback_chunk_size: %d kbytes\n"
1632 "odm_capability: %d\n"
1633 "dsc_capability: %d\n"
1634 "line_buffer_size: %d bits\n"
1635 "max_line_buffer_lines: %d\n"
1636 "is_line_buffer_bpp_fixed: %d\n"
1637 "line_buffer_fixed_bpp: %d\n"
1638 "writeback_luma_buffer_size: %d kbytes\n"
1639 "writeback_chroma_buffer_size: %d kbytes\n"
1640 "max_num_dpp: %d\n"
1641 "max_num_writeback: %d\n"
1642 "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1643 "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1644 "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1645 "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1646 "max_hscl_ratio: %f\n"
1647 "max_vscl_ratio: %f\n"
1648 "max_hscl_taps: %d\n"
1649 "max_vscl_taps: %d\n"
1650 "pte_buffer_size_in_requests: %d\n"
1651 "dispclk_ramping_margin: %f %%\n"
1652 "under_scan_factor: %f %%\n"
1653 "max_inter_dcn_tile_repeaters: %d\n"
1654 "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1655 "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1656 "dcfclk_cstate_latency: %d\n",
1657 dc->dcn_ip->rob_buffer_size_in_kbyte,
1658 dc->dcn_ip->det_buffer_size_in_kbyte,
1659 dc->dcn_ip->dpp_output_buffer_pixels,
1660 dc->dcn_ip->opp_output_buffer_lines,
1661 dc->dcn_ip->pixel_chunk_size_in_kbyte,
1662 dc->dcn_ip->pte_enable,
1663 dc->dcn_ip->pte_chunk_size,
1664 dc->dcn_ip->meta_chunk_size,
1665 dc->dcn_ip->writeback_chunk_size,
1666 dc->dcn_ip->odm_capability,
1667 dc->dcn_ip->dsc_capability,
1668 dc->dcn_ip->line_buffer_size,
1669 dc->dcn_ip->max_line_buffer_lines,
1670 dc->dcn_ip->is_line_buffer_bpp_fixed,
1671 dc->dcn_ip->line_buffer_fixed_bpp,
1672 dc->dcn_ip->writeback_luma_buffer_size,
1673 dc->dcn_ip->writeback_chroma_buffer_size,
1674 dc->dcn_ip->max_num_dpp,
1675 dc->dcn_ip->max_num_writeback,
1676 dc->dcn_ip->max_dchub_topscl_throughput,
1677 dc->dcn_ip->max_pscl_tolb_throughput,
1678 dc->dcn_ip->max_lb_tovscl_throughput,
1679 dc->dcn_ip->max_vscl_tohscl_throughput,
1680 dc->dcn_ip->max_hscl_ratio,
1681 dc->dcn_ip->max_vscl_ratio,
1682 dc->dcn_ip->max_hscl_taps,
1683 dc->dcn_ip->max_vscl_taps,
1684 dc->dcn_ip->pte_buffer_size_in_requests,
1685 dc->dcn_ip->dispclk_ramping_margin,
1686 dc->dcn_ip->under_scan_factor * 100,
1687 dc->dcn_ip->max_inter_dcn_tile_repeaters,
1688 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1689 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1690 dc->dcn_ip->dcfclk_cstate_latency);
1691
1692 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1693 dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1694 dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1695 dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1696 dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1697 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1698 dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1699 dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1700 dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1701 dc->dcn_soc->round_trip_ping_latency_cycles;
1702 dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1703 dc->dcn_soc->urgent_out_of_order_return_per_channel;
1704 dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1705 dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1706 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1707 dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1708
1709 dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1710 dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1711 dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1712 dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1713 dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1714 dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1715 dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1716 dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1717 dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1718 dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1719 dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1720 dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1721 dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1722 dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1723 dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1724 dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1725 dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1726 dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1727 dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1728 dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1729 dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1730 dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1731 dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1732 dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1733 dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1734 /*pte_buffer_size_in_requests missing in dml*/
1735 dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1736 dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1737 dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1738 dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1739 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1740 dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1741 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1742 dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1743 kernel_fpu_end();
1744}