1// SPDX-License-Identifier: GPL-2.0-only
  2/* Abilis Systems MODULE DESCRIPTION
  3 *
  4 * Copyright (C) Abilis Systems 2013
  5 *
  6 * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
  7 *          Christian Ruppert <christian.ruppert@abilis.com>
  8 */
  9
 10#include <linux/kernel.h>
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <linux/gpio/driver.h>
 14#include <linux/slab.h>
 15#include <linux/irq.h>
 16#include <linux/irqdomain.h>
 17#include <linux/interrupt.h>
 18#include <linux/io.h>
 19#include <linux/of.h>
 20#include <linux/of_platform.h>
 21#include <linux/spinlock.h>
 22#include <linux/bitops.h>
 23#include <linux/pinctrl/consumer.h>
 24
 25#define TB10X_GPIO_DIR_IN	(0x00000000)
 26#define TB10X_GPIO_DIR_OUT	(0x00000001)
 27#define OFFSET_TO_REG_DDR	(0x00)
 28#define OFFSET_TO_REG_DATA	(0x04)
 29#define OFFSET_TO_REG_INT_EN	(0x08)
 30#define OFFSET_TO_REG_CHANGE	(0x0C)
 31#define OFFSET_TO_REG_WRMASK	(0x10)
 32#define OFFSET_TO_REG_INT_TYPE	(0x14)
 33
 34
 35/**
 36 * @base: register base address
 37 * @domain: IRQ domain of GPIO generated interrupts managed by this controller
 38 * @irq: Interrupt line of parent interrupt controller
 39 * @gc: gpio_chip structure associated to this GPIO controller
 40 */
 41struct tb10x_gpio {
 42	void __iomem *base;
 43	struct irq_domain *domain;
 44	int irq;
 45	struct gpio_chip gc;
 46};
 47
 48static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
 49{
 50	return ioread32(gpio->base + offs);
 51}
 52
 53static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
 54				u32 val)
 55{
 56	iowrite32(val, gpio->base + offs);
 57}
 58
 59static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
 60				u32 mask, u32 val)
 61{
 62	u32 r;
 63	unsigned long flags;
 64
 65	spin_lock_irqsave(&gpio->gc.bgpio_lock, flags);
 66
 67	r = tb10x_reg_read(gpio, offs);
 68	r = (r & ~mask) | (val & mask);
 69
 70	tb10x_reg_write(gpio, offs, r);
 71
 72	spin_unlock_irqrestore(&gpio->gc.bgpio_lock, flags);
 73}
 74
 75static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 76{
 77	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
 78
 79	return irq_create_mapping(tb10x_gpio->domain, offset);
 80}
 81
 82static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
 83{
 84	if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
 85		pr_err("Only (both) edge triggered interrupts supported.\n");
 86		return -EINVAL;
 87	}
 88
 89	irqd_set_trigger_type(data, type);
 90
 91	return IRQ_SET_MASK_OK;
 92}
 93
 94static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
 95{
 96	struct tb10x_gpio *tb10x_gpio = data;
 97	u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
 98	u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
 99	const unsigned long bits = r & m;
100	int i;
101
102	for_each_set_bit(i, &bits, 32)
103		generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
104
105	return IRQ_HANDLED;
106}
107
108static int tb10x_gpio_probe(struct platform_device *pdev)
109{
110	struct tb10x_gpio *tb10x_gpio;
111	struct device *dev = &pdev->dev;
112	struct device_node *np = dev->of_node;
113	int ret = -EBUSY;
114	u32 ngpio;
115
116	if (!np)
117		return -EINVAL;
118
119	if (of_property_read_u32(np, "abilis,ngpio", &ngpio))
120		return -EINVAL;
121
122	tb10x_gpio = devm_kzalloc(dev, sizeof(*tb10x_gpio), GFP_KERNEL);
123	if (tb10x_gpio == NULL)
124		return -ENOMEM;
125
126	tb10x_gpio->base = devm_platform_ioremap_resource(pdev, 0);
127	if (IS_ERR(tb10x_gpio->base))
128		return PTR_ERR(tb10x_gpio->base);
129
130	tb10x_gpio->gc.label =
131		devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
132	if (!tb10x_gpio->gc.label)
133		return -ENOMEM;
134
135	/*
136	 * Initialize generic GPIO with one single register for reading and setting
137	 * the lines, no special set or clear registers and a data direction register
138	 * wher 1 means "output".
139	 */
140	ret = bgpio_init(&tb10x_gpio->gc, dev, 4,
141			 tb10x_gpio->base + OFFSET_TO_REG_DATA,
142			 NULL,
143			 NULL,
144			 tb10x_gpio->base + OFFSET_TO_REG_DDR,
145			 NULL,
146			 0);
147	if (ret) {
148		dev_err(dev, "unable to init generic GPIO\n");
149		return ret;
150	}
151	tb10x_gpio->gc.base = -1;
152	tb10x_gpio->gc.parent = dev;
153	tb10x_gpio->gc.owner = THIS_MODULE;
154	/*
155	 * ngpio is set by bgpio_init() but we override it, this .request()
156	 * callback also overrides the one set up by generic GPIO.
157	 */
158	tb10x_gpio->gc.ngpio = ngpio;
159	tb10x_gpio->gc.request = gpiochip_generic_request;
160	tb10x_gpio->gc.free = gpiochip_generic_free;
161
162	ret = devm_gpiochip_add_data(dev, &tb10x_gpio->gc, tb10x_gpio);
163	if (ret < 0) {
164		dev_err(dev, "Could not add gpiochip.\n");
165		return ret;
166	}
167
168	platform_set_drvdata(pdev, tb10x_gpio);
169
170	if (of_find_property(np, "interrupt-controller", NULL)) {
171		struct irq_chip_generic *gc;
172
173		ret = platform_get_irq(pdev, 0);
174		if (ret < 0)
175			return ret;
176
177		tb10x_gpio->gc.to_irq	= tb10x_gpio_to_irq;
178		tb10x_gpio->irq		= ret;
179
180		ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade,
181				IRQF_TRIGGER_NONE | IRQF_SHARED,
182				dev_name(dev), tb10x_gpio);
183		if (ret != 0)
184			return ret;
185
186		tb10x_gpio->domain = irq_domain_add_linear(np,
187						tb10x_gpio->gc.ngpio,
188						&irq_generic_chip_ops, NULL);
189		if (!tb10x_gpio->domain) {
190			return -ENOMEM;
191		}
192
193		ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
194				tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
195				handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
196				IRQ_GC_INIT_MASK_CACHE);
197		if (ret)
198			return ret;
199
200		gc = tb10x_gpio->domain->gc->gc[0];
201		gc->reg_base                         = tb10x_gpio->base;
202		gc->chip_types[0].type               = IRQ_TYPE_EDGE_BOTH;
203		gc->chip_types[0].chip.irq_ack       = irq_gc_ack_set_bit;
204		gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
205		gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
206		gc->chip_types[0].chip.irq_set_type  = tb10x_gpio_irq_set_type;
207		gc->chip_types[0].regs.ack           = OFFSET_TO_REG_CHANGE;
208		gc->chip_types[0].regs.mask          = OFFSET_TO_REG_INT_EN;
209	}
210
211	return 0;
212}
213
214static int tb10x_gpio_remove(struct platform_device *pdev)
215{
216	struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
217
218	if (tb10x_gpio->gc.to_irq) {
219		irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
220					BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
221		kfree(tb10x_gpio->domain->gc);
222		irq_domain_remove(tb10x_gpio->domain);
223	}
224
225	return 0;
226}
227
228static const struct of_device_id tb10x_gpio_dt_ids[] = {
229	{ .compatible = "abilis,tb10x-gpio" },
230	{ }
231};
232MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
233
234static struct platform_driver tb10x_gpio_driver = {
235	.probe		= tb10x_gpio_probe,
236	.remove		= tb10x_gpio_remove,
237	.driver = {
238		.name	= "tb10x-gpio",
239		.of_match_table = tb10x_gpio_dt_ids,
240	}
241};
242
243module_platform_driver(tb10x_gpio_driver);
244MODULE_LICENSE("GPL");
245MODULE_DESCRIPTION("tb10x gpio.");
246MODULE_VERSION("0.0.1");