1/* SPDX-License-Identifier: GPL-2.0-only */
  2/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
  3 */
  4#ifndef __QCOM_SCM_INT_H
  5#define __QCOM_SCM_INT_H
  6
  7#define QCOM_SCM_SVC_BOOT		0x1
  8#define QCOM_SCM_BOOT_ADDR		0x1
  9#define QCOM_SCM_SET_DLOAD_MODE		0x10
 10#define QCOM_SCM_BOOT_ADDR_MC		0x11
 11#define QCOM_SCM_SET_REMOTE_STATE	0xa
 12extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
 13extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
 14
 15#define QCOM_SCM_FLAG_HLOS		0x01
 16#define QCOM_SCM_FLAG_COLDBOOT_MC	0x02
 17#define QCOM_SCM_FLAG_WARMBOOT_MC	0x04
 18extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
 19		const cpumask_t *cpus);
 20extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
 21
 22#define QCOM_SCM_CMD_TERMINATE_PC	0x2
 23#define QCOM_SCM_FLUSH_FLAG_MASK	0x3
 24#define QCOM_SCM_CMD_CORE_HOTPLUGGED	0x10
 25extern void __qcom_scm_cpu_power_down(u32 flags);
 26
 27#define QCOM_SCM_SVC_IO			0x5
 28#define QCOM_SCM_IO_READ		0x1
 29#define QCOM_SCM_IO_WRITE		0x2
 30extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
 31extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
 32
 33#define QCOM_SCM_SVC_INFO		0x6
 34#define QCOM_IS_CALL_AVAIL_CMD		0x1
 35extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
 36		u32 cmd_id);
 37
 38#define QCOM_SCM_SVC_HDCP		0x11
 39#define QCOM_SCM_CMD_HDCP		0x01
 40extern int __qcom_scm_hdcp_req(struct device *dev,
 41		struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
 42
 43extern void __qcom_scm_init(void);
 44
 45#define QCOM_SCM_SVC_PIL		0x2
 46#define QCOM_SCM_PAS_INIT_IMAGE_CMD	0x1
 47#define QCOM_SCM_PAS_MEM_SETUP_CMD	0x2
 48#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD	0x5
 49#define QCOM_SCM_PAS_SHUTDOWN_CMD	0x6
 50#define QCOM_SCM_PAS_IS_SUPPORTED_CMD	0x7
 51#define QCOM_SCM_PAS_MSS_RESET		0xa
 52extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
 53extern int  __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
 54		dma_addr_t metadata_phys);
 55extern int  __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
 56		phys_addr_t addr, phys_addr_t size);
 57extern int  __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
 58extern int  __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
 59extern int  __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
 60
 61/* common error codes */
 62#define QCOM_SCM_V2_EBUSY	-12
 63#define QCOM_SCM_ENOMEM		-5
 64#define QCOM_SCM_EOPNOTSUPP	-4
 65#define QCOM_SCM_EINVAL_ADDR	-3
 66#define QCOM_SCM_EINVAL_ARG	-2
 67#define QCOM_SCM_ERROR		-1
 68#define QCOM_SCM_INTERRUPTED	1
 69
 70static inline int qcom_scm_remap_error(int err)
 71{
 72	switch (err) {
 73	case QCOM_SCM_ERROR:
 74		return -EIO;
 75	case QCOM_SCM_EINVAL_ADDR:
 76	case QCOM_SCM_EINVAL_ARG:
 77		return -EINVAL;
 78	case QCOM_SCM_EOPNOTSUPP:
 79		return -EOPNOTSUPP;
 80	case QCOM_SCM_ENOMEM:
 81		return -ENOMEM;
 82	case QCOM_SCM_V2_EBUSY:
 83		return -EBUSY;
 84	}
 85	return -EINVAL;
 86}
 87
 88#define QCOM_SCM_SVC_MP			0xc
 89#define QCOM_SCM_RESTORE_SEC_CFG	2
 90extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
 91				      u32 spare);
 92#define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE	3
 93#define QCOM_SCM_IOMMU_SECURE_PTBL_INIT	4
 94extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
 95					     size_t *size);
 96extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
 97					     u32 size, u32 spare);
 98#define QCOM_MEM_PROT_ASSIGN_ID	0x16
 99extern int  __qcom_scm_assign_mem(struct device *dev,
100				  phys_addr_t mem_region, size_t mem_sz,
101				  phys_addr_t src, size_t src_sz,
102				  phys_addr_t dest, size_t dest_sz);
103
104#endif