1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright 2019 NXP
  4 */
  5
  6#include <linux/cpu.h>
  7#include <linux/err.h>
  8#include <linux/init.h>
  9#include <linux/kernel.h>
 10#include <linux/module.h>
 11#include <linux/nvmem-consumer.h>
 12#include <linux/of.h>
 13#include <linux/platform_device.h>
 14#include <linux/pm_opp.h>
 15#include <linux/slab.h>
 16
 17#define OCOTP_CFG3_SPEED_GRADE_SHIFT	8
 18#define OCOTP_CFG3_SPEED_GRADE_MASK	(0x3 << 8)
 19#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK	(0xf << 8)
 20#define OCOTP_CFG3_MKT_SEGMENT_SHIFT    6
 21#define OCOTP_CFG3_MKT_SEGMENT_MASK     (0x3 << 6)
 22
 23/* cpufreq-dt device registered by imx-cpufreq-dt */
 24static struct platform_device *cpufreq_dt_pdev;
 25static struct opp_table *cpufreq_opp_table;
 26
 27static int imx_cpufreq_dt_probe(struct platform_device *pdev)
 28{
 29	struct device *cpu_dev = get_cpu_device(0);
 30	u32 cell_value, supported_hw[2];
 31	int speed_grade, mkt_segment;
 32	int ret;
 33
 34	ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
 35	if (ret)
 36		return ret;
 37
 38	if (of_machine_is_compatible("fsl,imx8mn"))
 39		speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
 40			      >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
 41	else
 42		speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
 43			      >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
 44	mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
 45
 46	/*
 47	 * Early samples without fuses written report "0 0" which means
 48	 * consumer segment and minimum speed grading.
 49	 *
 50	 * According to datasheet minimum speed grading is not supported for
 51	 * consumer parts so clamp to 1 to avoid warning for "no OPPs"
 52	 *
 53	 * Applies to i.MX8M series SoCs.
 54	 */
 55	if (mkt_segment == 0 && speed_grade == 0 && (
 56			of_machine_is_compatible("fsl,imx8mm") ||
 57			of_machine_is_compatible("fsl,imx8mn") ||
 58			of_machine_is_compatible("fsl,imx8mq")))
 59		speed_grade = 1;
 60
 61	supported_hw[0] = BIT(speed_grade);
 62	supported_hw[1] = BIT(mkt_segment);
 63	dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
 64			speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
 65
 66	cpufreq_opp_table = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
 67	if (IS_ERR(cpufreq_opp_table)) {
 68		ret = PTR_ERR(cpufreq_opp_table);
 69		dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
 70		return ret;
 71	}
 72
 73	cpufreq_dt_pdev = platform_device_register_data(
 74			&pdev->dev, "cpufreq-dt", -1, NULL, 0);
 75	if (IS_ERR(cpufreq_dt_pdev)) {
 76		dev_pm_opp_put_supported_hw(cpufreq_opp_table);
 77		ret = PTR_ERR(cpufreq_dt_pdev);
 78		dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
 79		return ret;
 80	}
 81
 82	return 0;
 83}
 84
 85static int imx_cpufreq_dt_remove(struct platform_device *pdev)
 86{
 87	platform_device_unregister(cpufreq_dt_pdev);
 88	dev_pm_opp_put_supported_hw(cpufreq_opp_table);
 89
 90	return 0;
 91}
 92
 93static struct platform_driver imx_cpufreq_dt_driver = {
 94	.probe = imx_cpufreq_dt_probe,
 95	.remove = imx_cpufreq_dt_remove,
 96	.driver = {
 97		.name = "imx-cpufreq-dt",
 98	},
 99};
100module_platform_driver(imx_cpufreq_dt_driver);
101
102MODULE_ALIAS("platform:imx-cpufreq-dt");
103MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
104MODULE_LICENSE("GPL v2");