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1/*
2 * SuperH Timer Support - MTU2
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clockchips.h>
31#include <linux/sh_timer.h>
32#include <linux/slab.h>
33
34struct sh_mtu2_priv {
35 void __iomem *mapbase;
36 struct clk *clk;
37 struct irqaction irqaction;
38 struct platform_device *pdev;
39 unsigned long rate;
40 unsigned long periodic;
41 struct clock_event_device ced;
42};
43
44static DEFINE_SPINLOCK(sh_mtu2_lock);
45
46#define TSTR -1 /* shared register */
47#define TCR 0 /* channel register */
48#define TMDR 1 /* channel register */
49#define TIOR 2 /* channel register */
50#define TIER 3 /* channel register */
51#define TSR 4 /* channel register */
52#define TCNT 5 /* channel register */
53#define TGR 6 /* channel register */
54
55static unsigned long mtu2_reg_offs[] = {
56 [TCR] = 0,
57 [TMDR] = 1,
58 [TIOR] = 2,
59 [TIER] = 4,
60 [TSR] = 5,
61 [TCNT] = 6,
62 [TGR] = 8,
63};
64
65static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
66{
67 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
68 void __iomem *base = p->mapbase;
69 unsigned long offs;
70
71 if (reg_nr == TSTR)
72 return ioread8(base + cfg->channel_offset);
73
74 offs = mtu2_reg_offs[reg_nr];
75
76 if ((reg_nr == TCNT) || (reg_nr == TGR))
77 return ioread16(base + offs);
78 else
79 return ioread8(base + offs);
80}
81
82static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
83 unsigned long value)
84{
85 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
86 void __iomem *base = p->mapbase;
87 unsigned long offs;
88
89 if (reg_nr == TSTR) {
90 iowrite8(value, base + cfg->channel_offset);
91 return;
92 }
93
94 offs = mtu2_reg_offs[reg_nr];
95
96 if ((reg_nr == TCNT) || (reg_nr == TGR))
97 iowrite16(value, base + offs);
98 else
99 iowrite8(value, base + offs);
100}
101
102static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
103{
104 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
105 unsigned long flags, value;
106
107 /* start stop register shared by multiple timer channels */
108 spin_lock_irqsave(&sh_mtu2_lock, flags);
109 value = sh_mtu2_read(p, TSTR);
110
111 if (start)
112 value |= 1 << cfg->timer_bit;
113 else
114 value &= ~(1 << cfg->timer_bit);
115
116 sh_mtu2_write(p, TSTR, value);
117 spin_unlock_irqrestore(&sh_mtu2_lock, flags);
118}
119
120static int sh_mtu2_enable(struct sh_mtu2_priv *p)
121{
122 int ret;
123
124 /* enable clock */
125 ret = clk_enable(p->clk);
126 if (ret) {
127 dev_err(&p->pdev->dev, "cannot enable clock\n");
128 return ret;
129 }
130
131 /* make sure channel is disabled */
132 sh_mtu2_start_stop_ch(p, 0);
133
134 p->rate = clk_get_rate(p->clk) / 64;
135 p->periodic = (p->rate + HZ/2) / HZ;
136
137 /* "Periodic Counter Operation" */
138 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
139 sh_mtu2_write(p, TIOR, 0);
140 sh_mtu2_write(p, TGR, p->periodic);
141 sh_mtu2_write(p, TCNT, 0);
142 sh_mtu2_write(p, TMDR, 0);
143 sh_mtu2_write(p, TIER, 0x01);
144
145 /* enable channel */
146 sh_mtu2_start_stop_ch(p, 1);
147
148 return 0;
149}
150
151static void sh_mtu2_disable(struct sh_mtu2_priv *p)
152{
153 /* disable channel */
154 sh_mtu2_start_stop_ch(p, 0);
155
156 /* stop clock */
157 clk_disable(p->clk);
158}
159
160static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
161{
162 struct sh_mtu2_priv *p = dev_id;
163
164 /* acknowledge interrupt */
165 sh_mtu2_read(p, TSR);
166 sh_mtu2_write(p, TSR, 0xfe);
167
168 /* notify clockevent layer */
169 p->ced.event_handler(&p->ced);
170 return IRQ_HANDLED;
171}
172
173static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
174{
175 return container_of(ced, struct sh_mtu2_priv, ced);
176}
177
178static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
179 struct clock_event_device *ced)
180{
181 struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
182 int disabled = 0;
183
184 /* deal with old setting first */
185 switch (ced->mode) {
186 case CLOCK_EVT_MODE_PERIODIC:
187 sh_mtu2_disable(p);
188 disabled = 1;
189 break;
190 default:
191 break;
192 }
193
194 switch (mode) {
195 case CLOCK_EVT_MODE_PERIODIC:
196 dev_info(&p->pdev->dev, "used for periodic clock events\n");
197 sh_mtu2_enable(p);
198 break;
199 case CLOCK_EVT_MODE_UNUSED:
200 if (!disabled)
201 sh_mtu2_disable(p);
202 break;
203 case CLOCK_EVT_MODE_SHUTDOWN:
204 default:
205 break;
206 }
207}
208
209static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
210 char *name, unsigned long rating)
211{
212 struct clock_event_device *ced = &p->ced;
213 int ret;
214
215 memset(ced, 0, sizeof(*ced));
216
217 ced->name = name;
218 ced->features = CLOCK_EVT_FEAT_PERIODIC;
219 ced->rating = rating;
220 ced->cpumask = cpumask_of(0);
221 ced->set_mode = sh_mtu2_clock_event_mode;
222
223 dev_info(&p->pdev->dev, "used for clock events\n");
224 clockevents_register_device(ced);
225
226 ret = setup_irq(p->irqaction.irq, &p->irqaction);
227 if (ret) {
228 dev_err(&p->pdev->dev, "failed to request irq %d\n",
229 p->irqaction.irq);
230 return;
231 }
232}
233
234static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
235 unsigned long clockevent_rating)
236{
237 if (clockevent_rating)
238 sh_mtu2_register_clockevent(p, name, clockevent_rating);
239
240 return 0;
241}
242
243static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
244{
245 struct sh_timer_config *cfg = pdev->dev.platform_data;
246 struct resource *res;
247 int irq, ret;
248 ret = -ENXIO;
249
250 memset(p, 0, sizeof(*p));
251 p->pdev = pdev;
252
253 if (!cfg) {
254 dev_err(&p->pdev->dev, "missing platform data\n");
255 goto err0;
256 }
257
258 platform_set_drvdata(pdev, p);
259
260 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
261 if (!res) {
262 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
263 goto err0;
264 }
265
266 irq = platform_get_irq(p->pdev, 0);
267 if (irq < 0) {
268 dev_err(&p->pdev->dev, "failed to get irq\n");
269 goto err0;
270 }
271
272 /* map memory, let mapbase point to our channel */
273 p->mapbase = ioremap_nocache(res->start, resource_size(res));
274 if (p->mapbase == NULL) {
275 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
276 goto err0;
277 }
278
279 /* setup data for setup_irq() (too early for request_irq()) */
280 p->irqaction.name = dev_name(&p->pdev->dev);
281 p->irqaction.handler = sh_mtu2_interrupt;
282 p->irqaction.dev_id = p;
283 p->irqaction.irq = irq;
284 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
285 IRQF_IRQPOLL | IRQF_NOBALANCING;
286
287 /* get hold of clock */
288 p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
289 if (IS_ERR(p->clk)) {
290 dev_err(&p->pdev->dev, "cannot get clock\n");
291 ret = PTR_ERR(p->clk);
292 goto err1;
293 }
294
295 return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
296 cfg->clockevent_rating);
297 err1:
298 iounmap(p->mapbase);
299 err0:
300 return ret;
301}
302
303static int __devinit sh_mtu2_probe(struct platform_device *pdev)
304{
305 struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
306 int ret;
307
308 if (p) {
309 dev_info(&pdev->dev, "kept as earlytimer\n");
310 return 0;
311 }
312
313 p = kmalloc(sizeof(*p), GFP_KERNEL);
314 if (p == NULL) {
315 dev_err(&pdev->dev, "failed to allocate driver data\n");
316 return -ENOMEM;
317 }
318
319 ret = sh_mtu2_setup(p, pdev);
320 if (ret) {
321 kfree(p);
322 platform_set_drvdata(pdev, NULL);
323 }
324 return ret;
325}
326
327static int __devexit sh_mtu2_remove(struct platform_device *pdev)
328{
329 return -EBUSY; /* cannot unregister clockevent */
330}
331
332static struct platform_driver sh_mtu2_device_driver = {
333 .probe = sh_mtu2_probe,
334 .remove = __devexit_p(sh_mtu2_remove),
335 .driver = {
336 .name = "sh_mtu2",
337 }
338};
339
340static int __init sh_mtu2_init(void)
341{
342 return platform_driver_register(&sh_mtu2_device_driver);
343}
344
345static void __exit sh_mtu2_exit(void)
346{
347 platform_driver_unregister(&sh_mtu2_device_driver);
348}
349
350early_platform_init("earlytimer", &sh_mtu2_device_driver);
351module_init(sh_mtu2_init);
352module_exit(sh_mtu2_exit);
353
354MODULE_AUTHOR("Magnus Damm");
355MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
356MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH Timer Support - MTU2
4 *
5 * Copyright (C) 2009 Magnus Damm
6 */
7
8#include <linux/clk.h>
9#include <linux/clockchips.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/irq.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pm_domain.h>
21#include <linux/pm_runtime.h>
22#include <linux/sh_timer.h>
23#include <linux/slab.h>
24#include <linux/spinlock.h>
25
26struct sh_mtu2_device;
27
28struct sh_mtu2_channel {
29 struct sh_mtu2_device *mtu;
30 unsigned int index;
31
32 void __iomem *base;
33
34 struct clock_event_device ced;
35};
36
37struct sh_mtu2_device {
38 struct platform_device *pdev;
39
40 void __iomem *mapbase;
41 struct clk *clk;
42
43 raw_spinlock_t lock; /* Protect the shared registers */
44
45 struct sh_mtu2_channel *channels;
46 unsigned int num_channels;
47
48 bool has_clockevent;
49};
50
51#define TSTR -1 /* shared register */
52#define TCR 0 /* channel register */
53#define TMDR 1 /* channel register */
54#define TIOR 2 /* channel register */
55#define TIER 3 /* channel register */
56#define TSR 4 /* channel register */
57#define TCNT 5 /* channel register */
58#define TGR 6 /* channel register */
59
60#define TCR_CCLR_NONE (0 << 5)
61#define TCR_CCLR_TGRA (1 << 5)
62#define TCR_CCLR_TGRB (2 << 5)
63#define TCR_CCLR_SYNC (3 << 5)
64#define TCR_CCLR_TGRC (5 << 5)
65#define TCR_CCLR_TGRD (6 << 5)
66#define TCR_CCLR_MASK (7 << 5)
67#define TCR_CKEG_RISING (0 << 3)
68#define TCR_CKEG_FALLING (1 << 3)
69#define TCR_CKEG_BOTH (2 << 3)
70#define TCR_CKEG_MASK (3 << 3)
71/* Values 4 to 7 are channel-dependent */
72#define TCR_TPSC_P1 (0 << 0)
73#define TCR_TPSC_P4 (1 << 0)
74#define TCR_TPSC_P16 (2 << 0)
75#define TCR_TPSC_P64 (3 << 0)
76#define TCR_TPSC_CH0_TCLKA (4 << 0)
77#define TCR_TPSC_CH0_TCLKB (5 << 0)
78#define TCR_TPSC_CH0_TCLKC (6 << 0)
79#define TCR_TPSC_CH0_TCLKD (7 << 0)
80#define TCR_TPSC_CH1_TCLKA (4 << 0)
81#define TCR_TPSC_CH1_TCLKB (5 << 0)
82#define TCR_TPSC_CH1_P256 (6 << 0)
83#define TCR_TPSC_CH1_TCNT2 (7 << 0)
84#define TCR_TPSC_CH2_TCLKA (4 << 0)
85#define TCR_TPSC_CH2_TCLKB (5 << 0)
86#define TCR_TPSC_CH2_TCLKC (6 << 0)
87#define TCR_TPSC_CH2_P1024 (7 << 0)
88#define TCR_TPSC_CH34_P256 (4 << 0)
89#define TCR_TPSC_CH34_P1024 (5 << 0)
90#define TCR_TPSC_CH34_TCLKA (6 << 0)
91#define TCR_TPSC_CH34_TCLKB (7 << 0)
92#define TCR_TPSC_MASK (7 << 0)
93
94#define TMDR_BFE (1 << 6)
95#define TMDR_BFB (1 << 5)
96#define TMDR_BFA (1 << 4)
97#define TMDR_MD_NORMAL (0 << 0)
98#define TMDR_MD_PWM_1 (2 << 0)
99#define TMDR_MD_PWM_2 (3 << 0)
100#define TMDR_MD_PHASE_1 (4 << 0)
101#define TMDR_MD_PHASE_2 (5 << 0)
102#define TMDR_MD_PHASE_3 (6 << 0)
103#define TMDR_MD_PHASE_4 (7 << 0)
104#define TMDR_MD_PWM_SYNC (8 << 0)
105#define TMDR_MD_PWM_COMP_CREST (13 << 0)
106#define TMDR_MD_PWM_COMP_TROUGH (14 << 0)
107#define TMDR_MD_PWM_COMP_BOTH (15 << 0)
108#define TMDR_MD_MASK (15 << 0)
109
110#define TIOC_IOCH(n) ((n) << 4)
111#define TIOC_IOCL(n) ((n) << 0)
112#define TIOR_OC_RETAIN (0 << 0)
113#define TIOR_OC_0_CLEAR (1 << 0)
114#define TIOR_OC_0_SET (2 << 0)
115#define TIOR_OC_0_TOGGLE (3 << 0)
116#define TIOR_OC_1_CLEAR (5 << 0)
117#define TIOR_OC_1_SET (6 << 0)
118#define TIOR_OC_1_TOGGLE (7 << 0)
119#define TIOR_IC_RISING (8 << 0)
120#define TIOR_IC_FALLING (9 << 0)
121#define TIOR_IC_BOTH (10 << 0)
122#define TIOR_IC_TCNT (12 << 0)
123#define TIOR_MASK (15 << 0)
124
125#define TIER_TTGE (1 << 7)
126#define TIER_TTGE2 (1 << 6)
127#define TIER_TCIEU (1 << 5)
128#define TIER_TCIEV (1 << 4)
129#define TIER_TGIED (1 << 3)
130#define TIER_TGIEC (1 << 2)
131#define TIER_TGIEB (1 << 1)
132#define TIER_TGIEA (1 << 0)
133
134#define TSR_TCFD (1 << 7)
135#define TSR_TCFU (1 << 5)
136#define TSR_TCFV (1 << 4)
137#define TSR_TGFD (1 << 3)
138#define TSR_TGFC (1 << 2)
139#define TSR_TGFB (1 << 1)
140#define TSR_TGFA (1 << 0)
141
142static unsigned long mtu2_reg_offs[] = {
143 [TCR] = 0,
144 [TMDR] = 1,
145 [TIOR] = 2,
146 [TIER] = 4,
147 [TSR] = 5,
148 [TCNT] = 6,
149 [TGR] = 8,
150};
151
152static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
153{
154 unsigned long offs;
155
156 if (reg_nr == TSTR)
157 return ioread8(ch->mtu->mapbase + 0x280);
158
159 offs = mtu2_reg_offs[reg_nr];
160
161 if ((reg_nr == TCNT) || (reg_nr == TGR))
162 return ioread16(ch->base + offs);
163 else
164 return ioread8(ch->base + offs);
165}
166
167static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
168 unsigned long value)
169{
170 unsigned long offs;
171
172 if (reg_nr == TSTR)
173 return iowrite8(value, ch->mtu->mapbase + 0x280);
174
175 offs = mtu2_reg_offs[reg_nr];
176
177 if ((reg_nr == TCNT) || (reg_nr == TGR))
178 iowrite16(value, ch->base + offs);
179 else
180 iowrite8(value, ch->base + offs);
181}
182
183static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
184{
185 unsigned long flags, value;
186
187 /* start stop register shared by multiple timer channels */
188 raw_spin_lock_irqsave(&ch->mtu->lock, flags);
189 value = sh_mtu2_read(ch, TSTR);
190
191 if (start)
192 value |= 1 << ch->index;
193 else
194 value &= ~(1 << ch->index);
195
196 sh_mtu2_write(ch, TSTR, value);
197 raw_spin_unlock_irqrestore(&ch->mtu->lock, flags);
198}
199
200static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
201{
202 unsigned long periodic;
203 unsigned long rate;
204 int ret;
205
206 pm_runtime_get_sync(&ch->mtu->pdev->dev);
207 dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
208
209 /* enable clock */
210 ret = clk_enable(ch->mtu->clk);
211 if (ret) {
212 dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
213 ch->index);
214 return ret;
215 }
216
217 /* make sure channel is disabled */
218 sh_mtu2_start_stop_ch(ch, 0);
219
220 rate = clk_get_rate(ch->mtu->clk) / 64;
221 periodic = (rate + HZ/2) / HZ;
222
223 /*
224 * "Periodic Counter Operation"
225 * Clear on TGRA compare match, divide clock by 64.
226 */
227 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
228 sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
229 TIOC_IOCL(TIOR_OC_0_CLEAR));
230 sh_mtu2_write(ch, TGR, periodic);
231 sh_mtu2_write(ch, TCNT, 0);
232 sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
233 sh_mtu2_write(ch, TIER, TIER_TGIEA);
234
235 /* enable channel */
236 sh_mtu2_start_stop_ch(ch, 1);
237
238 return 0;
239}
240
241static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
242{
243 /* disable channel */
244 sh_mtu2_start_stop_ch(ch, 0);
245
246 /* stop clock */
247 clk_disable(ch->mtu->clk);
248
249 dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
250 pm_runtime_put(&ch->mtu->pdev->dev);
251}
252
253static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
254{
255 struct sh_mtu2_channel *ch = dev_id;
256
257 /* acknowledge interrupt */
258 sh_mtu2_read(ch, TSR);
259 sh_mtu2_write(ch, TSR, ~TSR_TGFA);
260
261 /* notify clockevent layer */
262 ch->ced.event_handler(&ch->ced);
263 return IRQ_HANDLED;
264}
265
266static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
267{
268 return container_of(ced, struct sh_mtu2_channel, ced);
269}
270
271static int sh_mtu2_clock_event_shutdown(struct clock_event_device *ced)
272{
273 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
274
275 if (clockevent_state_periodic(ced))
276 sh_mtu2_disable(ch);
277
278 return 0;
279}
280
281static int sh_mtu2_clock_event_set_periodic(struct clock_event_device *ced)
282{
283 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
284
285 if (clockevent_state_periodic(ced))
286 sh_mtu2_disable(ch);
287
288 dev_info(&ch->mtu->pdev->dev, "ch%u: used for periodic clock events\n",
289 ch->index);
290 sh_mtu2_enable(ch);
291 return 0;
292}
293
294static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
295{
296 pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
297}
298
299static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
300{
301 pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
302}
303
304static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
305 const char *name)
306{
307 struct clock_event_device *ced = &ch->ced;
308
309 ced->name = name;
310 ced->features = CLOCK_EVT_FEAT_PERIODIC;
311 ced->rating = 200;
312 ced->cpumask = cpu_possible_mask;
313 ced->set_state_shutdown = sh_mtu2_clock_event_shutdown;
314 ced->set_state_periodic = sh_mtu2_clock_event_set_periodic;
315 ced->suspend = sh_mtu2_clock_event_suspend;
316 ced->resume = sh_mtu2_clock_event_resume;
317
318 dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
319 ch->index);
320 clockevents_register_device(ced);
321}
322
323static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name)
324{
325 ch->mtu->has_clockevent = true;
326 sh_mtu2_register_clockevent(ch, name);
327
328 return 0;
329}
330
331static const unsigned int sh_mtu2_channel_offsets[] = {
332 0x300, 0x380, 0x000,
333};
334
335static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
336 struct sh_mtu2_device *mtu)
337{
338 char name[6];
339 int irq;
340 int ret;
341
342 ch->mtu = mtu;
343
344 sprintf(name, "tgi%ua", index);
345 irq = platform_get_irq_byname(mtu->pdev, name);
346 if (irq < 0) {
347 /* Skip channels with no declared interrupt. */
348 return 0;
349 }
350
351 ret = request_irq(irq, sh_mtu2_interrupt,
352 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
353 dev_name(&ch->mtu->pdev->dev), ch);
354 if (ret) {
355 dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
356 index, irq);
357 return ret;
358 }
359
360 ch->base = mtu->mapbase + sh_mtu2_channel_offsets[index];
361 ch->index = index;
362
363 return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev));
364}
365
366static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
367{
368 struct resource *res;
369
370 res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
371 if (!res) {
372 dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
373 return -ENXIO;
374 }
375
376 mtu->mapbase = ioremap_nocache(res->start, resource_size(res));
377 if (mtu->mapbase == NULL)
378 return -ENXIO;
379
380 return 0;
381}
382
383static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
384 struct platform_device *pdev)
385{
386 unsigned int i;
387 int ret;
388
389 mtu->pdev = pdev;
390
391 raw_spin_lock_init(&mtu->lock);
392
393 /* Get hold of clock. */
394 mtu->clk = clk_get(&mtu->pdev->dev, "fck");
395 if (IS_ERR(mtu->clk)) {
396 dev_err(&mtu->pdev->dev, "cannot get clock\n");
397 return PTR_ERR(mtu->clk);
398 }
399
400 ret = clk_prepare(mtu->clk);
401 if (ret < 0)
402 goto err_clk_put;
403
404 /* Map the memory resource. */
405 ret = sh_mtu2_map_memory(mtu);
406 if (ret < 0) {
407 dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
408 goto err_clk_unprepare;
409 }
410
411 /* Allocate and setup the channels. */
412 ret = platform_irq_count(pdev);
413 if (ret < 0)
414 goto err_unmap;
415
416 mtu->num_channels = min_t(unsigned int, ret,
417 ARRAY_SIZE(sh_mtu2_channel_offsets));
418
419 mtu->channels = kcalloc(mtu->num_channels, sizeof(*mtu->channels),
420 GFP_KERNEL);
421 if (mtu->channels == NULL) {
422 ret = -ENOMEM;
423 goto err_unmap;
424 }
425
426 for (i = 0; i < mtu->num_channels; ++i) {
427 ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
428 if (ret < 0)
429 goto err_unmap;
430 }
431
432 platform_set_drvdata(pdev, mtu);
433
434 return 0;
435
436err_unmap:
437 kfree(mtu->channels);
438 iounmap(mtu->mapbase);
439err_clk_unprepare:
440 clk_unprepare(mtu->clk);
441err_clk_put:
442 clk_put(mtu->clk);
443 return ret;
444}
445
446static int sh_mtu2_probe(struct platform_device *pdev)
447{
448 struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
449 int ret;
450
451 if (!is_early_platform_device(pdev)) {
452 pm_runtime_set_active(&pdev->dev);
453 pm_runtime_enable(&pdev->dev);
454 }
455
456 if (mtu) {
457 dev_info(&pdev->dev, "kept as earlytimer\n");
458 goto out;
459 }
460
461 mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
462 if (mtu == NULL)
463 return -ENOMEM;
464
465 ret = sh_mtu2_setup(mtu, pdev);
466 if (ret) {
467 kfree(mtu);
468 pm_runtime_idle(&pdev->dev);
469 return ret;
470 }
471 if (is_early_platform_device(pdev))
472 return 0;
473
474 out:
475 if (mtu->has_clockevent)
476 pm_runtime_irq_safe(&pdev->dev);
477 else
478 pm_runtime_idle(&pdev->dev);
479
480 return 0;
481}
482
483static int sh_mtu2_remove(struct platform_device *pdev)
484{
485 return -EBUSY; /* cannot unregister clockevent */
486}
487
488static const struct platform_device_id sh_mtu2_id_table[] = {
489 { "sh-mtu2", 0 },
490 { },
491};
492MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
493
494static const struct of_device_id sh_mtu2_of_table[] __maybe_unused = {
495 { .compatible = "renesas,mtu2" },
496 { }
497};
498MODULE_DEVICE_TABLE(of, sh_mtu2_of_table);
499
500static struct platform_driver sh_mtu2_device_driver = {
501 .probe = sh_mtu2_probe,
502 .remove = sh_mtu2_remove,
503 .driver = {
504 .name = "sh_mtu2",
505 .of_match_table = of_match_ptr(sh_mtu2_of_table),
506 },
507 .id_table = sh_mtu2_id_table,
508};
509
510static int __init sh_mtu2_init(void)
511{
512 return platform_driver_register(&sh_mtu2_device_driver);
513}
514
515static void __exit sh_mtu2_exit(void)
516{
517 platform_driver_unregister(&sh_mtu2_device_driver);
518}
519
520early_platform_init("earlytimer", &sh_mtu2_device_driver);
521subsys_initcall(sh_mtu2_init);
522module_exit(sh_mtu2_exit);
523
524MODULE_AUTHOR("Magnus Damm");
525MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
526MODULE_LICENSE("GPL v2");