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1/*
2 * OpenRISC Linux
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 *
17 * DMA mapping callbacks...
18 * As alloc_coherent is the only DMA callback being used currently, that's
19 * the only thing implemented properly. The rest need looking into...
20 */
21
22#include <linux/dma-mapping.h>
23#include <linux/dma-debug.h>
24
25#include <asm/cpuinfo.h>
26#include <asm/spr_defs.h>
27#include <asm/tlbflush.h>
28
29static int page_set_nocache(pte_t *pte, unsigned long addr,
30 unsigned long next, struct mm_walk *walk)
31{
32 unsigned long cl;
33
34 pte_val(*pte) |= _PAGE_CI;
35
36 /*
37 * Flush the page out of the TLB so that the new page flags get
38 * picked up next time there's an access
39 */
40 flush_tlb_page(NULL, addr);
41
42 /* Flush page out of dcache */
43 for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo.dcache_block_size)
44 mtspr(SPR_DCBFR, cl);
45
46 return 0;
47}
48
49static int page_clear_nocache(pte_t *pte, unsigned long addr,
50 unsigned long next, struct mm_walk *walk)
51{
52 pte_val(*pte) &= ~_PAGE_CI;
53
54 /*
55 * Flush the page out of the TLB so that the new page flags get
56 * picked up next time there's an access
57 */
58 flush_tlb_page(NULL, addr);
59
60 return 0;
61}
62
63/*
64 * Alloc "coherent" memory, which for OpenRISC means simply uncached.
65 *
66 * This function effectively just calls __get_free_pages, sets the
67 * cache-inhibit bit on those pages, and makes sure that the pages are
68 * flushed out of the cache before they are used.
69 *
70 */
71void *or1k_dma_alloc_coherent(struct device *dev, size_t size,
72 dma_addr_t *dma_handle, gfp_t gfp)
73{
74 unsigned long va;
75 void *page;
76 struct mm_walk walk = {
77 .pte_entry = page_set_nocache,
78 .mm = &init_mm
79 };
80
81 page = alloc_pages_exact(size, gfp);
82 if (!page)
83 return NULL;
84
85 /* This gives us the real physical address of the first page. */
86 *dma_handle = __pa(page);
87
88 va = (unsigned long)page;
89
90 /*
91 * We need to iterate through the pages, clearing the dcache for
92 * them and setting the cache-inhibit bit.
93 */
94 if (walk_page_range(va, va + size, &walk)) {
95 free_pages_exact(page, size);
96 return NULL;
97 }
98
99 return (void *)va;
100}
101
102void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
103 dma_addr_t dma_handle)
104{
105 unsigned long va = (unsigned long)vaddr;
106 struct mm_walk walk = {
107 .pte_entry = page_clear_nocache,
108 .mm = &init_mm
109 };
110
111 /* walk_page_range shouldn't be able to fail here */
112 WARN_ON(walk_page_range(va, va + size, &walk));
113
114 free_pages_exact(vaddr, size);
115}
116
117dma_addr_t or1k_map_page(struct device *dev, struct page *page,
118 unsigned long offset, size_t size,
119 enum dma_data_direction dir,
120 struct dma_attrs *attrs)
121{
122 unsigned long cl;
123 dma_addr_t addr = page_to_phys(page) + offset;
124
125 switch (dir) {
126 case DMA_TO_DEVICE:
127 /* Flush the dcache for the requested range */
128 for (cl = addr; cl < addr + size;
129 cl += cpuinfo.dcache_block_size)
130 mtspr(SPR_DCBFR, cl);
131 break;
132 case DMA_FROM_DEVICE:
133 /* Invalidate the dcache for the requested range */
134 for (cl = addr; cl < addr + size;
135 cl += cpuinfo.dcache_block_size)
136 mtspr(SPR_DCBIR, cl);
137 break;
138 default:
139 /*
140 * NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
141 * flush nor invalidate the cache here as the area will need
142 * to be manually synced anyway.
143 */
144 break;
145 }
146
147 return addr;
148}
149
150void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
151 size_t size, enum dma_data_direction dir,
152 struct dma_attrs *attrs)
153{
154 /* Nothing special to do here... */
155}
156
157int or1k_map_sg(struct device *dev, struct scatterlist *sg,
158 int nents, enum dma_data_direction dir,
159 struct dma_attrs *attrs)
160{
161 struct scatterlist *s;
162 int i;
163
164 for_each_sg(sg, s, nents, i) {
165 s->dma_address = or1k_map_page(dev, sg_page(s), s->offset,
166 s->length, dir, NULL);
167 }
168
169 return nents;
170}
171
172void or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
173 int nents, enum dma_data_direction dir,
174 struct dma_attrs *attrs)
175{
176 struct scatterlist *s;
177 int i;
178
179 for_each_sg(sg, s, nents, i) {
180 or1k_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, NULL);
181 }
182}
183
184void or1k_sync_single_for_cpu(struct device *dev,
185 dma_addr_t dma_handle, size_t size,
186 enum dma_data_direction dir)
187{
188 unsigned long cl;
189 dma_addr_t addr = dma_handle;
190
191 /* Invalidate the dcache for the requested range */
192 for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
193 mtspr(SPR_DCBIR, cl);
194}
195
196void or1k_sync_single_for_device(struct device *dev,
197 dma_addr_t dma_handle, size_t size,
198 enum dma_data_direction dir)
199{
200 unsigned long cl;
201 dma_addr_t addr = dma_handle;
202
203 /* Flush the dcache for the requested range */
204 for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
205 mtspr(SPR_DCBFR, cl);
206}
207
208/* Number of entries preallocated for DMA-API debugging */
209#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
210
211static int __init dma_init(void)
212{
213 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
214
215 return 0;
216}
217fs_initcall(dma_init);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * OpenRISC Linux
4 *
5 * Linux architectural port borrowing liberally from similar works of
6 * others. All original copyrights apply as per the original source
7 * declaration.
8 *
9 * Modifications for the OpenRISC architecture:
10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12 *
13 * DMA mapping callbacks...
14 * As alloc_coherent is the only DMA callback being used currently, that's
15 * the only thing implemented properly. The rest need looking into...
16 */
17
18#include <linux/dma-noncoherent.h>
19#include <linux/pagewalk.h>
20
21#include <asm/cpuinfo.h>
22#include <asm/spr_defs.h>
23#include <asm/tlbflush.h>
24
25static int
26page_set_nocache(pte_t *pte, unsigned long addr,
27 unsigned long next, struct mm_walk *walk)
28{
29 unsigned long cl;
30 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
31
32 pte_val(*pte) |= _PAGE_CI;
33
34 /*
35 * Flush the page out of the TLB so that the new page flags get
36 * picked up next time there's an access
37 */
38 flush_tlb_page(NULL, addr);
39
40 /* Flush page out of dcache */
41 for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
42 mtspr(SPR_DCBFR, cl);
43
44 return 0;
45}
46
47static const struct mm_walk_ops set_nocache_walk_ops = {
48 .pte_entry = page_set_nocache,
49};
50
51static int
52page_clear_nocache(pte_t *pte, unsigned long addr,
53 unsigned long next, struct mm_walk *walk)
54{
55 pte_val(*pte) &= ~_PAGE_CI;
56
57 /*
58 * Flush the page out of the TLB so that the new page flags get
59 * picked up next time there's an access
60 */
61 flush_tlb_page(NULL, addr);
62
63 return 0;
64}
65
66static const struct mm_walk_ops clear_nocache_walk_ops = {
67 .pte_entry = page_clear_nocache,
68};
69
70/*
71 * Alloc "coherent" memory, which for OpenRISC means simply uncached.
72 *
73 * This function effectively just calls __get_free_pages, sets the
74 * cache-inhibit bit on those pages, and makes sure that the pages are
75 * flushed out of the cache before they are used.
76 *
77 * If the NON_CONSISTENT attribute is set, then this function just
78 * returns "normal", cachable memory.
79 *
80 * There are additional flags WEAK_ORDERING and WRITE_COMBINE to take
81 * into consideration here, too. All current known implementations of
82 * the OR1K support only strongly ordered memory accesses, so that flag
83 * is being ignored for now; uncached but write-combined memory is a
84 * missing feature of the OR1K.
85 */
86void *
87arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
88 gfp_t gfp, unsigned long attrs)
89{
90 unsigned long va;
91 void *page;
92
93 page = alloc_pages_exact(size, gfp | __GFP_ZERO);
94 if (!page)
95 return NULL;
96
97 /* This gives us the real physical address of the first page. */
98 *dma_handle = __pa(page);
99
100 va = (unsigned long)page;
101
102 /*
103 * We need to iterate through the pages, clearing the dcache for
104 * them and setting the cache-inhibit bit.
105 */
106 if (walk_page_range(&init_mm, va, va + size, &set_nocache_walk_ops,
107 NULL)) {
108 free_pages_exact(page, size);
109 return NULL;
110 }
111
112 return (void *)va;
113}
114
115void
116arch_dma_free(struct device *dev, size_t size, void *vaddr,
117 dma_addr_t dma_handle, unsigned long attrs)
118{
119 unsigned long va = (unsigned long)vaddr;
120
121 /* walk_page_range shouldn't be able to fail here */
122 WARN_ON(walk_page_range(&init_mm, va, va + size,
123 &clear_nocache_walk_ops, NULL));
124
125 free_pages_exact(vaddr, size);
126}
127
128void arch_sync_dma_for_device(struct device *dev, phys_addr_t addr, size_t size,
129 enum dma_data_direction dir)
130{
131 unsigned long cl;
132 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
133
134 switch (dir) {
135 case DMA_TO_DEVICE:
136 /* Flush the dcache for the requested range */
137 for (cl = addr; cl < addr + size;
138 cl += cpuinfo->dcache_block_size)
139 mtspr(SPR_DCBFR, cl);
140 break;
141 case DMA_FROM_DEVICE:
142 /* Invalidate the dcache for the requested range */
143 for (cl = addr; cl < addr + size;
144 cl += cpuinfo->dcache_block_size)
145 mtspr(SPR_DCBIR, cl);
146 break;
147 default:
148 /*
149 * NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
150 * flush nor invalidate the cache here as the area will need
151 * to be manually synced anyway.
152 */
153 break;
154 }
155}