1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 *  ARM64 cacheinfo support
  4 *
  5 *  Copyright (C) 2015 ARM Ltd.
  6 *  All Rights Reserved
  7 */
  8
  9#include <linux/acpi.h>
 10#include <linux/cacheinfo.h>
 11#include <linux/of.h>
 12
 13#define MAX_CACHE_LEVEL			7	/* Max 7 level supported */
 14/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
 15#define CLIDR_CTYPE_SHIFT(level)	(3 * (level - 1))
 16#define CLIDR_CTYPE_MASK(level)		(7 << CLIDR_CTYPE_SHIFT(level))
 17#define CLIDR_CTYPE(clidr, level)	\
 18	(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
 19
 20int cache_line_size(void)
 21{
 22	if (coherency_max_size != 0)
 23		return coherency_max_size;
 24
 25	return cache_line_size_of_cpu();
 26}
 27EXPORT_SYMBOL_GPL(cache_line_size);
 28
 29static inline enum cache_type get_cache_type(int level)
 30{
 31	u64 clidr;
 32
 33	if (level > MAX_CACHE_LEVEL)
 34		return CACHE_TYPE_NOCACHE;
 35	clidr = read_sysreg(clidr_el1);
 36	return CLIDR_CTYPE(clidr, level);
 37}
 38
 39static void ci_leaf_init(struct cacheinfo *this_leaf,
 40			 enum cache_type type, unsigned int level)
 41{
 42	this_leaf->level = level;
 43	this_leaf->type = type;
 44}
 45
 46static int __init_cache_level(unsigned int cpu)
 47{
 48	unsigned int ctype, level, leaves, fw_level;
 49	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 50
 51	for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
 52		ctype = get_cache_type(level);
 53		if (ctype == CACHE_TYPE_NOCACHE) {
 54			level--;
 55			break;
 56		}
 57		/* Separate instruction and data caches */
 58		leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
 59	}
 60
 61	if (acpi_disabled)
 62		fw_level = of_find_last_cache_level(cpu);
 63	else
 64		fw_level = acpi_find_last_cache_level(cpu);
 65
 66	if (level < fw_level) {
 67		/*
 68		 * some external caches not specified in CLIDR_EL1
 69		 * the information may be available in the device tree
 70		 * only unified external caches are considered here
 71		 */
 72		leaves += (fw_level - level);
 73		level = fw_level;
 74	}
 75
 76	this_cpu_ci->num_levels = level;
 77	this_cpu_ci->num_leaves = leaves;
 78	return 0;
 79}
 80
 81static int __populate_cache_leaves(unsigned int cpu)
 82{
 83	unsigned int level, idx;
 84	enum cache_type type;
 85	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 86	struct cacheinfo *this_leaf = this_cpu_ci->info_list;
 87
 88	for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
 89	     idx < this_cpu_ci->num_leaves; idx++, level++) {
 90		type = get_cache_type(level);
 91		if (type == CACHE_TYPE_SEPARATE) {
 92			ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
 93			ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
 94		} else {
 95			ci_leaf_init(this_leaf++, type, level);
 96		}
 97	}
 98	return 0;
 99}
100
101DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
102DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)