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1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/omapfb.h>
26
27#include <asm/tlb.h>
28
29#include <asm/mach/map.h>
30
31#include <plat/sram.h>
32#include <plat/sdrc.h>
33#include <plat/serial.h>
34
35#include "clock2xxx.h"
36#include "clock3xxx.h"
37#include "clock44xx.h"
38#include "io.h"
39
40#include <plat/omap-pm.h>
41#include "powerdomain.h"
42
43#include "clockdomain.h"
44#include <plat/omap_hwmod.h>
45#include <plat/multi.h>
46
47/*
48 * The machine specific code may provide the extra mapping besides the
49 * default mapping provided here.
50 */
51
52#ifdef CONFIG_ARCH_OMAP2
53static struct map_desc omap24xx_io_desc[] __initdata = {
54 {
55 .virtual = L3_24XX_VIRT,
56 .pfn = __phys_to_pfn(L3_24XX_PHYS),
57 .length = L3_24XX_SIZE,
58 .type = MT_DEVICE
59 },
60 {
61 .virtual = L4_24XX_VIRT,
62 .pfn = __phys_to_pfn(L4_24XX_PHYS),
63 .length = L4_24XX_SIZE,
64 .type = MT_DEVICE
65 },
66};
67
68#ifdef CONFIG_SOC_OMAP2420
69static struct map_desc omap242x_io_desc[] __initdata = {
70 {
71 .virtual = DSP_MEM_2420_VIRT,
72 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
73 .length = DSP_MEM_2420_SIZE,
74 .type = MT_DEVICE
75 },
76 {
77 .virtual = DSP_IPI_2420_VIRT,
78 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
79 .length = DSP_IPI_2420_SIZE,
80 .type = MT_DEVICE
81 },
82 {
83 .virtual = DSP_MMU_2420_VIRT,
84 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
85 .length = DSP_MMU_2420_SIZE,
86 .type = MT_DEVICE
87 },
88};
89
90#endif
91
92#ifdef CONFIG_SOC_OMAP2430
93static struct map_desc omap243x_io_desc[] __initdata = {
94 {
95 .virtual = L4_WK_243X_VIRT,
96 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
97 .length = L4_WK_243X_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = OMAP243X_GPMC_VIRT,
102 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
103 .length = OMAP243X_GPMC_SIZE,
104 .type = MT_DEVICE
105 },
106 {
107 .virtual = OMAP243X_SDRC_VIRT,
108 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
109 .length = OMAP243X_SDRC_SIZE,
110 .type = MT_DEVICE
111 },
112 {
113 .virtual = OMAP243X_SMS_VIRT,
114 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
115 .length = OMAP243X_SMS_SIZE,
116 .type = MT_DEVICE
117 },
118};
119#endif
120#endif
121
122#ifdef CONFIG_ARCH_OMAP3
123static struct map_desc omap34xx_io_desc[] __initdata = {
124 {
125 .virtual = L3_34XX_VIRT,
126 .pfn = __phys_to_pfn(L3_34XX_PHYS),
127 .length = L3_34XX_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = L4_34XX_VIRT,
132 .pfn = __phys_to_pfn(L4_34XX_PHYS),
133 .length = L4_34XX_SIZE,
134 .type = MT_DEVICE
135 },
136 {
137 .virtual = OMAP34XX_GPMC_VIRT,
138 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
139 .length = OMAP34XX_GPMC_SIZE,
140 .type = MT_DEVICE
141 },
142 {
143 .virtual = OMAP343X_SMS_VIRT,
144 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
145 .length = OMAP343X_SMS_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = OMAP343X_SDRC_VIRT,
150 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
151 .length = OMAP343X_SDRC_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = L4_PER_34XX_VIRT,
156 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
157 .length = L4_PER_34XX_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = L4_EMU_34XX_VIRT,
162 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
163 .length = L4_EMU_34XX_SIZE,
164 .type = MT_DEVICE
165 },
166#if defined(CONFIG_DEBUG_LL) && \
167 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
168 {
169 .virtual = ZOOM_UART_VIRT,
170 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
171 .length = SZ_1M,
172 .type = MT_DEVICE
173 },
174#endif
175};
176#endif
177
178#ifdef CONFIG_SOC_OMAPTI816X
179static struct map_desc omapti816x_io_desc[] __initdata = {
180 {
181 .virtual = L4_34XX_VIRT,
182 .pfn = __phys_to_pfn(L4_34XX_PHYS),
183 .length = L4_34XX_SIZE,
184 .type = MT_DEVICE
185 },
186};
187#endif
188
189#ifdef CONFIG_ARCH_OMAP4
190static struct map_desc omap44xx_io_desc[] __initdata = {
191 {
192 .virtual = L3_44XX_VIRT,
193 .pfn = __phys_to_pfn(L3_44XX_PHYS),
194 .length = L3_44XX_SIZE,
195 .type = MT_DEVICE,
196 },
197 {
198 .virtual = L4_44XX_VIRT,
199 .pfn = __phys_to_pfn(L4_44XX_PHYS),
200 .length = L4_44XX_SIZE,
201 .type = MT_DEVICE,
202 },
203 {
204 .virtual = OMAP44XX_GPMC_VIRT,
205 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
206 .length = OMAP44XX_GPMC_SIZE,
207 .type = MT_DEVICE,
208 },
209 {
210 .virtual = OMAP44XX_EMIF1_VIRT,
211 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
212 .length = OMAP44XX_EMIF1_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = OMAP44XX_EMIF2_VIRT,
217 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
218 .length = OMAP44XX_EMIF2_SIZE,
219 .type = MT_DEVICE,
220 },
221 {
222 .virtual = OMAP44XX_DMM_VIRT,
223 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
224 .length = OMAP44XX_DMM_SIZE,
225 .type = MT_DEVICE,
226 },
227 {
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
233 {
234 .virtual = L4_EMU_44XX_VIRT,
235 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
236 .length = L4_EMU_44XX_SIZE,
237 .type = MT_DEVICE,
238 },
239};
240#endif
241
242static void __init _omap2_map_common_io(void)
243{
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
247 */
248 local_flush_tlb_all();
249 flush_cache_all();
250
251 omap2_check_revision();
252 omap_sram_init();
253}
254
255#ifdef CONFIG_SOC_OMAP2420
256void __init omap242x_map_common_io(void)
257{
258 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
259 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
260 _omap2_map_common_io();
261}
262#endif
263
264#ifdef CONFIG_SOC_OMAP2430
265void __init omap243x_map_common_io(void)
266{
267 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
268 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
269 _omap2_map_common_io();
270}
271#endif
272
273#ifdef CONFIG_ARCH_OMAP3
274void __init omap34xx_map_common_io(void)
275{
276 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
277 _omap2_map_common_io();
278}
279#endif
280
281#ifdef CONFIG_SOC_OMAPTI816X
282void __init omapti816x_map_common_io(void)
283{
284 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
285 _omap2_map_common_io();
286}
287#endif
288
289#ifdef CONFIG_ARCH_OMAP4
290void __init omap44xx_map_common_io(void)
291{
292 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
293 _omap2_map_common_io();
294}
295#endif
296
297/*
298 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
299 *
300 * Sets the CORE DPLL3 M2 divider to the same value that it's at
301 * currently. This has the effect of setting the SDRC SDRAM AC timing
302 * registers to the values currently defined by the kernel. Currently
303 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
304 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
305 * or passes along the return value of clk_set_rate().
306 */
307static int __init _omap2_init_reprogram_sdrc(void)
308{
309 struct clk *dpll3_m2_ck;
310 int v = -EINVAL;
311 long rate;
312
313 if (!cpu_is_omap34xx())
314 return 0;
315
316 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
317 if (IS_ERR(dpll3_m2_ck))
318 return -EINVAL;
319
320 rate = clk_get_rate(dpll3_m2_ck);
321 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
322 v = clk_set_rate(dpll3_m2_ck, rate);
323 if (v)
324 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
325
326 clk_put(dpll3_m2_ck);
327
328 return v;
329}
330
331static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
332{
333 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
334}
335
336/* See irq.c, omap4-common.c and entry-macro.S */
337void __iomem *omap_irq_base;
338
339void __init omap2_init_common_infrastructure(void)
340{
341 u8 postsetup_state;
342
343 if (cpu_is_omap242x()) {
344 omap2xxx_powerdomains_init();
345 omap2xxx_clockdomains_init();
346 omap2420_hwmod_init();
347 } else if (cpu_is_omap243x()) {
348 omap2xxx_powerdomains_init();
349 omap2xxx_clockdomains_init();
350 omap2430_hwmod_init();
351 } else if (cpu_is_omap34xx()) {
352 omap3xxx_powerdomains_init();
353 omap3xxx_clockdomains_init();
354 omap3xxx_hwmod_init();
355 } else if (cpu_is_omap44xx()) {
356 omap44xx_powerdomains_init();
357 omap44xx_clockdomains_init();
358 omap44xx_hwmod_init();
359 } else {
360 pr_err("Could not init hwmod data - unknown SoC\n");
361 }
362
363 /* Set the default postsetup state for all hwmods */
364#ifdef CONFIG_PM_RUNTIME
365 postsetup_state = _HWMOD_STATE_IDLE;
366#else
367 postsetup_state = _HWMOD_STATE_ENABLED;
368#endif
369 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
370
371 /*
372 * Set the default postsetup state for unusual modules (like
373 * MPU WDT).
374 *
375 * The postsetup_state is not actually used until
376 * omap_hwmod_late_init(), so boards that desire full watchdog
377 * coverage of kernel initialization can reprogram the
378 * postsetup_state between the calls to
379 * omap2_init_common_infra() and omap2_init_common_devices().
380 *
381 * XXX ideally we could detect whether the MPU WDT was currently
382 * enabled here and make this conditional
383 */
384 postsetup_state = _HWMOD_STATE_DISABLED;
385 omap_hwmod_for_each_by_class("wd_timer",
386 _set_hwmod_postsetup_state,
387 &postsetup_state);
388
389 omap_pm_if_early_init();
390
391 if (cpu_is_omap2420())
392 omap2420_clk_init();
393 else if (cpu_is_omap2430())
394 omap2430_clk_init();
395 else if (cpu_is_omap34xx())
396 omap3xxx_clk_init();
397 else if (cpu_is_omap44xx())
398 omap4xxx_clk_init();
399 else
400 pr_err("Could not init clock framework - unknown SoC\n");
401}
402
403void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
404 struct omap_sdrc_params *sdrc_cs1)
405{
406 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
407 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
408 _omap2_init_reprogram_sdrc();
409 }
410
411}
412
413/*
414 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
415 */
416
417u8 omap_readb(u32 pa)
418{
419 return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
420}
421EXPORT_SYMBOL(omap_readb);
422
423u16 omap_readw(u32 pa)
424{
425 return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
426}
427EXPORT_SYMBOL(omap_readw);
428
429u32 omap_readl(u32 pa)
430{
431 return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
432}
433EXPORT_SYMBOL(omap_readl);
434
435void omap_writeb(u8 v, u32 pa)
436{
437 __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
438}
439EXPORT_SYMBOL(omap_writeb);
440
441void omap_writew(u16 v, u32 pa)
442{
443 __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
444}
445EXPORT_SYMBOL(omap_writew);
446
447void omap_writel(u32 v, u32 pa)
448{
449 __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
450}
451EXPORT_SYMBOL(omap_writel);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap2/io.c
4 *
5 * OMAP2 I/O mapping code
6 *
7 * Copyright (C) 2005 Nokia Corporation
8 * Copyright (C) 2007-2009 Texas Instruments
9 *
10 * Author:
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
13 *
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 */
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/clk.h>
21
22#include <asm/tlb.h>
23#include <asm/mach/map.h>
24
25#include <linux/omap-dma.h>
26
27#include "omap_hwmod.h"
28#include "soc.h"
29#include "iomap.h"
30#include "voltage.h"
31#include "powerdomain.h"
32#include "clockdomain.h"
33#include "common.h"
34#include "clock.h"
35#include "clock2xxx.h"
36#include "clock3xxx.h"
37#include "sdrc.h"
38#include "control.h"
39#include "serial.h"
40#include "sram.h"
41#include "cm2xxx.h"
42#include "cm3xxx.h"
43#include "cm33xx.h"
44#include "cm44xx.h"
45#include "prm.h"
46#include "cm.h"
47#include "prcm_mpu44xx.h"
48#include "prminst44xx.h"
49#include "prm2xxx.h"
50#include "prm3xxx.h"
51#include "prm33xx.h"
52#include "prm44xx.h"
53#include "opp2xxx.h"
54
55/*
56 * omap_clk_soc_init: points to a function that does the SoC-specific
57 * clock initializations
58 */
59static int (*omap_clk_soc_init)(void);
60
61/*
62 * The machine specific code may provide the extra mapping besides the
63 * default mapping provided here.
64 */
65
66#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
67static struct map_desc omap24xx_io_desc[] __initdata = {
68 {
69 .virtual = L3_24XX_VIRT,
70 .pfn = __phys_to_pfn(L3_24XX_PHYS),
71 .length = L3_24XX_SIZE,
72 .type = MT_DEVICE
73 },
74 {
75 .virtual = L4_24XX_VIRT,
76 .pfn = __phys_to_pfn(L4_24XX_PHYS),
77 .length = L4_24XX_SIZE,
78 .type = MT_DEVICE
79 },
80};
81
82#ifdef CONFIG_SOC_OMAP2420
83static struct map_desc omap242x_io_desc[] __initdata = {
84 {
85 .virtual = DSP_MEM_2420_VIRT,
86 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
87 .length = DSP_MEM_2420_SIZE,
88 .type = MT_DEVICE
89 },
90 {
91 .virtual = DSP_IPI_2420_VIRT,
92 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
93 .length = DSP_IPI_2420_SIZE,
94 .type = MT_DEVICE
95 },
96 {
97 .virtual = DSP_MMU_2420_VIRT,
98 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
99 .length = DSP_MMU_2420_SIZE,
100 .type = MT_DEVICE
101 },
102};
103
104#endif
105
106#ifdef CONFIG_SOC_OMAP2430
107static struct map_desc omap243x_io_desc[] __initdata = {
108 {
109 .virtual = L4_WK_243X_VIRT,
110 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
111 .length = L4_WK_243X_SIZE,
112 .type = MT_DEVICE
113 },
114 {
115 .virtual = OMAP243X_GPMC_VIRT,
116 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
117 .length = OMAP243X_GPMC_SIZE,
118 .type = MT_DEVICE
119 },
120 {
121 .virtual = OMAP243X_SDRC_VIRT,
122 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
123 .length = OMAP243X_SDRC_SIZE,
124 .type = MT_DEVICE
125 },
126 {
127 .virtual = OMAP243X_SMS_VIRT,
128 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
129 .length = OMAP243X_SMS_SIZE,
130 .type = MT_DEVICE
131 },
132};
133#endif
134#endif
135
136#ifdef CONFIG_ARCH_OMAP3
137static struct map_desc omap34xx_io_desc[] __initdata = {
138 {
139 .virtual = L3_34XX_VIRT,
140 .pfn = __phys_to_pfn(L3_34XX_PHYS),
141 .length = L3_34XX_SIZE,
142 .type = MT_DEVICE
143 },
144 {
145 .virtual = L4_34XX_VIRT,
146 .pfn = __phys_to_pfn(L4_34XX_PHYS),
147 .length = L4_34XX_SIZE,
148 .type = MT_DEVICE
149 },
150 {
151 .virtual = OMAP34XX_GPMC_VIRT,
152 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
153 .length = OMAP34XX_GPMC_SIZE,
154 .type = MT_DEVICE
155 },
156 {
157 .virtual = OMAP343X_SMS_VIRT,
158 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
159 .length = OMAP343X_SMS_SIZE,
160 .type = MT_DEVICE
161 },
162 {
163 .virtual = OMAP343X_SDRC_VIRT,
164 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
165 .length = OMAP343X_SDRC_SIZE,
166 .type = MT_DEVICE
167 },
168 {
169 .virtual = L4_PER_34XX_VIRT,
170 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
171 .length = L4_PER_34XX_SIZE,
172 .type = MT_DEVICE
173 },
174 {
175 .virtual = L4_EMU_34XX_VIRT,
176 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
177 .length = L4_EMU_34XX_SIZE,
178 .type = MT_DEVICE
179 },
180};
181#endif
182
183#ifdef CONFIG_SOC_TI81XX
184static struct map_desc omapti81xx_io_desc[] __initdata = {
185 {
186 .virtual = L4_34XX_VIRT,
187 .pfn = __phys_to_pfn(L4_34XX_PHYS),
188 .length = L4_34XX_SIZE,
189 .type = MT_DEVICE
190 }
191};
192#endif
193
194#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
195static struct map_desc omapam33xx_io_desc[] __initdata = {
196 {
197 .virtual = L4_34XX_VIRT,
198 .pfn = __phys_to_pfn(L4_34XX_PHYS),
199 .length = L4_34XX_SIZE,
200 .type = MT_DEVICE
201 },
202 {
203 .virtual = L4_WK_AM33XX_VIRT,
204 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
205 .length = L4_WK_AM33XX_SIZE,
206 .type = MT_DEVICE
207 }
208};
209#endif
210
211#ifdef CONFIG_ARCH_OMAP4
212static struct map_desc omap44xx_io_desc[] __initdata = {
213 {
214 .virtual = L3_44XX_VIRT,
215 .pfn = __phys_to_pfn(L3_44XX_PHYS),
216 .length = L3_44XX_SIZE,
217 .type = MT_DEVICE,
218 },
219 {
220 .virtual = L4_44XX_VIRT,
221 .pfn = __phys_to_pfn(L4_44XX_PHYS),
222 .length = L4_44XX_SIZE,
223 .type = MT_DEVICE,
224 },
225 {
226 .virtual = L4_PER_44XX_VIRT,
227 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
228 .length = L4_PER_44XX_SIZE,
229 .type = MT_DEVICE,
230 },
231};
232#endif
233
234#ifdef CONFIG_SOC_OMAP5
235static struct map_desc omap54xx_io_desc[] __initdata = {
236 {
237 .virtual = L3_54XX_VIRT,
238 .pfn = __phys_to_pfn(L3_54XX_PHYS),
239 .length = L3_54XX_SIZE,
240 .type = MT_DEVICE,
241 },
242 {
243 .virtual = L4_54XX_VIRT,
244 .pfn = __phys_to_pfn(L4_54XX_PHYS),
245 .length = L4_54XX_SIZE,
246 .type = MT_DEVICE,
247 },
248 {
249 .virtual = L4_WK_54XX_VIRT,
250 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
251 .length = L4_WK_54XX_SIZE,
252 .type = MT_DEVICE,
253 },
254 {
255 .virtual = L4_PER_54XX_VIRT,
256 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
257 .length = L4_PER_54XX_SIZE,
258 .type = MT_DEVICE,
259 },
260};
261#endif
262
263#ifdef CONFIG_SOC_DRA7XX
264static struct map_desc dra7xx_io_desc[] __initdata = {
265 {
266 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
267 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
268 .length = L4_CFG_MPU_DRA7XX_SIZE,
269 .type = MT_DEVICE,
270 },
271 {
272 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
273 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
274 .length = L3_MAIN_SN_DRA7XX_SIZE,
275 .type = MT_DEVICE,
276 },
277 {
278 .virtual = L4_PER1_DRA7XX_VIRT,
279 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
280 .length = L4_PER1_DRA7XX_SIZE,
281 .type = MT_DEVICE,
282 },
283 {
284 .virtual = L4_PER2_DRA7XX_VIRT,
285 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
286 .length = L4_PER2_DRA7XX_SIZE,
287 .type = MT_DEVICE,
288 },
289 {
290 .virtual = L4_PER3_DRA7XX_VIRT,
291 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
292 .length = L4_PER3_DRA7XX_SIZE,
293 .type = MT_DEVICE,
294 },
295 {
296 .virtual = L4_CFG_DRA7XX_VIRT,
297 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
298 .length = L4_CFG_DRA7XX_SIZE,
299 .type = MT_DEVICE,
300 },
301 {
302 .virtual = L4_WKUP_DRA7XX_VIRT,
303 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
304 .length = L4_WKUP_DRA7XX_SIZE,
305 .type = MT_DEVICE,
306 },
307};
308#endif
309
310#ifdef CONFIG_SOC_OMAP2420
311void __init omap242x_map_io(void)
312{
313 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
314 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
315}
316#endif
317
318#ifdef CONFIG_SOC_OMAP2430
319void __init omap243x_map_io(void)
320{
321 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
322 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
323}
324#endif
325
326#ifdef CONFIG_ARCH_OMAP3
327void __init omap3_map_io(void)
328{
329 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
330}
331#endif
332
333#ifdef CONFIG_SOC_TI81XX
334void __init ti81xx_map_io(void)
335{
336 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
337}
338#endif
339
340#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
341void __init am33xx_map_io(void)
342{
343 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
344}
345#endif
346
347#ifdef CONFIG_ARCH_OMAP4
348void __init omap4_map_io(void)
349{
350 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
351 omap_barriers_init();
352}
353#endif
354
355#ifdef CONFIG_SOC_OMAP5
356void __init omap5_map_io(void)
357{
358 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
359 omap_barriers_init();
360}
361#endif
362
363#ifdef CONFIG_SOC_DRA7XX
364void __init dra7xx_map_io(void)
365{
366 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
367 omap_barriers_init();
368}
369#endif
370/*
371 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
372 *
373 * Sets the CORE DPLL3 M2 divider to the same value that it's at
374 * currently. This has the effect of setting the SDRC SDRAM AC timing
375 * registers to the values currently defined by the kernel. Currently
376 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
377 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
378 * or passes along the return value of clk_set_rate().
379 */
380static int __init _omap2_init_reprogram_sdrc(void)
381{
382 struct clk *dpll3_m2_ck;
383 int v = -EINVAL;
384 long rate;
385
386 if (!cpu_is_omap34xx())
387 return 0;
388
389 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
390 if (IS_ERR(dpll3_m2_ck))
391 return -EINVAL;
392
393 rate = clk_get_rate(dpll3_m2_ck);
394 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
395 v = clk_set_rate(dpll3_m2_ck, rate);
396 if (v)
397 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
398
399 clk_put(dpll3_m2_ck);
400
401 return v;
402}
403
404static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
405{
406 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
407}
408
409static void __init __maybe_unused omap_hwmod_init_postsetup(void)
410{
411 u8 postsetup_state = _HWMOD_STATE_DEFAULT;
412
413 /* Set the default postsetup state for all hwmods */
414 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
415}
416
417#ifdef CONFIG_SOC_OMAP2420
418void __init omap2420_init_early(void)
419{
420 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
421 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
422 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
423 omap2_control_base_init();
424 omap2xxx_check_revision();
425 omap2_prcm_base_init();
426 omap2xxx_voltagedomains_init();
427 omap242x_powerdomains_init();
428 omap242x_clockdomains_init();
429 omap2420_hwmod_init();
430 omap_hwmod_init_postsetup();
431 omap_clk_soc_init = omap2420_dt_clk_init;
432 rate_table = omap2420_rate_table;
433}
434
435void __init omap2420_init_late(void)
436{
437 omap_pm_soc_init = omap2_pm_init;
438}
439#endif
440
441#ifdef CONFIG_SOC_OMAP2430
442void __init omap2430_init_early(void)
443{
444 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
445 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
446 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
447 omap2_control_base_init();
448 omap2xxx_check_revision();
449 omap2_prcm_base_init();
450 omap2xxx_voltagedomains_init();
451 omap243x_powerdomains_init();
452 omap243x_clockdomains_init();
453 omap2430_hwmod_init();
454 omap_hwmod_init_postsetup();
455 omap_clk_soc_init = omap2430_dt_clk_init;
456 rate_table = omap2430_rate_table;
457}
458
459void __init omap2430_init_late(void)
460{
461 omap_pm_soc_init = omap2_pm_init;
462}
463#endif
464
465/*
466 * Currently only board-omap3beagle.c should call this because of the
467 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
468 */
469#ifdef CONFIG_ARCH_OMAP3
470void __init omap3_init_early(void)
471{
472 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
473 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
474 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
475 omap2_control_base_init();
476 omap3xxx_check_revision();
477 omap3xxx_check_features();
478 omap2_prcm_base_init();
479 omap3xxx_voltagedomains_init();
480 omap3xxx_powerdomains_init();
481 omap3xxx_clockdomains_init();
482 omap3xxx_hwmod_init();
483 omap_hwmod_init_postsetup();
484}
485
486void __init omap3430_init_early(void)
487{
488 omap3_init_early();
489 omap_clk_soc_init = omap3430_dt_clk_init;
490}
491
492void __init omap35xx_init_early(void)
493{
494 omap3_init_early();
495 omap_clk_soc_init = omap3430_dt_clk_init;
496}
497
498void __init omap3630_init_early(void)
499{
500 omap3_init_early();
501 omap_clk_soc_init = omap3630_dt_clk_init;
502}
503
504void __init am35xx_init_early(void)
505{
506 omap3_init_early();
507 omap_clk_soc_init = am35xx_dt_clk_init;
508}
509
510void __init omap3_init_late(void)
511{
512 omap_pm_soc_init = omap3_pm_init;
513}
514
515void __init ti81xx_init_late(void)
516{
517 omap_pm_soc_init = omap_pm_nop_init;
518}
519#endif
520
521#ifdef CONFIG_SOC_TI81XX
522void __init ti814x_init_early(void)
523{
524 omap2_set_globals_tap(TI814X_CLASS,
525 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
526 omap2_control_base_init();
527 omap3xxx_check_revision();
528 ti81xx_check_features();
529 omap2_prcm_base_init();
530 omap3xxx_voltagedomains_init();
531 omap3xxx_powerdomains_init();
532 ti814x_clockdomains_init();
533 dm814x_hwmod_init();
534 omap_hwmod_init_postsetup();
535 omap_clk_soc_init = dm814x_dt_clk_init;
536}
537
538void __init ti816x_init_early(void)
539{
540 omap2_set_globals_tap(TI816X_CLASS,
541 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
542 omap2_control_base_init();
543 omap3xxx_check_revision();
544 ti81xx_check_features();
545 omap2_prcm_base_init();
546 omap3xxx_voltagedomains_init();
547 omap3xxx_powerdomains_init();
548 ti816x_clockdomains_init();
549 dm816x_hwmod_init();
550 omap_hwmod_init_postsetup();
551 omap_clk_soc_init = dm816x_dt_clk_init;
552}
553#endif
554
555#ifdef CONFIG_SOC_AM33XX
556void __init am33xx_init_early(void)
557{
558 omap2_set_globals_tap(AM335X_CLASS,
559 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
560 omap2_control_base_init();
561 omap3xxx_check_revision();
562 am33xx_check_features();
563 omap2_prcm_base_init();
564 am33xx_powerdomains_init();
565 am33xx_clockdomains_init();
566 am33xx_hwmod_init();
567 omap_hwmod_init_postsetup();
568 omap_clk_soc_init = am33xx_dt_clk_init;
569}
570
571void __init am33xx_init_late(void)
572{
573 omap_pm_soc_init = amx3_common_pm_init;
574}
575#endif
576
577#ifdef CONFIG_SOC_AM43XX
578void __init am43xx_init_early(void)
579{
580 omap2_set_globals_tap(AM335X_CLASS,
581 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
582 omap2_control_base_init();
583 omap3xxx_check_revision();
584 am33xx_check_features();
585 omap2_prcm_base_init();
586 am43xx_powerdomains_init();
587 am43xx_clockdomains_init();
588 am43xx_hwmod_init();
589 omap_hwmod_init_postsetup();
590 omap_l2_cache_init();
591 omap_clk_soc_init = am43xx_dt_clk_init;
592}
593
594void __init am43xx_init_late(void)
595{
596 omap_pm_soc_init = amx3_common_pm_init;
597}
598#endif
599
600#ifdef CONFIG_ARCH_OMAP4
601void __init omap4430_init_early(void)
602{
603 omap2_set_globals_tap(OMAP443X_CLASS,
604 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
605 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
606 omap2_control_base_init();
607 omap4xxx_check_revision();
608 omap4xxx_check_features();
609 omap2_prcm_base_init();
610 omap4_sar_ram_init();
611 omap4_mpuss_early_init();
612 omap4_pm_init_early();
613 omap44xx_voltagedomains_init();
614 omap44xx_powerdomains_init();
615 omap44xx_clockdomains_init();
616 omap44xx_hwmod_init();
617 omap_hwmod_init_postsetup();
618 omap_l2_cache_init();
619 omap_clk_soc_init = omap4xxx_dt_clk_init;
620}
621
622void __init omap4430_init_late(void)
623{
624 omap_pm_soc_init = omap4_pm_init;
625}
626#endif
627
628#ifdef CONFIG_SOC_OMAP5
629void __init omap5_init_early(void)
630{
631 omap2_set_globals_tap(OMAP54XX_CLASS,
632 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
633 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
634 omap2_control_base_init();
635 omap2_prcm_base_init();
636 omap5xxx_check_revision();
637 omap4_sar_ram_init();
638 omap4_mpuss_early_init();
639 omap4_pm_init_early();
640 omap54xx_voltagedomains_init();
641 omap54xx_powerdomains_init();
642 omap54xx_clockdomains_init();
643 omap54xx_hwmod_init();
644 omap_hwmod_init_postsetup();
645 omap_clk_soc_init = omap5xxx_dt_clk_init;
646}
647
648void __init omap5_init_late(void)
649{
650 omap_pm_soc_init = omap4_pm_init;
651}
652#endif
653
654#ifdef CONFIG_SOC_DRA7XX
655void __init dra7xx_init_early(void)
656{
657 omap2_set_globals_tap(DRA7XX_CLASS,
658 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
659 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
660 omap2_control_base_init();
661 omap4_pm_init_early();
662 omap2_prcm_base_init();
663 dra7xxx_check_revision();
664 dra7xx_powerdomains_init();
665 dra7xx_clockdomains_init();
666 dra7xx_hwmod_init();
667 omap_hwmod_init_postsetup();
668 omap_clk_soc_init = dra7xx_dt_clk_init;
669}
670
671void __init dra7xx_init_late(void)
672{
673 omap_pm_soc_init = omap4_pm_init;
674}
675#endif
676
677
678void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
679 struct omap_sdrc_params *sdrc_cs1)
680{
681 omap_sram_init();
682
683 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
684 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
685 _omap2_init_reprogram_sdrc();
686 }
687}
688
689int __init omap_clk_init(void)
690{
691 int ret = 0;
692
693 if (!omap_clk_soc_init)
694 return 0;
695
696 ti_clk_init_features();
697
698 omap2_clk_setup_ll_ops();
699
700 ret = omap_control_init();
701 if (ret)
702 return ret;
703
704 ret = omap_prcm_init();
705 if (ret)
706 return ret;
707
708 of_clk_init(NULL);
709
710 ti_dt_clk_init_retry_clks();
711
712 ti_dt_clockdomains_setup();
713
714 ret = omap_clk_soc_init();
715
716 return ret;
717}