1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * Copyright (c) 2012 Linaro Limited.
  4 */
  5
  6#include <linux/init.h>
  7#include <linux/irqchip/arm-gic-v3.h>
  8#include <linux/linkage.h>
  9#include <asm/assembler.h>
 10#include <asm/virt.h>
 11
 12#ifndef ZIMAGE
 13/*
 14 * For the kernel proper, we need to find out the CPU boot mode long after
 15 * boot, so we need to store it in a writable variable.
 16 *
 17 * This is not in .bss, because we set it sufficiently early that the boot-time
 18 * zeroing of .bss would clobber it.
 19 */
 20.data
 21	.align	2
 22ENTRY(__boot_cpu_mode)
 23	.long	0
 24.text
 25
 26	/*
 27	 * Save the primary CPU boot mode. Requires 3 scratch registers.
 28	 */
 29	.macro	store_primary_cpu_mode	reg1, reg2, reg3
 30	mrs	\reg1, cpsr
 31	and	\reg1, \reg1, #MODE_MASK
 32	adr	\reg2, .L__boot_cpu_mode_offset
 33	ldr	\reg3, [\reg2]
 34	str	\reg1, [\reg2, \reg3]
 35	.endm
 36
 37	/*
 38	 * Compare the current mode with the one saved on the primary CPU.
 39	 * If they don't match, record that fact. The Z bit indicates
 40	 * if there's a match or not.
 41	 * Requires 3 additionnal scratch registers.
 42	 */
 43	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
 44	adr	\reg2, .L__boot_cpu_mode_offset
 45	ldr	\reg3, [\reg2]
 46	ldr	\reg1, [\reg2, \reg3]
 47	cmp	\mode, \reg1		@ matches primary CPU boot mode?
 48	orrne	\reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
 49	strne	\reg1, [\reg2, \reg3]	@ record what happened and give up
 50	.endm
 51
 52#else	/* ZIMAGE */
 53
 54	.macro	store_primary_cpu_mode	reg1:req, reg2:req, reg3:req
 55	.endm
 56
 57/*
 58 * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
 59 * consistency checking:
 60 */
 61	.macro	compare_cpu_mode_with_primary mode, reg1, reg2, reg3
 62	cmp	\mode, \mode
 63	.endm
 64
 65#endif /* ZIMAGE */
 66
 67/*
 68 * Hypervisor stub installation functions.
 69 *
 70 * These must be called with the MMU and D-cache off.
 71 * They are not ABI compliant and are only intended to be called from the kernel
 72 * entry points in head.S.
 73 */
 74@ Call this from the primary CPU
 75ENTRY(__hyp_stub_install)
 76	store_primary_cpu_mode	r4, r5, r6
 77ENDPROC(__hyp_stub_install)
 78
 79	@ fall through...
 80
 81@ Secondary CPUs should call here
 82ENTRY(__hyp_stub_install_secondary)
 83	mrs	r4, cpsr
 84	and	r4, r4, #MODE_MASK
 85
 86	/*
 87	 * If the secondary has booted with a different mode, give up
 88	 * immediately.
 89	 */
 90	compare_cpu_mode_with_primary	r4, r5, r6, r7
 91	retne	lr
 92
 93	/*
 94	 * Once we have given up on one CPU, we do not try to install the
 95	 * stub hypervisor on the remaining ones: because the saved boot mode
 96	 * is modified, it can't compare equal to the CPSR mode field any
 97	 * more.
 98	 *
 99	 * Otherwise...
100	 */
101
102	cmp	r4, #HYP_MODE
103	retne	lr			@ give up if the CPU is not in HYP mode
104
105/*
106 * Configure HSCTLR to set correct exception endianness/instruction set
107 * state etc.
108 * Turn off all traps
109 * Eventually, CPU-specific code might be needed -- assume not for now
110 *
111 * This code relies on the "eret" instruction to synchronize the
112 * various coprocessor accesses. This is done when we switch to SVC
113 * (see safe_svcmode_maskall).
114 */
115	@ Now install the hypervisor stub:
116	W(adr)	r7, __hyp_stub_vectors
117	mcr	p15, 4, r7, c12, c0, 0	@ set hypervisor vector base (HVBAR)
118
119	@ Disable all traps, so we don't get any nasty surprise
120	mov	r7, #0
121	mcr	p15, 4, r7, c1, c1, 0	@ HCR
122	mcr	p15, 4, r7, c1, c1, 2	@ HCPTR
123	mcr	p15, 4, r7, c1, c1, 3	@ HSTR
124
125THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
126ARM_BE8(orr	r7, r7, #(1 << 25))     @ HSCTLR.EE
127	mcr	p15, 4, r7, c1, c0, 0	@ HSCTLR
128
129	mrc	p15, 4, r7, c1, c1, 1	@ HDCR
130	and	r7, #0x1f		@ Preserve HPMN
131	mcr	p15, 4, r7, c1, c1, 1	@ HDCR
132
133	@ Make sure NS-SVC is initialised appropriately
134	mrc	p15, 0, r7, c1, c0, 0	@ SCTLR
135	orr	r7, #(1 << 5)		@ CP15 barriers enabled
136	bic	r7, #(3 << 7)		@ Clear SED/ITD for v8 (RES0 for v7)
137	bic	r7, #(3 << 19)		@ WXN and UWXN disabled
138	mcr	p15, 0, r7, c1, c0, 0	@ SCTLR
139
140	mrc	p15, 0, r7, c0, c0, 0	@ MIDR
141	mcr	p15, 4, r7, c0, c0, 0	@ VPIDR
142
143	mrc	p15, 0, r7, c0, c0, 5	@ MPIDR
144	mcr	p15, 4, r7, c0, c0, 5	@ VMPIDR
145
146#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
147	@ make CNTP_* and CNTPCT accessible from PL1
148	mrc	p15, 0, r7, c0, c1, 1	@ ID_PFR1
149	lsr	r7, #16
150	and	r7, #0xf
151	cmp	r7, #1
152	bne	1f
153	mrc	p15, 4, r7, c14, c1, 0	@ CNTHCTL
154	orr	r7, r7, #3		@ PL1PCEN | PL1PCTEN
155	mcr	p15, 4, r7, c14, c1, 0	@ CNTHCTL
156	mov	r7, #0
157	mcrr	p15, 4, r7, r7, c14	@ CNTVOFF
158
159	@ Disable virtual timer in case it was counting
160	mrc	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
161	bic	r7, #1			@ Clear ENABLE
162	mcr	p15, 0, r7, c14, c3, 1	@ CNTV_CTL
1631:
164#endif
165
166#ifdef CONFIG_ARM_GIC_V3
167	@ Check whether GICv3 system registers are available
168	mrc	p15, 0, r7, c0, c1, 1	@ ID_PFR1
169	ubfx	r7, r7, #28, #4
170	teq	r7, #0
171	beq	2f
172
173	@ Enable system register accesses
174	mrc	p15, 4, r7, c12, c9, 5	@ ICC_HSRE
175	orr	r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
176	mcr	p15, 4, r7, c12, c9, 5	@ ICC_HSRE
177	isb
178
179	@ SRE bit could be forced to 0 by firmware.
180	@ Check whether it sticks before accessing any other sysreg
181	mrc	p15, 4, r7, c12, c9, 5	@ ICC_HSRE
182	tst	r7, #ICC_SRE_EL2_SRE
183	beq	2f
184	mov	r7, #0
185	mcr	p15, 4, r7, c12, c11, 0	@ ICH_HCR
1862:
187#endif
188
189	bx	lr			@ The boot CPU mode is left in r4.
190ENDPROC(__hyp_stub_install_secondary)
191
192__hyp_stub_do_trap:
193	teq	r0, #HVC_SET_VECTORS
194	bne	1f
195	mcr	p15, 4, r1, c12, c0, 0	@ set HVBAR
196	b	__hyp_stub_exit
197
1981:	teq	r0, #HVC_SOFT_RESTART
199	bne	1f
200	bx	r1
201
2021:	teq	r0, #HVC_RESET_VECTORS
203	beq	__hyp_stub_exit
204
205	ldr	r0, =HVC_STUB_ERR
206	__ERET
207
208__hyp_stub_exit:
209	mov	r0, #0
210	__ERET
211ENDPROC(__hyp_stub_do_trap)
212
213/*
214 * __hyp_set_vectors: Call this after boot to set the initial hypervisor
215 * vectors as part of hypervisor installation.  On an SMP system, this should
216 * be called on each CPU.
217 *
218 * r0 must be the physical address of the new vector table (which must lie in
219 * the bottom 4GB of physical address space.
220 *
221 * r0 must be 32-byte aligned.
222 *
223 * Before calling this, you must check that the stub hypervisor is installed
224 * everywhere, by waiting for any secondary CPUs to be brought up and then
225 * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
226 *
227 * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
228 * something else went wrong... in such cases, trying to install a new
229 * hypervisor is unlikely to work as desired.
230 *
231 * When you call into your shiny new hypervisor, sp_hyp will contain junk,
232 * so you will need to set that to something sensible at the new hypervisor's
233 * initialisation entry point.
234 */
235ENTRY(__hyp_set_vectors)
236	mov	r1, r0
237	mov	r0, #HVC_SET_VECTORS
238	__HVC(0)
239	ret	lr
240ENDPROC(__hyp_set_vectors)
241
242ENTRY(__hyp_soft_restart)
243	mov	r1, r0
244	mov	r0, #HVC_SOFT_RESTART
245	__HVC(0)
246	ret	lr
247ENDPROC(__hyp_soft_restart)
248
249ENTRY(__hyp_reset_vectors)
250	mov	r0, #HVC_RESET_VECTORS
251	__HVC(0)
252	ret	lr
253ENDPROC(__hyp_reset_vectors)
254
255#ifndef ZIMAGE
256.align 2
257.L__boot_cpu_mode_offset:
258	.long	__boot_cpu_mode - .
259#endif
260
261.align 5
262ENTRY(__hyp_stub_vectors)
263__hyp_stub_reset:	W(b)	.
264__hyp_stub_und:		W(b)	.
265__hyp_stub_svc:		W(b)	.
266__hyp_stub_pabort:	W(b)	.
267__hyp_stub_dabort:	W(b)	.
268__hyp_stub_trap:	W(b)	__hyp_stub_do_trap
269__hyp_stub_irq:		W(b)	.
270__hyp_stub_fiq:		W(b)	.
271ENDPROC(__hyp_stub_vectors)
272