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1/*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef DRM_FOURCC_H
25#define DRM_FOURCC_H
26
27#include "drm.h"
28
29#if defined(__cplusplus)
30extern "C" {
31#endif
32
33/**
34 * DOC: overview
35 *
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
40 *
41 * Format Modifiers
42 * ----------------
43 *
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
48 *
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
53 *
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
60 *
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
63 * another modifier. For instance, it's incorrect to encode pitch alignment in
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
65 * aligned modifier. That said, modifiers can have implicit minimal
66 * requirements.
67 *
68 * For modifiers where the combination of fourcc code and modifier can alias,
69 * a canonical pair needs to be defined and used by all drivers. Preferred
70 * combinations are also encouraged where all combinations might lead to
71 * confusion and unnecessarily reduced interoperability. An example for the
72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
73 *
74 * There are two kinds of modifier users:
75 *
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
77 * don't alias, otherwise two drivers might support the same format but use
78 * different aliases, preventing them from sharing buffers in an efficient
79 * format.
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81 * see modifiers as opaque tokens they can check for equality and intersect.
82 * These users musn't need to know to reason about the modifier value
83 * (i.e. they are not expected to extract information out of the modifier).
84 *
85 * Vendors should document their modifier usage in as much detail as
86 * possible, to ensure maximum compatibility across devices, drivers and
87 * applications.
88 *
89 * The authoritative list of format modifier codes is found in
90 * `include/uapi/drm/drm_fourcc.h`
91 */
92
93#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
94 ((__u32)(c) << 16) | ((__u32)(d) << 24))
95
96#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
97
98/* Reserve 0 for the invalid format specifier */
99#define DRM_FORMAT_INVALID 0
100
101/* color index */
102#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
103
104/* 8 bpp Red */
105#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
106
107/* 16 bpp Red */
108#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
109
110/* 16 bpp RG */
111#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
112#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
113
114/* 32 bpp RG */
115#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
116#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
117
118/* 8 bpp RGB */
119#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
120#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
121
122/* 16 bpp RGB */
123#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
124#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
125#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
126#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
127
128#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
129#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
130#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
131#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
132
133#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
134#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
135#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
136#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
137
138#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
139#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
140#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
141#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
142
143#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
144#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
145
146/* 24 bpp RGB */
147#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
148#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
149
150/* 32 bpp RGB */
151#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
152#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
153#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
154#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
155
156#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
157#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
158#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
159#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
160
161#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
162#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
163#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
164#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
165
166#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
167#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
168#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
169#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
170
171/* 64 bpp RGB */
172#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
173#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
174
175#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
176#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
177
178/*
179 * Floating point 64bpp RGB
180 * IEEE 754-2008 binary16 half-precision float
181 * [15:0] sign:exponent:mantissa 1:5:10
182 */
183#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
184#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
185
186#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
187#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
188
189/*
190 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
191 * of unused padding per component:
192 */
193#define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
194
195/* packed YCbCr */
196#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
197#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
198#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
199#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
200
201#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
202#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
203#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
204#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
205
206/*
207 * packed Y2xx indicate for each component, xx valid data occupy msb
208 * 16-xx padding occupy lsb
209 */
210#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
211#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
212#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
213
214/*
215 * packed Y4xx indicate for each component, xx valid data occupy msb
216 * 16-xx padding occupy lsb except Y410
217 */
218#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
219#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
220#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
221
222#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
223#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
224#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
225
226/*
227 * packed YCbCr420 2x2 tiled formats
228 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
229 */
230/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
231#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
232/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
233#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
234
235/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
236#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
237/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
238#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
239
240/*
241 * 1-plane YUV 4:2:0
242 * In these formats, the component ordering is specified (Y, followed by U
243 * then V), but the exact Linear layout is undefined.
244 * These formats can only be used with a non-Linear modifier.
245 */
246#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
247#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
248
249/*
250 * 2 plane RGB + A
251 * index 0 = RGB plane, same format as the corresponding non _A8 format has
252 * index 1 = A plane, [7:0] A
253 */
254#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
255#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
256#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
257#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
258#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
259#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
260#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
261#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
262
263/*
264 * 2 plane YCbCr
265 * index 0 = Y plane, [7:0] Y
266 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
267 * or
268 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
269 */
270#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
271#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
272#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
273#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
274#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
275#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
276/*
277 * 2 plane YCbCr
278 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
279 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
280 */
281#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
282
283/*
284 * 2 plane YCbCr MSB aligned
285 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
286 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
287 */
288#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
289
290/*
291 * 2 plane YCbCr MSB aligned
292 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
293 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
294 */
295#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
296
297/*
298 * 2 plane YCbCr MSB aligned
299 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
300 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
301 */
302#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
303
304/*
305 * 2 plane YCbCr MSB aligned
306 * index 0 = Y plane, [15:0] Y little endian
307 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
308 */
309#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
310
311/* 3 plane non-subsampled (444) YCbCr
312 * 16 bits per component, but only 10 bits are used and 6 bits are padded
313 * index 0: Y plane, [15:0] Y:x [10:6] little endian
314 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
315 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
316 */
317#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
318
319/* 3 plane non-subsampled (444) YCrCb
320 * 16 bits per component, but only 10 bits are used and 6 bits are padded
321 * index 0: Y plane, [15:0] Y:x [10:6] little endian
322 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
323 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
324 */
325#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
326
327/*
328 * 3 plane YCbCr
329 * index 0: Y plane, [7:0] Y
330 * index 1: Cb plane, [7:0] Cb
331 * index 2: Cr plane, [7:0] Cr
332 * or
333 * index 1: Cr plane, [7:0] Cr
334 * index 2: Cb plane, [7:0] Cb
335 */
336#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
337#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
338#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
339#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
340#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
341#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
342#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
343#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
344#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
345#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
346
347
348/*
349 * Format Modifiers:
350 *
351 * Format modifiers describe, typically, a re-ordering or modification
352 * of the data in a plane of an FB. This can be used to express tiled/
353 * swizzled formats, or compression, or a combination of the two.
354 *
355 * The upper 8 bits of the format modifier are a vendor-id as assigned
356 * below. The lower 56 bits are assigned as vendor sees fit.
357 */
358
359/* Vendor Ids: */
360#define DRM_FORMAT_MOD_VENDOR_NONE 0
361#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
362#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
363#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
364#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
365#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
366#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
367#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
368#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
369#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
370#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
371
372/* add more to the end as needed */
373
374#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
375
376#define fourcc_mod_code(vendor, val) \
377 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
378
379/*
380 * Format Modifier tokens:
381 *
382 * When adding a new token please document the layout with a code comment,
383 * similar to the fourcc codes above. drm_fourcc.h is considered the
384 * authoritative source for all of these.
385 *
386 * Generic modifier names:
387 *
388 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
389 * for layouts which are common across multiple vendors. To preserve
390 * compatibility, in cases where a vendor-specific definition already exists and
391 * a generic name for it is desired, the common name is a purely symbolic alias
392 * and must use the same numerical value as the original definition.
393 *
394 * Note that generic names should only be used for modifiers which describe
395 * generic layouts (such as pixel re-ordering), which may have
396 * independently-developed support across multiple vendors.
397 *
398 * In future cases where a generic layout is identified before merging with a
399 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
400 * 'NONE' could be considered. This should only be for obvious, exceptional
401 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
402 * apply to a single vendor.
403 *
404 * Generic names should not be used for cases where multiple hardware vendors
405 * have implementations of the same standardised compression scheme (such as
406 * AFBC). In those cases, all implementations should use the same format
407 * modifier(s), reflecting the vendor of the standard.
408 */
409
410#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
411
412/*
413 * Invalid Modifier
414 *
415 * This modifier can be used as a sentinel to terminate the format modifiers
416 * list, or to initialize a variable with an invalid modifier. It might also be
417 * used to report an error back to userspace for certain APIs.
418 */
419#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
420
421/*
422 * Linear Layout
423 *
424 * Just plain linear layout. Note that this is different from no specifying any
425 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
426 * which tells the driver to also take driver-internal information into account
427 * and so might actually result in a tiled framebuffer.
428 */
429#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
430
431/*
432 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
433 *
434 * The "none" format modifier doesn't actually mean that the modifier is
435 * implicit, instead it means that the layout is linear. Whether modifiers are
436 * used is out-of-band information carried in an API-specific way (e.g. in a
437 * flag for drm_mode_fb_cmd2).
438 */
439#define DRM_FORMAT_MOD_NONE 0
440
441/* Intel framebuffer modifiers */
442
443/*
444 * Intel X-tiling layout
445 *
446 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
447 * in row-major layout. Within the tile bytes are laid out row-major, with
448 * a platform-dependent stride. On top of that the memory can apply
449 * platform-depending swizzling of some higher address bits into bit6.
450 *
451 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
452 * On earlier platforms the is highly platforms specific and not useful for
453 * cross-driver sharing. It exists since on a given platform it does uniquely
454 * identify the layout in a simple way for i915-specific userspace, which
455 * facilitated conversion of userspace to modifiers. Additionally the exact
456 * format on some really old platforms is not known.
457 */
458#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
459
460/*
461 * Intel Y-tiling layout
462 *
463 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
464 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
465 * chunks column-major, with a platform-dependent height. On top of that the
466 * memory can apply platform-depending swizzling of some higher address bits
467 * into bit6.
468 *
469 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
470 * On earlier platforms the is highly platforms specific and not useful for
471 * cross-driver sharing. It exists since on a given platform it does uniquely
472 * identify the layout in a simple way for i915-specific userspace, which
473 * facilitated conversion of userspace to modifiers. Additionally the exact
474 * format on some really old platforms is not known.
475 */
476#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
477
478/*
479 * Intel Yf-tiling layout
480 *
481 * This is a tiled layout using 4Kb tiles in row-major layout.
482 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
483 * are arranged in four groups (two wide, two high) with column-major layout.
484 * Each group therefore consits out of four 256 byte units, which are also laid
485 * out as 2x2 column-major.
486 * 256 byte units are made out of four 64 byte blocks of pixels, producing
487 * either a square block or a 2:1 unit.
488 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
489 * in pixel depends on the pixel depth.
490 */
491#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
492
493/*
494 * Intel color control surface (CCS) for render compression
495 *
496 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
497 * The main surface will be plane index 0 and must be Y/Yf-tiled,
498 * the CCS will be plane index 1.
499 *
500 * Each CCS tile matches a 1024x512 pixel area of the main surface.
501 * To match certain aspects of the 3D hardware the CCS is
502 * considered to be made up of normal 128Bx32 Y tiles, Thus
503 * the CCS pitch must be specified in multiples of 128 bytes.
504 *
505 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
506 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
507 * But that fact is not relevant unless the memory is accessed
508 * directly.
509 */
510#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
511#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
512
513/*
514 * Intel color control surfaces (CCS) for Gen-12 render compression.
515 *
516 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
517 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
518 * main surface. In other words, 4 bits in CCS map to a main surface cache
519 * line pair. The main surface pitch is required to be a multiple of four
520 * Y-tile widths.
521 */
522#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
523
524/*
525 * Intel color control surfaces (CCS) for Gen-12 media compression
526 *
527 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
528 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
529 * main surface. In other words, 4 bits in CCS map to a main surface cache
530 * line pair. The main surface pitch is required to be a multiple of four
531 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
532 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
533 * planes 2 and 3 for the respective CCS.
534 */
535#define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
536
537/*
538 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
539 * compression.
540 *
541 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
542 * and at index 1. The clear color is stored at index 2, and the pitch should
543 * be ignored. The clear color structure is 256 bits. The first 128 bits
544 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
545 * by 32 bits. The raw clear color is consumed by the 3d engine and generates
546 * the converted clear color of size 64 bits. The first 32 bits store the Lower
547 * Converted Clear Color value and the next 32 bits store the Higher Converted
548 * Clear Color value when applicable. The Converted Clear Color values are
549 * consumed by the DE. The last 64 bits are used to store Color Discard Enable
550 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
551 * corresponds to an area of 4x1 tiles in the main surface. The main surface
552 * pitch is required to be a multiple of 4 tile widths.
553 */
554#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
555
556/*
557 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
558 *
559 * Macroblocks are laid in a Z-shape, and each pixel data is following the
560 * standard NV12 style.
561 * As for NV12, an image is the result of two frame buffers: one for Y,
562 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
563 * Alignment requirements are (for each buffer):
564 * - multiple of 128 pixels for the width
565 * - multiple of 32 pixels for the height
566 *
567 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
568 */
569#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
570
571/*
572 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
573 *
574 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
575 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
576 * they correspond to their 16x16 luma block.
577 */
578#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
579
580/*
581 * Qualcomm Compressed Format
582 *
583 * Refers to a compressed variant of the base format that is compressed.
584 * Implementation may be platform and base-format specific.
585 *
586 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
587 * Pixel data pitch/stride is aligned with macrotile width.
588 * Pixel data height is aligned with macrotile height.
589 * Entire pixel data buffer is aligned with 4k(bytes).
590 */
591#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
592
593/* Vivante framebuffer modifiers */
594
595/*
596 * Vivante 4x4 tiling layout
597 *
598 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
599 * layout.
600 */
601#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
602
603/*
604 * Vivante 64x64 super-tiling layout
605 *
606 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
607 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
608 * major layout.
609 *
610 * For more information: see
611 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
612 */
613#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
614
615/*
616 * Vivante 4x4 tiling layout for dual-pipe
617 *
618 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
619 * different base address. Offsets from the base addresses are therefore halved
620 * compared to the non-split tiled layout.
621 */
622#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
623
624/*
625 * Vivante 64x64 super-tiling layout for dual-pipe
626 *
627 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
628 * starts at a different base address. Offsets from the base addresses are
629 * therefore halved compared to the non-split super-tiled layout.
630 */
631#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
632
633/* NVIDIA frame buffer modifiers */
634
635/*
636 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
637 *
638 * Pixels are arranged in simple tiles of 16 x 16 bytes.
639 */
640#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
641
642/*
643 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
644 * and Tegra GPUs starting with Tegra K1.
645 *
646 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
647 * based on the architecture generation. GOBs themselves are then arranged in
648 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
649 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
650 * a block depth or height of "4").
651 *
652 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
653 * in full detail.
654 *
655 * Macro
656 * Bits Param Description
657 * ---- ----- -----------------------------------------------------------------
658 *
659 * 3:0 h log2(height) of each block, in GOBs. Placed here for
660 * compatibility with the existing
661 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
662 *
663 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
664 * compatibility with the existing
665 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
666 *
667 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
668 * size). Must be zero.
669 *
670 * Note there is no log2(width) parameter. Some portions of the
671 * hardware support a block width of two gobs, but it is impractical
672 * to use due to lack of support elsewhere, and has no known
673 * benefits.
674 *
675 * 11:9 - Reserved (To support 2D-array textures with variable array stride
676 * in blocks, specified via log2(tile width in blocks)). Must be
677 * zero.
678 *
679 * 19:12 k Page Kind. This value directly maps to a field in the page
680 * tables of all GPUs >= NV50. It affects the exact layout of bits
681 * in memory and can be derived from the tuple
682 *
683 * (format, GPU model, compression type, samples per pixel)
684 *
685 * Where compression type is defined below. If GPU model were
686 * implied by the format modifier, format, or memory buffer, page
687 * kind would not need to be included in the modifier itself, but
688 * since the modifier should define the layout of the associated
689 * memory buffer independent from any device or other context, it
690 * must be included here.
691 *
692 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
693 * starting with Fermi GPUs. Additionally, the mapping between page
694 * kind and bit layout has changed at various points.
695 *
696 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
697 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
698 * 2 = Gob Height 8, Turing+ Page Kind mapping
699 * 3 = Reserved for future use.
700 *
701 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
702 * bit remapping step that occurs at an even lower level than the
703 * page kind and block linear swizzles. This causes the layout of
704 * surfaces mapped in those SOC's GPUs to be incompatible with the
705 * equivalent mapping on other GPUs in the same system.
706 *
707 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
708 * 1 = Desktop GPU and Tegra Xavier+ Layout
709 *
710 * 25:23 c Lossless Framebuffer Compression type.
711 *
712 * 0 = none
713 * 1 = ROP/3D, layout 1, exact compression format implied by Page
714 * Kind field
715 * 2 = ROP/3D, layout 2, exact compression format implied by Page
716 * Kind field
717 * 3 = CDE horizontal
718 * 4 = CDE vertical
719 * 5 = Reserved for future use
720 * 6 = Reserved for future use
721 * 7 = Reserved for future use
722 *
723 * 55:25 - Reserved for future use. Must be zero.
724 */
725#define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
726 fourcc_mod_code(NVIDIA, (0x10 | \
727 ((h) & 0xf) | \
728 (((k) & 0xff) << 12) | \
729 (((g) & 0x3) << 20) | \
730 (((s) & 0x1) << 22) | \
731 (((c) & 0x7) << 23)))
732
733/* To grandfather in prior block linear format modifiers to the above layout,
734 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
735 * with block-linear layouts, is remapped within drivers to the value 0xfe,
736 * which corresponds to the "generic" kind used for simple single-sample
737 * uncompressed color formats on Fermi - Volta GPUs.
738 */
739static inline __u64
740drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
741{
742 if (!(modifier & 0x10) || (modifier & (0xff << 12)))
743 return modifier;
744 else
745 return modifier | (0xfe << 12);
746}
747
748/*
749 * 16Bx2 Block Linear layout, used by Tegra K1 and later
750 *
751 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
752 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
753 *
754 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
755 *
756 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
757 * Valid values are:
758 *
759 * 0 == ONE_GOB
760 * 1 == TWO_GOBS
761 * 2 == FOUR_GOBS
762 * 3 == EIGHT_GOBS
763 * 4 == SIXTEEN_GOBS
764 * 5 == THIRTYTWO_GOBS
765 *
766 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
767 * in full detail.
768 */
769#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
770 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
771
772#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
773 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
774#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
775 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
776#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
777 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
778#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
779 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
780#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
781 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
782#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
783 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
784
785/*
786 * Some Broadcom modifiers take parameters, for example the number of
787 * vertical lines in the image. Reserve the lower 32 bits for modifier
788 * type, and the next 24 bits for parameters. Top 8 bits are the
789 * vendor code.
790 */
791#define __fourcc_mod_broadcom_param_shift 8
792#define __fourcc_mod_broadcom_param_bits 48
793#define fourcc_mod_broadcom_code(val, params) \
794 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
795#define fourcc_mod_broadcom_param(m) \
796 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
797 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
798#define fourcc_mod_broadcom_mod(m) \
799 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
800 __fourcc_mod_broadcom_param_shift))
801
802/*
803 * Broadcom VC4 "T" format
804 *
805 * This is the primary layout that the V3D GPU can texture from (it
806 * can't do linear). The T format has:
807 *
808 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
809 * pixels at 32 bit depth.
810 *
811 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
812 * 16x16 pixels).
813 *
814 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
815 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
816 * they're (TR, BR, BL, TL), where bottom left is start of memory.
817 *
818 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
819 * tiles) or right-to-left (odd rows of 4k tiles).
820 */
821#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
822
823/*
824 * Broadcom SAND format
825 *
826 * This is the native format that the H.264 codec block uses. For VC4
827 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
828 *
829 * The image can be considered to be split into columns, and the
830 * columns are placed consecutively into memory. The width of those
831 * columns can be either 32, 64, 128, or 256 pixels, but in practice
832 * only 128 pixel columns are used.
833 *
834 * The pitch between the start of each column is set to optimally
835 * switch between SDRAM banks. This is passed as the number of lines
836 * of column width in the modifier (we can't use the stride value due
837 * to various core checks that look at it , so you should set the
838 * stride to width*cpp).
839 *
840 * Note that the column height for this format modifier is the same
841 * for all of the planes, assuming that each column contains both Y
842 * and UV. Some SAND-using hardware stores UV in a separate tiled
843 * image from Y to reduce the column height, which is not supported
844 * with these modifiers.
845 */
846
847#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
848 fourcc_mod_broadcom_code(2, v)
849#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
850 fourcc_mod_broadcom_code(3, v)
851#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
852 fourcc_mod_broadcom_code(4, v)
853#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
854 fourcc_mod_broadcom_code(5, v)
855
856#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
857 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
858#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
859 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
860#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
861 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
862#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
863 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
864
865/* Broadcom UIF format
866 *
867 * This is the common format for the current Broadcom multimedia
868 * blocks, including V3D 3.x and newer, newer video codecs, and
869 * displays.
870 *
871 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
872 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
873 * stored in columns, with padding between the columns to ensure that
874 * moving from one column to the next doesn't hit the same SDRAM page
875 * bank.
876 *
877 * To calculate the padding, it is assumed that each hardware block
878 * and the software driving it knows the platform's SDRAM page size,
879 * number of banks, and XOR address, and that it's identical between
880 * all blocks using the format. This tiling modifier will use XOR as
881 * necessary to reduce the padding. If a hardware block can't do XOR,
882 * the assumption is that a no-XOR tiling modifier will be created.
883 */
884#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
885
886/*
887 * Arm Framebuffer Compression (AFBC) modifiers
888 *
889 * AFBC is a proprietary lossless image compression protocol and format.
890 * It provides fine-grained random access and minimizes the amount of data
891 * transferred between IP blocks.
892 *
893 * AFBC has several features which may be supported and/or used, which are
894 * represented using bits in the modifier. Not all combinations are valid,
895 * and different devices or use-cases may support different combinations.
896 *
897 * Further information on the use of AFBC modifiers can be found in
898 * Documentation/gpu/afbc.rst
899 */
900
901/*
902 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
903 * modifiers) denote the category for modifiers. Currently we have only two
904 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
905 * different categories.
906 */
907#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
908 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
909
910#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
911#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
912
913#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
914 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
915
916/*
917 * AFBC superblock size
918 *
919 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
920 * size (in pixels) must be aligned to a multiple of the superblock size.
921 * Four lowest significant bits(LSBs) are reserved for block size.
922 *
923 * Where one superblock size is specified, it applies to all planes of the
924 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
925 * the first applies to the Luma plane and the second applies to the Chroma
926 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
927 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
928 */
929#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
930#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
931#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
932#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
933#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
934
935/*
936 * AFBC lossless colorspace transform
937 *
938 * Indicates that the buffer makes use of the AFBC lossless colorspace
939 * transform.
940 */
941#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
942
943/*
944 * AFBC block-split
945 *
946 * Indicates that the payload of each superblock is split. The second
947 * half of the payload is positioned at a predefined offset from the start
948 * of the superblock payload.
949 */
950#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
951
952/*
953 * AFBC sparse layout
954 *
955 * This flag indicates that the payload of each superblock must be stored at a
956 * predefined position relative to the other superblocks in the same AFBC
957 * buffer. This order is the same order used by the header buffer. In this mode
958 * each superblock is given the same amount of space as an uncompressed
959 * superblock of the particular format would require, rounding up to the next
960 * multiple of 128 bytes in size.
961 */
962#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
963
964/*
965 * AFBC copy-block restrict
966 *
967 * Buffers with this flag must obey the copy-block restriction. The restriction
968 * is such that there are no copy-blocks referring across the border of 8x8
969 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
970 */
971#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
972
973/*
974 * AFBC tiled layout
975 *
976 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
977 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
978 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
979 * larger bpp formats. The order between the tiles is scan line.
980 * When the tiled layout is used, the buffer size (in pixels) must be aligned
981 * to the tile size.
982 */
983#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
984
985/*
986 * AFBC solid color blocks
987 *
988 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
989 * can be reduced if a whole superblock is a single color.
990 */
991#define AFBC_FORMAT_MOD_SC (1ULL << 9)
992
993/*
994 * AFBC double-buffer
995 *
996 * Indicates that the buffer is allocated in a layout safe for front-buffer
997 * rendering.
998 */
999#define AFBC_FORMAT_MOD_DB (1ULL << 10)
1000
1001/*
1002 * AFBC buffer content hints
1003 *
1004 * Indicates that the buffer includes per-superblock content hints.
1005 */
1006#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1007
1008/* AFBC uncompressed storage mode
1009 *
1010 * Indicates that the buffer is using AFBC uncompressed storage mode.
1011 * In this mode all superblock payloads in the buffer use the uncompressed
1012 * storage mode, which is usually only used for data which cannot be compressed.
1013 * The buffer layout is the same as for AFBC buffers without USM set, this only
1014 * affects the storage mode of the individual superblocks. Note that even a
1015 * buffer without USM set may use uncompressed storage mode for some or all
1016 * superblocks, USM just guarantees it for all.
1017 */
1018#define AFBC_FORMAT_MOD_USM (1ULL << 12)
1019
1020/*
1021 * Arm 16x16 Block U-Interleaved modifier
1022 *
1023 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1024 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1025 * in the block are reordered.
1026 */
1027#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1028 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1029
1030/*
1031 * Allwinner tiled modifier
1032 *
1033 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1034 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1035 * planes.
1036 *
1037 * With this tiling, the luminance samples are disposed in tiles representing
1038 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1039 * The pixel order in each tile is linear and the tiles are disposed linearly,
1040 * both in row-major order.
1041 */
1042#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1043
1044/*
1045 * Amlogic Video Framebuffer Compression modifiers
1046 *
1047 * Amlogic uses a proprietary lossless image compression protocol and format
1048 * for their hardware video codec accelerators, either video decoders or
1049 * video input encoders.
1050 *
1051 * It considerably reduces memory bandwidth while writing and reading
1052 * frames in memory.
1053 *
1054 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1055 * per component YCbCr 420, single plane :
1056 * - DRM_FORMAT_YUV420_8BIT
1057 * - DRM_FORMAT_YUV420_10BIT
1058 *
1059 * The first 8 bits of the mode defines the layout, then the following 8 bits
1060 * defines the options changing the layout.
1061 *
1062 * Not all combinations are valid, and different SoCs may support different
1063 * combinations of layout and options.
1064 */
1065#define __fourcc_mod_amlogic_layout_mask 0xff
1066#define __fourcc_mod_amlogic_options_shift 8
1067#define __fourcc_mod_amlogic_options_mask 0xff
1068
1069#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1070 fourcc_mod_code(AMLOGIC, \
1071 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1072 (((__options) & __fourcc_mod_amlogic_options_mask) \
1073 << __fourcc_mod_amlogic_options_shift))
1074
1075/* Amlogic FBC Layouts */
1076
1077/*
1078 * Amlogic FBC Basic Layout
1079 *
1080 * The basic layout is composed of:
1081 * - a body content organized in 64x32 superblocks with 4096 bytes per
1082 * superblock in default mode.
1083 * - a 32 bytes per 128x64 header block
1084 *
1085 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1086 */
1087#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1088
1089/*
1090 * Amlogic FBC Scatter Memory layout
1091 *
1092 * Indicates the header contains IOMMU references to the compressed
1093 * frames content to optimize memory access and layout.
1094 *
1095 * In this mode, only the header memory address is needed, thus the
1096 * content memory organization is tied to the current producer
1097 * execution and cannot be saved/dumped neither transferrable between
1098 * Amlogic SoCs supporting this modifier.
1099 *
1100 * Due to the nature of the layout, these buffers are not expected to
1101 * be accessible by the user-space clients, but only accessible by the
1102 * hardware producers and consumers.
1103 *
1104 * The user-space clients should expect a failure while trying to mmap
1105 * the DMA-BUF handle returned by the producer.
1106 */
1107#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1108
1109/* Amlogic FBC Layout Options Bit Mask */
1110
1111/*
1112 * Amlogic FBC Memory Saving mode
1113 *
1114 * Indicates the storage is packed when pixel size is multiple of word
1115 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1116 * memory.
1117 *
1118 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1119 * the basic layout and 3200 bytes per 64x32 superblock combined with
1120 * the scatter layout.
1121 */
1122#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1123
1124/*
1125 * AMD modifiers
1126 *
1127 * Memory layout:
1128 *
1129 * without DCC:
1130 * - main surface
1131 *
1132 * with DCC & without DCC_RETILE:
1133 * - main surface in plane 0
1134 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1135 *
1136 * with DCC & DCC_RETILE:
1137 * - main surface in plane 0
1138 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1139 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1140 *
1141 * For multi-plane formats the above surfaces get merged into one plane for
1142 * each format plane, based on the required alignment only.
1143 *
1144 * Bits Parameter Notes
1145 * ----- ------------------------ ---------------------------------------------
1146 *
1147 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
1148 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1149 * 13 DCC
1150 * 14 DCC_RETILE
1151 * 15 DCC_PIPE_ALIGN
1152 * 16 DCC_INDEPENDENT_64B
1153 * 17 DCC_INDEPENDENT_128B
1154 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1155 * 20 DCC_CONSTANT_ENCODE
1156 * 23:21 PIPE_XOR_BITS Only for some chips
1157 * 26:24 BANK_XOR_BITS Only for some chips
1158 * 29:27 PACKERS Only for some chips
1159 * 32:30 RB Only for some chips
1160 * 35:33 PIPE Only for some chips
1161 * 55:36 - Reserved for future use, must be zero
1162 */
1163#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1164
1165#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1166
1167/* Reserve 0 for GFX8 and older */
1168#define AMD_FMT_MOD_TILE_VER_GFX9 1
1169#define AMD_FMT_MOD_TILE_VER_GFX10 2
1170#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1171
1172/*
1173 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1174 * version.
1175 */
1176#define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1177
1178/*
1179 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1180 * GFX9 as canonical version.
1181 */
1182#define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1183#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1184#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1185#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1186
1187#define AMD_FMT_MOD_DCC_BLOCK_64B 0
1188#define AMD_FMT_MOD_DCC_BLOCK_128B 1
1189#define AMD_FMT_MOD_DCC_BLOCK_256B 2
1190
1191#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1192#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1193#define AMD_FMT_MOD_TILE_SHIFT 8
1194#define AMD_FMT_MOD_TILE_MASK 0x1F
1195
1196/* Whether DCC compression is enabled. */
1197#define AMD_FMT_MOD_DCC_SHIFT 13
1198#define AMD_FMT_MOD_DCC_MASK 0x1
1199
1200/*
1201 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1202 * one which is not-aligned.
1203 */
1204#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1205#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1206
1207/* Only set if DCC_RETILE = false */
1208#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1209#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1210
1211#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1212#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1213#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1214#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1215#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1216#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1217
1218/*
1219 * DCC supports embedding some clear colors directly in the DCC surface.
1220 * However, on older GPUs the rendering HW ignores the embedded clear color
1221 * and prefers the driver provided color. This necessitates doing a fastclear
1222 * eliminate operation before a process transfers control.
1223 *
1224 * If this bit is set that means the fastclear eliminate is not needed for these
1225 * embeddable colors.
1226 */
1227#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1228#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1229
1230/*
1231 * The below fields are for accounting for per GPU differences. These are only
1232 * relevant for GFX9 and later and if the tile field is *_X/_T.
1233 *
1234 * PIPE_XOR_BITS = always needed
1235 * BANK_XOR_BITS = only for TILE_VER_GFX9
1236 * PACKERS = only for TILE_VER_GFX10_RBPLUS
1237 * RB = only for TILE_VER_GFX9 & DCC
1238 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1239 */
1240#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1241#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1242#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1243#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1244#define AMD_FMT_MOD_PACKERS_SHIFT 27
1245#define AMD_FMT_MOD_PACKERS_MASK 0x7
1246#define AMD_FMT_MOD_RB_SHIFT 30
1247#define AMD_FMT_MOD_RB_MASK 0x7
1248#define AMD_FMT_MOD_PIPE_SHIFT 33
1249#define AMD_FMT_MOD_PIPE_MASK 0x7
1250
1251#define AMD_FMT_MOD_SET(field, value) \
1252 ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
1253#define AMD_FMT_MOD_GET(field, value) \
1254 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1255#define AMD_FMT_MOD_CLEAR(field) \
1256 (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1257
1258#if defined(__cplusplus)
1259}
1260#endif
1261
1262#endif /* DRM_FOURCC_H */