1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Core pinctrl/GPIO driver for Intel GPIO controllers
  4 *
  5 * Copyright (C) 2015, Intel Corporation
  6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
  7 *          Mika Westerberg <mika.westerberg@linux.intel.com>
  8 */
  9
 10#ifndef PINCTRL_INTEL_H
 11#define PINCTRL_INTEL_H
 12
 13#include <linux/bits.h>
 14#include <linux/compiler_types.h>
 15#include <linux/gpio/driver.h>
 16#include <linux/irq.h>
 17#include <linux/kernel.h>
 18#include <linux/pm.h>
 19#include <linux/pinctrl/pinctrl.h>
 20#include <linux/spinlock_types.h>
 21
 22struct platform_device;
 23struct device;
 24
 25/**
 26 * struct intel_pingroup - Description about group of pins
 27 * @name: Name of the groups
 28 * @pins: All pins in this group
 29 * @npins: Number of pins in this groups
 30 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
 31 *        is %NULL.
 32 * @modes: If not %NULL this will hold mode for each pin in @pins
 33 */
 34struct intel_pingroup {
 35	const char *name;
 36	const unsigned int *pins;
 37	size_t npins;
 38	unsigned short mode;
 39	const unsigned int *modes;
 40};
 41
 42/**
 43 * struct intel_function - Description about a function
 44 * @name: Name of the function
 45 * @groups: An array of groups for this function
 46 * @ngroups: Number of groups in @groups
 47 */
 48struct intel_function {
 49	const char *name;
 50	const char * const *groups;
 51	size_t ngroups;
 52};
 53
 54/**
 55 * struct intel_padgroup - Hardware pad group information
 56 * @reg_num: GPI_IS register number
 57 * @base: Starting pin of this group
 58 * @size: Size of this group (maximum is 32).
 59 * @gpio_base: Starting GPIO base of this group
 60 * @padown_num: PAD_OWN register number (assigned by the core driver)
 61 *
 62 * If pad groups of a community are not the same size, use this structure
 63 * to specify them.
 64 */
 65struct intel_padgroup {
 66	unsigned int reg_num;
 67	unsigned int base;
 68	unsigned int size;
 69	int gpio_base;
 70	unsigned int padown_num;
 71};
 72
 73/**
 74 * enum - Special treatment for GPIO base in pad group
 75 *
 76 * @INTEL_GPIO_BASE_ZERO:	force GPIO base to be 0
 77 * @INTEL_GPIO_BASE_NOMAP:	no GPIO mapping should be created
 78 * @INTEL_GPIO_BASE_MATCH:	matches with starting pin number
 79 */
 80enum {
 81	INTEL_GPIO_BASE_ZERO	= -2,
 82	INTEL_GPIO_BASE_NOMAP	= -1,
 83	INTEL_GPIO_BASE_MATCH	= 0,
 84};
 85
 86/**
 87 * struct intel_community - Intel pin community description
 88 * @barno: MMIO BAR number where registers for this community reside
 89 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
 90 *                 then there is no support for owner.
 91 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
 92 *                     locking is not supported.
 93 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
 94 *                  is assumed that the host owns the pin (rather than
 95 *                  ACPI).
 96 * @is_offset: Register offset of GPI_IS from @regs.
 97 * @ie_offset: Register offset of GPI_IE from @regs.
 98 * @features: Additional features supported by the hardware
 99 * @pin_base: Starting pin of pins in this community
100 * @npins: Number of pins in this community
101 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
102 *            HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
103 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
104 *			 minimum. Use %0 if the number of registers can be
105 *			 determined by the size of the group.
106 * @gpps: Pad groups if the controller has variable size pad groups
107 * @ngpps: Number of pad groups in this community
108 * @pad_map: Optional non-linear mapping of the pads
109 * @nirqs: Optional total number of IRQs this community can generate
110 * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
111 * @regs: Community specific common registers (reserved for core driver)
112 * @pad_regs: Community specific pad registers (reserved for core driver)
113 *
114 * In some of Intel GPIO host controllers this driver supports each pad group
115 * is of equal size (except the last one). In that case the driver can just
116 * fill in @gpp_size field and let the core driver to handle the rest. If
117 * the controller has pad groups of variable size the client driver can
118 * pass custom @gpps and @ngpps instead.
119 */
120struct intel_community {
121	unsigned int barno;
122	unsigned int padown_offset;
123	unsigned int padcfglock_offset;
124	unsigned int hostown_offset;
125	unsigned int is_offset;
126	unsigned int ie_offset;
127	unsigned int features;
128	unsigned int pin_base;
129	size_t npins;
130	unsigned int gpp_size;
131	unsigned int gpp_num_padown_regs;
132	const struct intel_padgroup *gpps;
133	size_t ngpps;
134	const unsigned int *pad_map;
135	unsigned short nirqs;
136	unsigned short acpi_space_id;
137
138	/* Reserved for the core driver */
139	void __iomem *regs;
140	void __iomem *pad_regs;
141};
142
143/* Additional features supported by the hardware */
144#define PINCTRL_FEATURE_DEBOUNCE	BIT(0)
145#define PINCTRL_FEATURE_1K_PD		BIT(1)
146#define PINCTRL_FEATURE_GPIO_HW_INFO	BIT(2)
147#define PINCTRL_FEATURE_PWM		BIT(3)
148#define PINCTRL_FEATURE_BLINK		BIT(4)
149#define PINCTRL_FEATURE_EXP		BIT(5)
150
151/**
152 * PIN_GROUP - Declare a pin group
153 * @n: Name of the group
154 * @p: An array of pins this group consists
155 * @m: Mode which the pins are put when this group is active. Can be either
156 *     a single integer or an array of integers in which case mode is per
157 *     pin.
158 */
159#define PIN_GROUP(n, p, m)					\
160	{							\
161		.name = (n),					\
162		.pins = (p),					\
163		.npins = ARRAY_SIZE((p)),			\
164		.mode = __builtin_choose_expr(			\
165			__builtin_constant_p((m)), (m), 0),	\
166		.modes = __builtin_choose_expr(			\
167			__builtin_constant_p((m)), NULL, (m)),	\
168	}
169
170#define FUNCTION(n, g)				\
171	{					\
172		.name = (n),			\
173		.groups = (g),			\
174		.ngroups = ARRAY_SIZE((g)),	\
175	}
176
177/**
178 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
179 * @uid: ACPI _UID for the probe driver use if needed
180 * @pins: Array if pins this pinctrl controls
181 * @npins: Number of pins in the array
182 * @groups: Array of pin groups
183 * @ngroups: Number of groups in the array
184 * @functions: Array of functions
185 * @nfunctions: Number of functions in the array
186 * @communities: Array of communities this pinctrl handles
187 * @ncommunities: Number of communities in the array
188 *
189 * The @communities is used as a template by the core driver. It will make
190 * copy of all communities and fill in rest of the information.
191 */
192struct intel_pinctrl_soc_data {
193	const char *uid;
194	const struct pinctrl_pin_desc *pins;
195	size_t npins;
196	const struct intel_pingroup *groups;
197	size_t ngroups;
198	const struct intel_function *functions;
199	size_t nfunctions;
200	const struct intel_community *communities;
201	size_t ncommunities;
202};
203
204const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
205
206struct intel_pad_context;
207struct intel_community_context;
208
209/**
210 * struct intel_pinctrl_context - context to be saved during suspend-resume
211 * @pads: Opaque context per pad (driver dependent)
212 * @communities: Opaque context per community (driver dependent)
213 */
214struct intel_pinctrl_context {
215	struct intel_pad_context *pads;
216	struct intel_community_context *communities;
217};
218
219/**
220 * struct intel_pinctrl - Intel pinctrl private structure
221 * @dev: Pointer to the device structure
222 * @lock: Lock to serialize register access
223 * @pctldesc: Pin controller description
224 * @pctldev: Pointer to the pin controller device
225 * @chip: GPIO chip in this pin controller
226 * @irqchip: IRQ chip in this pin controller
227 * @soc: SoC/PCH specific pin configuration data
228 * @communities: All communities in this pin controller
229 * @ncommunities: Number of communities in this pin controller
230 * @context: Configuration saved over system sleep
231 * @irq: pinctrl/GPIO chip irq number
232 */
233struct intel_pinctrl {
234	struct device *dev;
235	raw_spinlock_t lock;
236	struct pinctrl_desc pctldesc;
237	struct pinctrl_dev *pctldev;
238	struct gpio_chip chip;
239	struct irq_chip irqchip;
240	const struct intel_pinctrl_soc_data *soc;
241	struct intel_community *communities;
242	size_t ncommunities;
243	struct intel_pinctrl_context context;
244	int irq;
245};
246
247int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
248int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
249
250#ifdef CONFIG_PM_SLEEP
251int intel_pinctrl_suspend_noirq(struct device *dev);
252int intel_pinctrl_resume_noirq(struct device *dev);
253#endif
254
255#define INTEL_PINCTRL_PM_OPS(_name)					\
256const struct dev_pm_ops _name = {					\
257	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq,	\
258				      intel_pinctrl_resume_noirq)	\
259}
260
261#endif /* PINCTRL_INTEL_H */