1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2015 - 2016 Cavium, Inc.
  4 */
  5
  6#include <linux/bitfield.h>
  7#include <linux/kernel.h>
  8#include <linux/init.h>
  9#include <linux/pci.h>
 10#include <linux/of_address.h>
 11#include <linux/of_pci.h>
 12#include <linux/pci-acpi.h>
 13#include <linux/pci-ecam.h>
 14#include <linux/platform_device.h>
 15#include <linux/io-64-nonatomic-lo-hi.h>
 16#include "../pci.h"
 17
 18#if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
 19
 20#define PEM_CFG_WR 0x28
 21#define PEM_CFG_RD 0x30
 22
 23/*
 24 * Enhanced Configuration Access Mechanism (ECAM)
 25 *
 26 * N.B. This is a non-standard platform-specific ECAM bus shift value.  For
 27 * standard values defined in the PCI Express Base Specification see
 28 * include/linux/pci-ecam.h.
 29 */
 30#define THUNDER_PCIE_ECAM_BUS_SHIFT	24
 31
 32struct thunder_pem_pci {
 33	u32		ea_entry[3];
 34	void __iomem	*pem_reg_base;
 35};
 36
 37static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
 38				   int where, int size, u32 *val)
 39{
 40	u64 read_val, tmp_val;
 41	struct pci_config_window *cfg = bus->sysdata;
 42	struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
 43
 44	if (devfn != 0 || where >= 2048) {
 45		*val = ~0;
 46		return PCIBIOS_DEVICE_NOT_FOUND;
 47	}
 48
 49	/*
 50	 * 32-bit accesses only.  Write the address to the low order
 51	 * bits of PEM_CFG_RD, then trigger the read by reading back.
 52	 * The config data lands in the upper 32-bits of PEM_CFG_RD.
 53	 */
 54	read_val = where & ~3ull;
 55	writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
 56	read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
 57	read_val >>= 32;
 58
 59	/*
 60	 * The config space contains some garbage, fix it up.  Also
 61	 * synthesize an EA capability for the BAR used by MSI-X.
 62	 */
 63	switch (where & ~3) {
 64	case 0x40:
 65		read_val &= 0xffff00ff;
 66		read_val |= 0x00007000; /* Skip MSI CAP */
 67		break;
 68	case 0x70: /* Express Cap */
 69		/*
 70		 * Change PME interrupt to vector 2 on T88 where it
 71		 * reads as 0, else leave it alone.
 72		 */
 73		if (!(read_val & (0x1f << 25)))
 74			read_val |= (2u << 25);
 75		break;
 76	case 0xb0: /* MSI-X Cap */
 77		/* TableSize=2 or 4, Next Cap is EA */
 78		read_val &= 0xc00000ff;
 79		/*
 80		 * If Express Cap(0x70) raw PME vector reads as 0 we are on
 81		 * T88 and TableSize is reported as 4, else TableSize
 82		 * is 2.
 83		 */
 84		writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
 85		tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
 86		tmp_val >>= 32;
 87		if (!(tmp_val & (0x1f << 25)))
 88			read_val |= 0x0003bc00;
 89		else
 90			read_val |= 0x0001bc00;
 91		break;
 92	case 0xb4:
 93		/* Table offset=0, BIR=0 */
 94		read_val = 0x00000000;
 95		break;
 96	case 0xb8:
 97		/* BPA offset=0xf0000, BIR=0 */
 98		read_val = 0x000f0000;
 99		break;
100	case 0xbc:
101		/* EA, 1 entry, no next Cap */
102		read_val = 0x00010014;
103		break;
104	case 0xc0:
105		/* DW2 for type-1 */
106		read_val = 0x00000000;
107		break;
108	case 0xc4:
109		/* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
110		read_val = 0x80ff0003;
111		break;
112	case 0xc8:
113		read_val = pem_pci->ea_entry[0];
114		break;
115	case 0xcc:
116		read_val = pem_pci->ea_entry[1];
117		break;
118	case 0xd0:
119		read_val = pem_pci->ea_entry[2];
120		break;
121	default:
122		break;
123	}
124	read_val >>= (8 * (where & 3));
125	switch (size) {
126	case 1:
127		read_val &= 0xff;
128		break;
129	case 2:
130		read_val &= 0xffff;
131		break;
132	default:
133		break;
134	}
135	*val = read_val;
136	return PCIBIOS_SUCCESSFUL;
137}
138
139static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
140				   int where, int size, u32 *val)
141{
142	struct pci_config_window *cfg = bus->sysdata;
143
144	if (bus->number < cfg->busr.start ||
145	    bus->number > cfg->busr.end)
146		return PCIBIOS_DEVICE_NOT_FOUND;
147
148	/*
149	 * The first device on the bus is the PEM PCIe bridge.
150	 * Special case its config access.
151	 */
152	if (bus->number == cfg->busr.start)
153		return thunder_pem_bridge_read(bus, devfn, where, size, val);
154
155	return pci_generic_config_read(bus, devfn, where, size, val);
156}
157
158/*
159 * Some of the w1c_bits below also include read-only or non-writable
160 * reserved bits, this makes the code simpler and is OK as the bits
161 * are not affected by writing zeros to them.
162 */
163static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
164{
165	u32 w1c_bits = 0;
166
167	switch (where_aligned) {
168	case 0x04: /* Command/Status */
169	case 0x1c: /* Base and I/O Limit/Secondary Status */
170		w1c_bits = 0xff000000;
171		break;
172	case 0x44: /* Power Management Control and Status */
173		w1c_bits = 0xfffffe00;
174		break;
175	case 0x78: /* Device Control/Device Status */
176	case 0x80: /* Link Control/Link Status */
177	case 0x88: /* Slot Control/Slot Status */
178	case 0x90: /* Root Status */
179	case 0xa0: /* Link Control 2 Registers/Link Status 2 */
180		w1c_bits = 0xffff0000;
181		break;
182	case 0x104: /* Uncorrectable Error Status */
183	case 0x110: /* Correctable Error Status */
184	case 0x130: /* Error Status */
185	case 0x160: /* Link Control 4 */
186		w1c_bits = 0xffffffff;
187		break;
188	default:
189		break;
190	}
191	return w1c_bits;
192}
193
194/* Some bits must be written to one so they appear to be read-only. */
195static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
196{
197	u32 w1_bits;
198
199	switch (where_aligned) {
200	case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
201		/* Force 32-bit I/O addressing. */
202		w1_bits = 0x0101;
203		break;
204	case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
205		/* Force 64-bit addressing */
206		w1_bits = 0x00010001;
207		break;
208	default:
209		w1_bits = 0;
210		break;
211	}
212	return w1_bits;
213}
214
215static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
216				    int where, int size, u32 val)
217{
218	struct pci_config_window *cfg = bus->sysdata;
219	struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
220	u64 write_val, read_val;
221	u64 where_aligned = where & ~3ull;
222	u32 mask = 0;
223
224
225	if (devfn != 0 || where >= 2048)
226		return PCIBIOS_DEVICE_NOT_FOUND;
227
228	/*
229	 * 32-bit accesses only.  If the write is for a size smaller
230	 * than 32-bits, we must first read the 32-bit value and merge
231	 * in the desired bits and then write the whole 32-bits back
232	 * out.
233	 */
234	switch (size) {
235	case 1:
236		writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
237		read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
238		read_val >>= 32;
239		mask = ~(0xff << (8 * (where & 3)));
240		read_val &= mask;
241		val = (val & 0xff) << (8 * (where & 3));
242		val |= (u32)read_val;
243		break;
244	case 2:
245		writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
246		read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
247		read_val >>= 32;
248		mask = ~(0xffff << (8 * (where & 3)));
249		read_val &= mask;
250		val = (val & 0xffff) << (8 * (where & 3));
251		val |= (u32)read_val;
252		break;
253	default:
254		break;
255	}
256
257	/*
258	 * By expanding the write width to 32 bits, we may
259	 * inadvertently hit some W1C bits that were not intended to
260	 * be written.  Calculate the mask that must be applied to the
261	 * data to be written to avoid these cases.
262	 */
263	if (mask) {
264		u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
265
266		if (w1c_bits) {
267			mask &= w1c_bits;
268			val &= ~mask;
269		}
270	}
271
272	/*
273	 * Some bits must be read-only with value of one.  Since the
274	 * access method allows these to be cleared if a zero is
275	 * written, force them to one before writing.
276	 */
277	val |= thunder_pem_bridge_w1_bits(where_aligned);
278
279	/*
280	 * Low order bits are the config address, the high order 32
281	 * bits are the data to be written.
282	 */
283	write_val = (((u64)val) << 32) | where_aligned;
284	writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
285	return PCIBIOS_SUCCESSFUL;
286}
287
288static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
289				    int where, int size, u32 val)
290{
291	struct pci_config_window *cfg = bus->sysdata;
292
293	if (bus->number < cfg->busr.start ||
294	    bus->number > cfg->busr.end)
295		return PCIBIOS_DEVICE_NOT_FOUND;
296	/*
297	 * The first device on the bus is the PEM PCIe bridge.
298	 * Special case its config access.
299	 */
300	if (bus->number == cfg->busr.start)
301		return thunder_pem_bridge_write(bus, devfn, where, size, val);
302
303
304	return pci_generic_config_write(bus, devfn, where, size, val);
305}
306
307static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
308			    struct resource *res_pem)
309{
310	struct thunder_pem_pci *pem_pci;
311	resource_size_t bar4_start;
312
313	pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
314	if (!pem_pci)
315		return -ENOMEM;
316
317	pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
318	if (!pem_pci->pem_reg_base)
319		return -ENOMEM;
320
321	/*
322	 * The MSI-X BAR for the PEM and AER interrupts is located at
323	 * a fixed offset from the PEM register base.  Generate a
324	 * fragment of the synthesized Enhanced Allocation capability
325	 * structure here for the BAR.
326	 */
327	bar4_start = res_pem->start + 0xf00000;
328	pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
329	pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
330	pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
331
332	cfg->priv = pem_pci;
333	return 0;
334}
335
336#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
337
338#define PEM_RES_BASE		0x87e0c0000000ULL
339#define PEM_NODE_MASK		GENMASK_ULL(45, 44)
340#define PEM_INDX_MASK		GENMASK_ULL(26, 24)
341#define PEM_MIN_DOM_IN_NODE	4
342#define PEM_MAX_DOM_IN_NODE	10
343
344static void thunder_pem_reserve_range(struct device *dev, int seg,
345				      struct resource *r)
346{
347	resource_size_t start = r->start, end = r->end;
348	struct resource *res;
349	const char *regionid;
350
351	regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
352	if (!regionid)
353		return;
354
355	res = request_mem_region(start, end - start + 1, regionid);
356	if (res)
357		res->flags &= ~IORESOURCE_BUSY;
358	else
359		kfree(regionid);
360
361	dev_info(dev, "%pR %s reserved\n", r,
362		 res ? "has been" : "could not be");
363}
364
365static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
366				 struct resource *res_pem)
367{
368	int node = acpi_get_node(root->device->handle);
369	int index;
370
371	if (node == NUMA_NO_NODE)
372		node = 0;
373
374	index = root->segment - PEM_MIN_DOM_IN_NODE;
375	index -= node * PEM_MAX_DOM_IN_NODE;
376	res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
377					FIELD_PREP(PEM_INDX_MASK, index);
378	res_pem->flags = IORESOURCE_MEM;
379}
380
381static int thunder_pem_acpi_init(struct pci_config_window *cfg)
382{
383	struct device *dev = cfg->parent;
384	struct acpi_device *adev = to_acpi_device(dev);
385	struct acpi_pci_root *root = acpi_driver_data(adev);
386	struct resource *res_pem;
387	int ret;
388
389	res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
390	if (!res_pem)
391		return -ENOMEM;
392
393	ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
394
395	/*
396	 * If we fail to gather resources it means that we run with old
397	 * FW where we need to calculate PEM-specific resources manually.
398	 */
399	if (ret) {
400		thunder_pem_legacy_fw(root, res_pem);
401		/*
402		 * Reserve 64K size PEM specific resources. The full 16M range
403		 * size is required for thunder_pem_init() call.
404		 */
405		res_pem->end = res_pem->start + SZ_64K - 1;
406		thunder_pem_reserve_range(dev, root->segment, res_pem);
407		res_pem->end = res_pem->start + SZ_16M - 1;
408
409		/* Reserve PCI configuration space as well. */
410		thunder_pem_reserve_range(dev, root->segment, &cfg->res);
411	}
412
413	return thunder_pem_init(dev, cfg, res_pem);
414}
415
416const struct pci_ecam_ops thunder_pem_ecam_ops = {
417	.bus_shift	= THUNDER_PCIE_ECAM_BUS_SHIFT,
418	.init		= thunder_pem_acpi_init,
419	.pci_ops	= {
420		.map_bus	= pci_ecam_map_bus,
421		.read		= thunder_pem_config_read,
422		.write		= thunder_pem_config_write,
423	}
424};
425
426#endif
427
428#ifdef CONFIG_PCI_HOST_THUNDER_PEM
429
430static int thunder_pem_platform_init(struct pci_config_window *cfg)
431{
432	struct device *dev = cfg->parent;
433	struct platform_device *pdev = to_platform_device(dev);
434	struct resource *res_pem;
435
436	if (!dev->of_node)
437		return -EINVAL;
438
439	/*
440	 * The second register range is the PEM bridge to the PCIe
441	 * bus.  It has a different config access method than those
442	 * devices behind the bridge.
443	 */
444	res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
445	if (!res_pem) {
446		dev_err(dev, "missing \"reg[1]\"property\n");
447		return -EINVAL;
448	}
449
450	return thunder_pem_init(dev, cfg, res_pem);
451}
452
453static const struct pci_ecam_ops pci_thunder_pem_ops = {
454	.bus_shift	= THUNDER_PCIE_ECAM_BUS_SHIFT,
455	.init		= thunder_pem_platform_init,
456	.pci_ops	= {
457		.map_bus	= pci_ecam_map_bus,
458		.read		= thunder_pem_config_read,
459		.write		= thunder_pem_config_write,
460	}
461};
462
463static const struct of_device_id thunder_pem_of_match[] = {
464	{
465		.compatible = "cavium,pci-host-thunder-pem",
466		.data = &pci_thunder_pem_ops,
467	},
468	{ },
469};
470
471static struct platform_driver thunder_pem_driver = {
472	.driver = {
473		.name = KBUILD_MODNAME,
474		.of_match_table = thunder_pem_of_match,
475		.suppress_bind_attrs = true,
476	},
477	.probe = pci_host_common_probe,
478};
479builtin_platform_driver(thunder_pem_driver);
480
481#endif
482#endif