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1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/sched.h>
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
52#define DRV_NAME "iwl4965"
53
54#include "iwl-eeprom.h"
55#include "iwl-dev.h"
56#include "iwl-core.h"
57#include "iwl-io.h"
58#include "iwl-helpers.h"
59#include "iwl-sta.h"
60#include "iwl-4965-calib.h"
61#include "iwl-4965.h"
62#include "iwl-4965-led.h"
63
64
65/******************************************************************************
66 *
67 * module boiler plate
68 *
69 ******************************************************************************/
70
71/*
72 * module name, copyright, version, etc.
73 */
74#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
75
76#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
77#define VD "d"
78#else
79#define VD
80#endif
81
82#define DRV_VERSION IWLWIFI_VERSION VD
83
84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
88MODULE_LICENSE("GPL");
89MODULE_ALIAS("iwl4965");
90
91void iwl4965_update_chain_flags(struct iwl_priv *priv)
92{
93 struct iwl_rxon_context *ctx;
94
95 if (priv->cfg->ops->hcmd->set_rxon_chain) {
96 for_each_context(priv, ctx) {
97 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
98 if (ctx->active.rx_chain != ctx->staging.rx_chain)
99 iwl_legacy_commit_rxon(priv, ctx);
100 }
101 }
102}
103
104static void iwl4965_clear_free_frames(struct iwl_priv *priv)
105{
106 struct list_head *element;
107
108 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
109 priv->frames_count);
110
111 while (!list_empty(&priv->free_frames)) {
112 element = priv->free_frames.next;
113 list_del(element);
114 kfree(list_entry(element, struct iwl_frame, list));
115 priv->frames_count--;
116 }
117
118 if (priv->frames_count) {
119 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
120 priv->frames_count);
121 priv->frames_count = 0;
122 }
123}
124
125static struct iwl_frame *iwl4965_get_free_frame(struct iwl_priv *priv)
126{
127 struct iwl_frame *frame;
128 struct list_head *element;
129 if (list_empty(&priv->free_frames)) {
130 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
131 if (!frame) {
132 IWL_ERR(priv, "Could not allocate frame!\n");
133 return NULL;
134 }
135
136 priv->frames_count++;
137 return frame;
138 }
139
140 element = priv->free_frames.next;
141 list_del(element);
142 return list_entry(element, struct iwl_frame, list);
143}
144
145static void iwl4965_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
146{
147 memset(frame, 0, sizeof(*frame));
148 list_add(&frame->list, &priv->free_frames);
149}
150
151static u32 iwl4965_fill_beacon_frame(struct iwl_priv *priv,
152 struct ieee80211_hdr *hdr,
153 int left)
154{
155 lockdep_assert_held(&priv->mutex);
156
157 if (!priv->beacon_skb)
158 return 0;
159
160 if (priv->beacon_skb->len > left)
161 return 0;
162
163 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
164
165 return priv->beacon_skb->len;
166}
167
168/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
169static void iwl4965_set_beacon_tim(struct iwl_priv *priv,
170 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
171 u8 *beacon, u32 frame_size)
172{
173 u16 tim_idx;
174 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
175
176 /*
177 * The index is relative to frame start but we start looking at the
178 * variable-length part of the beacon.
179 */
180 tim_idx = mgmt->u.beacon.variable - beacon;
181
182 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
183 while ((tim_idx < (frame_size - 2)) &&
184 (beacon[tim_idx] != WLAN_EID_TIM))
185 tim_idx += beacon[tim_idx+1] + 2;
186
187 /* If TIM field was found, set variables */
188 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
189 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
190 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
191 } else
192 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
193}
194
195static unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
196 struct iwl_frame *frame)
197{
198 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
199 u32 frame_size;
200 u32 rate_flags;
201 u32 rate;
202 /*
203 * We have to set up the TX command, the TX Beacon command, and the
204 * beacon contents.
205 */
206
207 lockdep_assert_held(&priv->mutex);
208
209 if (!priv->beacon_ctx) {
210 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
211 return 0;
212 }
213
214 /* Initialize memory */
215 tx_beacon_cmd = &frame->u.beacon;
216 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
217
218 /* Set up TX beacon contents */
219 frame_size = iwl4965_fill_beacon_frame(priv, tx_beacon_cmd->frame,
220 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
221 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
222 return 0;
223 if (!frame_size)
224 return 0;
225
226 /* Set up TX command fields */
227 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
228 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
229 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
230 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
231 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
232
233 /* Set up TX beacon command fields */
234 iwl4965_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
235 frame_size);
236
237 /* Set up packet rate and flags */
238 rate = iwl_legacy_get_lowest_plcp(priv, priv->beacon_ctx);
239 priv->mgmt_tx_ant = iwl4965_toggle_tx_ant(priv, priv->mgmt_tx_ant,
240 priv->hw_params.valid_tx_ant);
241 rate_flags = iwl4965_ant_idx_to_flags(priv->mgmt_tx_ant);
242 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
243 rate_flags |= RATE_MCS_CCK_MSK;
244 tx_beacon_cmd->tx.rate_n_flags = iwl4965_hw_set_rate_n_flags(rate,
245 rate_flags);
246
247 return sizeof(*tx_beacon_cmd) + frame_size;
248}
249
250int iwl4965_send_beacon_cmd(struct iwl_priv *priv)
251{
252 struct iwl_frame *frame;
253 unsigned int frame_size;
254 int rc;
255
256 frame = iwl4965_get_free_frame(priv);
257 if (!frame) {
258 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
259 "command.\n");
260 return -ENOMEM;
261 }
262
263 frame_size = iwl4965_hw_get_beacon_cmd(priv, frame);
264 if (!frame_size) {
265 IWL_ERR(priv, "Error configuring the beacon command\n");
266 iwl4965_free_frame(priv, frame);
267 return -EINVAL;
268 }
269
270 rc = iwl_legacy_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
271 &frame->u.cmd[0]);
272
273 iwl4965_free_frame(priv, frame);
274
275 return rc;
276}
277
278static inline dma_addr_t iwl4965_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
279{
280 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
281
282 dma_addr_t addr = get_unaligned_le32(&tb->lo);
283 if (sizeof(dma_addr_t) > sizeof(u32))
284 addr |=
285 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
286
287 return addr;
288}
289
290static inline u16 iwl4965_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
291{
292 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
293
294 return le16_to_cpu(tb->hi_n_len) >> 4;
295}
296
297static inline void iwl4965_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
298 dma_addr_t addr, u16 len)
299{
300 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
301 u16 hi_n_len = len << 4;
302
303 put_unaligned_le32(addr, &tb->lo);
304 if (sizeof(dma_addr_t) > sizeof(u32))
305 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
306
307 tb->hi_n_len = cpu_to_le16(hi_n_len);
308
309 tfd->num_tbs = idx + 1;
310}
311
312static inline u8 iwl4965_tfd_get_num_tbs(struct iwl_tfd *tfd)
313{
314 return tfd->num_tbs & 0x1f;
315}
316
317/**
318 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
319 * @priv - driver private data
320 * @txq - tx queue
321 *
322 * Does NOT advance any TFD circular buffer read/write indexes
323 * Does NOT free the TFD itself (which is within circular buffer)
324 */
325void iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
326{
327 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
328 struct iwl_tfd *tfd;
329 struct pci_dev *dev = priv->pci_dev;
330 int index = txq->q.read_ptr;
331 int i;
332 int num_tbs;
333
334 tfd = &tfd_tmp[index];
335
336 /* Sanity check on number of chunks */
337 num_tbs = iwl4965_tfd_get_num_tbs(tfd);
338
339 if (num_tbs >= IWL_NUM_OF_TBS) {
340 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
341 /* @todo issue fatal error, it is quite serious situation */
342 return;
343 }
344
345 /* Unmap tx_cmd */
346 if (num_tbs)
347 pci_unmap_single(dev,
348 dma_unmap_addr(&txq->meta[index], mapping),
349 dma_unmap_len(&txq->meta[index], len),
350 PCI_DMA_BIDIRECTIONAL);
351
352 /* Unmap chunks, if any. */
353 for (i = 1; i < num_tbs; i++)
354 pci_unmap_single(dev, iwl4965_tfd_tb_get_addr(tfd, i),
355 iwl4965_tfd_tb_get_len(tfd, i),
356 PCI_DMA_TODEVICE);
357
358 /* free SKB */
359 if (txq->txb) {
360 struct sk_buff *skb;
361
362 skb = txq->txb[txq->q.read_ptr].skb;
363
364 /* can be called from irqs-disabled context */
365 if (skb) {
366 dev_kfree_skb_any(skb);
367 txq->txb[txq->q.read_ptr].skb = NULL;
368 }
369 }
370}
371
372int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
373 struct iwl_tx_queue *txq,
374 dma_addr_t addr, u16 len,
375 u8 reset, u8 pad)
376{
377 struct iwl_queue *q;
378 struct iwl_tfd *tfd, *tfd_tmp;
379 u32 num_tbs;
380
381 q = &txq->q;
382 tfd_tmp = (struct iwl_tfd *)txq->tfds;
383 tfd = &tfd_tmp[q->write_ptr];
384
385 if (reset)
386 memset(tfd, 0, sizeof(*tfd));
387
388 num_tbs = iwl4965_tfd_get_num_tbs(tfd);
389
390 /* Each TFD can point to a maximum 20 Tx buffers */
391 if (num_tbs >= IWL_NUM_OF_TBS) {
392 IWL_ERR(priv, "Error can not send more than %d chunks\n",
393 IWL_NUM_OF_TBS);
394 return -EINVAL;
395 }
396
397 BUG_ON(addr & ~DMA_BIT_MASK(36));
398 if (unlikely(addr & ~IWL_TX_DMA_MASK))
399 IWL_ERR(priv, "Unaligned address = %llx\n",
400 (unsigned long long)addr);
401
402 iwl4965_tfd_set_tb(tfd, num_tbs, addr, len);
403
404 return 0;
405}
406
407/*
408 * Tell nic where to find circular buffer of Tx Frame Descriptors for
409 * given Tx queue, and enable the DMA channel used for that queue.
410 *
411 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
412 * channels supported in hardware.
413 */
414int iwl4965_hw_tx_queue_init(struct iwl_priv *priv,
415 struct iwl_tx_queue *txq)
416{
417 int txq_id = txq->q.id;
418
419 /* Circular buffer (TFD queue in DRAM) physical base address */
420 iwl_legacy_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
421 txq->q.dma_addr >> 8);
422
423 return 0;
424}
425
426/******************************************************************************
427 *
428 * Generic RX handler implementations
429 *
430 ******************************************************************************/
431static void iwl4965_rx_reply_alive(struct iwl_priv *priv,
432 struct iwl_rx_mem_buffer *rxb)
433{
434 struct iwl_rx_packet *pkt = rxb_addr(rxb);
435 struct iwl_alive_resp *palive;
436 struct delayed_work *pwork;
437
438 palive = &pkt->u.alive_frame;
439
440 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
441 "0x%01X 0x%01X\n",
442 palive->is_valid, palive->ver_type,
443 palive->ver_subtype);
444
445 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
446 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
447 memcpy(&priv->card_alive_init,
448 &pkt->u.alive_frame,
449 sizeof(struct iwl_init_alive_resp));
450 pwork = &priv->init_alive_start;
451 } else {
452 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
453 memcpy(&priv->card_alive, &pkt->u.alive_frame,
454 sizeof(struct iwl_alive_resp));
455 pwork = &priv->alive_start;
456 }
457
458 /* We delay the ALIVE response by 5ms to
459 * give the HW RF Kill time to activate... */
460 if (palive->is_valid == UCODE_VALID_OK)
461 queue_delayed_work(priv->workqueue, pwork,
462 msecs_to_jiffies(5));
463 else
464 IWL_WARN(priv, "uCode did not respond OK.\n");
465}
466
467/**
468 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
469 *
470 * This callback is provided in order to send a statistics request.
471 *
472 * This timer function is continually reset to execute within
473 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
474 * was received. We need to ensure we receive the statistics in order
475 * to update the temperature used for calibrating the TXPOWER.
476 */
477static void iwl4965_bg_statistics_periodic(unsigned long data)
478{
479 struct iwl_priv *priv = (struct iwl_priv *)data;
480
481 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
482 return;
483
484 /* dont send host command if rf-kill is on */
485 if (!iwl_legacy_is_ready_rf(priv))
486 return;
487
488 iwl_legacy_send_statistics_request(priv, CMD_ASYNC, false);
489}
490
491static void iwl4965_rx_beacon_notif(struct iwl_priv *priv,
492 struct iwl_rx_mem_buffer *rxb)
493{
494 struct iwl_rx_packet *pkt = rxb_addr(rxb);
495 struct iwl4965_beacon_notif *beacon =
496 (struct iwl4965_beacon_notif *)pkt->u.raw;
497#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
498 u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
499
500 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
501 "tsf %d %d rate %d\n",
502 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
503 beacon->beacon_notify_hdr.failure_frame,
504 le32_to_cpu(beacon->ibss_mgr_status),
505 le32_to_cpu(beacon->high_tsf),
506 le32_to_cpu(beacon->low_tsf), rate);
507#endif
508
509 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
510}
511
512static void iwl4965_perform_ct_kill_task(struct iwl_priv *priv)
513{
514 unsigned long flags;
515
516 IWL_DEBUG_POWER(priv, "Stop all queues\n");
517
518 if (priv->mac80211_registered)
519 ieee80211_stop_queues(priv->hw);
520
521 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
522 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
523 iwl_read32(priv, CSR_UCODE_DRV_GP1);
524
525 spin_lock_irqsave(&priv->reg_lock, flags);
526 if (!iwl_grab_nic_access(priv))
527 iwl_release_nic_access(priv);
528 spin_unlock_irqrestore(&priv->reg_lock, flags);
529}
530
531/* Handle notification from uCode that card's power state is changing
532 * due to software, hardware, or critical temperature RFKILL */
533static void iwl4965_rx_card_state_notif(struct iwl_priv *priv,
534 struct iwl_rx_mem_buffer *rxb)
535{
536 struct iwl_rx_packet *pkt = rxb_addr(rxb);
537 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
538 unsigned long status = priv->status;
539
540 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
541 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
542 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
543 (flags & CT_CARD_DISABLED) ?
544 "Reached" : "Not reached");
545
546 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
547 CT_CARD_DISABLED)) {
548
549 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
550 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
551
552 iwl_legacy_write_direct32(priv, HBUS_TARG_MBX_C,
553 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
554
555 if (!(flags & RXON_CARD_DISABLED)) {
556 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
557 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
558 iwl_legacy_write_direct32(priv, HBUS_TARG_MBX_C,
559 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
560 }
561 }
562
563 if (flags & CT_CARD_DISABLED)
564 iwl4965_perform_ct_kill_task(priv);
565
566 if (flags & HW_CARD_DISABLED)
567 set_bit(STATUS_RF_KILL_HW, &priv->status);
568 else
569 clear_bit(STATUS_RF_KILL_HW, &priv->status);
570
571 if (!(flags & RXON_CARD_DISABLED))
572 iwl_legacy_scan_cancel(priv);
573
574 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
575 test_bit(STATUS_RF_KILL_HW, &priv->status)))
576 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
577 test_bit(STATUS_RF_KILL_HW, &priv->status));
578 else
579 wake_up(&priv->wait_command_queue);
580}
581
582/**
583 * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks
584 *
585 * Setup the RX handlers for each of the reply types sent from the uCode
586 * to the host.
587 *
588 * This function chains into the hardware specific files for them to setup
589 * any hardware specific handlers as well.
590 */
591static void iwl4965_setup_rx_handlers(struct iwl_priv *priv)
592{
593 priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive;
594 priv->rx_handlers[REPLY_ERROR] = iwl_legacy_rx_reply_error;
595 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_legacy_rx_csa;
596 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
597 iwl_legacy_rx_spectrum_measure_notif;
598 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_legacy_rx_pm_sleep_notif;
599 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
600 iwl_legacy_rx_pm_debug_statistics_notif;
601 priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif;
602
603 /*
604 * The same handler is used for both the REPLY to a discrete
605 * statistics request from the host as well as for the periodic
606 * statistics notifications (after received beacons) from the uCode.
607 */
608 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_reply_statistics;
609 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_rx_statistics;
610
611 iwl_legacy_setup_rx_scan_handlers(priv);
612
613 /* status change handler */
614 priv->rx_handlers[CARD_STATE_NOTIFICATION] =
615 iwl4965_rx_card_state_notif;
616
617 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
618 iwl4965_rx_missed_beacon_notif;
619 /* Rx handlers */
620 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
621 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
622 /* block ack */
623 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
624 /* Set up hardware specific Rx handlers */
625 priv->cfg->ops->lib->rx_handler_setup(priv);
626}
627
628/**
629 * iwl4965_rx_handle - Main entry function for receiving responses from uCode
630 *
631 * Uses the priv->rx_handlers callback function array to invoke
632 * the appropriate handlers, including command responses,
633 * frame-received notifications, and other notifications.
634 */
635void iwl4965_rx_handle(struct iwl_priv *priv)
636{
637 struct iwl_rx_mem_buffer *rxb;
638 struct iwl_rx_packet *pkt;
639 struct iwl_rx_queue *rxq = &priv->rxq;
640 u32 r, i;
641 int reclaim;
642 unsigned long flags;
643 u8 fill_rx = 0;
644 u32 count = 8;
645 int total_empty;
646
647 /* uCode's read index (stored in shared DRAM) indicates the last Rx
648 * buffer that the driver may process (last buffer filled by ucode). */
649 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
650 i = rxq->read;
651
652 /* Rx interrupt, but nothing sent from uCode */
653 if (i == r)
654 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
655
656 /* calculate total frames need to be restock after handling RX */
657 total_empty = r - rxq->write_actual;
658 if (total_empty < 0)
659 total_empty += RX_QUEUE_SIZE;
660
661 if (total_empty > (RX_QUEUE_SIZE / 2))
662 fill_rx = 1;
663
664 while (i != r) {
665 int len;
666
667 rxb = rxq->queue[i];
668
669 /* If an RXB doesn't have a Rx queue slot associated with it,
670 * then a bug has been introduced in the queue refilling
671 * routines -- catch it here */
672 BUG_ON(rxb == NULL);
673
674 rxq->queue[i] = NULL;
675
676 pci_unmap_page(priv->pci_dev, rxb->page_dma,
677 PAGE_SIZE << priv->hw_params.rx_page_order,
678 PCI_DMA_FROMDEVICE);
679 pkt = rxb_addr(rxb);
680
681 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
682 len += sizeof(u32); /* account for status word */
683 trace_iwlwifi_legacy_dev_rx(priv, pkt, len);
684
685 /* Reclaim a command buffer only if this packet is a response
686 * to a (driver-originated) command.
687 * If the packet (e.g. Rx frame) originated from uCode,
688 * there is no command buffer to reclaim.
689 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
690 * but apparently a few don't get set; catch them here. */
691 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
692 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
693 (pkt->hdr.cmd != REPLY_RX) &&
694 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
695 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
696 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
697 (pkt->hdr.cmd != REPLY_TX);
698
699 /* Based on type of command response or notification,
700 * handle those that need handling via function in
701 * rx_handlers table. See iwl4965_setup_rx_handlers() */
702 if (priv->rx_handlers[pkt->hdr.cmd]) {
703 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
704 i, iwl_legacy_get_cmd_string(pkt->hdr.cmd),
705 pkt->hdr.cmd);
706 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
707 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
708 } else {
709 /* No handling needed */
710 IWL_DEBUG_RX(priv,
711 "r %d i %d No handler needed for %s, 0x%02x\n",
712 r, i, iwl_legacy_get_cmd_string(pkt->hdr.cmd),
713 pkt->hdr.cmd);
714 }
715
716 /*
717 * XXX: After here, we should always check rxb->page
718 * against NULL before touching it or its virtual
719 * memory (pkt). Because some rx_handler might have
720 * already taken or freed the pages.
721 */
722
723 if (reclaim) {
724 /* Invoke any callbacks, transfer the buffer to caller,
725 * and fire off the (possibly) blocking iwl_legacy_send_cmd()
726 * as we reclaim the driver command queue */
727 if (rxb->page)
728 iwl_legacy_tx_cmd_complete(priv, rxb);
729 else
730 IWL_WARN(priv, "Claim null rxb?\n");
731 }
732
733 /* Reuse the page if possible. For notification packets and
734 * SKBs that fail to Rx correctly, add them back into the
735 * rx_free list for reuse later. */
736 spin_lock_irqsave(&rxq->lock, flags);
737 if (rxb->page != NULL) {
738 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
739 0, PAGE_SIZE << priv->hw_params.rx_page_order,
740 PCI_DMA_FROMDEVICE);
741 list_add_tail(&rxb->list, &rxq->rx_free);
742 rxq->free_count++;
743 } else
744 list_add_tail(&rxb->list, &rxq->rx_used);
745
746 spin_unlock_irqrestore(&rxq->lock, flags);
747
748 i = (i + 1) & RX_QUEUE_MASK;
749 /* If there are a lot of unused frames,
750 * restock the Rx queue so ucode wont assert. */
751 if (fill_rx) {
752 count++;
753 if (count >= 8) {
754 rxq->read = i;
755 iwl4965_rx_replenish_now(priv);
756 count = 0;
757 }
758 }
759 }
760
761 /* Backtrack one entry */
762 rxq->read = i;
763 if (fill_rx)
764 iwl4965_rx_replenish_now(priv);
765 else
766 iwl4965_rx_queue_restock(priv);
767}
768
769/* call this function to flush any scheduled tasklet */
770static inline void iwl4965_synchronize_irq(struct iwl_priv *priv)
771{
772 /* wait to make sure we flush pending tasklet*/
773 synchronize_irq(priv->pci_dev->irq);
774 tasklet_kill(&priv->irq_tasklet);
775}
776
777static void iwl4965_irq_tasklet(struct iwl_priv *priv)
778{
779 u32 inta, handled = 0;
780 u32 inta_fh;
781 unsigned long flags;
782 u32 i;
783#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
784 u32 inta_mask;
785#endif
786
787 spin_lock_irqsave(&priv->lock, flags);
788
789 /* Ack/clear/reset pending uCode interrupts.
790 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
791 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
792 inta = iwl_read32(priv, CSR_INT);
793 iwl_write32(priv, CSR_INT, inta);
794
795 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
796 * Any new interrupts that happen after this, either while we're
797 * in this tasklet, or later, will show up in next ISR/tasklet. */
798 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
799 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
800
801#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
802 if (iwl_legacy_get_debug_level(priv) & IWL_DL_ISR) {
803 /* just for debug */
804 inta_mask = iwl_read32(priv, CSR_INT_MASK);
805 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
806 inta, inta_mask, inta_fh);
807 }
808#endif
809
810 spin_unlock_irqrestore(&priv->lock, flags);
811
812 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
813 * atomic, make sure that inta covers all the interrupts that
814 * we've discovered, even if FH interrupt came in just after
815 * reading CSR_INT. */
816 if (inta_fh & CSR49_FH_INT_RX_MASK)
817 inta |= CSR_INT_BIT_FH_RX;
818 if (inta_fh & CSR49_FH_INT_TX_MASK)
819 inta |= CSR_INT_BIT_FH_TX;
820
821 /* Now service all interrupt bits discovered above. */
822 if (inta & CSR_INT_BIT_HW_ERR) {
823 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
824
825 /* Tell the device to stop sending interrupts */
826 iwl_legacy_disable_interrupts(priv);
827
828 priv->isr_stats.hw++;
829 iwl_legacy_irq_handle_error(priv);
830
831 handled |= CSR_INT_BIT_HW_ERR;
832
833 return;
834 }
835
836#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
837 if (iwl_legacy_get_debug_level(priv) & (IWL_DL_ISR)) {
838 /* NIC fires this, but we don't use it, redundant with WAKEUP */
839 if (inta & CSR_INT_BIT_SCD) {
840 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
841 "the frame/frames.\n");
842 priv->isr_stats.sch++;
843 }
844
845 /* Alive notification via Rx interrupt will do the real work */
846 if (inta & CSR_INT_BIT_ALIVE) {
847 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
848 priv->isr_stats.alive++;
849 }
850 }
851#endif
852 /* Safely ignore these bits for debug checks below */
853 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
854
855 /* HW RF KILL switch toggled */
856 if (inta & CSR_INT_BIT_RF_KILL) {
857 int hw_rf_kill = 0;
858 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
859 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
860 hw_rf_kill = 1;
861
862 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
863 hw_rf_kill ? "disable radio" : "enable radio");
864
865 priv->isr_stats.rfkill++;
866
867 /* driver only loads ucode once setting the interface up.
868 * the driver allows loading the ucode even if the radio
869 * is killed. Hence update the killswitch state here. The
870 * rfkill handler will care about restarting if needed.
871 */
872 if (!test_bit(STATUS_ALIVE, &priv->status)) {
873 if (hw_rf_kill)
874 set_bit(STATUS_RF_KILL_HW, &priv->status);
875 else
876 clear_bit(STATUS_RF_KILL_HW, &priv->status);
877 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
878 }
879
880 handled |= CSR_INT_BIT_RF_KILL;
881 }
882
883 /* Chip got too hot and stopped itself */
884 if (inta & CSR_INT_BIT_CT_KILL) {
885 IWL_ERR(priv, "Microcode CT kill error detected.\n");
886 priv->isr_stats.ctkill++;
887 handled |= CSR_INT_BIT_CT_KILL;
888 }
889
890 /* Error detected by uCode */
891 if (inta & CSR_INT_BIT_SW_ERR) {
892 IWL_ERR(priv, "Microcode SW error detected. "
893 " Restarting 0x%X.\n", inta);
894 priv->isr_stats.sw++;
895 iwl_legacy_irq_handle_error(priv);
896 handled |= CSR_INT_BIT_SW_ERR;
897 }
898
899 /*
900 * uCode wakes up after power-down sleep.
901 * Tell device about any new tx or host commands enqueued,
902 * and about any Rx buffers made available while asleep.
903 */
904 if (inta & CSR_INT_BIT_WAKEUP) {
905 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
906 iwl_legacy_rx_queue_update_write_ptr(priv, &priv->rxq);
907 for (i = 0; i < priv->hw_params.max_txq_num; i++)
908 iwl_legacy_txq_update_write_ptr(priv, &priv->txq[i]);
909 priv->isr_stats.wakeup++;
910 handled |= CSR_INT_BIT_WAKEUP;
911 }
912
913 /* All uCode command responses, including Tx command responses,
914 * Rx "responses" (frame-received notification), and other
915 * notifications from uCode come through here*/
916 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
917 iwl4965_rx_handle(priv);
918 priv->isr_stats.rx++;
919 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
920 }
921
922 /* This "Tx" DMA channel is used only for loading uCode */
923 if (inta & CSR_INT_BIT_FH_TX) {
924 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
925 priv->isr_stats.tx++;
926 handled |= CSR_INT_BIT_FH_TX;
927 /* Wake up uCode load routine, now that load is complete */
928 priv->ucode_write_complete = 1;
929 wake_up(&priv->wait_command_queue);
930 }
931
932 if (inta & ~handled) {
933 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
934 priv->isr_stats.unhandled++;
935 }
936
937 if (inta & ~(priv->inta_mask)) {
938 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
939 inta & ~priv->inta_mask);
940 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
941 }
942
943 /* Re-enable all interrupts */
944 /* only Re-enable if disabled by irq */
945 if (test_bit(STATUS_INT_ENABLED, &priv->status))
946 iwl_legacy_enable_interrupts(priv);
947 /* Re-enable RF_KILL if it occurred */
948 else if (handled & CSR_INT_BIT_RF_KILL)
949 iwl_legacy_enable_rfkill_int(priv);
950
951#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
952 if (iwl_legacy_get_debug_level(priv) & (IWL_DL_ISR)) {
953 inta = iwl_read32(priv, CSR_INT);
954 inta_mask = iwl_read32(priv, CSR_INT_MASK);
955 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
956 IWL_DEBUG_ISR(priv,
957 "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
958 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
959 }
960#endif
961}
962
963/*****************************************************************************
964 *
965 * sysfs attributes
966 *
967 *****************************************************************************/
968
969#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
970
971/*
972 * The following adds a new attribute to the sysfs representation
973 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
974 * used for controlling the debug level.
975 *
976 * See the level definitions in iwl for details.
977 *
978 * The debug_level being managed using sysfs below is a per device debug
979 * level that is used instead of the global debug level if it (the per
980 * device debug level) is set.
981 */
982static ssize_t iwl4965_show_debug_level(struct device *d,
983 struct device_attribute *attr, char *buf)
984{
985 struct iwl_priv *priv = dev_get_drvdata(d);
986 return sprintf(buf, "0x%08X\n", iwl_legacy_get_debug_level(priv));
987}
988static ssize_t iwl4965_store_debug_level(struct device *d,
989 struct device_attribute *attr,
990 const char *buf, size_t count)
991{
992 struct iwl_priv *priv = dev_get_drvdata(d);
993 unsigned long val;
994 int ret;
995
996 ret = strict_strtoul(buf, 0, &val);
997 if (ret)
998 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
999 else {
1000 priv->debug_level = val;
1001 if (iwl_legacy_alloc_traffic_mem(priv))
1002 IWL_ERR(priv,
1003 "Not enough memory to generate traffic log\n");
1004 }
1005 return strnlen(buf, count);
1006}
1007
1008static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1009 iwl4965_show_debug_level, iwl4965_store_debug_level);
1010
1011
1012#endif /* CONFIG_IWLWIFI_LEGACY_DEBUG */
1013
1014
1015static ssize_t iwl4965_show_temperature(struct device *d,
1016 struct device_attribute *attr, char *buf)
1017{
1018 struct iwl_priv *priv = dev_get_drvdata(d);
1019
1020 if (!iwl_legacy_is_alive(priv))
1021 return -EAGAIN;
1022
1023 return sprintf(buf, "%d\n", priv->temperature);
1024}
1025
1026static DEVICE_ATTR(temperature, S_IRUGO, iwl4965_show_temperature, NULL);
1027
1028static ssize_t iwl4965_show_tx_power(struct device *d,
1029 struct device_attribute *attr, char *buf)
1030{
1031 struct iwl_priv *priv = dev_get_drvdata(d);
1032
1033 if (!iwl_legacy_is_ready_rf(priv))
1034 return sprintf(buf, "off\n");
1035 else
1036 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1037}
1038
1039static ssize_t iwl4965_store_tx_power(struct device *d,
1040 struct device_attribute *attr,
1041 const char *buf, size_t count)
1042{
1043 struct iwl_priv *priv = dev_get_drvdata(d);
1044 unsigned long val;
1045 int ret;
1046
1047 ret = strict_strtoul(buf, 10, &val);
1048 if (ret)
1049 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1050 else {
1051 ret = iwl_legacy_set_tx_power(priv, val, false);
1052 if (ret)
1053 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1054 ret);
1055 else
1056 ret = count;
1057 }
1058 return ret;
1059}
1060
1061static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO,
1062 iwl4965_show_tx_power, iwl4965_store_tx_power);
1063
1064static struct attribute *iwl_sysfs_entries[] = {
1065 &dev_attr_temperature.attr,
1066 &dev_attr_tx_power.attr,
1067#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
1068 &dev_attr_debug_level.attr,
1069#endif
1070 NULL
1071};
1072
1073static struct attribute_group iwl_attribute_group = {
1074 .name = NULL, /* put in device directory */
1075 .attrs = iwl_sysfs_entries,
1076};
1077
1078/******************************************************************************
1079 *
1080 * uCode download functions
1081 *
1082 ******************************************************************************/
1083
1084static void iwl4965_dealloc_ucode_pci(struct iwl_priv *priv)
1085{
1086 iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1087 iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1088 iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1089 iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1090 iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1091 iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1092}
1093
1094static void iwl4965_nic_start(struct iwl_priv *priv)
1095{
1096 /* Remove all resets to allow NIC to operate */
1097 iwl_write32(priv, CSR_RESET, 0);
1098}
1099
1100static void iwl4965_ucode_callback(const struct firmware *ucode_raw,
1101 void *context);
1102static int iwl4965_mac_setup_register(struct iwl_priv *priv,
1103 u32 max_probe_length);
1104
1105static int __must_check iwl4965_request_firmware(struct iwl_priv *priv, bool first)
1106{
1107 const char *name_pre = priv->cfg->fw_name_pre;
1108 char tag[8];
1109
1110 if (first) {
1111 priv->fw_index = priv->cfg->ucode_api_max;
1112 sprintf(tag, "%d", priv->fw_index);
1113 } else {
1114 priv->fw_index--;
1115 sprintf(tag, "%d", priv->fw_index);
1116 }
1117
1118 if (priv->fw_index < priv->cfg->ucode_api_min) {
1119 IWL_ERR(priv, "no suitable firmware found!\n");
1120 return -ENOENT;
1121 }
1122
1123 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1124
1125 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1126 priv->firmware_name);
1127
1128 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1129 &priv->pci_dev->dev, GFP_KERNEL, priv,
1130 iwl4965_ucode_callback);
1131}
1132
1133struct iwl4965_firmware_pieces {
1134 const void *inst, *data, *init, *init_data, *boot;
1135 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1136};
1137
1138static int iwl4965_load_firmware(struct iwl_priv *priv,
1139 const struct firmware *ucode_raw,
1140 struct iwl4965_firmware_pieces *pieces)
1141{
1142 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1143 u32 api_ver, hdr_size;
1144 const u8 *src;
1145
1146 priv->ucode_ver = le32_to_cpu(ucode->ver);
1147 api_ver = IWL_UCODE_API(priv->ucode_ver);
1148
1149 switch (api_ver) {
1150 default:
1151 case 0:
1152 case 1:
1153 case 2:
1154 hdr_size = 24;
1155 if (ucode_raw->size < hdr_size) {
1156 IWL_ERR(priv, "File size too small!\n");
1157 return -EINVAL;
1158 }
1159 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
1160 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
1161 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
1162 pieces->init_data_size =
1163 le32_to_cpu(ucode->v1.init_data_size);
1164 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
1165 src = ucode->v1.data;
1166 break;
1167 }
1168
1169 /* Verify size of file vs. image size info in file's header */
1170 if (ucode_raw->size != hdr_size + pieces->inst_size +
1171 pieces->data_size + pieces->init_size +
1172 pieces->init_data_size + pieces->boot_size) {
1173
1174 IWL_ERR(priv,
1175 "uCode file size %d does not match expected size\n",
1176 (int)ucode_raw->size);
1177 return -EINVAL;
1178 }
1179
1180 pieces->inst = src;
1181 src += pieces->inst_size;
1182 pieces->data = src;
1183 src += pieces->data_size;
1184 pieces->init = src;
1185 src += pieces->init_size;
1186 pieces->init_data = src;
1187 src += pieces->init_data_size;
1188 pieces->boot = src;
1189 src += pieces->boot_size;
1190
1191 return 0;
1192}
1193
1194/**
1195 * iwl4965_ucode_callback - callback when firmware was loaded
1196 *
1197 * If loaded successfully, copies the firmware into buffers
1198 * for the card to fetch (via DMA).
1199 */
1200static void
1201iwl4965_ucode_callback(const struct firmware *ucode_raw, void *context)
1202{
1203 struct iwl_priv *priv = context;
1204 struct iwl_ucode_header *ucode;
1205 int err;
1206 struct iwl4965_firmware_pieces pieces;
1207 const unsigned int api_max = priv->cfg->ucode_api_max;
1208 const unsigned int api_min = priv->cfg->ucode_api_min;
1209 u32 api_ver;
1210
1211 u32 max_probe_length = 200;
1212 u32 standard_phy_calibration_size =
1213 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1214
1215 memset(&pieces, 0, sizeof(pieces));
1216
1217 if (!ucode_raw) {
1218 if (priv->fw_index <= priv->cfg->ucode_api_max)
1219 IWL_ERR(priv,
1220 "request for firmware file '%s' failed.\n",
1221 priv->firmware_name);
1222 goto try_again;
1223 }
1224
1225 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1226 priv->firmware_name, ucode_raw->size);
1227
1228 /* Make sure that we got at least the API version number */
1229 if (ucode_raw->size < 4) {
1230 IWL_ERR(priv, "File size way too small!\n");
1231 goto try_again;
1232 }
1233
1234 /* Data from ucode file: header followed by uCode images */
1235 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1236
1237 err = iwl4965_load_firmware(priv, ucode_raw, &pieces);
1238
1239 if (err)
1240 goto try_again;
1241
1242 api_ver = IWL_UCODE_API(priv->ucode_ver);
1243
1244 /*
1245 * api_ver should match the api version forming part of the
1246 * firmware filename ... but we don't check for that and only rely
1247 * on the API version read from firmware header from here on forward
1248 */
1249 if (api_ver < api_min || api_ver > api_max) {
1250 IWL_ERR(priv,
1251 "Driver unable to support your firmware API. "
1252 "Driver supports v%u, firmware is v%u.\n",
1253 api_max, api_ver);
1254 goto try_again;
1255 }
1256
1257 if (api_ver != api_max)
1258 IWL_ERR(priv,
1259 "Firmware has old API version. Expected v%u, "
1260 "got v%u. New firmware can be obtained "
1261 "from http://www.intellinuxwireless.org.\n",
1262 api_max, api_ver);
1263
1264 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1265 IWL_UCODE_MAJOR(priv->ucode_ver),
1266 IWL_UCODE_MINOR(priv->ucode_ver),
1267 IWL_UCODE_API(priv->ucode_ver),
1268 IWL_UCODE_SERIAL(priv->ucode_ver));
1269
1270 snprintf(priv->hw->wiphy->fw_version,
1271 sizeof(priv->hw->wiphy->fw_version),
1272 "%u.%u.%u.%u",
1273 IWL_UCODE_MAJOR(priv->ucode_ver),
1274 IWL_UCODE_MINOR(priv->ucode_ver),
1275 IWL_UCODE_API(priv->ucode_ver),
1276 IWL_UCODE_SERIAL(priv->ucode_ver));
1277
1278 /*
1279 * For any of the failures below (before allocating pci memory)
1280 * we will try to load a version with a smaller API -- maybe the
1281 * user just got a corrupted version of the latest API.
1282 */
1283
1284 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1285 priv->ucode_ver);
1286 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1287 pieces.inst_size);
1288 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1289 pieces.data_size);
1290 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1291 pieces.init_size);
1292 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1293 pieces.init_data_size);
1294 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1295 pieces.boot_size);
1296
1297 /* Verify that uCode images will fit in card's SRAM */
1298 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1299 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1300 pieces.inst_size);
1301 goto try_again;
1302 }
1303
1304 if (pieces.data_size > priv->hw_params.max_data_size) {
1305 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1306 pieces.data_size);
1307 goto try_again;
1308 }
1309
1310 if (pieces.init_size > priv->hw_params.max_inst_size) {
1311 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1312 pieces.init_size);
1313 goto try_again;
1314 }
1315
1316 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1317 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1318 pieces.init_data_size);
1319 goto try_again;
1320 }
1321
1322 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1323 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1324 pieces.boot_size);
1325 goto try_again;
1326 }
1327
1328 /* Allocate ucode buffers for card's bus-master loading ... */
1329
1330 /* Runtime instructions and 2 copies of data:
1331 * 1) unmodified from disk
1332 * 2) backup cache for save/restore during power-downs */
1333 priv->ucode_code.len = pieces.inst_size;
1334 iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1335
1336 priv->ucode_data.len = pieces.data_size;
1337 iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1338
1339 priv->ucode_data_backup.len = pieces.data_size;
1340 iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1341
1342 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1343 !priv->ucode_data_backup.v_addr)
1344 goto err_pci_alloc;
1345
1346 /* Initialization instructions and data */
1347 if (pieces.init_size && pieces.init_data_size) {
1348 priv->ucode_init.len = pieces.init_size;
1349 iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1350
1351 priv->ucode_init_data.len = pieces.init_data_size;
1352 iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1353
1354 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1355 goto err_pci_alloc;
1356 }
1357
1358 /* Bootstrap (instructions only, no data) */
1359 if (pieces.boot_size) {
1360 priv->ucode_boot.len = pieces.boot_size;
1361 iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1362
1363 if (!priv->ucode_boot.v_addr)
1364 goto err_pci_alloc;
1365 }
1366
1367 /* Now that we can no longer fail, copy information */
1368
1369 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1370
1371 /* Copy images into buffers for card's bus-master reads ... */
1372
1373 /* Runtime instructions (first block of data in file) */
1374 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1375 pieces.inst_size);
1376 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1377
1378 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1379 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1380
1381 /*
1382 * Runtime data
1383 * NOTE: Copy into backup buffer will be done in iwl_up()
1384 */
1385 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1386 pieces.data_size);
1387 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1388 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1389
1390 /* Initialization instructions */
1391 if (pieces.init_size) {
1392 IWL_DEBUG_INFO(priv,
1393 "Copying (but not loading) init instr len %Zd\n",
1394 pieces.init_size);
1395 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1396 }
1397
1398 /* Initialization data */
1399 if (pieces.init_data_size) {
1400 IWL_DEBUG_INFO(priv,
1401 "Copying (but not loading) init data len %Zd\n",
1402 pieces.init_data_size);
1403 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1404 pieces.init_data_size);
1405 }
1406
1407 /* Bootstrap instructions */
1408 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1409 pieces.boot_size);
1410 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1411
1412 /*
1413 * figure out the offset of chain noise reset and gain commands
1414 * base on the size of standard phy calibration commands table size
1415 */
1416 priv->_4965.phy_calib_chain_noise_reset_cmd =
1417 standard_phy_calibration_size;
1418 priv->_4965.phy_calib_chain_noise_gain_cmd =
1419 standard_phy_calibration_size + 1;
1420
1421 /**************************************************
1422 * This is still part of probe() in a sense...
1423 *
1424 * 9. Setup and register with mac80211 and debugfs
1425 **************************************************/
1426 err = iwl4965_mac_setup_register(priv, max_probe_length);
1427 if (err)
1428 goto out_unbind;
1429
1430 err = iwl_legacy_dbgfs_register(priv, DRV_NAME);
1431 if (err)
1432 IWL_ERR(priv,
1433 "failed to create debugfs files. Ignoring error: %d\n", err);
1434
1435 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1436 &iwl_attribute_group);
1437 if (err) {
1438 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1439 goto out_unbind;
1440 }
1441
1442 /* We have our copies now, allow OS release its copies */
1443 release_firmware(ucode_raw);
1444 complete(&priv->_4965.firmware_loading_complete);
1445 return;
1446
1447 try_again:
1448 /* try next, if any */
1449 if (iwl4965_request_firmware(priv, false))
1450 goto out_unbind;
1451 release_firmware(ucode_raw);
1452 return;
1453
1454 err_pci_alloc:
1455 IWL_ERR(priv, "failed to allocate pci memory\n");
1456 iwl4965_dealloc_ucode_pci(priv);
1457 out_unbind:
1458 complete(&priv->_4965.firmware_loading_complete);
1459 device_release_driver(&priv->pci_dev->dev);
1460 release_firmware(ucode_raw);
1461}
1462
1463static const char * const desc_lookup_text[] = {
1464 "OK",
1465 "FAIL",
1466 "BAD_PARAM",
1467 "BAD_CHECKSUM",
1468 "NMI_INTERRUPT_WDG",
1469 "SYSASSERT",
1470 "FATAL_ERROR",
1471 "BAD_COMMAND",
1472 "HW_ERROR_TUNE_LOCK",
1473 "HW_ERROR_TEMPERATURE",
1474 "ILLEGAL_CHAN_FREQ",
1475 "VCC_NOT_STABLE",
1476 "FH_ERROR",
1477 "NMI_INTERRUPT_HOST",
1478 "NMI_INTERRUPT_ACTION_PT",
1479 "NMI_INTERRUPT_UNKNOWN",
1480 "UCODE_VERSION_MISMATCH",
1481 "HW_ERROR_ABS_LOCK",
1482 "HW_ERROR_CAL_LOCK_FAIL",
1483 "NMI_INTERRUPT_INST_ACTION_PT",
1484 "NMI_INTERRUPT_DATA_ACTION_PT",
1485 "NMI_TRM_HW_ER",
1486 "NMI_INTERRUPT_TRM",
1487 "NMI_INTERRUPT_BREAK_POINT",
1488 "DEBUG_0",
1489 "DEBUG_1",
1490 "DEBUG_2",
1491 "DEBUG_3",
1492};
1493
1494static struct { char *name; u8 num; } advanced_lookup[] = {
1495 { "NMI_INTERRUPT_WDG", 0x34 },
1496 { "SYSASSERT", 0x35 },
1497 { "UCODE_VERSION_MISMATCH", 0x37 },
1498 { "BAD_COMMAND", 0x38 },
1499 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1500 { "FATAL_ERROR", 0x3D },
1501 { "NMI_TRM_HW_ERR", 0x46 },
1502 { "NMI_INTERRUPT_TRM", 0x4C },
1503 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1504 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1505 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1506 { "NMI_INTERRUPT_HOST", 0x66 },
1507 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1508 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1509 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1510 { "ADVANCED_SYSASSERT", 0 },
1511};
1512
1513static const char *iwl4965_desc_lookup(u32 num)
1514{
1515 int i;
1516 int max = ARRAY_SIZE(desc_lookup_text);
1517
1518 if (num < max)
1519 return desc_lookup_text[num];
1520
1521 max = ARRAY_SIZE(advanced_lookup) - 1;
1522 for (i = 0; i < max; i++) {
1523 if (advanced_lookup[i].num == num)
1524 break;
1525 }
1526 return advanced_lookup[i].name;
1527}
1528
1529#define ERROR_START_OFFSET (1 * sizeof(u32))
1530#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1531
1532void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
1533{
1534 u32 data2, line;
1535 u32 desc, time, count, base, data1;
1536 u32 blink1, blink2, ilink1, ilink2;
1537 u32 pc, hcmd;
1538
1539 if (priv->ucode_type == UCODE_INIT) {
1540 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1541 } else {
1542 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1543 }
1544
1545 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1546 IWL_ERR(priv,
1547 "Not valid error log pointer 0x%08X for %s uCode\n",
1548 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1549 return;
1550 }
1551
1552 count = iwl_legacy_read_targ_mem(priv, base);
1553
1554 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1555 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1556 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1557 priv->status, count);
1558 }
1559
1560 desc = iwl_legacy_read_targ_mem(priv, base + 1 * sizeof(u32));
1561 priv->isr_stats.err_code = desc;
1562 pc = iwl_legacy_read_targ_mem(priv, base + 2 * sizeof(u32));
1563 blink1 = iwl_legacy_read_targ_mem(priv, base + 3 * sizeof(u32));
1564 blink2 = iwl_legacy_read_targ_mem(priv, base + 4 * sizeof(u32));
1565 ilink1 = iwl_legacy_read_targ_mem(priv, base + 5 * sizeof(u32));
1566 ilink2 = iwl_legacy_read_targ_mem(priv, base + 6 * sizeof(u32));
1567 data1 = iwl_legacy_read_targ_mem(priv, base + 7 * sizeof(u32));
1568 data2 = iwl_legacy_read_targ_mem(priv, base + 8 * sizeof(u32));
1569 line = iwl_legacy_read_targ_mem(priv, base + 9 * sizeof(u32));
1570 time = iwl_legacy_read_targ_mem(priv, base + 11 * sizeof(u32));
1571 hcmd = iwl_legacy_read_targ_mem(priv, base + 22 * sizeof(u32));
1572
1573 trace_iwlwifi_legacy_dev_ucode_error(priv, desc,
1574 time, data1, data2, line,
1575 blink1, blink2, ilink1, ilink2);
1576
1577 IWL_ERR(priv, "Desc Time "
1578 "data1 data2 line\n");
1579 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1580 iwl4965_desc_lookup(desc), desc, time, data1, data2, line);
1581 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1582 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1583 pc, blink1, blink2, ilink1, ilink2, hcmd);
1584}
1585
1586static void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
1587{
1588 struct iwl_ct_kill_config cmd;
1589 unsigned long flags;
1590 int ret = 0;
1591
1592 spin_lock_irqsave(&priv->lock, flags);
1593 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1594 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1595 spin_unlock_irqrestore(&priv->lock, flags);
1596
1597 cmd.critical_temperature_R =
1598 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1599
1600 ret = iwl_legacy_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1601 sizeof(cmd), &cmd);
1602 if (ret)
1603 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1604 else
1605 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
1606 "succeeded, "
1607 "critical temperature is %d\n",
1608 priv->hw_params.ct_kill_threshold);
1609}
1610
1611static const s8 default_queue_to_tx_fifo[] = {
1612 IWL_TX_FIFO_VO,
1613 IWL_TX_FIFO_VI,
1614 IWL_TX_FIFO_BE,
1615 IWL_TX_FIFO_BK,
1616 IWL49_CMD_FIFO_NUM,
1617 IWL_TX_FIFO_UNUSED,
1618 IWL_TX_FIFO_UNUSED,
1619};
1620
1621static int iwl4965_alive_notify(struct iwl_priv *priv)
1622{
1623 u32 a;
1624 unsigned long flags;
1625 int i, chan;
1626 u32 reg_val;
1627
1628 spin_lock_irqsave(&priv->lock, flags);
1629
1630 /* Clear 4965's internal Tx Scheduler data base */
1631 priv->scd_base_addr = iwl_legacy_read_prph(priv,
1632 IWL49_SCD_SRAM_BASE_ADDR);
1633 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
1634 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1635 iwl_legacy_write_targ_mem(priv, a, 0);
1636 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
1637 iwl_legacy_write_targ_mem(priv, a, 0);
1638 for (; a < priv->scd_base_addr +
1639 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
1640 iwl_legacy_write_targ_mem(priv, a, 0);
1641
1642 /* Tel 4965 where to find Tx byte count tables */
1643 iwl_legacy_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
1644 priv->scd_bc_tbls.dma >> 10);
1645
1646 /* Enable DMA channel */
1647 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
1648 iwl_legacy_write_direct32(priv,
1649 FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1650 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1651 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1652
1653 /* Update FH chicken bits */
1654 reg_val = iwl_legacy_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
1655 iwl_legacy_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
1656 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1657
1658 /* Disable chain mode for all queues */
1659 iwl_legacy_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
1660
1661 /* Initialize each Tx queue (including the command queue) */
1662 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
1663
1664 /* TFD circular buffer read/write indexes */
1665 iwl_legacy_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
1666 iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1667
1668 /* Max Tx Window size for Scheduler-ACK mode */
1669 iwl_legacy_write_targ_mem(priv, priv->scd_base_addr +
1670 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
1671 (SCD_WIN_SIZE <<
1672 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1673 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1674
1675 /* Frame limit */
1676 iwl_legacy_write_targ_mem(priv, priv->scd_base_addr +
1677 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
1678 sizeof(u32),
1679 (SCD_FRAME_LIMIT <<
1680 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1681 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1682
1683 }
1684 iwl_legacy_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1685 (1 << priv->hw_params.max_txq_num) - 1);
1686
1687 /* Activate all Tx DMA/FIFO channels */
1688 iwl4965_txq_set_sched(priv, IWL_MASK(0, 6));
1689
1690 iwl4965_set_wr_ptrs(priv, IWL_DEFAULT_CMD_QUEUE_NUM, 0);
1691
1692 /* make sure all queue are not stopped */
1693 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
1694 for (i = 0; i < 4; i++)
1695 atomic_set(&priv->queue_stop_count[i], 0);
1696
1697 /* reset to 0 to enable all the queue first */
1698 priv->txq_ctx_active_msk = 0;
1699 /* Map each Tx/cmd queue to its corresponding fifo */
1700 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
1701
1702 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1703 int ac = default_queue_to_tx_fifo[i];
1704
1705 iwl_txq_ctx_activate(priv, i);
1706
1707 if (ac == IWL_TX_FIFO_UNUSED)
1708 continue;
1709
1710 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1711 }
1712
1713 spin_unlock_irqrestore(&priv->lock, flags);
1714
1715 return 0;
1716}
1717
1718/**
1719 * iwl4965_alive_start - called after REPLY_ALIVE notification received
1720 * from protocol/runtime uCode (initialization uCode's
1721 * Alive gets handled by iwl_init_alive_start()).
1722 */
1723static void iwl4965_alive_start(struct iwl_priv *priv)
1724{
1725 int ret = 0;
1726 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1727
1728 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
1729
1730 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1731 /* We had an error bringing up the hardware, so take it
1732 * all the way back down so we can try again */
1733 IWL_DEBUG_INFO(priv, "Alive failed.\n");
1734 goto restart;
1735 }
1736
1737 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1738 * This is a paranoid check, because we would not have gotten the
1739 * "runtime" alive if code weren't properly loaded. */
1740 if (iwl4965_verify_ucode(priv)) {
1741 /* Runtime instruction load was bad;
1742 * take it all the way back down so we can try again */
1743 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
1744 goto restart;
1745 }
1746
1747 ret = iwl4965_alive_notify(priv);
1748 if (ret) {
1749 IWL_WARN(priv,
1750 "Could not complete ALIVE transition [ntf]: %d\n", ret);
1751 goto restart;
1752 }
1753
1754
1755 /* After the ALIVE response, we can send host commands to the uCode */
1756 set_bit(STATUS_ALIVE, &priv->status);
1757
1758 /* Enable watchdog to monitor the driver tx queues */
1759 iwl_legacy_setup_watchdog(priv);
1760
1761 if (iwl_legacy_is_rfkill(priv))
1762 return;
1763
1764 ieee80211_wake_queues(priv->hw);
1765
1766 priv->active_rate = IWL_RATES_MASK;
1767
1768 if (iwl_legacy_is_associated_ctx(ctx)) {
1769 struct iwl_legacy_rxon_cmd *active_rxon =
1770 (struct iwl_legacy_rxon_cmd *)&ctx->active;
1771 /* apply any changes in staging */
1772 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
1773 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1774 } else {
1775 struct iwl_rxon_context *tmp;
1776 /* Initialize our rx_config data */
1777 for_each_context(priv, tmp)
1778 iwl_legacy_connection_init_rx_config(priv, tmp);
1779
1780 if (priv->cfg->ops->hcmd->set_rxon_chain)
1781 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
1782 }
1783
1784 /* Configure bluetooth coexistence if enabled */
1785 iwl_legacy_send_bt_config(priv);
1786
1787 iwl4965_reset_run_time_calib(priv);
1788
1789 set_bit(STATUS_READY, &priv->status);
1790
1791 /* Configure the adapter for unassociated operation */
1792 iwl_legacy_commit_rxon(priv, ctx);
1793
1794 /* At this point, the NIC is initialized and operational */
1795 iwl4965_rf_kill_ct_config(priv);
1796
1797 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
1798 wake_up(&priv->wait_command_queue);
1799
1800 iwl_legacy_power_update_mode(priv, true);
1801 IWL_DEBUG_INFO(priv, "Updated power mode\n");
1802
1803 return;
1804
1805 restart:
1806 queue_work(priv->workqueue, &priv->restart);
1807}
1808
1809static void iwl4965_cancel_deferred_work(struct iwl_priv *priv);
1810
1811static void __iwl4965_down(struct iwl_priv *priv)
1812{
1813 unsigned long flags;
1814 int exit_pending;
1815
1816 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
1817
1818 iwl_legacy_scan_cancel_timeout(priv, 200);
1819
1820 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
1821
1822 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
1823 * to prevent rearm timer */
1824 del_timer_sync(&priv->watchdog);
1825
1826 iwl_legacy_clear_ucode_stations(priv, NULL);
1827 iwl_legacy_dealloc_bcast_stations(priv);
1828 iwl_legacy_clear_driver_stations(priv);
1829
1830 /* Unblock any waiting calls */
1831 wake_up_all(&priv->wait_command_queue);
1832
1833 /* Wipe out the EXIT_PENDING status bit if we are not actually
1834 * exiting the module */
1835 if (!exit_pending)
1836 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1837
1838 /* stop and reset the on-board processor */
1839 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1840
1841 /* tell the device to stop sending interrupts */
1842 spin_lock_irqsave(&priv->lock, flags);
1843 iwl_legacy_disable_interrupts(priv);
1844 spin_unlock_irqrestore(&priv->lock, flags);
1845 iwl4965_synchronize_irq(priv);
1846
1847 if (priv->mac80211_registered)
1848 ieee80211_stop_queues(priv->hw);
1849
1850 /* If we have not previously called iwl_init() then
1851 * clear all bits but the RF Kill bit and return */
1852 if (!iwl_legacy_is_init(priv)) {
1853 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1854 STATUS_RF_KILL_HW |
1855 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1856 STATUS_GEO_CONFIGURED |
1857 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1858 STATUS_EXIT_PENDING;
1859 goto exit;
1860 }
1861
1862 /* ...otherwise clear out all the status bits but the RF Kill
1863 * bit and continue taking the NIC down. */
1864 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1865 STATUS_RF_KILL_HW |
1866 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1867 STATUS_GEO_CONFIGURED |
1868 test_bit(STATUS_FW_ERROR, &priv->status) <<
1869 STATUS_FW_ERROR |
1870 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1871 STATUS_EXIT_PENDING;
1872
1873 iwl4965_txq_ctx_stop(priv);
1874 iwl4965_rxq_stop(priv);
1875
1876 /* Power-down device's busmaster DMA clocks */
1877 iwl_legacy_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
1878 udelay(5);
1879
1880 /* Make sure (redundant) we've released our request to stay awake */
1881 iwl_legacy_clear_bit(priv, CSR_GP_CNTRL,
1882 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1883
1884 /* Stop the device, and put it in low power state */
1885 iwl_legacy_apm_stop(priv);
1886
1887 exit:
1888 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
1889
1890 dev_kfree_skb(priv->beacon_skb);
1891 priv->beacon_skb = NULL;
1892
1893 /* clear out any free frames */
1894 iwl4965_clear_free_frames(priv);
1895}
1896
1897static void iwl4965_down(struct iwl_priv *priv)
1898{
1899 mutex_lock(&priv->mutex);
1900 __iwl4965_down(priv);
1901 mutex_unlock(&priv->mutex);
1902
1903 iwl4965_cancel_deferred_work(priv);
1904}
1905
1906#define HW_READY_TIMEOUT (50)
1907
1908static int iwl4965_set_hw_ready(struct iwl_priv *priv)
1909{
1910 int ret = 0;
1911
1912 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1913 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1914
1915 /* See if we got it */
1916 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1917 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1918 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1919 HW_READY_TIMEOUT);
1920 if (ret != -ETIMEDOUT)
1921 priv->hw_ready = true;
1922 else
1923 priv->hw_ready = false;
1924
1925 IWL_DEBUG_INFO(priv, "hardware %s\n",
1926 (priv->hw_ready == 1) ? "ready" : "not ready");
1927 return ret;
1928}
1929
1930static int iwl4965_prepare_card_hw(struct iwl_priv *priv)
1931{
1932 int ret = 0;
1933
1934 IWL_DEBUG_INFO(priv, "iwl4965_prepare_card_hw enter\n");
1935
1936 ret = iwl4965_set_hw_ready(priv);
1937 if (priv->hw_ready)
1938 return ret;
1939
1940 /* If HW is not ready, prepare the conditions to check again */
1941 iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1942 CSR_HW_IF_CONFIG_REG_PREPARE);
1943
1944 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1945 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1946 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1947
1948 /* HW should be ready by now, check again. */
1949 if (ret != -ETIMEDOUT)
1950 iwl4965_set_hw_ready(priv);
1951
1952 return ret;
1953}
1954
1955#define MAX_HW_RESTARTS 5
1956
1957static int __iwl4965_up(struct iwl_priv *priv)
1958{
1959 struct iwl_rxon_context *ctx;
1960 int i;
1961 int ret;
1962
1963 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
1964 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
1965 return -EIO;
1966 }
1967
1968 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
1969 IWL_ERR(priv, "ucode not available for device bringup\n");
1970 return -EIO;
1971 }
1972
1973 for_each_context(priv, ctx) {
1974 ret = iwl4965_alloc_bcast_station(priv, ctx);
1975 if (ret) {
1976 iwl_legacy_dealloc_bcast_stations(priv);
1977 return ret;
1978 }
1979 }
1980
1981 iwl4965_prepare_card_hw(priv);
1982
1983 if (!priv->hw_ready) {
1984 IWL_WARN(priv, "Exit HW not ready\n");
1985 return -EIO;
1986 }
1987
1988 /* If platform's RF_KILL switch is NOT set to KILL */
1989 if (iwl_read32(priv,
1990 CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1991 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1992 else
1993 set_bit(STATUS_RF_KILL_HW, &priv->status);
1994
1995 if (iwl_legacy_is_rfkill(priv)) {
1996 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
1997
1998 iwl_legacy_enable_interrupts(priv);
1999 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2000 return 0;
2001 }
2002
2003 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2004
2005 /* must be initialised before iwl_hw_nic_init */
2006 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2007
2008 ret = iwl4965_hw_nic_init(priv);
2009 if (ret) {
2010 IWL_ERR(priv, "Unable to init nic\n");
2011 return ret;
2012 }
2013
2014 /* make sure rfkill handshake bits are cleared */
2015 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2016 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2017 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2018
2019 /* clear (again), then enable host interrupts */
2020 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2021 iwl_legacy_enable_interrupts(priv);
2022
2023 /* really make sure rfkill handshake bits are cleared */
2024 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2025 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2026
2027 /* Copy original ucode data image from disk into backup cache.
2028 * This will be used to initialize the on-board processor's
2029 * data SRAM for a clean start when the runtime program first loads. */
2030 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2031 priv->ucode_data.len);
2032
2033 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2034
2035 /* load bootstrap state machine,
2036 * load bootstrap program into processor's memory,
2037 * prepare to load the "initialize" uCode */
2038 ret = priv->cfg->ops->lib->load_ucode(priv);
2039
2040 if (ret) {
2041 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2042 ret);
2043 continue;
2044 }
2045
2046 /* start card; "initialize" will load runtime ucode */
2047 iwl4965_nic_start(priv);
2048
2049 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2050
2051 return 0;
2052 }
2053
2054 set_bit(STATUS_EXIT_PENDING, &priv->status);
2055 __iwl4965_down(priv);
2056 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2057
2058 /* tried to restart and config the device for as long as our
2059 * patience could withstand */
2060 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2061 return -EIO;
2062}
2063
2064
2065/*****************************************************************************
2066 *
2067 * Workqueue callbacks
2068 *
2069 *****************************************************************************/
2070
2071static void iwl4965_bg_init_alive_start(struct work_struct *data)
2072{
2073 struct iwl_priv *priv =
2074 container_of(data, struct iwl_priv, init_alive_start.work);
2075
2076 mutex_lock(&priv->mutex);
2077 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2078 goto out;
2079
2080 priv->cfg->ops->lib->init_alive_start(priv);
2081out:
2082 mutex_unlock(&priv->mutex);
2083}
2084
2085static void iwl4965_bg_alive_start(struct work_struct *data)
2086{
2087 struct iwl_priv *priv =
2088 container_of(data, struct iwl_priv, alive_start.work);
2089
2090 mutex_lock(&priv->mutex);
2091 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2092 goto out;
2093
2094 iwl4965_alive_start(priv);
2095out:
2096 mutex_unlock(&priv->mutex);
2097}
2098
2099static void iwl4965_bg_run_time_calib_work(struct work_struct *work)
2100{
2101 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2102 run_time_calib_work);
2103
2104 mutex_lock(&priv->mutex);
2105
2106 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2107 test_bit(STATUS_SCANNING, &priv->status)) {
2108 mutex_unlock(&priv->mutex);
2109 return;
2110 }
2111
2112 if (priv->start_calib) {
2113 iwl4965_chain_noise_calibration(priv,
2114 (void *)&priv->_4965.statistics);
2115 iwl4965_sensitivity_calibration(priv,
2116 (void *)&priv->_4965.statistics);
2117 }
2118
2119 mutex_unlock(&priv->mutex);
2120}
2121
2122static void iwl4965_bg_restart(struct work_struct *data)
2123{
2124 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2125
2126 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2127 return;
2128
2129 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2130 struct iwl_rxon_context *ctx;
2131
2132 mutex_lock(&priv->mutex);
2133 for_each_context(priv, ctx)
2134 ctx->vif = NULL;
2135 priv->is_open = 0;
2136
2137 __iwl4965_down(priv);
2138
2139 mutex_unlock(&priv->mutex);
2140 iwl4965_cancel_deferred_work(priv);
2141 ieee80211_restart_hw(priv->hw);
2142 } else {
2143 iwl4965_down(priv);
2144
2145 mutex_lock(&priv->mutex);
2146 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2147 mutex_unlock(&priv->mutex);
2148 return;
2149 }
2150
2151 __iwl4965_up(priv);
2152 mutex_unlock(&priv->mutex);
2153 }
2154}
2155
2156static void iwl4965_bg_rx_replenish(struct work_struct *data)
2157{
2158 struct iwl_priv *priv =
2159 container_of(data, struct iwl_priv, rx_replenish);
2160
2161 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2162 return;
2163
2164 mutex_lock(&priv->mutex);
2165 iwl4965_rx_replenish(priv);
2166 mutex_unlock(&priv->mutex);
2167}
2168
2169/*****************************************************************************
2170 *
2171 * mac80211 entry point functions
2172 *
2173 *****************************************************************************/
2174
2175#define UCODE_READY_TIMEOUT (4 * HZ)
2176
2177/*
2178 * Not a mac80211 entry point function, but it fits in with all the
2179 * other mac80211 functions grouped here.
2180 */
2181static int iwl4965_mac_setup_register(struct iwl_priv *priv,
2182 u32 max_probe_length)
2183{
2184 int ret;
2185 struct ieee80211_hw *hw = priv->hw;
2186 struct iwl_rxon_context *ctx;
2187
2188 hw->rate_control_algorithm = "iwl-4965-rs";
2189
2190 /* Tell mac80211 our characteristics */
2191 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2192 IEEE80211_HW_AMPDU_AGGREGATION |
2193 IEEE80211_HW_NEED_DTIM_PERIOD |
2194 IEEE80211_HW_SPECTRUM_MGMT |
2195 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2196
2197 if (priv->cfg->sku & IWL_SKU_N)
2198 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2199 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2200
2201 hw->sta_data_size = sizeof(struct iwl_station_priv);
2202 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2203
2204 for_each_context(priv, ctx) {
2205 hw->wiphy->interface_modes |= ctx->interface_modes;
2206 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2207 }
2208
2209 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2210 WIPHY_FLAG_DISABLE_BEACON_HINTS;
2211
2212 /*
2213 * For now, disable PS by default because it affects
2214 * RX performance significantly.
2215 */
2216 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2217
2218 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2219 /* we create the 802.11 header and a zero-length SSID element */
2220 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
2221
2222 /* Default value; 4 EDCA QOS priorities */
2223 hw->queues = 4;
2224
2225 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2226
2227 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2228 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2229 &priv->bands[IEEE80211_BAND_2GHZ];
2230 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2231 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2232 &priv->bands[IEEE80211_BAND_5GHZ];
2233
2234 iwl_legacy_leds_init(priv);
2235
2236 ret = ieee80211_register_hw(priv->hw);
2237 if (ret) {
2238 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2239 return ret;
2240 }
2241 priv->mac80211_registered = 1;
2242
2243 return 0;
2244}
2245
2246
2247int iwl4965_mac_start(struct ieee80211_hw *hw)
2248{
2249 struct iwl_priv *priv = hw->priv;
2250 int ret;
2251
2252 IWL_DEBUG_MAC80211(priv, "enter\n");
2253
2254 /* we should be verifying the device is ready to be opened */
2255 mutex_lock(&priv->mutex);
2256 ret = __iwl4965_up(priv);
2257 mutex_unlock(&priv->mutex);
2258
2259 if (ret)
2260 return ret;
2261
2262 if (iwl_legacy_is_rfkill(priv))
2263 goto out;
2264
2265 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2266
2267 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2268 * mac80211 will not be run successfully. */
2269 ret = wait_event_timeout(priv->wait_command_queue,
2270 test_bit(STATUS_READY, &priv->status),
2271 UCODE_READY_TIMEOUT);
2272 if (!ret) {
2273 if (!test_bit(STATUS_READY, &priv->status)) {
2274 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2275 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2276 return -ETIMEDOUT;
2277 }
2278 }
2279
2280 iwl4965_led_enable(priv);
2281
2282out:
2283 priv->is_open = 1;
2284 IWL_DEBUG_MAC80211(priv, "leave\n");
2285 return 0;
2286}
2287
2288void iwl4965_mac_stop(struct ieee80211_hw *hw)
2289{
2290 struct iwl_priv *priv = hw->priv;
2291
2292 IWL_DEBUG_MAC80211(priv, "enter\n");
2293
2294 if (!priv->is_open)
2295 return;
2296
2297 priv->is_open = 0;
2298
2299 iwl4965_down(priv);
2300
2301 flush_workqueue(priv->workqueue);
2302
2303 /* User space software may expect getting rfkill changes
2304 * even if interface is down */
2305 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2306 iwl_legacy_enable_rfkill_int(priv);
2307
2308 IWL_DEBUG_MAC80211(priv, "leave\n");
2309}
2310
2311void iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2312{
2313 struct iwl_priv *priv = hw->priv;
2314
2315 IWL_DEBUG_MACDUMP(priv, "enter\n");
2316
2317 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2318 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2319
2320 if (iwl4965_tx_skb(priv, skb))
2321 dev_kfree_skb_any(skb);
2322
2323 IWL_DEBUG_MACDUMP(priv, "leave\n");
2324}
2325
2326void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw,
2327 struct ieee80211_vif *vif,
2328 struct ieee80211_key_conf *keyconf,
2329 struct ieee80211_sta *sta,
2330 u32 iv32, u16 *phase1key)
2331{
2332 struct iwl_priv *priv = hw->priv;
2333 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2334
2335 IWL_DEBUG_MAC80211(priv, "enter\n");
2336
2337 iwl4965_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2338 iv32, phase1key);
2339
2340 IWL_DEBUG_MAC80211(priv, "leave\n");
2341}
2342
2343int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2344 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2345 struct ieee80211_key_conf *key)
2346{
2347 struct iwl_priv *priv = hw->priv;
2348 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2349 struct iwl_rxon_context *ctx = vif_priv->ctx;
2350 int ret;
2351 u8 sta_id;
2352 bool is_default_wep_key = false;
2353
2354 IWL_DEBUG_MAC80211(priv, "enter\n");
2355
2356 if (priv->cfg->mod_params->sw_crypto) {
2357 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2358 return -EOPNOTSUPP;
2359 }
2360
2361 sta_id = iwl_legacy_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
2362 if (sta_id == IWL_INVALID_STATION)
2363 return -EINVAL;
2364
2365 mutex_lock(&priv->mutex);
2366 iwl_legacy_scan_cancel_timeout(priv, 100);
2367
2368 /*
2369 * If we are getting WEP group key and we didn't receive any key mapping
2370 * so far, we are in legacy wep mode (group key only), otherwise we are
2371 * in 1X mode.
2372 * In legacy wep mode, we use another host command to the uCode.
2373 */
2374 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2375 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2376 !sta) {
2377 if (cmd == SET_KEY)
2378 is_default_wep_key = !ctx->key_mapping_keys;
2379 else
2380 is_default_wep_key =
2381 (key->hw_key_idx == HW_KEY_DEFAULT);
2382 }
2383
2384 switch (cmd) {
2385 case SET_KEY:
2386 if (is_default_wep_key)
2387 ret = iwl4965_set_default_wep_key(priv,
2388 vif_priv->ctx, key);
2389 else
2390 ret = iwl4965_set_dynamic_key(priv, vif_priv->ctx,
2391 key, sta_id);
2392
2393 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2394 break;
2395 case DISABLE_KEY:
2396 if (is_default_wep_key)
2397 ret = iwl4965_remove_default_wep_key(priv, ctx, key);
2398 else
2399 ret = iwl4965_remove_dynamic_key(priv, ctx,
2400 key, sta_id);
2401
2402 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2403 break;
2404 default:
2405 ret = -EINVAL;
2406 }
2407
2408 mutex_unlock(&priv->mutex);
2409 IWL_DEBUG_MAC80211(priv, "leave\n");
2410
2411 return ret;
2412}
2413
2414int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
2415 struct ieee80211_vif *vif,
2416 enum ieee80211_ampdu_mlme_action action,
2417 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2418 u8 buf_size)
2419{
2420 struct iwl_priv *priv = hw->priv;
2421 int ret = -EINVAL;
2422
2423 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2424 sta->addr, tid);
2425
2426 if (!(priv->cfg->sku & IWL_SKU_N))
2427 return -EACCES;
2428
2429 mutex_lock(&priv->mutex);
2430
2431 switch (action) {
2432 case IEEE80211_AMPDU_RX_START:
2433 IWL_DEBUG_HT(priv, "start Rx\n");
2434 ret = iwl4965_sta_rx_agg_start(priv, sta, tid, *ssn);
2435 break;
2436 case IEEE80211_AMPDU_RX_STOP:
2437 IWL_DEBUG_HT(priv, "stop Rx\n");
2438 ret = iwl4965_sta_rx_agg_stop(priv, sta, tid);
2439 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2440 ret = 0;
2441 break;
2442 case IEEE80211_AMPDU_TX_START:
2443 IWL_DEBUG_HT(priv, "start Tx\n");
2444 ret = iwl4965_tx_agg_start(priv, vif, sta, tid, ssn);
2445 break;
2446 case IEEE80211_AMPDU_TX_STOP:
2447 IWL_DEBUG_HT(priv, "stop Tx\n");
2448 ret = iwl4965_tx_agg_stop(priv, vif, sta, tid);
2449 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2450 ret = 0;
2451 break;
2452 case IEEE80211_AMPDU_TX_OPERATIONAL:
2453 ret = 0;
2454 break;
2455 }
2456 mutex_unlock(&priv->mutex);
2457
2458 return ret;
2459}
2460
2461int iwl4965_mac_sta_add(struct ieee80211_hw *hw,
2462 struct ieee80211_vif *vif,
2463 struct ieee80211_sta *sta)
2464{
2465 struct iwl_priv *priv = hw->priv;
2466 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
2467 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2468 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2469 int ret;
2470 u8 sta_id;
2471
2472 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
2473 sta->addr);
2474 mutex_lock(&priv->mutex);
2475 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
2476 sta->addr);
2477 sta_priv->common.sta_id = IWL_INVALID_STATION;
2478
2479 atomic_set(&sta_priv->pending_frames, 0);
2480
2481 ret = iwl_legacy_add_station_common(priv, vif_priv->ctx, sta->addr,
2482 is_ap, sta, &sta_id);
2483 if (ret) {
2484 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
2485 sta->addr, ret);
2486 /* Should we return success if return code is EEXIST ? */
2487 mutex_unlock(&priv->mutex);
2488 return ret;
2489 }
2490
2491 sta_priv->common.sta_id = sta_id;
2492
2493 /* Initialize rate scaling */
2494 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
2495 sta->addr);
2496 iwl4965_rs_rate_init(priv, sta, sta_id);
2497 mutex_unlock(&priv->mutex);
2498
2499 return 0;
2500}
2501
2502void iwl4965_mac_channel_switch(struct ieee80211_hw *hw,
2503 struct ieee80211_channel_switch *ch_switch)
2504{
2505 struct iwl_priv *priv = hw->priv;
2506 const struct iwl_channel_info *ch_info;
2507 struct ieee80211_conf *conf = &hw->conf;
2508 struct ieee80211_channel *channel = ch_switch->channel;
2509 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
2510
2511 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2512 u16 ch;
2513
2514 IWL_DEBUG_MAC80211(priv, "enter\n");
2515
2516 mutex_lock(&priv->mutex);
2517
2518 if (iwl_legacy_is_rfkill(priv))
2519 goto out;
2520
2521 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2522 test_bit(STATUS_SCANNING, &priv->status) ||
2523 test_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
2524 goto out;
2525
2526 if (!iwl_legacy_is_associated_ctx(ctx))
2527 goto out;
2528
2529 if (!priv->cfg->ops->lib->set_channel_switch)
2530 goto out;
2531
2532 ch = channel->hw_value;
2533 if (le16_to_cpu(ctx->active.channel) == ch)
2534 goto out;
2535
2536 ch_info = iwl_legacy_get_channel_info(priv, channel->band, ch);
2537 if (!iwl_legacy_is_channel_valid(ch_info)) {
2538 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
2539 goto out;
2540 }
2541
2542 spin_lock_irq(&priv->lock);
2543
2544 priv->current_ht_config.smps = conf->smps_mode;
2545
2546 /* Configure HT40 channels */
2547 ctx->ht.enabled = conf_is_ht(conf);
2548 if (ctx->ht.enabled) {
2549 if (conf_is_ht40_minus(conf)) {
2550 ctx->ht.extension_chan_offset =
2551 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2552 ctx->ht.is_40mhz = true;
2553 } else if (conf_is_ht40_plus(conf)) {
2554 ctx->ht.extension_chan_offset =
2555 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2556 ctx->ht.is_40mhz = true;
2557 } else {
2558 ctx->ht.extension_chan_offset =
2559 IEEE80211_HT_PARAM_CHA_SEC_NONE;
2560 ctx->ht.is_40mhz = false;
2561 }
2562 } else
2563 ctx->ht.is_40mhz = false;
2564
2565 if ((le16_to_cpu(ctx->staging.channel) != ch))
2566 ctx->staging.flags = 0;
2567
2568 iwl_legacy_set_rxon_channel(priv, channel, ctx);
2569 iwl_legacy_set_rxon_ht(priv, ht_conf);
2570 iwl_legacy_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
2571
2572 spin_unlock_irq(&priv->lock);
2573
2574 iwl_legacy_set_rate(priv);
2575 /*
2576 * at this point, staging_rxon has the
2577 * configuration for channel switch
2578 */
2579 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2580 priv->switch_channel = cpu_to_le16(ch);
2581 if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
2582 clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2583 priv->switch_channel = 0;
2584 ieee80211_chswitch_done(ctx->vif, false);
2585 }
2586
2587out:
2588 mutex_unlock(&priv->mutex);
2589 IWL_DEBUG_MAC80211(priv, "leave\n");
2590}
2591
2592void iwl4965_configure_filter(struct ieee80211_hw *hw,
2593 unsigned int changed_flags,
2594 unsigned int *total_flags,
2595 u64 multicast)
2596{
2597 struct iwl_priv *priv = hw->priv;
2598 __le32 filter_or = 0, filter_nand = 0;
2599 struct iwl_rxon_context *ctx;
2600
2601#define CHK(test, flag) do { \
2602 if (*total_flags & (test)) \
2603 filter_or |= (flag); \
2604 else \
2605 filter_nand |= (flag); \
2606 } while (0)
2607
2608 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
2609 changed_flags, *total_flags);
2610
2611 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
2612 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
2613 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
2614 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
2615
2616#undef CHK
2617
2618 mutex_lock(&priv->mutex);
2619
2620 for_each_context(priv, ctx) {
2621 ctx->staging.filter_flags &= ~filter_nand;
2622 ctx->staging.filter_flags |= filter_or;
2623
2624 /*
2625 * Not committing directly because hardware can perform a scan,
2626 * but we'll eventually commit the filter flags change anyway.
2627 */
2628 }
2629
2630 mutex_unlock(&priv->mutex);
2631
2632 /*
2633 * Receiving all multicast frames is always enabled by the
2634 * default flags setup in iwl_legacy_connection_init_rx_config()
2635 * since we currently do not support programming multicast
2636 * filters into the device.
2637 */
2638 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
2639 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
2640}
2641
2642/*****************************************************************************
2643 *
2644 * driver setup and teardown
2645 *
2646 *****************************************************************************/
2647
2648static void iwl4965_bg_txpower_work(struct work_struct *work)
2649{
2650 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2651 txpower_work);
2652
2653 mutex_lock(&priv->mutex);
2654
2655 /* If a scan happened to start before we got here
2656 * then just return; the statistics notification will
2657 * kick off another scheduled work to compensate for
2658 * any temperature delta we missed here. */
2659 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2660 test_bit(STATUS_SCANNING, &priv->status))
2661 goto out;
2662
2663 /* Regardless of if we are associated, we must reconfigure the
2664 * TX power since frames can be sent on non-radar channels while
2665 * not associated */
2666 priv->cfg->ops->lib->send_tx_power(priv);
2667
2668 /* Update last_temperature to keep is_calib_needed from running
2669 * when it isn't needed... */
2670 priv->last_temperature = priv->temperature;
2671out:
2672 mutex_unlock(&priv->mutex);
2673}
2674
2675static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2676{
2677 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
2678
2679 init_waitqueue_head(&priv->wait_command_queue);
2680
2681 INIT_WORK(&priv->restart, iwl4965_bg_restart);
2682 INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish);
2683 INIT_WORK(&priv->run_time_calib_work, iwl4965_bg_run_time_calib_work);
2684 INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start);
2685 INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start);
2686
2687 iwl_legacy_setup_scan_deferred_work(priv);
2688
2689 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2690
2691 init_timer(&priv->statistics_periodic);
2692 priv->statistics_periodic.data = (unsigned long)priv;
2693 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
2694
2695 init_timer(&priv->watchdog);
2696 priv->watchdog.data = (unsigned long)priv;
2697 priv->watchdog.function = iwl_legacy_bg_watchdog;
2698
2699 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2700 iwl4965_irq_tasklet, (unsigned long)priv);
2701}
2702
2703static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2704{
2705 cancel_work_sync(&priv->txpower_work);
2706 cancel_delayed_work_sync(&priv->init_alive_start);
2707 cancel_delayed_work(&priv->alive_start);
2708 cancel_work_sync(&priv->run_time_calib_work);
2709
2710 iwl_legacy_cancel_scan_deferred_work(priv);
2711
2712 del_timer_sync(&priv->statistics_periodic);
2713}
2714
2715static void iwl4965_init_hw_rates(struct iwl_priv *priv,
2716 struct ieee80211_rate *rates)
2717{
2718 int i;
2719
2720 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
2721 rates[i].bitrate = iwlegacy_rates[i].ieee * 5;
2722 rates[i].hw_value = i; /* Rate scaling will work on indexes */
2723 rates[i].hw_value_short = i;
2724 rates[i].flags = 0;
2725 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
2726 /*
2727 * If CCK != 1M then set short preamble rate flag.
2728 */
2729 rates[i].flags |=
2730 (iwlegacy_rates[i].plcp == IWL_RATE_1M_PLCP) ?
2731 0 : IEEE80211_RATE_SHORT_PREAMBLE;
2732 }
2733 }
2734}
2735/*
2736 * Acquire priv->lock before calling this function !
2737 */
2738void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
2739{
2740 iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR,
2741 (index & 0xff) | (txq_id << 8));
2742 iwl_legacy_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
2743}
2744
2745void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
2746 struct iwl_tx_queue *txq,
2747 int tx_fifo_id, int scd_retry)
2748{
2749 int txq_id = txq->q.id;
2750
2751 /* Find out whether to activate Tx queue */
2752 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
2753
2754 /* Set up and activate */
2755 iwl_legacy_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
2756 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2757 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
2758 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
2759 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
2760 IWL49_SCD_QUEUE_STTS_REG_MSK);
2761
2762 txq->sched_retry = scd_retry;
2763
2764 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
2765 active ? "Activate" : "Deactivate",
2766 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
2767}
2768
2769
2770static int iwl4965_init_drv(struct iwl_priv *priv)
2771{
2772 int ret;
2773
2774 spin_lock_init(&priv->sta_lock);
2775 spin_lock_init(&priv->hcmd_lock);
2776
2777 INIT_LIST_HEAD(&priv->free_frames);
2778
2779 mutex_init(&priv->mutex);
2780
2781 priv->ieee_channels = NULL;
2782 priv->ieee_rates = NULL;
2783 priv->band = IEEE80211_BAND_2GHZ;
2784
2785 priv->iw_mode = NL80211_IFTYPE_STATION;
2786 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
2787 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
2788
2789 /* initialize force reset */
2790 priv->force_reset.reset_duration = IWL_DELAY_NEXT_FORCE_FW_RELOAD;
2791
2792 /* Choose which receivers/antennas to use */
2793 if (priv->cfg->ops->hcmd->set_rxon_chain)
2794 priv->cfg->ops->hcmd->set_rxon_chain(priv,
2795 &priv->contexts[IWL_RXON_CTX_BSS]);
2796
2797 iwl_legacy_init_scan_params(priv);
2798
2799 ret = iwl_legacy_init_channel_map(priv);
2800 if (ret) {
2801 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
2802 goto err;
2803 }
2804
2805 ret = iwl_legacy_init_geos(priv);
2806 if (ret) {
2807 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
2808 goto err_free_channel_map;
2809 }
2810 iwl4965_init_hw_rates(priv, priv->ieee_rates);
2811
2812 return 0;
2813
2814err_free_channel_map:
2815 iwl_legacy_free_channel_map(priv);
2816err:
2817 return ret;
2818}
2819
2820static void iwl4965_uninit_drv(struct iwl_priv *priv)
2821{
2822 iwl4965_calib_free_results(priv);
2823 iwl_legacy_free_geos(priv);
2824 iwl_legacy_free_channel_map(priv);
2825 kfree(priv->scan_cmd);
2826}
2827
2828static void iwl4965_hw_detect(struct iwl_priv *priv)
2829{
2830 priv->hw_rev = _iwl_legacy_read32(priv, CSR_HW_REV);
2831 priv->hw_wa_rev = _iwl_legacy_read32(priv, CSR_HW_REV_WA_REG);
2832 priv->rev_id = priv->pci_dev->revision;
2833 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
2834}
2835
2836static int iwl4965_set_hw_params(struct iwl_priv *priv)
2837{
2838 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2839 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2840 if (priv->cfg->mod_params->amsdu_size_8K)
2841 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
2842 else
2843 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
2844
2845 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
2846
2847 if (priv->cfg->mod_params->disable_11n)
2848 priv->cfg->sku &= ~IWL_SKU_N;
2849
2850 /* Device-specific setup */
2851 return priv->cfg->ops->lib->set_hw_params(priv);
2852}
2853
2854static const u8 iwl4965_bss_ac_to_fifo[] = {
2855 IWL_TX_FIFO_VO,
2856 IWL_TX_FIFO_VI,
2857 IWL_TX_FIFO_BE,
2858 IWL_TX_FIFO_BK,
2859};
2860
2861static const u8 iwl4965_bss_ac_to_queue[] = {
2862 0, 1, 2, 3,
2863};
2864
2865static int
2866iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2867{
2868 int err = 0, i;
2869 struct iwl_priv *priv;
2870 struct ieee80211_hw *hw;
2871 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
2872 unsigned long flags;
2873 u16 pci_cmd;
2874
2875 /************************
2876 * 1. Allocating HW data
2877 ************************/
2878
2879 hw = iwl_legacy_alloc_all(cfg);
2880 if (!hw) {
2881 err = -ENOMEM;
2882 goto out;
2883 }
2884 priv = hw->priv;
2885 /* At this point both hw and priv are allocated. */
2886
2887 /*
2888 * The default context is always valid,
2889 * more may be discovered when firmware
2890 * is loaded.
2891 */
2892 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
2893
2894 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
2895 priv->contexts[i].ctxid = i;
2896
2897 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
2898 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
2899 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
2900 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
2901 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
2902 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2903 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
2904 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
2905 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwl4965_bss_ac_to_fifo;
2906 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwl4965_bss_ac_to_queue;
2907 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
2908 BIT(NL80211_IFTYPE_ADHOC);
2909 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
2910 BIT(NL80211_IFTYPE_STATION);
2911 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
2912 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
2913 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
2914 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
2915
2916 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 1);
2917
2918 SET_IEEE80211_DEV(hw, &pdev->dev);
2919
2920 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
2921 priv->cfg = cfg;
2922 priv->pci_dev = pdev;
2923 priv->inta_mask = CSR_INI_SET_MASK;
2924
2925 if (iwl_legacy_alloc_traffic_mem(priv))
2926 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
2927
2928 /**************************
2929 * 2. Initializing PCI bus
2930 **************************/
2931 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2932 PCIE_LINK_STATE_CLKPM);
2933
2934 if (pci_enable_device(pdev)) {
2935 err = -ENODEV;
2936 goto out_ieee80211_free_hw;
2937 }
2938
2939 pci_set_master(pdev);
2940
2941 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2942 if (!err)
2943 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2944 if (err) {
2945 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2946 if (!err)
2947 err = pci_set_consistent_dma_mask(pdev,
2948 DMA_BIT_MASK(32));
2949 /* both attempts failed: */
2950 if (err) {
2951 IWL_WARN(priv, "No suitable DMA available.\n");
2952 goto out_pci_disable_device;
2953 }
2954 }
2955
2956 err = pci_request_regions(pdev, DRV_NAME);
2957 if (err)
2958 goto out_pci_disable_device;
2959
2960 pci_set_drvdata(pdev, priv);
2961
2962
2963 /***********************
2964 * 3. Read REV register
2965 ***********************/
2966 priv->hw_base = pci_iomap(pdev, 0, 0);
2967 if (!priv->hw_base) {
2968 err = -ENODEV;
2969 goto out_pci_release_regions;
2970 }
2971
2972 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
2973 (unsigned long long) pci_resource_len(pdev, 0));
2974 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
2975
2976 /* these spin locks will be used in apm_ops.init and EEPROM access
2977 * we should init now
2978 */
2979 spin_lock_init(&priv->reg_lock);
2980 spin_lock_init(&priv->lock);
2981
2982 /*
2983 * stop and reset the on-board processor just in case it is in a
2984 * strange state ... like being left stranded by a primary kernel
2985 * and this is now the kdump kernel trying to start up
2986 */
2987 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2988
2989 iwl4965_hw_detect(priv);
2990 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
2991 priv->cfg->name, priv->hw_rev);
2992
2993 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2994 * PCI Tx retries from interfering with C3 CPU state */
2995 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2996
2997 iwl4965_prepare_card_hw(priv);
2998 if (!priv->hw_ready) {
2999 IWL_WARN(priv, "Failed, HW not ready\n");
3000 goto out_iounmap;
3001 }
3002
3003 /*****************
3004 * 4. Read EEPROM
3005 *****************/
3006 /* Read the EEPROM */
3007 err = iwl_legacy_eeprom_init(priv);
3008 if (err) {
3009 IWL_ERR(priv, "Unable to init EEPROM\n");
3010 goto out_iounmap;
3011 }
3012 err = iwl4965_eeprom_check_version(priv);
3013 if (err)
3014 goto out_free_eeprom;
3015
3016 if (err)
3017 goto out_free_eeprom;
3018
3019 /* extract MAC Address */
3020 iwl4965_eeprom_get_mac(priv, priv->addresses[0].addr);
3021 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3022 priv->hw->wiphy->addresses = priv->addresses;
3023 priv->hw->wiphy->n_addresses = 1;
3024
3025 /************************
3026 * 5. Setup HW constants
3027 ************************/
3028 if (iwl4965_set_hw_params(priv)) {
3029 IWL_ERR(priv, "failed to set hw parameters\n");
3030 goto out_free_eeprom;
3031 }
3032
3033 /*******************
3034 * 6. Setup priv
3035 *******************/
3036
3037 err = iwl4965_init_drv(priv);
3038 if (err)
3039 goto out_free_eeprom;
3040 /* At this point both hw and priv are initialized. */
3041
3042 /********************
3043 * 7. Setup services
3044 ********************/
3045 spin_lock_irqsave(&priv->lock, flags);
3046 iwl_legacy_disable_interrupts(priv);
3047 spin_unlock_irqrestore(&priv->lock, flags);
3048
3049 pci_enable_msi(priv->pci_dev);
3050
3051 err = request_irq(priv->pci_dev->irq, iwl_legacy_isr,
3052 IRQF_SHARED, DRV_NAME, priv);
3053 if (err) {
3054 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3055 goto out_disable_msi;
3056 }
3057
3058 iwl4965_setup_deferred_work(priv);
3059 iwl4965_setup_rx_handlers(priv);
3060
3061 /*********************************************
3062 * 8. Enable interrupts and read RFKILL state
3063 *********************************************/
3064
3065 /* enable rfkill interrupt: hw bug w/a */
3066 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3067 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3068 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3069 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3070 }
3071
3072 iwl_legacy_enable_rfkill_int(priv);
3073
3074 /* If platform's RF_KILL switch is NOT set to KILL */
3075 if (iwl_read32(priv, CSR_GP_CNTRL) &
3076 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3077 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3078 else
3079 set_bit(STATUS_RF_KILL_HW, &priv->status);
3080
3081 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3082 test_bit(STATUS_RF_KILL_HW, &priv->status));
3083
3084 iwl_legacy_power_initialize(priv);
3085
3086 init_completion(&priv->_4965.firmware_loading_complete);
3087
3088 err = iwl4965_request_firmware(priv, true);
3089 if (err)
3090 goto out_destroy_workqueue;
3091
3092 return 0;
3093
3094 out_destroy_workqueue:
3095 destroy_workqueue(priv->workqueue);
3096 priv->workqueue = NULL;
3097 free_irq(priv->pci_dev->irq, priv);
3098 out_disable_msi:
3099 pci_disable_msi(priv->pci_dev);
3100 iwl4965_uninit_drv(priv);
3101 out_free_eeprom:
3102 iwl_legacy_eeprom_free(priv);
3103 out_iounmap:
3104 pci_iounmap(pdev, priv->hw_base);
3105 out_pci_release_regions:
3106 pci_set_drvdata(pdev, NULL);
3107 pci_release_regions(pdev);
3108 out_pci_disable_device:
3109 pci_disable_device(pdev);
3110 out_ieee80211_free_hw:
3111 iwl_legacy_free_traffic_mem(priv);
3112 ieee80211_free_hw(priv->hw);
3113 out:
3114 return err;
3115}
3116
3117static void __devexit iwl4965_pci_remove(struct pci_dev *pdev)
3118{
3119 struct iwl_priv *priv = pci_get_drvdata(pdev);
3120 unsigned long flags;
3121
3122 if (!priv)
3123 return;
3124
3125 wait_for_completion(&priv->_4965.firmware_loading_complete);
3126
3127 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3128
3129 iwl_legacy_dbgfs_unregister(priv);
3130 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3131
3132 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3133 * to be called and iwl4965_down since we are removing the device
3134 * we need to set STATUS_EXIT_PENDING bit.
3135 */
3136 set_bit(STATUS_EXIT_PENDING, &priv->status);
3137
3138 iwl_legacy_leds_exit(priv);
3139
3140 if (priv->mac80211_registered) {
3141 ieee80211_unregister_hw(priv->hw);
3142 priv->mac80211_registered = 0;
3143 } else {
3144 iwl4965_down(priv);
3145 }
3146
3147 /*
3148 * Make sure device is reset to low power before unloading driver.
3149 * This may be redundant with iwl4965_down(), but there are paths to
3150 * run iwl4965_down() without calling apm_ops.stop(), and there are
3151 * paths to avoid running iwl4965_down() at all before leaving driver.
3152 * This (inexpensive) call *makes sure* device is reset.
3153 */
3154 iwl_legacy_apm_stop(priv);
3155
3156 /* make sure we flush any pending irq or
3157 * tasklet for the driver
3158 */
3159 spin_lock_irqsave(&priv->lock, flags);
3160 iwl_legacy_disable_interrupts(priv);
3161 spin_unlock_irqrestore(&priv->lock, flags);
3162
3163 iwl4965_synchronize_irq(priv);
3164
3165 iwl4965_dealloc_ucode_pci(priv);
3166
3167 if (priv->rxq.bd)
3168 iwl4965_rx_queue_free(priv, &priv->rxq);
3169 iwl4965_hw_txq_ctx_free(priv);
3170
3171 iwl_legacy_eeprom_free(priv);
3172
3173
3174 /*netif_stop_queue(dev); */
3175 flush_workqueue(priv->workqueue);
3176
3177 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3178 * priv->workqueue... so we can't take down the workqueue
3179 * until now... */
3180 destroy_workqueue(priv->workqueue);
3181 priv->workqueue = NULL;
3182 iwl_legacy_free_traffic_mem(priv);
3183
3184 free_irq(priv->pci_dev->irq, priv);
3185 pci_disable_msi(priv->pci_dev);
3186 pci_iounmap(pdev, priv->hw_base);
3187 pci_release_regions(pdev);
3188 pci_disable_device(pdev);
3189 pci_set_drvdata(pdev, NULL);
3190
3191 iwl4965_uninit_drv(priv);
3192
3193 dev_kfree_skb(priv->beacon_skb);
3194
3195 ieee80211_free_hw(priv->hw);
3196}
3197
3198/*
3199 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
3200 * must be called under priv->lock and mac access
3201 */
3202void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
3203{
3204 iwl_legacy_write_prph(priv, IWL49_SCD_TXFACT, mask);
3205}
3206
3207/*****************************************************************************
3208 *
3209 * driver and module entry point
3210 *
3211 *****************************************************************************/
3212
3213/* Hardware specific file defines the PCI IDs table for that hardware module */
3214static DEFINE_PCI_DEVICE_TABLE(iwl4965_hw_card_ids) = {
3215#if defined(CONFIG_IWL4965_MODULE) || defined(CONFIG_IWL4965)
3216 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_cfg)},
3217 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_cfg)},
3218#endif /* CONFIG_IWL4965 */
3219
3220 {0}
3221};
3222MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
3223
3224static struct pci_driver iwl4965_driver = {
3225 .name = DRV_NAME,
3226 .id_table = iwl4965_hw_card_ids,
3227 .probe = iwl4965_pci_probe,
3228 .remove = __devexit_p(iwl4965_pci_remove),
3229 .driver.pm = IWL_LEGACY_PM_OPS,
3230};
3231
3232static int __init iwl4965_init(void)
3233{
3234
3235 int ret;
3236 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3237 pr_info(DRV_COPYRIGHT "\n");
3238
3239 ret = iwl4965_rate_control_register();
3240 if (ret) {
3241 pr_err("Unable to register rate control algorithm: %d\n", ret);
3242 return ret;
3243 }
3244
3245 ret = pci_register_driver(&iwl4965_driver);
3246 if (ret) {
3247 pr_err("Unable to initialize PCI module\n");
3248 goto error_register;
3249 }
3250
3251 return ret;
3252
3253error_register:
3254 iwl4965_rate_control_unregister();
3255 return ret;
3256}
3257
3258static void __exit iwl4965_exit(void)
3259{
3260 pci_unregister_driver(&iwl4965_driver);
3261 iwl4965_rate_control_unregister();
3262}
3263
3264module_exit(iwl4965_exit);
3265module_init(iwl4965_init);
3266
3267#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
3268module_param_named(debug, iwlegacy_debug_level, uint, S_IRUGO | S_IWUSR);
3269MODULE_PARM_DESC(debug, "debug output mask");
3270#endif
3271
3272module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, S_IRUGO);
3273MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
3274module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, S_IRUGO);
3275MODULE_PARM_DESC(queues_num, "number of hw queues.");
3276module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, S_IRUGO);
3277MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
3278module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K,
3279 int, S_IRUGO);
3280MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3281module_param_named(fw_restart, iwl4965_mod_params.restart_fw, int, S_IRUGO);
3282MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");