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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/at803x.c
4 *
5 * Driver for Qualcomm Atheros AR803x PHY
6 *
7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
8 */
9
10#include <linux/phy.h>
11#include <linux/module.h>
12#include <linux/string.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/ethtool_netlink.h>
16#include <linux/of_gpio.h>
17#include <linux/bitfield.h>
18#include <linux/gpio/consumer.h>
19#include <linux/regulator/of_regulator.h>
20#include <linux/regulator/driver.h>
21#include <linux/regulator/consumer.h>
22#include <dt-bindings/net/qca-ar803x.h>
23
24#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
25#define AT803X_SFC_ASSERT_CRS BIT(11)
26#define AT803X_SFC_FORCE_LINK BIT(10)
27#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
28#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
29#define AT803X_SFC_MANUAL_MDIX 0x1
30#define AT803X_SFC_MANUAL_MDI 0x0
31#define AT803X_SFC_SQE_TEST BIT(2)
32#define AT803X_SFC_POLARITY_REVERSAL BIT(1)
33#define AT803X_SFC_DISABLE_JABBER BIT(0)
34
35#define AT803X_SPECIFIC_STATUS 0x11
36#define AT803X_SS_SPEED_MASK (3 << 14)
37#define AT803X_SS_SPEED_1000 (2 << 14)
38#define AT803X_SS_SPEED_100 (1 << 14)
39#define AT803X_SS_SPEED_10 (0 << 14)
40#define AT803X_SS_DUPLEX BIT(13)
41#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
42#define AT803X_SS_MDIX BIT(6)
43
44#define AT803X_INTR_ENABLE 0x12
45#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
46#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
47#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
48#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
49#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
50#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
51#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
52#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
53#define AT803X_INTR_ENABLE_WOL BIT(0)
54
55#define AT803X_INTR_STATUS 0x13
56
57#define AT803X_SMART_SPEED 0x14
58#define AT803X_SMART_SPEED_ENABLE BIT(5)
59#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
60#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
61#define AT803X_CDT 0x16
62#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
63#define AT803X_CDT_ENABLE_TEST BIT(0)
64#define AT803X_CDT_STATUS 0x1c
65#define AT803X_CDT_STATUS_STAT_NORMAL 0
66#define AT803X_CDT_STATUS_STAT_SHORT 1
67#define AT803X_CDT_STATUS_STAT_OPEN 2
68#define AT803X_CDT_STATUS_STAT_FAIL 3
69#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
70#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
71#define AT803X_LED_CONTROL 0x18
72
73#define AT803X_DEVICE_ADDR 0x03
74#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
75#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
76#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
77#define AT803X_REG_CHIP_CONFIG 0x1f
78#define AT803X_BT_BX_REG_SEL 0x8000
79
80#define AT803X_DEBUG_ADDR 0x1D
81#define AT803X_DEBUG_DATA 0x1E
82
83#define AT803X_MODE_CFG_MASK 0x0F
84#define AT803X_MODE_CFG_SGMII 0x01
85
86#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
87#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
88
89#define AT803X_DEBUG_REG_0 0x00
90#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
91
92#define AT803X_DEBUG_REG_5 0x05
93#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
94
95#define AT803X_DEBUG_REG_3C 0x3C
96
97#define AT803X_DEBUG_REG_3D 0x3D
98
99#define AT803X_DEBUG_REG_1F 0x1F
100#define AT803X_DEBUG_PLL_ON BIT(2)
101#define AT803X_DEBUG_RGMII_1V8 BIT(3)
102
103#define MDIO_AZ_DEBUG 0x800D
104
105/* AT803x supports either the XTAL input pad, an internal PLL or the
106 * DSP as clock reference for the clock output pad. The XTAL reference
107 * is only used for 25 MHz output, all other frequencies need the PLL.
108 * The DSP as a clock reference is used in synchronous ethernet
109 * applications.
110 *
111 * By default the PLL is only enabled if there is a link. Otherwise
112 * the PHY will go into low power state and disabled the PLL. You can
113 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
114 * enabled.
115 */
116#define AT803X_MMD7_CLK25M 0x8016
117#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
118#define AT803X_CLK_OUT_25MHZ_XTAL 0
119#define AT803X_CLK_OUT_25MHZ_DSP 1
120#define AT803X_CLK_OUT_50MHZ_PLL 2
121#define AT803X_CLK_OUT_50MHZ_DSP 3
122#define AT803X_CLK_OUT_62_5MHZ_PLL 4
123#define AT803X_CLK_OUT_62_5MHZ_DSP 5
124#define AT803X_CLK_OUT_125MHZ_PLL 6
125#define AT803X_CLK_OUT_125MHZ_DSP 7
126
127/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
128 * but doesn't support choosing between XTAL/PLL and DSP.
129 */
130#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
131
132#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
133#define AT803X_CLK_OUT_STRENGTH_FULL 0
134#define AT803X_CLK_OUT_STRENGTH_HALF 1
135#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
136
137#define AT803X_DEFAULT_DOWNSHIFT 5
138#define AT803X_MIN_DOWNSHIFT 2
139#define AT803X_MAX_DOWNSHIFT 9
140
141#define AT803X_MMD3_SMARTEEE_CTL1 0x805b
142#define AT803X_MMD3_SMARTEEE_CTL2 0x805c
143#define AT803X_MMD3_SMARTEEE_CTL3 0x805d
144#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
145
146#define ATH9331_PHY_ID 0x004dd041
147#define ATH8030_PHY_ID 0x004dd076
148#define ATH8031_PHY_ID 0x004dd074
149#define ATH8032_PHY_ID 0x004dd023
150#define ATH8035_PHY_ID 0x004dd072
151#define AT8030_PHY_ID_MASK 0xffffffef
152
153#define QCA8327_PHY_ID 0x004dd034
154#define QCA8337_PHY_ID 0x004dd036
155#define QCA8K_PHY_ID_MASK 0xffffffff
156
157#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
158
159#define AT803X_PAGE_FIBER 0
160#define AT803X_PAGE_COPPER 1
161
162/* don't turn off internal PLL */
163#define AT803X_KEEP_PLL_ENABLED BIT(0)
164#define AT803X_DISABLE_SMARTEEE BIT(1)
165
166MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
167MODULE_AUTHOR("Matus Ujhelyi");
168MODULE_LICENSE("GPL");
169
170enum stat_access_type {
171 PHY,
172 MMD
173};
174
175struct at803x_hw_stat {
176 const char *string;
177 u8 reg;
178 u32 mask;
179 enum stat_access_type access_type;
180};
181
182static struct at803x_hw_stat at803x_hw_stats[] = {
183 { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
184 { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
185 { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
186};
187
188struct at803x_priv {
189 int flags;
190 u16 clk_25m_reg;
191 u16 clk_25m_mask;
192 u8 smarteee_lpi_tw_1g;
193 u8 smarteee_lpi_tw_100m;
194 struct regulator_dev *vddio_rdev;
195 struct regulator_dev *vddh_rdev;
196 struct regulator *vddio;
197 u64 stats[ARRAY_SIZE(at803x_hw_stats)];
198};
199
200struct at803x_context {
201 u16 bmcr;
202 u16 advertise;
203 u16 control1000;
204 u16 int_enable;
205 u16 smart_speed;
206 u16 led_control;
207};
208
209static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
210{
211 int ret;
212
213 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
214 if (ret < 0)
215 return ret;
216
217 return phy_write(phydev, AT803X_DEBUG_DATA, data);
218}
219
220static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
221{
222 int ret;
223
224 ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
225 if (ret < 0)
226 return ret;
227
228 return phy_read(phydev, AT803X_DEBUG_DATA);
229}
230
231static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
232 u16 clear, u16 set)
233{
234 u16 val;
235 int ret;
236
237 ret = at803x_debug_reg_read(phydev, reg);
238 if (ret < 0)
239 return ret;
240
241 val = ret & 0xffff;
242 val &= ~clear;
243 val |= set;
244
245 return phy_write(phydev, AT803X_DEBUG_DATA, val);
246}
247
248static int at803x_write_page(struct phy_device *phydev, int page)
249{
250 int mask;
251 int set;
252
253 if (page == AT803X_PAGE_COPPER) {
254 set = AT803X_BT_BX_REG_SEL;
255 mask = 0;
256 } else {
257 set = 0;
258 mask = AT803X_BT_BX_REG_SEL;
259 }
260
261 return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
262}
263
264static int at803x_read_page(struct phy_device *phydev)
265{
266 int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
267
268 if (ccr < 0)
269 return ccr;
270
271 if (ccr & AT803X_BT_BX_REG_SEL)
272 return AT803X_PAGE_COPPER;
273
274 return AT803X_PAGE_FIBER;
275}
276
277static int at803x_enable_rx_delay(struct phy_device *phydev)
278{
279 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
280 AT803X_DEBUG_RX_CLK_DLY_EN);
281}
282
283static int at803x_enable_tx_delay(struct phy_device *phydev)
284{
285 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
286 AT803X_DEBUG_TX_CLK_DLY_EN);
287}
288
289static int at803x_disable_rx_delay(struct phy_device *phydev)
290{
291 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
292 AT803X_DEBUG_RX_CLK_DLY_EN, 0);
293}
294
295static int at803x_disable_tx_delay(struct phy_device *phydev)
296{
297 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
298 AT803X_DEBUG_TX_CLK_DLY_EN, 0);
299}
300
301/* save relevant PHY registers to private copy */
302static void at803x_context_save(struct phy_device *phydev,
303 struct at803x_context *context)
304{
305 context->bmcr = phy_read(phydev, MII_BMCR);
306 context->advertise = phy_read(phydev, MII_ADVERTISE);
307 context->control1000 = phy_read(phydev, MII_CTRL1000);
308 context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
309 context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
310 context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
311}
312
313/* restore relevant PHY registers from private copy */
314static void at803x_context_restore(struct phy_device *phydev,
315 const struct at803x_context *context)
316{
317 phy_write(phydev, MII_BMCR, context->bmcr);
318 phy_write(phydev, MII_ADVERTISE, context->advertise);
319 phy_write(phydev, MII_CTRL1000, context->control1000);
320 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
321 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
322 phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
323}
324
325static int at803x_set_wol(struct phy_device *phydev,
326 struct ethtool_wolinfo *wol)
327{
328 struct net_device *ndev = phydev->attached_dev;
329 const u8 *mac;
330 int ret;
331 u32 value;
332 unsigned int i, offsets[] = {
333 AT803X_LOC_MAC_ADDR_32_47_OFFSET,
334 AT803X_LOC_MAC_ADDR_16_31_OFFSET,
335 AT803X_LOC_MAC_ADDR_0_15_OFFSET,
336 };
337
338 if (!ndev)
339 return -ENODEV;
340
341 if (wol->wolopts & WAKE_MAGIC) {
342 mac = (const u8 *) ndev->dev_addr;
343
344 if (!is_valid_ether_addr(mac))
345 return -EINVAL;
346
347 for (i = 0; i < 3; i++)
348 phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
349 mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
350
351 value = phy_read(phydev, AT803X_INTR_ENABLE);
352 value |= AT803X_INTR_ENABLE_WOL;
353 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
354 if (ret)
355 return ret;
356 value = phy_read(phydev, AT803X_INTR_STATUS);
357 } else {
358 value = phy_read(phydev, AT803X_INTR_ENABLE);
359 value &= (~AT803X_INTR_ENABLE_WOL);
360 ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
361 if (ret)
362 return ret;
363 value = phy_read(phydev, AT803X_INTR_STATUS);
364 }
365
366 return ret;
367}
368
369static void at803x_get_wol(struct phy_device *phydev,
370 struct ethtool_wolinfo *wol)
371{
372 u32 value;
373
374 wol->supported = WAKE_MAGIC;
375 wol->wolopts = 0;
376
377 value = phy_read(phydev, AT803X_INTR_ENABLE);
378 if (value & AT803X_INTR_ENABLE_WOL)
379 wol->wolopts |= WAKE_MAGIC;
380}
381
382static int at803x_get_sset_count(struct phy_device *phydev)
383{
384 return ARRAY_SIZE(at803x_hw_stats);
385}
386
387static void at803x_get_strings(struct phy_device *phydev, u8 *data)
388{
389 int i;
390
391 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {
392 strscpy(data + i * ETH_GSTRING_LEN,
393 at803x_hw_stats[i].string, ETH_GSTRING_LEN);
394 }
395}
396
397static u64 at803x_get_stat(struct phy_device *phydev, int i)
398{
399 struct at803x_hw_stat stat = at803x_hw_stats[i];
400 struct at803x_priv *priv = phydev->priv;
401 int val;
402 u64 ret;
403
404 if (stat.access_type == MMD)
405 val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
406 else
407 val = phy_read(phydev, stat.reg);
408
409 if (val < 0) {
410 ret = U64_MAX;
411 } else {
412 val = val & stat.mask;
413 priv->stats[i] += val;
414 ret = priv->stats[i];
415 }
416
417 return ret;
418}
419
420static void at803x_get_stats(struct phy_device *phydev,
421 struct ethtool_stats *stats, u64 *data)
422{
423 int i;
424
425 for (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)
426 data[i] = at803x_get_stat(phydev, i);
427}
428
429static int at803x_suspend(struct phy_device *phydev)
430{
431 int value;
432 int wol_enabled;
433
434 value = phy_read(phydev, AT803X_INTR_ENABLE);
435 wol_enabled = value & AT803X_INTR_ENABLE_WOL;
436
437 if (wol_enabled)
438 value = BMCR_ISOLATE;
439 else
440 value = BMCR_PDOWN;
441
442 phy_modify(phydev, MII_BMCR, 0, value);
443
444 return 0;
445}
446
447static int at803x_resume(struct phy_device *phydev)
448{
449 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
450}
451
452static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
453 unsigned int selector)
454{
455 struct phy_device *phydev = rdev_get_drvdata(rdev);
456
457 if (selector)
458 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
459 0, AT803X_DEBUG_RGMII_1V8);
460 else
461 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
462 AT803X_DEBUG_RGMII_1V8, 0);
463}
464
465static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
466{
467 struct phy_device *phydev = rdev_get_drvdata(rdev);
468 int val;
469
470 val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
471 if (val < 0)
472 return val;
473
474 return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
475}
476
477static const struct regulator_ops vddio_regulator_ops = {
478 .list_voltage = regulator_list_voltage_table,
479 .set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
480 .get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
481};
482
483static const unsigned int vddio_voltage_table[] = {
484 1500000,
485 1800000,
486};
487
488static const struct regulator_desc vddio_desc = {
489 .name = "vddio",
490 .of_match = of_match_ptr("vddio-regulator"),
491 .n_voltages = ARRAY_SIZE(vddio_voltage_table),
492 .volt_table = vddio_voltage_table,
493 .ops = &vddio_regulator_ops,
494 .type = REGULATOR_VOLTAGE,
495 .owner = THIS_MODULE,
496};
497
498static const struct regulator_ops vddh_regulator_ops = {
499};
500
501static const struct regulator_desc vddh_desc = {
502 .name = "vddh",
503 .of_match = of_match_ptr("vddh-regulator"),
504 .n_voltages = 1,
505 .fixed_uV = 2500000,
506 .ops = &vddh_regulator_ops,
507 .type = REGULATOR_VOLTAGE,
508 .owner = THIS_MODULE,
509};
510
511static int at8031_register_regulators(struct phy_device *phydev)
512{
513 struct at803x_priv *priv = phydev->priv;
514 struct device *dev = &phydev->mdio.dev;
515 struct regulator_config config = { };
516
517 config.dev = dev;
518 config.driver_data = phydev;
519
520 priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
521 if (IS_ERR(priv->vddio_rdev)) {
522 phydev_err(phydev, "failed to register VDDIO regulator\n");
523 return PTR_ERR(priv->vddio_rdev);
524 }
525
526 priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
527 if (IS_ERR(priv->vddh_rdev)) {
528 phydev_err(phydev, "failed to register VDDH regulator\n");
529 return PTR_ERR(priv->vddh_rdev);
530 }
531
532 return 0;
533}
534
535static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
536{
537 return (phydev->phy_id & phydev->drv->phy_id_mask)
538 == (phy_id & phydev->drv->phy_id_mask);
539}
540
541static int at803x_parse_dt(struct phy_device *phydev)
542{
543 struct device_node *node = phydev->mdio.dev.of_node;
544 struct at803x_priv *priv = phydev->priv;
545 u32 freq, strength, tw;
546 unsigned int sel;
547 int ret;
548
549 if (!IS_ENABLED(CONFIG_OF_MDIO))
550 return 0;
551
552 if (of_property_read_bool(node, "qca,disable-smarteee"))
553 priv->flags |= AT803X_DISABLE_SMARTEEE;
554
555 if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
556 if (!tw || tw > 255) {
557 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
558 return -EINVAL;
559 }
560 priv->smarteee_lpi_tw_1g = tw;
561 }
562
563 if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
564 if (!tw || tw > 255) {
565 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
566 return -EINVAL;
567 }
568 priv->smarteee_lpi_tw_100m = tw;
569 }
570
571 ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
572 if (!ret) {
573 switch (freq) {
574 case 25000000:
575 sel = AT803X_CLK_OUT_25MHZ_XTAL;
576 break;
577 case 50000000:
578 sel = AT803X_CLK_OUT_50MHZ_PLL;
579 break;
580 case 62500000:
581 sel = AT803X_CLK_OUT_62_5MHZ_PLL;
582 break;
583 case 125000000:
584 sel = AT803X_CLK_OUT_125MHZ_PLL;
585 break;
586 default:
587 phydev_err(phydev, "invalid qca,clk-out-frequency\n");
588 return -EINVAL;
589 }
590
591 priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
592 priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
593
594 /* Fixup for the AR8030/AR8035. This chip has another mask and
595 * doesn't support the DSP reference. Eg. the lowest bit of the
596 * mask. The upper two bits select the same frequencies. Mask
597 * the lowest bit here.
598 *
599 * Warning:
600 * There was no datasheet for the AR8030 available so this is
601 * just a guess. But the AR8035 is listed as pin compatible
602 * to the AR8030 so there might be a good chance it works on
603 * the AR8030 too.
604 */
605 if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) ||
606 at803x_match_phy_id(phydev, ATH8035_PHY_ID)) {
607 priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
608 priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
609 }
610 }
611
612 ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
613 if (!ret) {
614 priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
615 switch (strength) {
616 case AR803X_STRENGTH_FULL:
617 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
618 break;
619 case AR803X_STRENGTH_HALF:
620 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
621 break;
622 case AR803X_STRENGTH_QUARTER:
623 priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
624 break;
625 default:
626 phydev_err(phydev, "invalid qca,clk-out-strength\n");
627 return -EINVAL;
628 }
629 }
630
631 /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
632 * options.
633 */
634 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
635 if (of_property_read_bool(node, "qca,keep-pll-enabled"))
636 priv->flags |= AT803X_KEEP_PLL_ENABLED;
637
638 ret = at8031_register_regulators(phydev);
639 if (ret < 0)
640 return ret;
641
642 priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
643 "vddio");
644 if (IS_ERR(priv->vddio)) {
645 phydev_err(phydev, "failed to get VDDIO regulator\n");
646 return PTR_ERR(priv->vddio);
647 }
648 }
649
650 return 0;
651}
652
653static int at803x_probe(struct phy_device *phydev)
654{
655 struct device *dev = &phydev->mdio.dev;
656 struct at803x_priv *priv;
657 int ret;
658
659 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
660 if (!priv)
661 return -ENOMEM;
662
663 phydev->priv = priv;
664
665 ret = at803x_parse_dt(phydev);
666 if (ret)
667 return ret;
668
669 if (priv->vddio) {
670 ret = regulator_enable(priv->vddio);
671 if (ret < 0)
672 return ret;
673 }
674
675 /* Some bootloaders leave the fiber page selected.
676 * Switch to the copper page, as otherwise we read
677 * the PHY capabilities from the fiber side.
678 */
679 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
680 phy_lock_mdio_bus(phydev);
681 ret = at803x_write_page(phydev, AT803X_PAGE_COPPER);
682 phy_unlock_mdio_bus(phydev);
683 if (ret)
684 goto err;
685 }
686
687 return 0;
688
689err:
690 if (priv->vddio)
691 regulator_disable(priv->vddio);
692
693 return ret;
694}
695
696static void at803x_remove(struct phy_device *phydev)
697{
698 struct at803x_priv *priv = phydev->priv;
699
700 if (priv->vddio)
701 regulator_disable(priv->vddio);
702}
703
704static int at803x_get_features(struct phy_device *phydev)
705{
706 int err;
707
708 err = genphy_read_abilities(phydev);
709 if (err)
710 return err;
711
712 if (!at803x_match_phy_id(phydev, ATH8031_PHY_ID))
713 return 0;
714
715 /* AR8031/AR8033 have different status registers
716 * for copper and fiber operation. However, the
717 * extended status register is the same for both
718 * operation modes.
719 *
720 * As a result of that, ESTATUS_1000_XFULL is set
721 * to 1 even when operating in copper TP mode.
722 *
723 * Remove this mode from the supported link modes,
724 * as this driver currently only supports copper
725 * operation.
726 */
727 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
728 phydev->supported);
729 return 0;
730}
731
732static int at803x_smarteee_config(struct phy_device *phydev)
733{
734 struct at803x_priv *priv = phydev->priv;
735 u16 mask = 0, val = 0;
736 int ret;
737
738 if (priv->flags & AT803X_DISABLE_SMARTEEE)
739 return phy_modify_mmd(phydev, MDIO_MMD_PCS,
740 AT803X_MMD3_SMARTEEE_CTL3,
741 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
742
743 if (priv->smarteee_lpi_tw_1g) {
744 mask |= 0xff00;
745 val |= priv->smarteee_lpi_tw_1g << 8;
746 }
747 if (priv->smarteee_lpi_tw_100m) {
748 mask |= 0x00ff;
749 val |= priv->smarteee_lpi_tw_100m;
750 }
751 if (!mask)
752 return 0;
753
754 ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
755 mask, val);
756 if (ret)
757 return ret;
758
759 return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
760 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
761 AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
762}
763
764static int at803x_clk_out_config(struct phy_device *phydev)
765{
766 struct at803x_priv *priv = phydev->priv;
767
768 if (!priv->clk_25m_mask)
769 return 0;
770
771 return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
772 priv->clk_25m_mask, priv->clk_25m_reg);
773}
774
775static int at8031_pll_config(struct phy_device *phydev)
776{
777 struct at803x_priv *priv = phydev->priv;
778
779 /* The default after hardware reset is PLL OFF. After a soft reset, the
780 * values are retained.
781 */
782 if (priv->flags & AT803X_KEEP_PLL_ENABLED)
783 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
784 0, AT803X_DEBUG_PLL_ON);
785 else
786 return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
787 AT803X_DEBUG_PLL_ON, 0);
788}
789
790static int at803x_config_init(struct phy_device *phydev)
791{
792 int ret;
793
794 /* The RX and TX delay default is:
795 * after HW reset: RX delay enabled and TX delay disabled
796 * after SW reset: RX delay enabled, while TX delay retains the
797 * value before reset.
798 */
799 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
800 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
801 ret = at803x_enable_rx_delay(phydev);
802 else
803 ret = at803x_disable_rx_delay(phydev);
804 if (ret < 0)
805 return ret;
806
807 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
808 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
809 ret = at803x_enable_tx_delay(phydev);
810 else
811 ret = at803x_disable_tx_delay(phydev);
812 if (ret < 0)
813 return ret;
814
815 ret = at803x_smarteee_config(phydev);
816 if (ret < 0)
817 return ret;
818
819 ret = at803x_clk_out_config(phydev);
820 if (ret < 0)
821 return ret;
822
823 if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
824 ret = at8031_pll_config(phydev);
825 if (ret < 0)
826 return ret;
827 }
828
829 /* Ar803x extended next page bit is enabled by default. Cisco
830 * multigig switches read this bit and attempt to negotiate 10Gbps
831 * rates even if the next page bit is disabled. This is incorrect
832 * behaviour but we still need to accommodate it. XNP is only needed
833 * for 10Gbps support, so disable XNP.
834 */
835 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
836}
837
838static int at803x_ack_interrupt(struct phy_device *phydev)
839{
840 int err;
841
842 err = phy_read(phydev, AT803X_INTR_STATUS);
843
844 return (err < 0) ? err : 0;
845}
846
847static int at803x_config_intr(struct phy_device *phydev)
848{
849 int err;
850 int value;
851
852 value = phy_read(phydev, AT803X_INTR_ENABLE);
853
854 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
855 /* Clear any pending interrupts */
856 err = at803x_ack_interrupt(phydev);
857 if (err)
858 return err;
859
860 value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
861 value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
862 value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
863 value |= AT803X_INTR_ENABLE_LINK_FAIL;
864 value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
865
866 err = phy_write(phydev, AT803X_INTR_ENABLE, value);
867 } else {
868 err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
869 if (err)
870 return err;
871
872 /* Clear any pending interrupts */
873 err = at803x_ack_interrupt(phydev);
874 }
875
876 return err;
877}
878
879static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
880{
881 int irq_status, int_enabled;
882
883 irq_status = phy_read(phydev, AT803X_INTR_STATUS);
884 if (irq_status < 0) {
885 phy_error(phydev);
886 return IRQ_NONE;
887 }
888
889 /* Read the current enabled interrupts */
890 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
891 if (int_enabled < 0) {
892 phy_error(phydev);
893 return IRQ_NONE;
894 }
895
896 /* See if this was one of our enabled interrupts */
897 if (!(irq_status & int_enabled))
898 return IRQ_NONE;
899
900 phy_trigger_machine(phydev);
901
902 return IRQ_HANDLED;
903}
904
905static void at803x_link_change_notify(struct phy_device *phydev)
906{
907 /*
908 * Conduct a hardware reset for AT8030 every time a link loss is
909 * signalled. This is necessary to circumvent a hardware bug that
910 * occurs when the cable is unplugged while TX packets are pending
911 * in the FIFO. In such cases, the FIFO enters an error mode it
912 * cannot recover from by software.
913 */
914 if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
915 struct at803x_context context;
916
917 at803x_context_save(phydev, &context);
918
919 phy_device_reset(phydev, 1);
920 msleep(1);
921 phy_device_reset(phydev, 0);
922 msleep(1);
923
924 at803x_context_restore(phydev, &context);
925
926 phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
927 }
928}
929
930static int at803x_read_status(struct phy_device *phydev)
931{
932 int ss, err, old_link = phydev->link;
933
934 /* Update the link, but return if there was an error */
935 err = genphy_update_link(phydev);
936 if (err)
937 return err;
938
939 /* why bother the PHY if nothing can have changed */
940 if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
941 return 0;
942
943 phydev->speed = SPEED_UNKNOWN;
944 phydev->duplex = DUPLEX_UNKNOWN;
945 phydev->pause = 0;
946 phydev->asym_pause = 0;
947
948 err = genphy_read_lpa(phydev);
949 if (err < 0)
950 return err;
951
952 /* Read the AT8035 PHY-Specific Status register, which indicates the
953 * speed and duplex that the PHY is actually using, irrespective of
954 * whether we are in autoneg mode or not.
955 */
956 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
957 if (ss < 0)
958 return ss;
959
960 if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
961 int sfc;
962
963 sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
964 if (sfc < 0)
965 return sfc;
966
967 switch (ss & AT803X_SS_SPEED_MASK) {
968 case AT803X_SS_SPEED_10:
969 phydev->speed = SPEED_10;
970 break;
971 case AT803X_SS_SPEED_100:
972 phydev->speed = SPEED_100;
973 break;
974 case AT803X_SS_SPEED_1000:
975 phydev->speed = SPEED_1000;
976 break;
977 }
978 if (ss & AT803X_SS_DUPLEX)
979 phydev->duplex = DUPLEX_FULL;
980 else
981 phydev->duplex = DUPLEX_HALF;
982
983 if (ss & AT803X_SS_MDIX)
984 phydev->mdix = ETH_TP_MDI_X;
985 else
986 phydev->mdix = ETH_TP_MDI;
987
988 switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
989 case AT803X_SFC_MANUAL_MDI:
990 phydev->mdix_ctrl = ETH_TP_MDI;
991 break;
992 case AT803X_SFC_MANUAL_MDIX:
993 phydev->mdix_ctrl = ETH_TP_MDI_X;
994 break;
995 case AT803X_SFC_AUTOMATIC_CROSSOVER:
996 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
997 break;
998 }
999 }
1000
1001 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1002 phy_resolve_aneg_pause(phydev);
1003
1004 return 0;
1005}
1006
1007static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1008{
1009 u16 val;
1010
1011 switch (ctrl) {
1012 case ETH_TP_MDI:
1013 val = AT803X_SFC_MANUAL_MDI;
1014 break;
1015 case ETH_TP_MDI_X:
1016 val = AT803X_SFC_MANUAL_MDIX;
1017 break;
1018 case ETH_TP_MDI_AUTO:
1019 val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1020 break;
1021 default:
1022 return 0;
1023 }
1024
1025 return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1026 AT803X_SFC_MDI_CROSSOVER_MODE_M,
1027 FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1028}
1029
1030static int at803x_config_aneg(struct phy_device *phydev)
1031{
1032 int ret;
1033
1034 ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1035 if (ret < 0)
1036 return ret;
1037
1038 /* Changes of the midx bits are disruptive to the normal operation;
1039 * therefore any changes to these registers must be followed by a
1040 * software reset to take effect.
1041 */
1042 if (ret == 1) {
1043 ret = genphy_soft_reset(phydev);
1044 if (ret < 0)
1045 return ret;
1046 }
1047
1048 return genphy_config_aneg(phydev);
1049}
1050
1051static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1052{
1053 int val;
1054
1055 val = phy_read(phydev, AT803X_SMART_SPEED);
1056 if (val < 0)
1057 return val;
1058
1059 if (val & AT803X_SMART_SPEED_ENABLE)
1060 *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1061 else
1062 *d = DOWNSHIFT_DEV_DISABLE;
1063
1064 return 0;
1065}
1066
1067static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1068{
1069 u16 mask, set;
1070 int ret;
1071
1072 switch (cnt) {
1073 case DOWNSHIFT_DEV_DEFAULT_COUNT:
1074 cnt = AT803X_DEFAULT_DOWNSHIFT;
1075 fallthrough;
1076 case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1077 set = AT803X_SMART_SPEED_ENABLE |
1078 AT803X_SMART_SPEED_BYPASS_TIMER |
1079 FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1080 mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1081 break;
1082 case DOWNSHIFT_DEV_DISABLE:
1083 set = 0;
1084 mask = AT803X_SMART_SPEED_ENABLE |
1085 AT803X_SMART_SPEED_BYPASS_TIMER;
1086 break;
1087 default:
1088 return -EINVAL;
1089 }
1090
1091 ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1092
1093 /* After changing the smart speed settings, we need to perform a
1094 * software reset, use phy_init_hw() to make sure we set the
1095 * reapply any values which might got lost during software reset.
1096 */
1097 if (ret == 1)
1098 ret = phy_init_hw(phydev);
1099
1100 return ret;
1101}
1102
1103static int at803x_get_tunable(struct phy_device *phydev,
1104 struct ethtool_tunable *tuna, void *data)
1105{
1106 switch (tuna->id) {
1107 case ETHTOOL_PHY_DOWNSHIFT:
1108 return at803x_get_downshift(phydev, data);
1109 default:
1110 return -EOPNOTSUPP;
1111 }
1112}
1113
1114static int at803x_set_tunable(struct phy_device *phydev,
1115 struct ethtool_tunable *tuna, const void *data)
1116{
1117 switch (tuna->id) {
1118 case ETHTOOL_PHY_DOWNSHIFT:
1119 return at803x_set_downshift(phydev, *(const u8 *)data);
1120 default:
1121 return -EOPNOTSUPP;
1122 }
1123}
1124
1125static int at803x_cable_test_result_trans(u16 status)
1126{
1127 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1128 case AT803X_CDT_STATUS_STAT_NORMAL:
1129 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1130 case AT803X_CDT_STATUS_STAT_SHORT:
1131 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1132 case AT803X_CDT_STATUS_STAT_OPEN:
1133 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1134 case AT803X_CDT_STATUS_STAT_FAIL:
1135 default:
1136 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1137 }
1138}
1139
1140static bool at803x_cdt_test_failed(u16 status)
1141{
1142 return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1143 AT803X_CDT_STATUS_STAT_FAIL;
1144}
1145
1146static bool at803x_cdt_fault_length_valid(u16 status)
1147{
1148 switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1149 case AT803X_CDT_STATUS_STAT_OPEN:
1150 case AT803X_CDT_STATUS_STAT_SHORT:
1151 return true;
1152 }
1153 return false;
1154}
1155
1156static int at803x_cdt_fault_length(u16 status)
1157{
1158 int dt;
1159
1160 /* According to the datasheet the distance to the fault is
1161 * DELTA_TIME * 0.824 meters.
1162 *
1163 * The author suspect the correct formula is:
1164 *
1165 * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1166 *
1167 * where c is the speed of light, VF is the velocity factor of
1168 * the twisted pair cable, 125MHz the counter frequency and
1169 * we need to divide by 2 because the hardware will measure the
1170 * round trip time to the fault and back to the PHY.
1171 *
1172 * With a VF of 0.69 we get the factor 0.824 mentioned in the
1173 * datasheet.
1174 */
1175 dt = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, status);
1176
1177 return (dt * 824) / 10;
1178}
1179
1180static int at803x_cdt_start(struct phy_device *phydev, int pair)
1181{
1182 u16 cdt;
1183
1184 cdt = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1185 AT803X_CDT_ENABLE_TEST;
1186
1187 return phy_write(phydev, AT803X_CDT, cdt);
1188}
1189
1190static int at803x_cdt_wait_for_completion(struct phy_device *phydev)
1191{
1192 int val, ret;
1193
1194 /* One test run takes about 25ms */
1195 ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1196 !(val & AT803X_CDT_ENABLE_TEST),
1197 30000, 100000, true);
1198
1199 return ret < 0 ? ret : 0;
1200}
1201
1202static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1203{
1204 static const int ethtool_pair[] = {
1205 ETHTOOL_A_CABLE_PAIR_A,
1206 ETHTOOL_A_CABLE_PAIR_B,
1207 ETHTOOL_A_CABLE_PAIR_C,
1208 ETHTOOL_A_CABLE_PAIR_D,
1209 };
1210 int ret, val;
1211
1212 ret = at803x_cdt_start(phydev, pair);
1213 if (ret)
1214 return ret;
1215
1216 ret = at803x_cdt_wait_for_completion(phydev);
1217 if (ret)
1218 return ret;
1219
1220 val = phy_read(phydev, AT803X_CDT_STATUS);
1221 if (val < 0)
1222 return val;
1223
1224 if (at803x_cdt_test_failed(val))
1225 return 0;
1226
1227 ethnl_cable_test_result(phydev, ethtool_pair[pair],
1228 at803x_cable_test_result_trans(val));
1229
1230 if (at803x_cdt_fault_length_valid(val))
1231 ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1232 at803x_cdt_fault_length(val));
1233
1234 return 1;
1235}
1236
1237static int at803x_cable_test_get_status(struct phy_device *phydev,
1238 bool *finished)
1239{
1240 unsigned long pair_mask;
1241 int retries = 20;
1242 int pair, ret;
1243
1244 if (phydev->phy_id == ATH9331_PHY_ID ||
1245 phydev->phy_id == ATH8032_PHY_ID)
1246 pair_mask = 0x3;
1247 else
1248 pair_mask = 0xf;
1249
1250 *finished = false;
1251
1252 /* According to the datasheet the CDT can be performed when
1253 * there is no link partner or when the link partner is
1254 * auto-negotiating. Starting the test will restart the AN
1255 * automatically. It seems that doing this repeatedly we will
1256 * get a slot where our link partner won't disturb our
1257 * measurement.
1258 */
1259 while (pair_mask && retries--) {
1260 for_each_set_bit(pair, &pair_mask, 4) {
1261 ret = at803x_cable_test_one_pair(phydev, pair);
1262 if (ret < 0)
1263 return ret;
1264 if (ret)
1265 clear_bit(pair, &pair_mask);
1266 }
1267 if (pair_mask)
1268 msleep(250);
1269 }
1270
1271 *finished = true;
1272
1273 return 0;
1274}
1275
1276static int at803x_cable_test_start(struct phy_device *phydev)
1277{
1278 /* Enable auto-negotiation, but advertise no capabilities, no link
1279 * will be established. A restart of the auto-negotiation is not
1280 * required, because the cable test will automatically break the link.
1281 */
1282 phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1283 phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1284 if (phydev->phy_id != ATH9331_PHY_ID &&
1285 phydev->phy_id != ATH8032_PHY_ID)
1286 phy_write(phydev, MII_CTRL1000, 0);
1287
1288 /* we do all the (time consuming) work later */
1289 return 0;
1290}
1291
1292static int qca83xx_config_init(struct phy_device *phydev)
1293{
1294 u8 switch_revision;
1295
1296 switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1297
1298 switch (switch_revision) {
1299 case 1:
1300 /* For 100M waveform */
1301 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);
1302 /* Turn on Gigabit clock */
1303 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);
1304 break;
1305
1306 case 2:
1307 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1308 fallthrough;
1309 case 4:
1310 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1311 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);
1312 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);
1313 at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1314 break;
1315 }
1316
1317 return 0;
1318}
1319
1320static struct phy_driver at803x_driver[] = {
1321{
1322 /* Qualcomm Atheros AR8035 */
1323 PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1324 .name = "Qualcomm Atheros AR8035",
1325 .flags = PHY_POLL_CABLE_TEST,
1326 .probe = at803x_probe,
1327 .remove = at803x_remove,
1328 .config_aneg = at803x_config_aneg,
1329 .config_init = at803x_config_init,
1330 .soft_reset = genphy_soft_reset,
1331 .set_wol = at803x_set_wol,
1332 .get_wol = at803x_get_wol,
1333 .suspend = at803x_suspend,
1334 .resume = at803x_resume,
1335 /* PHY_GBIT_FEATURES */
1336 .read_status = at803x_read_status,
1337 .config_intr = at803x_config_intr,
1338 .handle_interrupt = at803x_handle_interrupt,
1339 .get_tunable = at803x_get_tunable,
1340 .set_tunable = at803x_set_tunable,
1341 .cable_test_start = at803x_cable_test_start,
1342 .cable_test_get_status = at803x_cable_test_get_status,
1343}, {
1344 /* Qualcomm Atheros AR8030 */
1345 .phy_id = ATH8030_PHY_ID,
1346 .name = "Qualcomm Atheros AR8030",
1347 .phy_id_mask = AT8030_PHY_ID_MASK,
1348 .probe = at803x_probe,
1349 .remove = at803x_remove,
1350 .config_init = at803x_config_init,
1351 .link_change_notify = at803x_link_change_notify,
1352 .set_wol = at803x_set_wol,
1353 .get_wol = at803x_get_wol,
1354 .suspend = at803x_suspend,
1355 .resume = at803x_resume,
1356 /* PHY_BASIC_FEATURES */
1357 .config_intr = at803x_config_intr,
1358 .handle_interrupt = at803x_handle_interrupt,
1359}, {
1360 /* Qualcomm Atheros AR8031/AR8033 */
1361 PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1362 .name = "Qualcomm Atheros AR8031/AR8033",
1363 .flags = PHY_POLL_CABLE_TEST,
1364 .probe = at803x_probe,
1365 .remove = at803x_remove,
1366 .config_init = at803x_config_init,
1367 .config_aneg = at803x_config_aneg,
1368 .soft_reset = genphy_soft_reset,
1369 .set_wol = at803x_set_wol,
1370 .get_wol = at803x_get_wol,
1371 .suspend = at803x_suspend,
1372 .resume = at803x_resume,
1373 .read_page = at803x_read_page,
1374 .write_page = at803x_write_page,
1375 .get_features = at803x_get_features,
1376 .read_status = at803x_read_status,
1377 .config_intr = &at803x_config_intr,
1378 .handle_interrupt = at803x_handle_interrupt,
1379 .get_tunable = at803x_get_tunable,
1380 .set_tunable = at803x_set_tunable,
1381 .cable_test_start = at803x_cable_test_start,
1382 .cable_test_get_status = at803x_cable_test_get_status,
1383}, {
1384 /* Qualcomm Atheros AR8032 */
1385 PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1386 .name = "Qualcomm Atheros AR8032",
1387 .probe = at803x_probe,
1388 .remove = at803x_remove,
1389 .flags = PHY_POLL_CABLE_TEST,
1390 .config_init = at803x_config_init,
1391 .link_change_notify = at803x_link_change_notify,
1392 .set_wol = at803x_set_wol,
1393 .get_wol = at803x_get_wol,
1394 .suspend = at803x_suspend,
1395 .resume = at803x_resume,
1396 /* PHY_BASIC_FEATURES */
1397 .config_intr = at803x_config_intr,
1398 .handle_interrupt = at803x_handle_interrupt,
1399 .cable_test_start = at803x_cable_test_start,
1400 .cable_test_get_status = at803x_cable_test_get_status,
1401}, {
1402 /* ATHEROS AR9331 */
1403 PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1404 .name = "Qualcomm Atheros AR9331 built-in PHY",
1405 .suspend = at803x_suspend,
1406 .resume = at803x_resume,
1407 .flags = PHY_POLL_CABLE_TEST,
1408 /* PHY_BASIC_FEATURES */
1409 .config_intr = &at803x_config_intr,
1410 .handle_interrupt = at803x_handle_interrupt,
1411 .cable_test_start = at803x_cable_test_start,
1412 .cable_test_get_status = at803x_cable_test_get_status,
1413 .read_status = at803x_read_status,
1414 .soft_reset = genphy_soft_reset,
1415 .config_aneg = at803x_config_aneg,
1416}, {
1417 /* QCA8337 */
1418 .phy_id = QCA8337_PHY_ID,
1419 .phy_id_mask = QCA8K_PHY_ID_MASK,
1420 .name = "QCA PHY 8337",
1421 /* PHY_GBIT_FEATURES */
1422 .probe = at803x_probe,
1423 .flags = PHY_IS_INTERNAL,
1424 .config_init = qca83xx_config_init,
1425 .soft_reset = genphy_soft_reset,
1426 .get_sset_count = at803x_get_sset_count,
1427 .get_strings = at803x_get_strings,
1428 .get_stats = at803x_get_stats,
1429}, };
1430
1431module_phy_driver(at803x_driver);
1432
1433static struct mdio_device_id __maybe_unused atheros_tbl[] = {
1434 { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1435 { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1436 { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1437 { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1438 { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1439 { }
1440};
1441
1442MODULE_DEVICE_TABLE(mdio, atheros_tbl);