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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2/* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
5 */
6
7#include <linux/types.h>
8#include <asm/byteorder.h>
9#include <linux/io.h>
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/mutex.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/string.h>
18#include <linux/vmalloc.h>
19#include <linux/etherdevice.h>
20#include <linux/qed/qed_chain.h>
21#include <linux/qed/qed_if.h>
22#include "qed.h"
23#include "qed_cxt.h"
24#include "qed_dcbx.h"
25#include "qed_dev_api.h"
26#include "qed_fcoe.h"
27#include "qed_hsi.h"
28#include "qed_hw.h"
29#include "qed_init_ops.h"
30#include "qed_int.h"
31#include "qed_iscsi.h"
32#include "qed_ll2.h"
33#include "qed_mcp.h"
34#include "qed_ooo.h"
35#include "qed_reg_addr.h"
36#include "qed_sp.h"
37#include "qed_sriov.h"
38#include "qed_vf.h"
39#include "qed_rdma.h"
40#include "qed_nvmetcp.h"
41
42static DEFINE_SPINLOCK(qm_lock);
43
44/******************** Doorbell Recovery *******************/
45/* The doorbell recovery mechanism consists of a list of entries which represent
46 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each
47 * entity needs to register with the mechanism and provide the parameters
48 * describing it's doorbell, including a location where last used doorbell data
49 * can be found. The doorbell execute function will traverse the list and
50 * doorbell all of the registered entries.
51 */
52struct qed_db_recovery_entry {
53 struct list_head list_entry;
54 void __iomem *db_addr;
55 void *db_data;
56 enum qed_db_rec_width db_width;
57 enum qed_db_rec_space db_space;
58 u8 hwfn_idx;
59};
60
61/* Display a single doorbell recovery entry */
62static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn,
63 struct qed_db_recovery_entry *db_entry,
64 char *action)
65{
66 DP_VERBOSE(p_hwfn,
67 QED_MSG_SPQ,
68 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n",
69 action,
70 db_entry,
71 db_entry->db_addr,
72 db_entry->db_data,
73 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b",
74 db_entry->db_space == DB_REC_USER ? "user" : "kernel",
75 db_entry->hwfn_idx);
76}
77
78/* Doorbell address sanity (address within doorbell bar range) */
79static bool qed_db_rec_sanity(struct qed_dev *cdev,
80 void __iomem *db_addr,
81 enum qed_db_rec_width db_width,
82 void *db_data)
83{
84 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64;
85
86 /* Make sure doorbell address is within the doorbell bar */
87 if (db_addr < cdev->doorbells ||
88 (u8 __iomem *)db_addr + width >
89 (u8 __iomem *)cdev->doorbells + cdev->db_size) {
90 WARN(true,
91 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n",
92 db_addr,
93 cdev->doorbells,
94 (u8 __iomem *)cdev->doorbells + cdev->db_size);
95 return false;
96 }
97
98 /* ake sure doorbell data pointer is not null */
99 if (!db_data) {
100 WARN(true, "Illegal doorbell data pointer: %p", db_data);
101 return false;
102 }
103
104 return true;
105}
106
107/* Find hwfn according to the doorbell address */
108static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev,
109 void __iomem *db_addr)
110{
111 struct qed_hwfn *p_hwfn;
112
113 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */
114 if (cdev->num_hwfns > 1)
115 p_hwfn = db_addr < cdev->hwfns[1].doorbells ?
116 &cdev->hwfns[0] : &cdev->hwfns[1];
117 else
118 p_hwfn = QED_LEADING_HWFN(cdev);
119
120 return p_hwfn;
121}
122
123/* Add a new entry to the doorbell recovery mechanism */
124int qed_db_recovery_add(struct qed_dev *cdev,
125 void __iomem *db_addr,
126 void *db_data,
127 enum qed_db_rec_width db_width,
128 enum qed_db_rec_space db_space)
129{
130 struct qed_db_recovery_entry *db_entry;
131 struct qed_hwfn *p_hwfn;
132
133 /* Shortcircuit VFs, for now */
134 if (IS_VF(cdev)) {
135 DP_VERBOSE(cdev,
136 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
137 return 0;
138 }
139
140 /* Sanitize doorbell address */
141 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data))
142 return -EINVAL;
143
144 /* Obtain hwfn from doorbell address */
145 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
146
147 /* Create entry */
148 db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL);
149 if (!db_entry) {
150 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n");
151 return -ENOMEM;
152 }
153
154 /* Populate entry */
155 db_entry->db_addr = db_addr;
156 db_entry->db_data = db_data;
157 db_entry->db_width = db_width;
158 db_entry->db_space = db_space;
159 db_entry->hwfn_idx = p_hwfn->my_id;
160
161 /* Display */
162 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding");
163
164 /* Protect the list */
165 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
166 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list);
167 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
168
169 return 0;
170}
171
172/* Remove an entry from the doorbell recovery mechanism */
173int qed_db_recovery_del(struct qed_dev *cdev,
174 void __iomem *db_addr, void *db_data)
175{
176 struct qed_db_recovery_entry *db_entry = NULL;
177 struct qed_hwfn *p_hwfn;
178 int rc = -EINVAL;
179
180 /* Shortcircuit VFs, for now */
181 if (IS_VF(cdev)) {
182 DP_VERBOSE(cdev,
183 QED_MSG_IOV, "db recovery - skipping VF doorbell\n");
184 return 0;
185 }
186
187 /* Obtain hwfn from doorbell address */
188 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr);
189
190 /* Protect the list */
191 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
192 list_for_each_entry(db_entry,
193 &p_hwfn->db_recovery_info.list, list_entry) {
194 /* search according to db_data addr since db_addr is not unique (roce) */
195 if (db_entry->db_data == db_data) {
196 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting");
197 list_del(&db_entry->list_entry);
198 rc = 0;
199 break;
200 }
201 }
202
203 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
204
205 if (rc == -EINVAL)
206
207 DP_NOTICE(p_hwfn,
208 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n",
209 db_data, db_addr);
210 else
211 kfree(db_entry);
212
213 return rc;
214}
215
216/* Initialize the doorbell recovery mechanism */
217static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn)
218{
219 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n");
220
221 /* Make sure db_size was set in cdev */
222 if (!p_hwfn->cdev->db_size) {
223 DP_ERR(p_hwfn->cdev, "db_size not set\n");
224 return -EINVAL;
225 }
226
227 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list);
228 spin_lock_init(&p_hwfn->db_recovery_info.lock);
229 p_hwfn->db_recovery_info.db_recovery_counter = 0;
230
231 return 0;
232}
233
234/* Destroy the doorbell recovery mechanism */
235static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn)
236{
237 struct qed_db_recovery_entry *db_entry = NULL;
238
239 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n");
240 if (!list_empty(&p_hwfn->db_recovery_info.list)) {
241 DP_VERBOSE(p_hwfn,
242 QED_MSG_SPQ,
243 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n");
244 while (!list_empty(&p_hwfn->db_recovery_info.list)) {
245 db_entry =
246 list_first_entry(&p_hwfn->db_recovery_info.list,
247 struct qed_db_recovery_entry,
248 list_entry);
249 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging");
250 list_del(&db_entry->list_entry);
251 kfree(db_entry);
252 }
253 }
254 p_hwfn->db_recovery_info.db_recovery_counter = 0;
255}
256
257/* Print the content of the doorbell recovery mechanism */
258void qed_db_recovery_dp(struct qed_hwfn *p_hwfn)
259{
260 struct qed_db_recovery_entry *db_entry = NULL;
261
262 DP_NOTICE(p_hwfn,
263 "Displaying doorbell recovery database. Counter was %d\n",
264 p_hwfn->db_recovery_info.db_recovery_counter);
265
266 /* Protect the list */
267 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
268 list_for_each_entry(db_entry,
269 &p_hwfn->db_recovery_info.list, list_entry) {
270 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing");
271 }
272
273 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
274}
275
276/* Ring the doorbell of a single doorbell recovery entry */
277static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn,
278 struct qed_db_recovery_entry *db_entry)
279{
280 /* Print according to width */
281 if (db_entry->db_width == DB_REC_WIDTH_32B) {
282 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
283 "ringing doorbell address %p data %x\n",
284 db_entry->db_addr,
285 *(u32 *)db_entry->db_data);
286 } else {
287 DP_VERBOSE(p_hwfn, QED_MSG_SPQ,
288 "ringing doorbell address %p data %llx\n",
289 db_entry->db_addr,
290 *(u64 *)(db_entry->db_data));
291 }
292
293 /* Sanity */
294 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr,
295 db_entry->db_width, db_entry->db_data))
296 return;
297
298 /* Flush the write combined buffer. Since there are multiple doorbelling
299 * entities using the same address, if we don't flush, a transaction
300 * could be lost.
301 */
302 wmb();
303
304 /* Ring the doorbell */
305 if (db_entry->db_width == DB_REC_WIDTH_32B)
306 DIRECT_REG_WR(db_entry->db_addr,
307 *(u32 *)(db_entry->db_data));
308 else
309 DIRECT_REG_WR64(db_entry->db_addr,
310 *(u64 *)(db_entry->db_data));
311
312 /* Flush the write combined buffer. Next doorbell may come from a
313 * different entity to the same address...
314 */
315 wmb();
316}
317
318/* Traverse the doorbell recovery entry list and ring all the doorbells */
319void qed_db_recovery_execute(struct qed_hwfn *p_hwfn)
320{
321 struct qed_db_recovery_entry *db_entry = NULL;
322
323 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n",
324 p_hwfn->db_recovery_info.db_recovery_counter);
325
326 /* Track amount of times recovery was executed */
327 p_hwfn->db_recovery_info.db_recovery_counter++;
328
329 /* Protect the list */
330 spin_lock_bh(&p_hwfn->db_recovery_info.lock);
331 list_for_each_entry(db_entry,
332 &p_hwfn->db_recovery_info.list, list_entry)
333 qed_db_recovery_ring(p_hwfn, db_entry);
334 spin_unlock_bh(&p_hwfn->db_recovery_info.lock);
335}
336
337/******************** Doorbell Recovery end ****************/
338
339/********************************** NIG LLH ***********************************/
340
341enum qed_llh_filter_type {
342 QED_LLH_FILTER_TYPE_MAC,
343 QED_LLH_FILTER_TYPE_PROTOCOL,
344};
345
346struct qed_llh_mac_filter {
347 u8 addr[ETH_ALEN];
348};
349
350struct qed_llh_protocol_filter {
351 enum qed_llh_prot_filter_type_t type;
352 u16 source_port_or_eth_type;
353 u16 dest_port;
354};
355
356union qed_llh_filter {
357 struct qed_llh_mac_filter mac;
358 struct qed_llh_protocol_filter protocol;
359};
360
361struct qed_llh_filter_info {
362 bool b_enabled;
363 u32 ref_cnt;
364 enum qed_llh_filter_type type;
365 union qed_llh_filter filter;
366};
367
368struct qed_llh_info {
369 /* Number of LLH filters banks */
370 u8 num_ppfid;
371
372#define MAX_NUM_PPFID 8
373 u8 ppfid_array[MAX_NUM_PPFID];
374
375 /* Array of filters arrays:
376 * "num_ppfid" elements of filters banks, where each is an array of
377 * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters.
378 */
379 struct qed_llh_filter_info **pp_filters;
380};
381
382static void qed_llh_free(struct qed_dev *cdev)
383{
384 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
385 u32 i;
386
387 if (p_llh_info) {
388 if (p_llh_info->pp_filters)
389 for (i = 0; i < p_llh_info->num_ppfid; i++)
390 kfree(p_llh_info->pp_filters[i]);
391
392 kfree(p_llh_info->pp_filters);
393 }
394
395 kfree(p_llh_info);
396 cdev->p_llh_info = NULL;
397}
398
399static int qed_llh_alloc(struct qed_dev *cdev)
400{
401 struct qed_llh_info *p_llh_info;
402 u32 size, i;
403
404 p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL);
405 if (!p_llh_info)
406 return -ENOMEM;
407 cdev->p_llh_info = p_llh_info;
408
409 for (i = 0; i < MAX_NUM_PPFID; i++) {
410 if (!(cdev->ppfid_bitmap & (0x1 << i)))
411 continue;
412
413 p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;
414 DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n",
415 p_llh_info->num_ppfid, i);
416 p_llh_info->num_ppfid++;
417 }
418
419 size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);
420 p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL);
421 if (!p_llh_info->pp_filters)
422 return -ENOMEM;
423
424 size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
425 sizeof(**p_llh_info->pp_filters);
426 for (i = 0; i < p_llh_info->num_ppfid; i++) {
427 p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL);
428 if (!p_llh_info->pp_filters[i])
429 return -ENOMEM;
430 }
431
432 return 0;
433}
434
435static int qed_llh_shadow_sanity(struct qed_dev *cdev,
436 u8 ppfid, u8 filter_idx, const char *action)
437{
438 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
439
440 if (ppfid >= p_llh_info->num_ppfid) {
441 DP_NOTICE(cdev,
442 "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n",
443 action, ppfid, p_llh_info->num_ppfid);
444 return -EINVAL;
445 }
446
447 if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
448 DP_NOTICE(cdev,
449 "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n",
450 action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);
451 return -EINVAL;
452 }
453
454 return 0;
455}
456
457#define QED_LLH_INVALID_FILTER_IDX 0xff
458
459static int
460qed_llh_shadow_search_filter(struct qed_dev *cdev,
461 u8 ppfid,
462 union qed_llh_filter *p_filter, u8 *p_filter_idx)
463{
464 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
465 struct qed_llh_filter_info *p_filters;
466 int rc;
467 u8 i;
468
469 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search");
470 if (rc)
471 return rc;
472
473 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
474
475 p_filters = p_llh_info->pp_filters[ppfid];
476 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
477 if (!memcmp(p_filter, &p_filters[i].filter,
478 sizeof(*p_filter))) {
479 *p_filter_idx = i;
480 break;
481 }
482 }
483
484 return 0;
485}
486
487static int
488qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx)
489{
490 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
491 struct qed_llh_filter_info *p_filters;
492 int rc;
493 u8 i;
494
495 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx");
496 if (rc)
497 return rc;
498
499 *p_filter_idx = QED_LLH_INVALID_FILTER_IDX;
500
501 p_filters = p_llh_info->pp_filters[ppfid];
502 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
503 if (!p_filters[i].b_enabled) {
504 *p_filter_idx = i;
505 break;
506 }
507 }
508
509 return 0;
510}
511
512static int
513__qed_llh_shadow_add_filter(struct qed_dev *cdev,
514 u8 ppfid,
515 u8 filter_idx,
516 enum qed_llh_filter_type type,
517 union qed_llh_filter *p_filter, u32 *p_ref_cnt)
518{
519 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
520 struct qed_llh_filter_info *p_filters;
521 int rc;
522
523 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add");
524 if (rc)
525 return rc;
526
527 p_filters = p_llh_info->pp_filters[ppfid];
528 if (!p_filters[filter_idx].ref_cnt) {
529 p_filters[filter_idx].b_enabled = true;
530 p_filters[filter_idx].type = type;
531 memcpy(&p_filters[filter_idx].filter, p_filter,
532 sizeof(p_filters[filter_idx].filter));
533 }
534
535 *p_ref_cnt = ++p_filters[filter_idx].ref_cnt;
536
537 return 0;
538}
539
540static int
541qed_llh_shadow_add_filter(struct qed_dev *cdev,
542 u8 ppfid,
543 enum qed_llh_filter_type type,
544 union qed_llh_filter *p_filter,
545 u8 *p_filter_idx, u32 *p_ref_cnt)
546{
547 int rc;
548
549 /* Check if the same filter already exist */
550 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
551 if (rc)
552 return rc;
553
554 /* Find a new entry in case of a new filter */
555 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
556 rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx);
557 if (rc)
558 return rc;
559 }
560
561 /* No free entry was found */
562 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
563 DP_NOTICE(cdev,
564 "Failed to find an empty LLH filter to utilize [ppfid %d]\n",
565 ppfid);
566 return -EINVAL;
567 }
568
569 return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type,
570 p_filter, p_ref_cnt);
571}
572
573static int
574__qed_llh_shadow_remove_filter(struct qed_dev *cdev,
575 u8 ppfid, u8 filter_idx, u32 *p_ref_cnt)
576{
577 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
578 struct qed_llh_filter_info *p_filters;
579 int rc;
580
581 rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove");
582 if (rc)
583 return rc;
584
585 p_filters = p_llh_info->pp_filters[ppfid];
586 if (!p_filters[filter_idx].ref_cnt) {
587 DP_NOTICE(cdev,
588 "LLH shadow: trying to remove a filter with ref_cnt=0\n");
589 return -EINVAL;
590 }
591
592 *p_ref_cnt = --p_filters[filter_idx].ref_cnt;
593 if (!p_filters[filter_idx].ref_cnt)
594 memset(&p_filters[filter_idx],
595 0, sizeof(p_filters[filter_idx]));
596
597 return 0;
598}
599
600static int
601qed_llh_shadow_remove_filter(struct qed_dev *cdev,
602 u8 ppfid,
603 union qed_llh_filter *p_filter,
604 u8 *p_filter_idx, u32 *p_ref_cnt)
605{
606 int rc;
607
608 rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx);
609 if (rc)
610 return rc;
611
612 /* No matching filter was found */
613 if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) {
614 DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n");
615 return -EINVAL;
616 }
617
618 return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx,
619 p_ref_cnt);
620}
621
622static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid)
623{
624 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
625
626 if (ppfid >= p_llh_info->num_ppfid) {
627 DP_NOTICE(cdev,
628 "ppfid %d is not valid, available indices are 0..%hhd\n",
629 ppfid, p_llh_info->num_ppfid - 1);
630 *p_abs_ppfid = 0;
631 return -EINVAL;
632 }
633
634 *p_abs_ppfid = p_llh_info->ppfid_array[ppfid];
635
636 return 0;
637}
638
639static int
640qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
641{
642 struct qed_dev *cdev = p_hwfn->cdev;
643 enum qed_eng eng;
644 u8 ppfid;
645 int rc;
646
647 rc = qed_mcp_get_engine_config(p_hwfn, p_ptt);
648 if (rc != 0 && rc != -EOPNOTSUPP) {
649 DP_NOTICE(p_hwfn,
650 "Failed to get the engine affinity configuration\n");
651 return rc;
652 }
653
654 /* RoCE PF is bound to a single engine */
655 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
656 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
657 rc = qed_llh_set_roce_affinity(cdev, eng);
658 if (rc) {
659 DP_NOTICE(cdev,
660 "Failed to set the RoCE engine affinity\n");
661 return rc;
662 }
663
664 DP_VERBOSE(cdev,
665 QED_MSG_SP,
666 "LLH: Set the engine affinity of RoCE packets as %d\n",
667 eng);
668 }
669
670 /* Storage PF is bound to a single engine while L2 PF uses both */
671 if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn) ||
672 QED_IS_NVMETCP_PERSONALITY(p_hwfn))
673 eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0;
674 else /* L2_PERSONALITY */
675 eng = QED_BOTH_ENG;
676
677 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
678 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng);
679 if (rc) {
680 DP_NOTICE(cdev,
681 "Failed to set the engine affinity of ppfid %d\n",
682 ppfid);
683 return rc;
684 }
685 }
686
687 DP_VERBOSE(cdev, QED_MSG_SP,
688 "LLH: Set the engine affinity of non-RoCE packets as %d\n",
689 eng);
690
691 return 0;
692}
693
694static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn,
695 struct qed_ptt *p_ptt)
696{
697 struct qed_dev *cdev = p_hwfn->cdev;
698 u8 ppfid, abs_ppfid;
699 int rc;
700
701 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
702 u32 addr;
703
704 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
705 if (rc)
706 return rc;
707
708 addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;
709 qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
710 }
711
712 if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
713 !QED_IS_FCOE_PERSONALITY(p_hwfn)) {
714 rc = qed_llh_add_mac_filter(cdev, 0,
715 p_hwfn->hw_info.hw_mac_addr);
716 if (rc)
717 DP_NOTICE(cdev,
718 "Failed to add an LLH filter with the primary MAC\n");
719 }
720
721 if (QED_IS_CMT(cdev)) {
722 rc = qed_llh_set_engine_affin(p_hwfn, p_ptt);
723 if (rc)
724 return rc;
725 }
726
727 return 0;
728}
729
730u8 qed_llh_get_num_ppfid(struct qed_dev *cdev)
731{
732 return cdev->p_llh_info->num_ppfid;
733}
734
735#define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3
736#define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0
737#define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3
738#define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2
739
740int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng)
741{
742 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
743 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
744 u32 addr, val, eng_sel;
745 u8 abs_ppfid;
746 int rc = 0;
747
748 if (!p_ptt)
749 return -EAGAIN;
750
751 if (!QED_IS_CMT(cdev))
752 goto out;
753
754 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
755 if (rc)
756 goto out;
757
758 switch (eng) {
759 case QED_ENG0:
760 eng_sel = 0;
761 break;
762 case QED_ENG1:
763 eng_sel = 1;
764 break;
765 case QED_BOTH_ENG:
766 eng_sel = 2;
767 break;
768 default:
769 DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng);
770 rc = -EINVAL;
771 goto out;
772 }
773
774 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
775 val = qed_rd(p_hwfn, p_ptt, addr);
776 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);
777 qed_wr(p_hwfn, p_ptt, addr, val);
778
779 /* The iWARP affinity is set as the affinity of ppfid 0 */
780 if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn))
781 cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0;
782out:
783 qed_ptt_release(p_hwfn, p_ptt);
784
785 return rc;
786}
787
788int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng)
789{
790 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
791 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
792 u32 addr, val, eng_sel;
793 u8 ppfid, abs_ppfid;
794 int rc = 0;
795
796 if (!p_ptt)
797 return -EAGAIN;
798
799 if (!QED_IS_CMT(cdev))
800 goto out;
801
802 switch (eng) {
803 case QED_ENG0:
804 eng_sel = 0;
805 break;
806 case QED_ENG1:
807 eng_sel = 1;
808 break;
809 case QED_BOTH_ENG:
810 eng_sel = 2;
811 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,
812 0xf); /* QP bit 15 */
813 break;
814 default:
815 DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng);
816 rc = -EINVAL;
817 goto out;
818 }
819
820 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) {
821 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
822 if (rc)
823 goto out;
824
825 addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;
826 val = qed_rd(p_hwfn, p_ptt, addr);
827 SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);
828 qed_wr(p_hwfn, p_ptt, addr, val);
829 }
830out:
831 qed_ptt_release(p_hwfn, p_ptt);
832
833 return rc;
834}
835
836struct qed_llh_filter_details {
837 u64 value;
838 u32 mode;
839 u32 protocol_type;
840 u32 hdr_sel;
841 u32 enable;
842};
843
844static int
845qed_llh_access_filter(struct qed_hwfn *p_hwfn,
846 struct qed_ptt *p_ptt,
847 u8 abs_ppfid,
848 u8 filter_idx,
849 struct qed_llh_filter_details *p_details)
850{
851 struct qed_dmae_params params = {0};
852 u32 addr;
853 u8 pfid;
854 int rc;
855
856 /* The NIG/LLH registers that are accessed in this function have only 16
857 * rows which are exposed to a PF. I.e. only the 16 filters of its
858 * default ppfid. Accessing filters of other ppfids requires pretending
859 * to another PFs.
860 * The calculation of PPFID->PFID in AH is based on the relative index
861 * of a PF on its port.
862 * For BB the pfid is actually the abs_ppfid.
863 */
864 if (QED_IS_BB(p_hwfn->cdev))
865 pfid = abs_ppfid;
866 else
867 pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine +
868 MFW_PORT(p_hwfn);
869
870 /* Filter enable - should be done first when removing a filter */
871 if (!p_details->enable) {
872 qed_fid_pretend(p_hwfn, p_ptt,
873 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
874
875 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
876 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
877
878 qed_fid_pretend(p_hwfn, p_ptt,
879 p_hwfn->rel_pf_id <<
880 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
881 }
882
883 /* Filter value */
884 addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4;
885
886 SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1);
887 params.dst_pfid = pfid;
888 rc = qed_dmae_host2grc(p_hwfn,
889 p_ptt,
890 (u64)(uintptr_t)&p_details->value,
891 addr, 2 /* size_in_dwords */,
892 ¶ms);
893 if (rc)
894 return rc;
895
896 qed_fid_pretend(p_hwfn, p_ptt,
897 pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
898
899 /* Filter mode */
900 addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4;
901 qed_wr(p_hwfn, p_ptt, addr, p_details->mode);
902
903 /* Filter protocol type */
904 addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4;
905 qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type);
906
907 /* Filter header select */
908 addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4;
909 qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel);
910
911 /* Filter enable - should be done last when adding a filter */
912 if (p_details->enable) {
913 addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4;
914 qed_wr(p_hwfn, p_ptt, addr, p_details->enable);
915 }
916
917 qed_fid_pretend(p_hwfn, p_ptt,
918 p_hwfn->rel_pf_id <<
919 PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
920
921 return 0;
922}
923
924static int
925qed_llh_add_filter(struct qed_hwfn *p_hwfn,
926 struct qed_ptt *p_ptt,
927 u8 abs_ppfid,
928 u8 filter_idx, u8 filter_prot_type, u32 high, u32 low)
929{
930 struct qed_llh_filter_details filter_details;
931
932 filter_details.enable = 1;
933 filter_details.value = ((u64)high << 32) | low;
934 filter_details.hdr_sel = 0;
935 filter_details.protocol_type = filter_prot_type;
936 /* Mode: 0: MAC-address classification 1: protocol classification */
937 filter_details.mode = filter_prot_type ? 1 : 0;
938
939 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
940 &filter_details);
941}
942
943static int
944qed_llh_remove_filter(struct qed_hwfn *p_hwfn,
945 struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)
946{
947 struct qed_llh_filter_details filter_details = {0};
948
949 return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
950 &filter_details);
951}
952
953int qed_llh_add_mac_filter(struct qed_dev *cdev,
954 u8 ppfid, u8 mac_addr[ETH_ALEN])
955{
956 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
957 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
958 union qed_llh_filter filter = {};
959 u8 filter_idx, abs_ppfid = 0;
960 u32 high, low, ref_cnt;
961 int rc = 0;
962
963 if (!p_ptt)
964 return -EAGAIN;
965
966 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
967 goto out;
968
969 memcpy(filter.mac.addr, mac_addr, ETH_ALEN);
970 rc = qed_llh_shadow_add_filter(cdev, ppfid,
971 QED_LLH_FILTER_TYPE_MAC,
972 &filter, &filter_idx, &ref_cnt);
973 if (rc)
974 goto err;
975
976 /* Configure the LLH only in case of a new the filter */
977 if (ref_cnt == 1) {
978 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
979 if (rc)
980 goto err;
981
982 high = mac_addr[1] | (mac_addr[0] << 8);
983 low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |
984 (mac_addr[2] << 24);
985 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,
986 0, high, low);
987 if (rc)
988 goto err;
989 }
990
991 DP_VERBOSE(cdev,
992 QED_MSG_SP,
993 "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
994 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
995
996 goto out;
997
998err: DP_NOTICE(cdev,
999 "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n",
1000 mac_addr, ppfid);
1001out:
1002 qed_ptt_release(p_hwfn, p_ptt);
1003
1004 return rc;
1005}
1006
1007static int
1008qed_llh_protocol_filter_stringify(struct qed_dev *cdev,
1009 enum qed_llh_prot_filter_type_t type,
1010 u16 source_port_or_eth_type,
1011 u16 dest_port, u8 *str, size_t str_len)
1012{
1013 switch (type) {
1014 case QED_LLH_FILTER_ETHERTYPE:
1015 snprintf(str, str_len, "Ethertype 0x%04x",
1016 source_port_or_eth_type);
1017 break;
1018 case QED_LLH_FILTER_TCP_SRC_PORT:
1019 snprintf(str, str_len, "TCP src port 0x%04x",
1020 source_port_or_eth_type);
1021 break;
1022 case QED_LLH_FILTER_UDP_SRC_PORT:
1023 snprintf(str, str_len, "UDP src port 0x%04x",
1024 source_port_or_eth_type);
1025 break;
1026 case QED_LLH_FILTER_TCP_DEST_PORT:
1027 snprintf(str, str_len, "TCP dst port 0x%04x", dest_port);
1028 break;
1029 case QED_LLH_FILTER_UDP_DEST_PORT:
1030 snprintf(str, str_len, "UDP dst port 0x%04x", dest_port);
1031 break;
1032 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1033 snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x",
1034 source_port_or_eth_type, dest_port);
1035 break;
1036 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1037 snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x",
1038 source_port_or_eth_type, dest_port);
1039 break;
1040 default:
1041 DP_NOTICE(cdev,
1042 "Non valid LLH protocol filter type %d\n", type);
1043 return -EINVAL;
1044 }
1045
1046 return 0;
1047}
1048
1049static int
1050qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev,
1051 enum qed_llh_prot_filter_type_t type,
1052 u16 source_port_or_eth_type,
1053 u16 dest_port, u32 *p_high, u32 *p_low)
1054{
1055 *p_high = 0;
1056 *p_low = 0;
1057
1058 switch (type) {
1059 case QED_LLH_FILTER_ETHERTYPE:
1060 *p_high = source_port_or_eth_type;
1061 break;
1062 case QED_LLH_FILTER_TCP_SRC_PORT:
1063 case QED_LLH_FILTER_UDP_SRC_PORT:
1064 *p_low = source_port_or_eth_type << 16;
1065 break;
1066 case QED_LLH_FILTER_TCP_DEST_PORT:
1067 case QED_LLH_FILTER_UDP_DEST_PORT:
1068 *p_low = dest_port;
1069 break;
1070 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
1071 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
1072 *p_low = (source_port_or_eth_type << 16) | dest_port;
1073 break;
1074 default:
1075 DP_NOTICE(cdev,
1076 "Non valid LLH protocol filter type %d\n", type);
1077 return -EINVAL;
1078 }
1079
1080 return 0;
1081}
1082
1083int
1084qed_llh_add_protocol_filter(struct qed_dev *cdev,
1085 u8 ppfid,
1086 enum qed_llh_prot_filter_type_t type,
1087 u16 source_port_or_eth_type, u16 dest_port)
1088{
1089 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1090 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1091 u8 filter_idx, abs_ppfid, str[32], type_bitmap;
1092 union qed_llh_filter filter = {};
1093 u32 high, low, ref_cnt;
1094 int rc = 0;
1095
1096 if (!p_ptt)
1097 return -EAGAIN;
1098
1099 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1100 goto out;
1101
1102 rc = qed_llh_protocol_filter_stringify(cdev, type,
1103 source_port_or_eth_type,
1104 dest_port, str, sizeof(str));
1105 if (rc)
1106 goto err;
1107
1108 filter.protocol.type = type;
1109 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1110 filter.protocol.dest_port = dest_port;
1111 rc = qed_llh_shadow_add_filter(cdev,
1112 ppfid,
1113 QED_LLH_FILTER_TYPE_PROTOCOL,
1114 &filter, &filter_idx, &ref_cnt);
1115 if (rc)
1116 goto err;
1117
1118 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1119 if (rc)
1120 goto err;
1121
1122 /* Configure the LLH only in case of a new the filter */
1123 if (ref_cnt == 1) {
1124 rc = qed_llh_protocol_filter_to_hilo(cdev, type,
1125 source_port_or_eth_type,
1126 dest_port, &high, &low);
1127 if (rc)
1128 goto err;
1129
1130 type_bitmap = 0x1 << type;
1131 rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid,
1132 filter_idx, type_bitmap, high, low);
1133 if (rc)
1134 goto err;
1135 }
1136
1137 DP_VERBOSE(cdev,
1138 QED_MSG_SP,
1139 "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1140 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1141
1142 goto out;
1143
1144err: DP_NOTICE(p_hwfn,
1145 "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n",
1146 str, ppfid);
1147out:
1148 qed_ptt_release(p_hwfn, p_ptt);
1149
1150 return rc;
1151}
1152
1153void qed_llh_remove_mac_filter(struct qed_dev *cdev,
1154 u8 ppfid, u8 mac_addr[ETH_ALEN])
1155{
1156 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1157 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1158 union qed_llh_filter filter = {};
1159 u8 filter_idx, abs_ppfid;
1160 int rc = 0;
1161 u32 ref_cnt;
1162
1163 if (!p_ptt)
1164 return;
1165
1166 if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
1167 goto out;
1168
1169 if (QED_IS_NVMETCP_PERSONALITY(p_hwfn))
1170 return;
1171
1172 ether_addr_copy(filter.mac.addr, mac_addr);
1173 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1174 &ref_cnt);
1175 if (rc)
1176 goto err;
1177
1178 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1179 if (rc)
1180 goto err;
1181
1182 /* Remove from the LLH in case the filter is not in use */
1183 if (!ref_cnt) {
1184 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1185 filter_idx);
1186 if (rc)
1187 goto err;
1188 }
1189
1190 DP_VERBOSE(cdev,
1191 QED_MSG_SP,
1192 "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1193 mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt);
1194
1195 goto out;
1196
1197err: DP_NOTICE(cdev,
1198 "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n",
1199 mac_addr, ppfid);
1200out:
1201 qed_ptt_release(p_hwfn, p_ptt);
1202}
1203
1204void qed_llh_remove_protocol_filter(struct qed_dev *cdev,
1205 u8 ppfid,
1206 enum qed_llh_prot_filter_type_t type,
1207 u16 source_port_or_eth_type, u16 dest_port)
1208{
1209 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
1210 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
1211 u8 filter_idx, abs_ppfid, str[32];
1212 union qed_llh_filter filter = {};
1213 int rc = 0;
1214 u32 ref_cnt;
1215
1216 if (!p_ptt)
1217 return;
1218
1219 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits))
1220 goto out;
1221
1222 rc = qed_llh_protocol_filter_stringify(cdev, type,
1223 source_port_or_eth_type,
1224 dest_port, str, sizeof(str));
1225 if (rc)
1226 goto err;
1227
1228 filter.protocol.type = type;
1229 filter.protocol.source_port_or_eth_type = source_port_or_eth_type;
1230 filter.protocol.dest_port = dest_port;
1231 rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx,
1232 &ref_cnt);
1233 if (rc)
1234 goto err;
1235
1236 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
1237 if (rc)
1238 goto err;
1239
1240 /* Remove from the LLH in case the filter is not in use */
1241 if (!ref_cnt) {
1242 rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,
1243 filter_idx);
1244 if (rc)
1245 goto err;
1246 }
1247
1248 DP_VERBOSE(cdev,
1249 QED_MSG_SP,
1250 "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n",
1251 str, ppfid, abs_ppfid, filter_idx, ref_cnt);
1252
1253 goto out;
1254
1255err: DP_NOTICE(cdev,
1256 "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n",
1257 str, ppfid);
1258out:
1259 qed_ptt_release(p_hwfn, p_ptt);
1260}
1261
1262/******************************* NIG LLH - End ********************************/
1263
1264#define QED_MIN_DPIS (4)
1265#define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS)
1266
1267static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
1268 struct qed_ptt *p_ptt, enum BAR_ID bar_id)
1269{
1270 u32 bar_reg = (bar_id == BAR_ID_0 ?
1271 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
1272 u32 val;
1273
1274 if (IS_VF(p_hwfn->cdev))
1275 return qed_vf_hw_bar_size(p_hwfn, bar_id);
1276
1277 val = qed_rd(p_hwfn, p_ptt, bar_reg);
1278 if (val)
1279 return 1 << (val + 15);
1280
1281 /* Old MFW initialized above registered only conditionally */
1282 if (p_hwfn->cdev->num_hwfns > 1) {
1283 DP_INFO(p_hwfn,
1284 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
1285 return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
1286 } else {
1287 DP_INFO(p_hwfn,
1288 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
1289 return 512 * 1024;
1290 }
1291}
1292
1293void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
1294{
1295 u32 i;
1296
1297 cdev->dp_level = dp_level;
1298 cdev->dp_module = dp_module;
1299 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1300 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1301
1302 p_hwfn->dp_level = dp_level;
1303 p_hwfn->dp_module = dp_module;
1304 }
1305}
1306
1307void qed_init_struct(struct qed_dev *cdev)
1308{
1309 u8 i;
1310
1311 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
1312 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1313
1314 p_hwfn->cdev = cdev;
1315 p_hwfn->my_id = i;
1316 p_hwfn->b_active = false;
1317
1318 mutex_init(&p_hwfn->dmae_info.mutex);
1319 }
1320
1321 /* hwfn 0 is always active */
1322 cdev->hwfns[0].b_active = true;
1323
1324 /* set the default cache alignment to 128 */
1325 cdev->cache_shift = 7;
1326}
1327
1328static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
1329{
1330 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1331
1332 kfree(qm_info->qm_pq_params);
1333 qm_info->qm_pq_params = NULL;
1334 kfree(qm_info->qm_vport_params);
1335 qm_info->qm_vport_params = NULL;
1336 kfree(qm_info->qm_port_params);
1337 qm_info->qm_port_params = NULL;
1338 kfree(qm_info->wfq_data);
1339 qm_info->wfq_data = NULL;
1340}
1341
1342static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn)
1343{
1344 kfree(p_hwfn->dbg_user_info);
1345 p_hwfn->dbg_user_info = NULL;
1346}
1347
1348void qed_resc_free(struct qed_dev *cdev)
1349{
1350 struct qed_rdma_info *rdma_info;
1351 struct qed_hwfn *p_hwfn;
1352 int i;
1353
1354 if (IS_VF(cdev)) {
1355 for_each_hwfn(cdev, i)
1356 qed_l2_free(&cdev->hwfns[i]);
1357 return;
1358 }
1359
1360 kfree(cdev->fw_data);
1361 cdev->fw_data = NULL;
1362
1363 kfree(cdev->reset_stats);
1364 cdev->reset_stats = NULL;
1365
1366 qed_llh_free(cdev);
1367
1368 for_each_hwfn(cdev, i) {
1369 p_hwfn = cdev->hwfns + i;
1370 rdma_info = p_hwfn->p_rdma_info;
1371
1372 qed_cxt_mngr_free(p_hwfn);
1373 qed_qm_info_free(p_hwfn);
1374 qed_spq_free(p_hwfn);
1375 qed_eq_free(p_hwfn);
1376 qed_consq_free(p_hwfn);
1377 qed_int_free(p_hwfn);
1378#ifdef CONFIG_QED_LL2
1379 qed_ll2_free(p_hwfn);
1380#endif
1381 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1382 qed_fcoe_free(p_hwfn);
1383
1384 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1385 qed_iscsi_free(p_hwfn);
1386 qed_ooo_free(p_hwfn);
1387 }
1388
1389 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) {
1390 qed_nvmetcp_free(p_hwfn);
1391 qed_ooo_free(p_hwfn);
1392 }
1393
1394 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && rdma_info) {
1395 qed_spq_unregister_async_cb(p_hwfn, rdma_info->proto);
1396 qed_rdma_info_free(p_hwfn);
1397 }
1398
1399 qed_iov_free(p_hwfn);
1400 qed_l2_free(p_hwfn);
1401 qed_dmae_info_free(p_hwfn);
1402 qed_dcbx_info_free(p_hwfn);
1403 qed_dbg_user_data_free(p_hwfn);
1404 qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
1405
1406 /* Destroy doorbell recovery mechanism */
1407 qed_db_recovery_teardown(p_hwfn);
1408 }
1409}
1410
1411/******************** QM initialization *******************/
1412#define ACTIVE_TCS_BMAP 0x9f
1413#define ACTIVE_TCS_BMAP_4PORT_K2 0xf
1414
1415/* determines the physical queue flags for a given PF. */
1416static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
1417{
1418 u32 flags;
1419
1420 /* common flags */
1421 flags = PQ_FLAGS_LB;
1422
1423 /* feature flags */
1424 if (IS_QED_SRIOV(p_hwfn->cdev))
1425 flags |= PQ_FLAGS_VFS;
1426
1427 /* protocol flags */
1428 switch (p_hwfn->hw_info.personality) {
1429 case QED_PCI_ETH:
1430 flags |= PQ_FLAGS_MCOS;
1431 break;
1432 case QED_PCI_FCOE:
1433 flags |= PQ_FLAGS_OFLD;
1434 break;
1435 case QED_PCI_ISCSI:
1436 case QED_PCI_NVMETCP:
1437 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
1438 break;
1439 case QED_PCI_ETH_ROCE:
1440 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
1441 if (IS_QED_MULTI_TC_ROCE(p_hwfn))
1442 flags |= PQ_FLAGS_MTC;
1443 break;
1444 case QED_PCI_ETH_IWARP:
1445 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
1446 PQ_FLAGS_OFLD;
1447 break;
1448 default:
1449 DP_ERR(p_hwfn,
1450 "unknown personality %d\n", p_hwfn->hw_info.personality);
1451 return 0;
1452 }
1453
1454 return flags;
1455}
1456
1457/* Getters for resource amounts necessary for qm initialization */
1458static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
1459{
1460 return p_hwfn->hw_info.num_hw_tc;
1461}
1462
1463static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
1464{
1465 return IS_QED_SRIOV(p_hwfn->cdev) ?
1466 p_hwfn->cdev->p_iov_info->total_vfs : 0;
1467}
1468
1469static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn)
1470{
1471 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1472
1473 if (!(PQ_FLAGS_MTC & pq_flags))
1474 return 1;
1475
1476 return qed_init_qm_get_num_tcs(p_hwfn);
1477}
1478
1479#define NUM_DEFAULT_RLS 1
1480
1481static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
1482{
1483 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1484
1485 /* num RLs can't exceed resource amount of rls or vports */
1486 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
1487 RESC_NUM(p_hwfn, QED_VPORT));
1488
1489 /* Make sure after we reserve there's something left */
1490 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
1491 return 0;
1492
1493 /* subtract rls necessary for VFs and one default one for the PF */
1494 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
1495
1496 return num_pf_rls;
1497}
1498
1499static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
1500{
1501 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1502
1503 /* all pqs share the same vport, except for vfs and pf_rl pqs */
1504 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1505 qed_init_qm_get_num_pf_rls(p_hwfn) +
1506 (!!(PQ_FLAGS_VFS & pq_flags)) *
1507 qed_init_qm_get_num_vfs(p_hwfn) + 1;
1508}
1509
1510/* calc amount of PQs according to the requested flags */
1511static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
1512{
1513 u32 pq_flags = qed_get_pq_flags(p_hwfn);
1514
1515 return (!!(PQ_FLAGS_RLS & pq_flags)) *
1516 qed_init_qm_get_num_pf_rls(p_hwfn) +
1517 (!!(PQ_FLAGS_MCOS & pq_flags)) *
1518 qed_init_qm_get_num_tcs(p_hwfn) +
1519 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
1520 (!!(PQ_FLAGS_ACK & pq_flags)) +
1521 (!!(PQ_FLAGS_OFLD & pq_flags)) *
1522 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1523 (!!(PQ_FLAGS_LLT & pq_flags)) *
1524 qed_init_qm_get_num_mtc_tcs(p_hwfn) +
1525 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
1526}
1527
1528/* initialize the top level QM params */
1529static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
1530{
1531 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1532 bool four_port;
1533
1534 /* pq and vport bases for this PF */
1535 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
1536 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
1537
1538 /* rate limiting and weighted fair queueing are always enabled */
1539 qm_info->vport_rl_en = true;
1540 qm_info->vport_wfq_en = true;
1541
1542 /* TC config is different for AH 4 port */
1543 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
1544
1545 /* in AH 4 port we have fewer TCs per port */
1546 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
1547 NUM_OF_PHYS_TCS;
1548
1549 /* unless MFW indicated otherwise, ooo_tc == 3 for
1550 * AH 4-port and 4 otherwise.
1551 */
1552 if (!qm_info->ooo_tc)
1553 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
1554 DCBX_TCP_OOO_TC;
1555}
1556
1557/* initialize qm vport params */
1558static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
1559{
1560 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1561 u8 i;
1562
1563 /* all vports participate in weighted fair queueing */
1564 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
1565 qm_info->qm_vport_params[i].wfq = 1;
1566}
1567
1568/* initialize qm port params */
1569static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
1570{
1571 /* Initialize qm port parameters */
1572 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
1573 struct qed_dev *cdev = p_hwfn->cdev;
1574
1575 /* indicate how ooo and high pri traffic is dealt with */
1576 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
1577 ACTIVE_TCS_BMAP_4PORT_K2 :
1578 ACTIVE_TCS_BMAP;
1579
1580 for (i = 0; i < num_ports; i++) {
1581 struct init_qm_port_params *p_qm_port =
1582 &p_hwfn->qm_info.qm_port_params[i];
1583 u16 pbf_max_cmd_lines;
1584
1585 p_qm_port->active = 1;
1586 p_qm_port->active_phys_tcs = active_phys_tcs;
1587 pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev);
1588 p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
1589 p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports;
1590 }
1591}
1592
1593/* Reset the params which must be reset for qm init. QM init may be called as
1594 * a result of flows other than driver load (e.g. dcbx renegotiation). Other
1595 * params may be affected by the init but would simply recalculate to the same
1596 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
1597 * affected as these amounts stay the same.
1598 */
1599static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
1600{
1601 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1602
1603 qm_info->num_pqs = 0;
1604 qm_info->num_vports = 0;
1605 qm_info->num_pf_rls = 0;
1606 qm_info->num_vf_pqs = 0;
1607 qm_info->first_vf_pq = 0;
1608 qm_info->first_mcos_pq = 0;
1609 qm_info->first_rl_pq = 0;
1610}
1611
1612static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
1613{
1614 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1615
1616 qm_info->num_vports++;
1617
1618 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1619 DP_ERR(p_hwfn,
1620 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1621 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1622}
1623
1624/* initialize a single pq and manage qm_info resources accounting.
1625 * The pq_init_flags param determines whether the PQ is rate limited
1626 * (for VF or PF) and whether a new vport is allocated to the pq or not
1627 * (i.e. vport will be shared).
1628 */
1629
1630/* flags for pq init */
1631#define PQ_INIT_SHARE_VPORT (1 << 0)
1632#define PQ_INIT_PF_RL (1 << 1)
1633#define PQ_INIT_VF_RL (1 << 2)
1634
1635/* defines for pq init */
1636#define PQ_INIT_DEFAULT_WRR_GROUP 1
1637#define PQ_INIT_DEFAULT_TC 0
1638
1639void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc)
1640{
1641 p_info->offload_tc = tc;
1642 p_info->offload_tc_set = true;
1643}
1644
1645static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn)
1646{
1647 return p_hwfn->hw_info.offload_tc_set;
1648}
1649
1650static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn)
1651{
1652 if (qed_is_offload_tc_set(p_hwfn))
1653 return p_hwfn->hw_info.offload_tc;
1654
1655 return PQ_INIT_DEFAULT_TC;
1656}
1657
1658static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
1659 struct qed_qm_info *qm_info,
1660 u8 tc, u32 pq_init_flags)
1661{
1662 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
1663
1664 if (pq_idx > max_pq)
1665 DP_ERR(p_hwfn,
1666 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
1667
1668 /* init pq params */
1669 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
1670 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
1671 qm_info->num_vports;
1672 qm_info->qm_pq_params[pq_idx].tc_id = tc;
1673 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
1674 qm_info->qm_pq_params[pq_idx].rl_valid =
1675 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
1676
1677 /* qm params accounting */
1678 qm_info->num_pqs++;
1679 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
1680 qm_info->num_vports++;
1681
1682 if (pq_init_flags & PQ_INIT_PF_RL)
1683 qm_info->num_pf_rls++;
1684
1685 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
1686 DP_ERR(p_hwfn,
1687 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
1688 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
1689
1690 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
1691 DP_ERR(p_hwfn,
1692 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
1693 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
1694}
1695
1696/* get pq index according to PQ_FLAGS */
1697static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
1698 unsigned long pq_flags)
1699{
1700 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1701
1702 /* Can't have multiple flags set here */
1703 if (bitmap_weight(&pq_flags,
1704 sizeof(pq_flags) * BITS_PER_BYTE) > 1) {
1705 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags);
1706 goto err;
1707 }
1708
1709 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) {
1710 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags);
1711 goto err;
1712 }
1713
1714 switch (pq_flags) {
1715 case PQ_FLAGS_RLS:
1716 return &qm_info->first_rl_pq;
1717 case PQ_FLAGS_MCOS:
1718 return &qm_info->first_mcos_pq;
1719 case PQ_FLAGS_LB:
1720 return &qm_info->pure_lb_pq;
1721 case PQ_FLAGS_OOO:
1722 return &qm_info->ooo_pq;
1723 case PQ_FLAGS_ACK:
1724 return &qm_info->pure_ack_pq;
1725 case PQ_FLAGS_OFLD:
1726 return &qm_info->first_ofld_pq;
1727 case PQ_FLAGS_LLT:
1728 return &qm_info->first_llt_pq;
1729 case PQ_FLAGS_VFS:
1730 return &qm_info->first_vf_pq;
1731 default:
1732 goto err;
1733 }
1734
1735err:
1736 return &qm_info->start_pq;
1737}
1738
1739/* save pq index in qm info */
1740static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
1741 u32 pq_flags, u16 pq_val)
1742{
1743 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1744
1745 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
1746}
1747
1748/* get tx pq index, with the PQ TX base already set (ready for context init) */
1749u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
1750{
1751 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
1752
1753 return *base_pq_idx + CM_TX_PQ_BASE;
1754}
1755
1756u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
1757{
1758 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
1759
1760 if (max_tc == 0) {
1761 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1762 PQ_FLAGS_MCOS);
1763 return p_hwfn->qm_info.start_pq;
1764 }
1765
1766 if (tc > max_tc)
1767 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
1768
1769 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
1770}
1771
1772u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
1773{
1774 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
1775
1776 if (max_vf == 0) {
1777 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n",
1778 PQ_FLAGS_VFS);
1779 return p_hwfn->qm_info.start_pq;
1780 }
1781
1782 if (vf > max_vf)
1783 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
1784
1785 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
1786}
1787
1788u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1789{
1790 u16 first_ofld_pq, pq_offset;
1791
1792 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD);
1793 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1794 tc : PQ_INIT_DEFAULT_TC;
1795
1796 return first_ofld_pq + pq_offset;
1797}
1798
1799u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc)
1800{
1801 u16 first_llt_pq, pq_offset;
1802
1803 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT);
1804 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ?
1805 tc : PQ_INIT_DEFAULT_TC;
1806
1807 return first_llt_pq + pq_offset;
1808}
1809
1810/* Functions for creating specific types of pqs */
1811static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
1812{
1813 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1814
1815 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
1816 return;
1817
1818 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
1819 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
1820}
1821
1822static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
1823{
1824 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1825
1826 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
1827 return;
1828
1829 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
1830 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
1831}
1832
1833static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
1834{
1835 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1836
1837 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
1838 return;
1839
1840 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
1841 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1842 PQ_INIT_SHARE_VPORT);
1843}
1844
1845static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn)
1846{
1847 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn);
1848 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1849 u8 tc;
1850
1851 /* override pq's TC if offload TC is set */
1852 for (tc = 0; tc < num_tcs; tc++)
1853 qed_init_qm_pq(p_hwfn, qm_info,
1854 qed_is_offload_tc_set(p_hwfn) ?
1855 p_hwfn->hw_info.offload_tc : tc,
1856 PQ_INIT_SHARE_VPORT);
1857}
1858
1859static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
1860{
1861 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1862
1863 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
1864 return;
1865
1866 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
1867 qed_init_qm_mtc_pqs(p_hwfn);
1868}
1869
1870static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
1871{
1872 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1873
1874 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
1875 return;
1876
1877 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
1878 qed_init_qm_mtc_pqs(p_hwfn);
1879}
1880
1881static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
1882{
1883 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1884 u8 tc_idx;
1885
1886 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
1887 return;
1888
1889 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
1890 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
1891 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
1892}
1893
1894static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
1895{
1896 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1897 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
1898
1899 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
1900 return;
1901
1902 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
1903 qm_info->num_vf_pqs = num_vfs;
1904 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
1905 qed_init_qm_pq(p_hwfn,
1906 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
1907}
1908
1909static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
1910{
1911 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
1912 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1913
1914 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
1915 return;
1916
1917 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
1918 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
1919 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn),
1920 PQ_INIT_PF_RL);
1921}
1922
1923static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
1924{
1925 /* rate limited pqs, must come first (FW assumption) */
1926 qed_init_qm_rl_pqs(p_hwfn);
1927
1928 /* pqs for multi cos */
1929 qed_init_qm_mcos_pqs(p_hwfn);
1930
1931 /* pure loopback pq */
1932 qed_init_qm_lb_pq(p_hwfn);
1933
1934 /* out of order pq */
1935 qed_init_qm_ooo_pq(p_hwfn);
1936
1937 /* pure ack pq */
1938 qed_init_qm_pure_ack_pq(p_hwfn);
1939
1940 /* pq for offloaded protocol */
1941 qed_init_qm_offload_pq(p_hwfn);
1942
1943 /* low latency pq */
1944 qed_init_qm_low_latency_pq(p_hwfn);
1945
1946 /* done sharing vports */
1947 qed_init_qm_advance_vport(p_hwfn);
1948
1949 /* pqs for vfs */
1950 qed_init_qm_vf_pqs(p_hwfn);
1951}
1952
1953/* compare values of getters against resources amounts */
1954static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
1955{
1956 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
1957 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
1958 return -EINVAL;
1959 }
1960
1961 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1962 return 0;
1963
1964 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) {
1965 p_hwfn->hw_info.multi_tc_roce_en = false;
1966 DP_NOTICE(p_hwfn,
1967 "multi-tc roce was disabled to reduce requested amount of pqs\n");
1968 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ))
1969 return 0;
1970 }
1971
1972 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
1973 return -EINVAL;
1974}
1975
1976static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
1977{
1978 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1979 struct init_qm_vport_params *vport;
1980 struct init_qm_port_params *port;
1981 struct init_qm_pq_params *pq;
1982 int i, tc;
1983
1984 /* top level params */
1985 DP_VERBOSE(p_hwfn,
1986 NETIF_MSG_HW,
1987 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n",
1988 qm_info->start_pq,
1989 qm_info->start_vport,
1990 qm_info->pure_lb_pq,
1991 qm_info->first_ofld_pq,
1992 qm_info->first_llt_pq,
1993 qm_info->pure_ack_pq);
1994 DP_VERBOSE(p_hwfn,
1995 NETIF_MSG_HW,
1996 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
1997 qm_info->ooo_pq,
1998 qm_info->first_vf_pq,
1999 qm_info->num_pqs,
2000 qm_info->num_vf_pqs,
2001 qm_info->num_vports, qm_info->max_phys_tcs_per_port);
2002 DP_VERBOSE(p_hwfn,
2003 NETIF_MSG_HW,
2004 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
2005 qm_info->pf_rl_en,
2006 qm_info->pf_wfq_en,
2007 qm_info->vport_rl_en,
2008 qm_info->vport_wfq_en,
2009 qm_info->pf_wfq,
2010 qm_info->pf_rl,
2011 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
2012
2013 /* port table */
2014 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
2015 port = &(qm_info->qm_port_params[i]);
2016 DP_VERBOSE(p_hwfn,
2017 NETIF_MSG_HW,
2018 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
2019 i,
2020 port->active,
2021 port->active_phys_tcs,
2022 port->num_pbf_cmd_lines,
2023 port->num_btb_blocks, port->reserved);
2024 }
2025
2026 /* vport table */
2027 for (i = 0; i < qm_info->num_vports; i++) {
2028 vport = &(qm_info->qm_vport_params[i]);
2029 DP_VERBOSE(p_hwfn,
2030 NETIF_MSG_HW,
2031 "vport idx %d, wfq %d, first_tx_pq_id [ ",
2032 qm_info->start_vport + i, vport->wfq);
2033 for (tc = 0; tc < NUM_OF_TCS; tc++)
2034 DP_VERBOSE(p_hwfn,
2035 NETIF_MSG_HW,
2036 "%d ", vport->first_tx_pq_id[tc]);
2037 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
2038 }
2039
2040 /* pq table */
2041 for (i = 0; i < qm_info->num_pqs; i++) {
2042 pq = &(qm_info->qm_pq_params[i]);
2043 DP_VERBOSE(p_hwfn,
2044 NETIF_MSG_HW,
2045 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n",
2046 qm_info->start_pq + i,
2047 pq->port_id,
2048 pq->vport_id,
2049 pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id);
2050 }
2051}
2052
2053static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
2054{
2055 /* reset params required for init run */
2056 qed_init_qm_reset_params(p_hwfn);
2057
2058 /* init QM top level params */
2059 qed_init_qm_params(p_hwfn);
2060
2061 /* init QM port params */
2062 qed_init_qm_port_params(p_hwfn);
2063
2064 /* init QM vport params */
2065 qed_init_qm_vport_params(p_hwfn);
2066
2067 /* init QM physical queue params */
2068 qed_init_qm_pq_params(p_hwfn);
2069
2070 /* display all that init */
2071 qed_dp_init_qm_params(p_hwfn);
2072}
2073
2074/* This function reconfigures the QM pf on the fly.
2075 * For this purpose we:
2076 * 1. reconfigure the QM database
2077 * 2. set new values to runtime array
2078 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
2079 * 4. activate init tool in QM_PF stage
2080 * 5. send an sdm_qm_cmd through rbc interface to release the QM
2081 */
2082int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2083{
2084 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2085 bool b_rc;
2086 int rc;
2087
2088 /* initialize qed's qm data structure */
2089 qed_init_qm_info(p_hwfn);
2090
2091 /* stop PF's qm queues */
2092 spin_lock_bh(&qm_lock);
2093 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
2094 qm_info->start_pq, qm_info->num_pqs);
2095 spin_unlock_bh(&qm_lock);
2096 if (!b_rc)
2097 return -EINVAL;
2098
2099 /* prepare QM portion of runtime array */
2100 qed_qm_init_pf(p_hwfn, p_ptt, false);
2101
2102 /* activate init tool on runtime array */
2103 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
2104 p_hwfn->hw_info.hw_mode);
2105 if (rc)
2106 return rc;
2107
2108 /* start PF's qm queues */
2109 spin_lock_bh(&qm_lock);
2110 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
2111 qm_info->start_pq, qm_info->num_pqs);
2112 spin_unlock_bh(&qm_lock);
2113 if (!b_rc)
2114 return -EINVAL;
2115
2116 return 0;
2117}
2118
2119static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
2120{
2121 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2122 int rc;
2123
2124 rc = qed_init_qm_sanity(p_hwfn);
2125 if (rc)
2126 goto alloc_err;
2127
2128 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn),
2129 sizeof(*qm_info->qm_pq_params),
2130 GFP_KERNEL);
2131 if (!qm_info->qm_pq_params)
2132 goto alloc_err;
2133
2134 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2135 sizeof(*qm_info->qm_vport_params),
2136 GFP_KERNEL);
2137 if (!qm_info->qm_vport_params)
2138 goto alloc_err;
2139
2140 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine,
2141 sizeof(*qm_info->qm_port_params),
2142 GFP_KERNEL);
2143 if (!qm_info->qm_port_params)
2144 goto alloc_err;
2145
2146 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn),
2147 sizeof(*qm_info->wfq_data),
2148 GFP_KERNEL);
2149 if (!qm_info->wfq_data)
2150 goto alloc_err;
2151
2152 return 0;
2153
2154alloc_err:
2155 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
2156 qed_qm_info_free(p_hwfn);
2157 return -ENOMEM;
2158}
2159
2160int qed_resc_alloc(struct qed_dev *cdev)
2161{
2162 u32 rdma_tasks, excess_tasks;
2163 u32 line_count;
2164 int i, rc = 0;
2165
2166 if (IS_VF(cdev)) {
2167 for_each_hwfn(cdev, i) {
2168 rc = qed_l2_alloc(&cdev->hwfns[i]);
2169 if (rc)
2170 return rc;
2171 }
2172 return rc;
2173 }
2174
2175 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
2176 if (!cdev->fw_data)
2177 return -ENOMEM;
2178
2179 for_each_hwfn(cdev, i) {
2180 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2181 u32 n_eqes, num_cons;
2182
2183 /* Initialize the doorbell recovery mechanism */
2184 rc = qed_db_recovery_setup(p_hwfn);
2185 if (rc)
2186 goto alloc_err;
2187
2188 /* First allocate the context manager structure */
2189 rc = qed_cxt_mngr_alloc(p_hwfn);
2190 if (rc)
2191 goto alloc_err;
2192
2193 /* Set the HW cid/tid numbers (in the contest manager)
2194 * Must be done prior to any further computations.
2195 */
2196 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
2197 if (rc)
2198 goto alloc_err;
2199
2200 rc = qed_alloc_qm_data(p_hwfn);
2201 if (rc)
2202 goto alloc_err;
2203
2204 /* init qm info */
2205 qed_init_qm_info(p_hwfn);
2206
2207 /* Compute the ILT client partition */
2208 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2209 if (rc) {
2210 DP_NOTICE(p_hwfn,
2211 "too many ILT lines; re-computing with less lines\n");
2212 /* In case there are not enough ILT lines we reduce the
2213 * number of RDMA tasks and re-compute.
2214 */
2215 excess_tasks =
2216 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
2217 if (!excess_tasks)
2218 goto alloc_err;
2219
2220 rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
2221 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
2222 if (rc)
2223 goto alloc_err;
2224
2225 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
2226 if (rc) {
2227 DP_ERR(p_hwfn,
2228 "failed ILT compute. Requested too many lines: %u\n",
2229 line_count);
2230
2231 goto alloc_err;
2232 }
2233 }
2234
2235 /* CID map / ILT shadow table / T2
2236 * The talbes sizes are determined by the computations above
2237 */
2238 rc = qed_cxt_tables_alloc(p_hwfn);
2239 if (rc)
2240 goto alloc_err;
2241
2242 /* SPQ, must follow ILT because initializes SPQ context */
2243 rc = qed_spq_alloc(p_hwfn);
2244 if (rc)
2245 goto alloc_err;
2246
2247 /* SP status block allocation */
2248 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
2249 RESERVED_PTT_DPC);
2250
2251 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
2252 if (rc)
2253 goto alloc_err;
2254
2255 rc = qed_iov_alloc(p_hwfn);
2256 if (rc)
2257 goto alloc_err;
2258
2259 /* EQ */
2260 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
2261 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2262 u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn);
2263 enum protocol_type rdma_proto;
2264
2265 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
2266 rdma_proto = PROTOCOLID_ROCE;
2267 else
2268 rdma_proto = PROTOCOLID_IWARP;
2269
2270 num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
2271 rdma_proto,
2272 NULL) * 2;
2273 /* EQ should be able to get events from all SRQ's
2274 * at the same time
2275 */
2276 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq;
2277 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI ||
2278 p_hwfn->hw_info.personality == QED_PCI_NVMETCP) {
2279 num_cons =
2280 qed_cxt_get_proto_cid_count(p_hwfn,
2281 PROTOCOLID_TCP_ULP,
2282 NULL);
2283 n_eqes += 2 * num_cons;
2284 }
2285
2286 if (n_eqes > 0xFFFF) {
2287 DP_ERR(p_hwfn,
2288 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
2289 n_eqes, 0xFFFF);
2290 goto alloc_no_mem;
2291 }
2292
2293 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
2294 if (rc)
2295 goto alloc_err;
2296
2297 rc = qed_consq_alloc(p_hwfn);
2298 if (rc)
2299 goto alloc_err;
2300
2301 rc = qed_l2_alloc(p_hwfn);
2302 if (rc)
2303 goto alloc_err;
2304
2305#ifdef CONFIG_QED_LL2
2306 if (p_hwfn->using_ll2) {
2307 rc = qed_ll2_alloc(p_hwfn);
2308 if (rc)
2309 goto alloc_err;
2310 }
2311#endif
2312
2313 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2314 rc = qed_fcoe_alloc(p_hwfn);
2315 if (rc)
2316 goto alloc_err;
2317 }
2318
2319 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2320 rc = qed_iscsi_alloc(p_hwfn);
2321 if (rc)
2322 goto alloc_err;
2323 rc = qed_ooo_alloc(p_hwfn);
2324 if (rc)
2325 goto alloc_err;
2326 }
2327
2328 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) {
2329 rc = qed_nvmetcp_alloc(p_hwfn);
2330 if (rc)
2331 goto alloc_err;
2332 rc = qed_ooo_alloc(p_hwfn);
2333 if (rc)
2334 goto alloc_err;
2335 }
2336
2337 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2338 rc = qed_rdma_info_alloc(p_hwfn);
2339 if (rc)
2340 goto alloc_err;
2341 }
2342
2343 /* DMA info initialization */
2344 rc = qed_dmae_info_alloc(p_hwfn);
2345 if (rc)
2346 goto alloc_err;
2347
2348 /* DCBX initialization */
2349 rc = qed_dcbx_info_alloc(p_hwfn);
2350 if (rc)
2351 goto alloc_err;
2352
2353 rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info);
2354 if (rc)
2355 goto alloc_err;
2356 }
2357
2358 rc = qed_llh_alloc(cdev);
2359 if (rc) {
2360 DP_NOTICE(cdev,
2361 "Failed to allocate memory for the llh_info structure\n");
2362 goto alloc_err;
2363 }
2364
2365 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
2366 if (!cdev->reset_stats)
2367 goto alloc_no_mem;
2368
2369 return 0;
2370
2371alloc_no_mem:
2372 rc = -ENOMEM;
2373alloc_err:
2374 qed_resc_free(cdev);
2375 return rc;
2376}
2377
2378void qed_resc_setup(struct qed_dev *cdev)
2379{
2380 int i;
2381
2382 if (IS_VF(cdev)) {
2383 for_each_hwfn(cdev, i)
2384 qed_l2_setup(&cdev->hwfns[i]);
2385 return;
2386 }
2387
2388 for_each_hwfn(cdev, i) {
2389 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2390
2391 qed_cxt_mngr_setup(p_hwfn);
2392 qed_spq_setup(p_hwfn);
2393 qed_eq_setup(p_hwfn);
2394 qed_consq_setup(p_hwfn);
2395
2396 /* Read shadow of current MFW mailbox */
2397 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
2398 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2399 p_hwfn->mcp_info->mfw_mb_cur,
2400 p_hwfn->mcp_info->mfw_mb_length);
2401
2402 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
2403
2404 qed_l2_setup(p_hwfn);
2405 qed_iov_setup(p_hwfn);
2406#ifdef CONFIG_QED_LL2
2407 if (p_hwfn->using_ll2)
2408 qed_ll2_setup(p_hwfn);
2409#endif
2410 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2411 qed_fcoe_setup(p_hwfn);
2412
2413 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
2414 qed_iscsi_setup(p_hwfn);
2415 qed_ooo_setup(p_hwfn);
2416 }
2417
2418 if (p_hwfn->hw_info.personality == QED_PCI_NVMETCP) {
2419 qed_nvmetcp_setup(p_hwfn);
2420 qed_ooo_setup(p_hwfn);
2421 }
2422 }
2423}
2424
2425#define FINAL_CLEANUP_POLL_CNT (100)
2426#define FINAL_CLEANUP_POLL_TIME (10)
2427int qed_final_cleanup(struct qed_hwfn *p_hwfn,
2428 struct qed_ptt *p_ptt, u16 id, bool is_vf)
2429{
2430 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
2431 int rc = -EBUSY;
2432
2433 addr = GTT_BAR0_MAP_REG_USDM_RAM +
2434 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
2435
2436 if (is_vf)
2437 id += 0x10;
2438
2439 command |= X_FINAL_CLEANUP_AGG_INT <<
2440 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
2441 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
2442 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
2443 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
2444
2445 /* Make sure notification is not set before initiating final cleanup */
2446 if (REG_RD(p_hwfn, addr)) {
2447 DP_NOTICE(p_hwfn,
2448 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
2449 REG_WR(p_hwfn, addr, 0);
2450 }
2451
2452 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
2453 "Sending final cleanup for PFVF[%d] [Command %08x]\n",
2454 id, command);
2455
2456 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
2457
2458 /* Poll until completion */
2459 while (!REG_RD(p_hwfn, addr) && count--)
2460 msleep(FINAL_CLEANUP_POLL_TIME);
2461
2462 if (REG_RD(p_hwfn, addr))
2463 rc = 0;
2464 else
2465 DP_NOTICE(p_hwfn,
2466 "Failed to receive FW final cleanup notification\n");
2467
2468 /* Cleanup afterwards */
2469 REG_WR(p_hwfn, addr, 0);
2470
2471 return rc;
2472}
2473
2474static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
2475{
2476 int hw_mode = 0;
2477
2478 if (QED_IS_BB_B0(p_hwfn->cdev)) {
2479 hw_mode |= 1 << MODE_BB;
2480 } else if (QED_IS_AH(p_hwfn->cdev)) {
2481 hw_mode |= 1 << MODE_K2;
2482 } else {
2483 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
2484 p_hwfn->cdev->type);
2485 return -EINVAL;
2486 }
2487
2488 switch (p_hwfn->cdev->num_ports_in_engine) {
2489 case 1:
2490 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
2491 break;
2492 case 2:
2493 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
2494 break;
2495 case 4:
2496 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
2497 break;
2498 default:
2499 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
2500 p_hwfn->cdev->num_ports_in_engine);
2501 return -EINVAL;
2502 }
2503
2504 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
2505 hw_mode |= 1 << MODE_MF_SD;
2506 else
2507 hw_mode |= 1 << MODE_MF_SI;
2508
2509 hw_mode |= 1 << MODE_ASIC;
2510
2511 if (p_hwfn->cdev->num_hwfns > 1)
2512 hw_mode |= 1 << MODE_100G;
2513
2514 p_hwfn->hw_info.hw_mode = hw_mode;
2515
2516 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
2517 "Configuring function for hw_mode: 0x%08x\n",
2518 p_hwfn->hw_info.hw_mode);
2519
2520 return 0;
2521}
2522
2523/* Init run time data for all PFs on an engine. */
2524static void qed_init_cau_rt_data(struct qed_dev *cdev)
2525{
2526 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
2527 int i, igu_sb_id;
2528
2529 for_each_hwfn(cdev, i) {
2530 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
2531 struct qed_igu_info *p_igu_info;
2532 struct qed_igu_block *p_block;
2533 struct cau_sb_entry sb_entry;
2534
2535 p_igu_info = p_hwfn->hw_info.p_igu_info;
2536
2537 for (igu_sb_id = 0;
2538 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
2539 p_block = &p_igu_info->entry[igu_sb_id];
2540
2541 if (!p_block->is_pf)
2542 continue;
2543
2544 qed_init_cau_sb_entry(p_hwfn, &sb_entry,
2545 p_block->function_id, 0, 0);
2546 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
2547 sb_entry);
2548 }
2549 }
2550}
2551
2552static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
2553 struct qed_ptt *p_ptt)
2554{
2555 u32 val, wr_mbs, cache_line_size;
2556
2557 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
2558 switch (val) {
2559 case 0:
2560 wr_mbs = 128;
2561 break;
2562 case 1:
2563 wr_mbs = 256;
2564 break;
2565 case 2:
2566 wr_mbs = 512;
2567 break;
2568 default:
2569 DP_INFO(p_hwfn,
2570 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2571 val);
2572 return;
2573 }
2574
2575 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
2576 switch (cache_line_size) {
2577 case 32:
2578 val = 0;
2579 break;
2580 case 64:
2581 val = 1;
2582 break;
2583 case 128:
2584 val = 2;
2585 break;
2586 case 256:
2587 val = 3;
2588 break;
2589 default:
2590 DP_INFO(p_hwfn,
2591 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
2592 cache_line_size);
2593 }
2594
2595 if (L1_CACHE_BYTES > wr_mbs)
2596 DP_INFO(p_hwfn,
2597 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
2598 L1_CACHE_BYTES, wr_mbs);
2599
2600 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
2601 if (val > 0) {
2602 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
2603 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
2604 }
2605}
2606
2607static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
2608 struct qed_ptt *p_ptt, int hw_mode)
2609{
2610 struct qed_qm_info *qm_info = &p_hwfn->qm_info;
2611 struct qed_qm_common_rt_init_params params;
2612 struct qed_dev *cdev = p_hwfn->cdev;
2613 u8 vf_id, max_num_vfs;
2614 u16 num_pfs, pf_id;
2615 u32 concrete_fid;
2616 int rc = 0;
2617
2618 qed_init_cau_rt_data(cdev);
2619
2620 /* Program GTT windows */
2621 qed_gtt_init(p_hwfn);
2622
2623 if (p_hwfn->mcp_info) {
2624 if (p_hwfn->mcp_info->func_info.bandwidth_max)
2625 qm_info->pf_rl_en = true;
2626 if (p_hwfn->mcp_info->func_info.bandwidth_min)
2627 qm_info->pf_wfq_en = true;
2628 }
2629
2630 memset(¶ms, 0, sizeof(params));
2631 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
2632 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
2633 params.pf_rl_en = qm_info->pf_rl_en;
2634 params.pf_wfq_en = qm_info->pf_wfq_en;
2635 params.global_rl_en = qm_info->vport_rl_en;
2636 params.vport_wfq_en = qm_info->vport_wfq_en;
2637 params.port_params = qm_info->qm_port_params;
2638
2639 qed_qm_common_rt_init(p_hwfn, ¶ms);
2640
2641 qed_cxt_hw_init_common(p_hwfn);
2642
2643 qed_init_cache_line_size(p_hwfn, p_ptt);
2644
2645 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
2646 if (rc)
2647 return rc;
2648
2649 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
2650 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
2651
2652 if (QED_IS_BB(p_hwfn->cdev)) {
2653 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
2654 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
2655 qed_fid_pretend(p_hwfn, p_ptt, pf_id);
2656 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
2657 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
2658 }
2659 /* pretend to original PF */
2660 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2661 }
2662
2663 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
2664 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
2665 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
2666 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
2667 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
2668 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
2669 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
2670 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
2671 }
2672 /* pretend to original PF */
2673 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
2674
2675 return rc;
2676}
2677
2678static int
2679qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
2680 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
2681{
2682 u32 dpi_bit_shift, dpi_count, dpi_page_size;
2683 u32 min_dpis;
2684 u32 n_wids;
2685
2686 /* Calculate DPI size */
2687 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
2688 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
2689 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
2690 dpi_bit_shift = ilog2(dpi_page_size / 4096);
2691 dpi_count = pwm_region_size / dpi_page_size;
2692
2693 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
2694 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
2695
2696 p_hwfn->dpi_size = dpi_page_size;
2697 p_hwfn->dpi_count = dpi_count;
2698
2699 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
2700
2701 if (dpi_count < min_dpis)
2702 return -EINVAL;
2703
2704 return 0;
2705}
2706
2707enum QED_ROCE_EDPM_MODE {
2708 QED_ROCE_EDPM_MODE_ENABLE = 0,
2709 QED_ROCE_EDPM_MODE_FORCE_ON = 1,
2710 QED_ROCE_EDPM_MODE_DISABLE = 2,
2711};
2712
2713bool qed_edpm_enabled(struct qed_hwfn *p_hwfn)
2714{
2715 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm)
2716 return false;
2717
2718 return true;
2719}
2720
2721static int
2722qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2723{
2724 u32 pwm_regsize, norm_regsize;
2725 u32 non_pwm_conn, min_addr_reg1;
2726 u32 db_bar_size, n_cpus = 1;
2727 u32 roce_edpm_mode;
2728 u32 pf_dems_shift;
2729 int rc = 0;
2730 u8 cond;
2731
2732 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
2733 if (p_hwfn->cdev->num_hwfns > 1)
2734 db_bar_size /= 2;
2735
2736 /* Calculate doorbell regions */
2737 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
2738 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
2739 NULL) +
2740 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2741 NULL);
2742 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
2743 min_addr_reg1 = norm_regsize / 4096;
2744 pwm_regsize = db_bar_size - norm_regsize;
2745
2746 /* Check that the normal and PWM sizes are valid */
2747 if (db_bar_size < norm_regsize) {
2748 DP_ERR(p_hwfn->cdev,
2749 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
2750 db_bar_size, norm_regsize);
2751 return -EINVAL;
2752 }
2753
2754 if (pwm_regsize < QED_MIN_PWM_REGION) {
2755 DP_ERR(p_hwfn->cdev,
2756 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
2757 pwm_regsize,
2758 QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
2759 return -EINVAL;
2760 }
2761
2762 /* Calculate number of DPIs */
2763 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
2764 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
2765 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
2766 /* Either EDPM is mandatory, or we are attempting to allocate a
2767 * WID per CPU.
2768 */
2769 n_cpus = num_present_cpus();
2770 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2771 }
2772
2773 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
2774 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
2775 if (cond || p_hwfn->dcbx_no_edpm) {
2776 /* Either EDPM is disabled from user configuration, or it is
2777 * disabled via DCBx, or it is not mandatory and we failed to
2778 * allocated a WID per CPU.
2779 */
2780 n_cpus = 1;
2781 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
2782
2783 if (cond)
2784 qed_rdma_dpm_bar(p_hwfn, p_ptt);
2785 }
2786
2787 p_hwfn->wid_count = (u16) n_cpus;
2788
2789 DP_INFO(p_hwfn,
2790 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
2791 norm_regsize,
2792 pwm_regsize,
2793 p_hwfn->dpi_size,
2794 p_hwfn->dpi_count,
2795 (!qed_edpm_enabled(p_hwfn)) ?
2796 "disabled" : "enabled", PAGE_SIZE);
2797
2798 if (rc) {
2799 DP_ERR(p_hwfn,
2800 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
2801 p_hwfn->dpi_count,
2802 p_hwfn->pf_params.rdma_pf_params.min_dpis);
2803 return -EINVAL;
2804 }
2805
2806 p_hwfn->dpi_start_offset = norm_regsize;
2807
2808 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
2809 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
2810 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
2811 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
2812
2813 return 0;
2814}
2815
2816static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
2817 struct qed_ptt *p_ptt, int hw_mode)
2818{
2819 int rc = 0;
2820
2821 /* In CMT the gate should be cleared by the 2nd hwfn */
2822 if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn))
2823 STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
2824
2825 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
2826 if (rc)
2827 return rc;
2828
2829 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
2830
2831 return 0;
2832}
2833
2834static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
2835 struct qed_ptt *p_ptt,
2836 struct qed_tunnel_info *p_tunn,
2837 int hw_mode,
2838 bool b_hw_start,
2839 enum qed_int_mode int_mode,
2840 bool allow_npar_tx_switch)
2841{
2842 u8 rel_pf_id = p_hwfn->rel_pf_id;
2843 int rc = 0;
2844
2845 if (p_hwfn->mcp_info) {
2846 struct qed_mcp_function_info *p_info;
2847
2848 p_info = &p_hwfn->mcp_info->func_info;
2849 if (p_info->bandwidth_min)
2850 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
2851
2852 /* Update rate limit once we'll actually have a link */
2853 p_hwfn->qm_info.pf_rl = 100000;
2854 }
2855
2856 qed_cxt_hw_init_pf(p_hwfn, p_ptt);
2857
2858 qed_int_igu_init_rt(p_hwfn);
2859
2860 /* Set VLAN in NIG if needed */
2861 if (hw_mode & BIT(MODE_MF_SD)) {
2862 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
2863 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
2864 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
2865 p_hwfn->hw_info.ovlan);
2866
2867 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2868 "Configuring LLH_FUNC_FILTER_HDR_SEL\n");
2869 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
2870 1);
2871 }
2872
2873 /* Enable classification by MAC if needed */
2874 if (hw_mode & BIT(MODE_MF_SI)) {
2875 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
2876 "Configuring TAGMAC_CLS_TYPE\n");
2877 STORE_RT_REG(p_hwfn,
2878 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
2879 }
2880
2881 /* Protocol Configuration */
2882 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
2883 ((p_hwfn->hw_info.personality == QED_PCI_ISCSI) ||
2884 (p_hwfn->hw_info.personality == QED_PCI_NVMETCP)) ? 1 : 0);
2885 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
2886 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
2887 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
2888
2889 /* Sanity check before the PF init sequence that uses DMAE */
2890 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
2891 if (rc)
2892 return rc;
2893
2894 /* PF Init sequence */
2895 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
2896 if (rc)
2897 return rc;
2898
2899 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
2900 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
2901 if (rc)
2902 return rc;
2903
2904 qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
2905
2906 /* Pure runtime initializations - directly to the HW */
2907 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
2908
2909 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
2910 if (rc)
2911 return rc;
2912
2913 /* Use the leading hwfn since in CMT only NIG #0 is operational */
2914 if (IS_LEAD_HWFN(p_hwfn)) {
2915 rc = qed_llh_hw_init_pf(p_hwfn, p_ptt);
2916 if (rc)
2917 return rc;
2918 }
2919
2920 if (b_hw_start) {
2921 /* enable interrupts */
2922 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
2923
2924 /* send function start command */
2925 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
2926 allow_npar_tx_switch);
2927 if (rc) {
2928 DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
2929 return rc;
2930 }
2931 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
2932 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
2933 qed_wr(p_hwfn, p_ptt,
2934 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
2935 0x100);
2936 }
2937 }
2938 return rc;
2939}
2940
2941int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
2942 struct qed_ptt *p_ptt, bool b_enable)
2943{
2944 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0;
2945
2946 /* Configure the PF's internal FID_enable for master transactions */
2947 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
2948
2949 /* Wait until value is set - try for 1 second every 50us */
2950 for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
2951 val = qed_rd(p_hwfn, p_ptt,
2952 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
2953 if (val == set_val)
2954 break;
2955
2956 usleep_range(50, 60);
2957 }
2958
2959 if (val != set_val) {
2960 DP_NOTICE(p_hwfn,
2961 "PFID_ENABLE_MASTER wasn't changed after a second\n");
2962 return -EAGAIN;
2963 }
2964
2965 return 0;
2966}
2967
2968static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
2969 struct qed_ptt *p_main_ptt)
2970{
2971 /* Read shadow of current MFW mailbox */
2972 qed_mcp_read_mb(p_hwfn, p_main_ptt);
2973 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
2974 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
2975}
2976
2977static void
2978qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
2979 struct qed_drv_load_params *p_drv_load)
2980{
2981 memset(p_load_req, 0, sizeof(*p_load_req));
2982
2983 p_load_req->drv_role = p_drv_load->is_crash_kernel ?
2984 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
2985 p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
2986 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
2987 p_load_req->override_force_load = p_drv_load->override_force_load;
2988}
2989
2990static int qed_vf_start(struct qed_hwfn *p_hwfn,
2991 struct qed_hw_init_params *p_params)
2992{
2993 if (p_params->p_tunn) {
2994 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
2995 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
2996 }
2997
2998 p_hwfn->b_int_enabled = true;
2999
3000 return 0;
3001}
3002
3003static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3004{
3005 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR,
3006 BIT(p_hwfn->abs_pf_id));
3007}
3008
3009int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
3010{
3011 struct qed_load_req_params load_req_params;
3012 u32 load_code, resp, param, drv_mb_param;
3013 bool b_default_mtu = true;
3014 struct qed_hwfn *p_hwfn;
3015 const u32 *fw_overlays;
3016 u32 fw_overlays_len;
3017 u16 ether_type;
3018 int rc = 0, i;
3019
3020 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
3021 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
3022 return -EINVAL;
3023 }
3024
3025 if (IS_PF(cdev)) {
3026 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
3027 if (rc)
3028 return rc;
3029 }
3030
3031 for_each_hwfn(cdev, i) {
3032 p_hwfn = &cdev->hwfns[i];
3033
3034 /* If management didn't provide a default, set one of our own */
3035 if (!p_hwfn->hw_info.mtu) {
3036 p_hwfn->hw_info.mtu = 1500;
3037 b_default_mtu = false;
3038 }
3039
3040 if (IS_VF(cdev)) {
3041 qed_vf_start(p_hwfn, p_params);
3042 continue;
3043 }
3044
3045 rc = qed_calc_hw_mode(p_hwfn);
3046 if (rc)
3047 return rc;
3048
3049 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
3050 &cdev->mf_bits) ||
3051 test_bit(QED_MF_8021AD_TAGGING,
3052 &cdev->mf_bits))) {
3053 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
3054 ether_type = ETH_P_8021Q;
3055 else
3056 ether_type = ETH_P_8021AD;
3057 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3058 ether_type);
3059 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3060 ether_type);
3061 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
3062 ether_type);
3063 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
3064 ether_type);
3065 }
3066
3067 qed_fill_load_req_params(&load_req_params,
3068 p_params->p_drv_load_params);
3069 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
3070 &load_req_params);
3071 if (rc) {
3072 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
3073 return rc;
3074 }
3075
3076 load_code = load_req_params.load_code;
3077 DP_VERBOSE(p_hwfn, QED_MSG_SP,
3078 "Load request was sent. Load code: 0x%x\n",
3079 load_code);
3080
3081 /* Only relevant for recovery:
3082 * Clear the indication after LOAD_REQ is responded by the MFW.
3083 */
3084 cdev->recov_in_prog = false;
3085
3086 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
3087
3088 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
3089
3090 /* Clean up chip from previous driver if such remains exist.
3091 * This is not needed when the PF is the first one on the
3092 * engine, since afterwards we are going to init the FW.
3093 */
3094 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) {
3095 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt,
3096 p_hwfn->rel_pf_id, false);
3097 if (rc) {
3098 qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt,
3099 QED_HW_ERR_RAMROD_FAIL,
3100 "Final cleanup failed\n");
3101 goto load_err;
3102 }
3103 }
3104
3105 /* Log and clear previous pglue_b errors if such exist */
3106 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt, true);
3107
3108 /* Enable the PF's internal FID_enable in the PXP */
3109 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt,
3110 true);
3111 if (rc)
3112 goto load_err;
3113
3114 /* Clear the pglue_b was_error indication.
3115 * In E4 it must be done after the BME and the internal
3116 * FID_enable for the PF are set, since VDMs may cause the
3117 * indication to be set again.
3118 */
3119 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3120
3121 fw_overlays = cdev->fw_data->fw_overlays;
3122 fw_overlays_len = cdev->fw_data->fw_overlays_len;
3123 p_hwfn->fw_overlay_mem =
3124 qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
3125 fw_overlays_len);
3126 if (!p_hwfn->fw_overlay_mem) {
3127 DP_NOTICE(p_hwfn,
3128 "Failed to allocate fw overlay memory\n");
3129 rc = -ENOMEM;
3130 goto load_err;
3131 }
3132
3133 switch (load_code) {
3134 case FW_MSG_CODE_DRV_LOAD_ENGINE:
3135 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
3136 p_hwfn->hw_info.hw_mode);
3137 if (rc)
3138 break;
3139 fallthrough;
3140 case FW_MSG_CODE_DRV_LOAD_PORT:
3141 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
3142 p_hwfn->hw_info.hw_mode);
3143 if (rc)
3144 break;
3145
3146 fallthrough;
3147 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
3148 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
3149 p_params->p_tunn,
3150 p_hwfn->hw_info.hw_mode,
3151 p_params->b_hw_start,
3152 p_params->int_mode,
3153 p_params->allow_npar_tx_switch);
3154 break;
3155 default:
3156 DP_NOTICE(p_hwfn,
3157 "Unexpected load code [0x%08x]", load_code);
3158 rc = -EINVAL;
3159 break;
3160 }
3161
3162 if (rc) {
3163 DP_NOTICE(p_hwfn,
3164 "init phase failed for loadcode 0x%x (rc %d)\n",
3165 load_code, rc);
3166 goto load_err;
3167 }
3168
3169 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3170 if (rc)
3171 return rc;
3172
3173 /* send DCBX attention request command */
3174 DP_VERBOSE(p_hwfn,
3175 QED_MSG_DCB,
3176 "sending phony dcbx set command to trigger DCBx attention handling\n");
3177 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3178 DRV_MSG_CODE_SET_DCBX,
3179 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
3180 &resp, ¶m);
3181 if (rc) {
3182 DP_NOTICE(p_hwfn,
3183 "Failed to send DCBX attention request\n");
3184 return rc;
3185 }
3186
3187 p_hwfn->hw_init_done = true;
3188 }
3189
3190 if (IS_PF(cdev)) {
3191 p_hwfn = QED_LEADING_HWFN(cdev);
3192
3193 /* Get pre-negotiated values for stag, bandwidth etc. */
3194 DP_VERBOSE(p_hwfn,
3195 QED_MSG_SPQ,
3196 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
3197 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET;
3198 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3199 DRV_MSG_CODE_GET_OEM_UPDATES,
3200 drv_mb_param, &resp, ¶m);
3201 if (rc)
3202 DP_NOTICE(p_hwfn,
3203 "Failed to send GET_OEM_UPDATES attention request\n");
3204
3205 drv_mb_param = STORM_FW_VERSION;
3206 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
3207 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
3208 drv_mb_param, &load_code, ¶m);
3209 if (rc)
3210 DP_INFO(p_hwfn, "Failed to update firmware version\n");
3211
3212 if (!b_default_mtu) {
3213 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
3214 p_hwfn->hw_info.mtu);
3215 if (rc)
3216 DP_INFO(p_hwfn,
3217 "Failed to update default mtu\n");
3218 }
3219
3220 rc = qed_mcp_ov_update_driver_state(p_hwfn,
3221 p_hwfn->p_main_ptt,
3222 QED_OV_DRIVER_STATE_DISABLED);
3223 if (rc)
3224 DP_INFO(p_hwfn, "Failed to update driver state\n");
3225
3226 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
3227 QED_OV_ESWITCH_NONE);
3228 if (rc)
3229 DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
3230 }
3231
3232 return 0;
3233
3234load_err:
3235 /* The MFW load lock should be released also when initialization fails.
3236 */
3237 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt);
3238 return rc;
3239}
3240
3241#define QED_HW_STOP_RETRY_LIMIT (10)
3242static void qed_hw_timers_stop(struct qed_dev *cdev,
3243 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3244{
3245 int i;
3246
3247 /* close timers */
3248 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
3249 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
3250
3251 if (cdev->recov_in_prog)
3252 return;
3253
3254 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
3255 if ((!qed_rd(p_hwfn, p_ptt,
3256 TM_REG_PF_SCAN_ACTIVE_CONN)) &&
3257 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
3258 break;
3259
3260 /* Dependent on number of connection/tasks, possibly
3261 * 1ms sleep is required between polls
3262 */
3263 usleep_range(1000, 2000);
3264 }
3265
3266 if (i < QED_HW_STOP_RETRY_LIMIT)
3267 return;
3268
3269 DP_NOTICE(p_hwfn,
3270 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
3271 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
3272 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
3273}
3274
3275void qed_hw_timers_stop_all(struct qed_dev *cdev)
3276{
3277 int j;
3278
3279 for_each_hwfn(cdev, j) {
3280 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3281 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
3282
3283 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3284 }
3285}
3286
3287int qed_hw_stop(struct qed_dev *cdev)
3288{
3289 struct qed_hwfn *p_hwfn;
3290 struct qed_ptt *p_ptt;
3291 int rc, rc2 = 0;
3292 int j;
3293
3294 for_each_hwfn(cdev, j) {
3295 p_hwfn = &cdev->hwfns[j];
3296 p_ptt = p_hwfn->p_main_ptt;
3297
3298 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
3299
3300 if (IS_VF(cdev)) {
3301 qed_vf_pf_int_cleanup(p_hwfn);
3302 rc = qed_vf_pf_reset(p_hwfn);
3303 if (rc) {
3304 DP_NOTICE(p_hwfn,
3305 "qed_vf_pf_reset failed. rc = %d.\n",
3306 rc);
3307 rc2 = -EINVAL;
3308 }
3309 continue;
3310 }
3311
3312 /* mark the hw as uninitialized... */
3313 p_hwfn->hw_init_done = false;
3314
3315 /* Send unload command to MCP */
3316 if (!cdev->recov_in_prog) {
3317 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
3318 if (rc) {
3319 DP_NOTICE(p_hwfn,
3320 "Failed sending a UNLOAD_REQ command. rc = %d.\n",
3321 rc);
3322 rc2 = -EINVAL;
3323 }
3324 }
3325
3326 qed_slowpath_irq_sync(p_hwfn);
3327
3328 /* After this point no MFW attentions are expected, e.g. prevent
3329 * race between pf stop and dcbx pf update.
3330 */
3331 rc = qed_sp_pf_stop(p_hwfn);
3332 if (rc) {
3333 DP_NOTICE(p_hwfn,
3334 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
3335 rc);
3336 rc2 = -EINVAL;
3337 }
3338
3339 qed_wr(p_hwfn, p_ptt,
3340 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3341
3342 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3343 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3344 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3345 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3346 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3347
3348 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
3349
3350 /* Disable Attention Generation */
3351 qed_int_igu_disable_int(p_hwfn, p_ptt);
3352
3353 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
3354 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
3355
3356 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
3357
3358 /* Need to wait 1ms to guarantee SBs are cleared */
3359 usleep_range(1000, 2000);
3360
3361 /* Disable PF in HW blocks */
3362 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
3363 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
3364
3365 if (IS_LEAD_HWFN(p_hwfn) &&
3366 test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) &&
3367 !QED_IS_FCOE_PERSONALITY(p_hwfn))
3368 qed_llh_remove_mac_filter(cdev, 0,
3369 p_hwfn->hw_info.hw_mac_addr);
3370
3371 if (!cdev->recov_in_prog) {
3372 rc = qed_mcp_unload_done(p_hwfn, p_ptt);
3373 if (rc) {
3374 DP_NOTICE(p_hwfn,
3375 "Failed sending a UNLOAD_DONE command. rc = %d.\n",
3376 rc);
3377 rc2 = -EINVAL;
3378 }
3379 }
3380 }
3381
3382 if (IS_PF(cdev) && !cdev->recov_in_prog) {
3383 p_hwfn = QED_LEADING_HWFN(cdev);
3384 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
3385
3386 /* Clear the PF's internal FID_enable in the PXP.
3387 * In CMT this should only be done for first hw-function, and
3388 * only after all transactions have stopped for all active
3389 * hw-functions.
3390 */
3391 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3392 if (rc) {
3393 DP_NOTICE(p_hwfn,
3394 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n",
3395 rc);
3396 rc2 = -EINVAL;
3397 }
3398 }
3399
3400 return rc2;
3401}
3402
3403int qed_hw_stop_fastpath(struct qed_dev *cdev)
3404{
3405 int j;
3406
3407 for_each_hwfn(cdev, j) {
3408 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
3409 struct qed_ptt *p_ptt;
3410
3411 if (IS_VF(cdev)) {
3412 qed_vf_pf_int_cleanup(p_hwfn);
3413 continue;
3414 }
3415 p_ptt = qed_ptt_acquire(p_hwfn);
3416 if (!p_ptt)
3417 return -EAGAIN;
3418
3419 DP_VERBOSE(p_hwfn,
3420 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
3421
3422 qed_wr(p_hwfn, p_ptt,
3423 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
3424
3425 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
3426 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
3427 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
3428 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
3429 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
3430
3431 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
3432
3433 /* Need to wait 1ms to guarantee SBs are cleared */
3434 usleep_range(1000, 2000);
3435 qed_ptt_release(p_hwfn, p_ptt);
3436 }
3437
3438 return 0;
3439}
3440
3441int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
3442{
3443 struct qed_ptt *p_ptt;
3444
3445 if (IS_VF(p_hwfn->cdev))
3446 return 0;
3447
3448 p_ptt = qed_ptt_acquire(p_hwfn);
3449 if (!p_ptt)
3450 return -EAGAIN;
3451
3452 if (p_hwfn->p_rdma_info &&
3453 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs)
3454 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
3455
3456 /* Re-open incoming traffic */
3457 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
3458 qed_ptt_release(p_hwfn, p_ptt);
3459
3460 return 0;
3461}
3462
3463/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
3464static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
3465{
3466 qed_ptt_pool_free(p_hwfn);
3467 kfree(p_hwfn->hw_info.p_igu_info);
3468 p_hwfn->hw_info.p_igu_info = NULL;
3469}
3470
3471/* Setup bar access */
3472static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
3473{
3474 /* clear indirect access */
3475 if (QED_IS_AH(p_hwfn->cdev)) {
3476 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3477 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
3478 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3479 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
3480 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3481 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
3482 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3483 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
3484 } else {
3485 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3486 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
3487 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3488 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
3489 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3490 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
3491 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3492 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
3493 }
3494
3495 /* Clean previous pglue_b errors if such exist */
3496 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
3497
3498 /* enable internal target-read */
3499 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
3500 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
3501}
3502
3503static void get_function_id(struct qed_hwfn *p_hwfn)
3504{
3505 /* ME Register */
3506 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
3507 PXP_PF_ME_OPAQUE_ADDR);
3508
3509 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
3510
3511 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
3512 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3513 PXP_CONCRETE_FID_PFID);
3514 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
3515 PXP_CONCRETE_FID_PORT);
3516
3517 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
3518 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
3519 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
3520}
3521
3522static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
3523{
3524 u32 *feat_num = p_hwfn->hw_info.feat_num;
3525 struct qed_sb_cnt_info sb_cnt;
3526 u32 non_l2_sbs = 0;
3527
3528 memset(&sb_cnt, 0, sizeof(sb_cnt));
3529 qed_int_get_num_sbs(p_hwfn, &sb_cnt);
3530
3531 if (IS_ENABLED(CONFIG_QED_RDMA) &&
3532 QED_IS_RDMA_PERSONALITY(p_hwfn)) {
3533 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
3534 * the status blocks equally between L2 / RoCE but with
3535 * consideration as to how many l2 queues / cnqs we have.
3536 */
3537 feat_num[QED_RDMA_CNQ] =
3538 min_t(u32, sb_cnt.cnt / 2,
3539 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
3540
3541 non_l2_sbs = feat_num[QED_RDMA_CNQ];
3542 }
3543 if (QED_IS_L2_PERSONALITY(p_hwfn)) {
3544 /* Start by allocating VF queues, then PF's */
3545 feat_num[QED_VF_L2_QUE] = min_t(u32,
3546 RESC_NUM(p_hwfn, QED_L2_QUEUE),
3547 sb_cnt.iov_cnt);
3548 feat_num[QED_PF_L2_QUE] = min_t(u32,
3549 sb_cnt.cnt - non_l2_sbs,
3550 RESC_NUM(p_hwfn,
3551 QED_L2_QUEUE) -
3552 FEAT_NUM(p_hwfn,
3553 QED_VF_L2_QUE));
3554 }
3555
3556 if (QED_IS_FCOE_PERSONALITY(p_hwfn))
3557 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt,
3558 RESC_NUM(p_hwfn,
3559 QED_CMDQS_CQS));
3560
3561 if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
3562 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
3563 RESC_NUM(p_hwfn,
3564 QED_CMDQS_CQS));
3565
3566 if (QED_IS_NVMETCP_PERSONALITY(p_hwfn))
3567 feat_num[QED_NVMETCP_CQ] = min_t(u32, sb_cnt.cnt,
3568 RESC_NUM(p_hwfn,
3569 QED_CMDQS_CQS));
3570
3571 DP_VERBOSE(p_hwfn,
3572 NETIF_MSG_PROBE,
3573 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d NVMETCP_CQ=%d #SBS=%d\n",
3574 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
3575 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
3576 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
3577 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
3578 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
3579 (int)FEAT_NUM(p_hwfn, QED_NVMETCP_CQ),
3580 (int)sb_cnt.cnt);
3581}
3582
3583const char *qed_hw_get_resc_name(enum qed_resources res_id)
3584{
3585 switch (res_id) {
3586 case QED_L2_QUEUE:
3587 return "L2_QUEUE";
3588 case QED_VPORT:
3589 return "VPORT";
3590 case QED_RSS_ENG:
3591 return "RSS_ENG";
3592 case QED_PQ:
3593 return "PQ";
3594 case QED_RL:
3595 return "RL";
3596 case QED_MAC:
3597 return "MAC";
3598 case QED_VLAN:
3599 return "VLAN";
3600 case QED_RDMA_CNQ_RAM:
3601 return "RDMA_CNQ_RAM";
3602 case QED_ILT:
3603 return "ILT";
3604 case QED_LL2_RAM_QUEUE:
3605 return "LL2_RAM_QUEUE";
3606 case QED_LL2_CTX_QUEUE:
3607 return "LL2_CTX_QUEUE";
3608 case QED_CMDQS_CQS:
3609 return "CMDQS_CQS";
3610 case QED_RDMA_STATS_QUEUE:
3611 return "RDMA_STATS_QUEUE";
3612 case QED_BDQ:
3613 return "BDQ";
3614 case QED_SB:
3615 return "SB";
3616 default:
3617 return "UNKNOWN_RESOURCE";
3618 }
3619}
3620
3621static int
3622__qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
3623 struct qed_ptt *p_ptt,
3624 enum qed_resources res_id,
3625 u32 resc_max_val, u32 *p_mcp_resp)
3626{
3627 int rc;
3628
3629 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
3630 resc_max_val, p_mcp_resp);
3631 if (rc) {
3632 DP_NOTICE(p_hwfn,
3633 "MFW response failure for a max value setting of resource %d [%s]\n",
3634 res_id, qed_hw_get_resc_name(res_id));
3635 return rc;
3636 }
3637
3638 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
3639 DP_INFO(p_hwfn,
3640 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
3641 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
3642
3643 return 0;
3644}
3645
3646static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
3647 {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
3648 {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
3649 {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
3650 {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,},
3651 {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
3652 {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
3653 {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
3654 {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
3655 {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
3656 {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
3657 {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
3658 {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
3659 {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
3660};
3661
3662u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
3663{
3664 enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2;
3665
3666 if (type >= QED_NUM_HSI_DEFS) {
3667 DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type);
3668 return 0;
3669 }
3670
3671 return qed_hsi_def_val[type][chip_id];
3672}
3673static int
3674qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3675{
3676 u32 resc_max_val, mcp_resp;
3677 u8 res_id;
3678 int rc;
3679 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3680 switch (res_id) {
3681 case QED_LL2_RAM_QUEUE:
3682 resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES;
3683 break;
3684 case QED_LL2_CTX_QUEUE:
3685 resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES;
3686 break;
3687 case QED_RDMA_CNQ_RAM:
3688 /* No need for a case for QED_CMDQS_CQS since
3689 * CNQ/CMDQS are the same resource.
3690 */
3691 resc_max_val = NUM_OF_GLOBAL_QUEUES;
3692 break;
3693 case QED_RDMA_STATS_QUEUE:
3694 resc_max_val =
3695 NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev);
3696 break;
3697 case QED_BDQ:
3698 resc_max_val = BDQ_NUM_RESOURCES;
3699 break;
3700 default:
3701 continue;
3702 }
3703
3704 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
3705 resc_max_val, &mcp_resp);
3706 if (rc)
3707 return rc;
3708
3709 /* There's no point to continue to the next resource if the
3710 * command is not supported by the MFW.
3711 * We do continue if the command is supported but the resource
3712 * is unknown to the MFW. Such a resource will be later
3713 * configured with the default allocation values.
3714 */
3715 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
3716 return -EINVAL;
3717 }
3718
3719 return 0;
3720}
3721
3722static
3723int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
3724 enum qed_resources res_id,
3725 u32 *p_resc_num, u32 *p_resc_start)
3726{
3727 u8 num_funcs = p_hwfn->num_funcs_on_engine;
3728 struct qed_dev *cdev = p_hwfn->cdev;
3729
3730 switch (res_id) {
3731 case QED_L2_QUEUE:
3732 *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs;
3733 break;
3734 case QED_VPORT:
3735 *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs;
3736 break;
3737 case QED_RSS_ENG:
3738 *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs;
3739 break;
3740 case QED_PQ:
3741 *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs;
3742 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
3743 break;
3744 case QED_RL:
3745 *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs;
3746 break;
3747 case QED_MAC:
3748 case QED_VLAN:
3749 /* Each VFC resource can accommodate both a MAC and a VLAN */
3750 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
3751 break;
3752 case QED_ILT:
3753 *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs;
3754 break;
3755 case QED_LL2_RAM_QUEUE:
3756 *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
3757 break;
3758 case QED_LL2_CTX_QUEUE:
3759 *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs;
3760 break;
3761 case QED_RDMA_CNQ_RAM:
3762 case QED_CMDQS_CQS:
3763 /* CNQ/CMDQS are the same resource */
3764 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
3765 break;
3766 case QED_RDMA_STATS_QUEUE:
3767 *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs;
3768 break;
3769 case QED_BDQ:
3770 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
3771 p_hwfn->hw_info.personality != QED_PCI_FCOE &&
3772 p_hwfn->hw_info.personality != QED_PCI_NVMETCP)
3773 *p_resc_num = 0;
3774 else
3775 *p_resc_num = 1;
3776 break;
3777 case QED_SB:
3778 /* Since we want its value to reflect whether MFW supports
3779 * the new scheme, have a default of 0.
3780 */
3781 *p_resc_num = 0;
3782 break;
3783 default:
3784 return -EINVAL;
3785 }
3786
3787 switch (res_id) {
3788 case QED_BDQ:
3789 if (!*p_resc_num)
3790 *p_resc_start = 0;
3791 else if (p_hwfn->cdev->num_ports_in_engine == 4)
3792 *p_resc_start = p_hwfn->port_id;
3793 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI ||
3794 p_hwfn->hw_info.personality == QED_PCI_NVMETCP)
3795 *p_resc_start = p_hwfn->port_id;
3796 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
3797 *p_resc_start = p_hwfn->port_id + 2;
3798 break;
3799 default:
3800 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
3801 break;
3802 }
3803
3804 return 0;
3805}
3806
3807static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
3808 enum qed_resources res_id)
3809{
3810 u32 dflt_resc_num = 0, dflt_resc_start = 0;
3811 u32 mcp_resp, *p_resc_num, *p_resc_start;
3812 int rc;
3813
3814 p_resc_num = &RESC_NUM(p_hwfn, res_id);
3815 p_resc_start = &RESC_START(p_hwfn, res_id);
3816
3817 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
3818 &dflt_resc_start);
3819 if (rc) {
3820 DP_ERR(p_hwfn,
3821 "Failed to get default amount for resource %d [%s]\n",
3822 res_id, qed_hw_get_resc_name(res_id));
3823 return rc;
3824 }
3825
3826 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
3827 &mcp_resp, p_resc_num, p_resc_start);
3828 if (rc) {
3829 DP_NOTICE(p_hwfn,
3830 "MFW response failure for an allocation request for resource %d [%s]\n",
3831 res_id, qed_hw_get_resc_name(res_id));
3832 return rc;
3833 }
3834
3835 /* Default driver values are applied in the following cases:
3836 * - The resource allocation MB command is not supported by the MFW
3837 * - There is an internal error in the MFW while processing the request
3838 * - The resource ID is unknown to the MFW
3839 */
3840 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3841 DP_INFO(p_hwfn,
3842 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
3843 res_id,
3844 qed_hw_get_resc_name(res_id),
3845 mcp_resp, dflt_resc_num, dflt_resc_start);
3846 *p_resc_num = dflt_resc_num;
3847 *p_resc_start = dflt_resc_start;
3848 goto out;
3849 }
3850
3851out:
3852 /* PQs have to divide by 8 [that's the HW granularity].
3853 * Reduce number so it would fit.
3854 */
3855 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
3856 DP_INFO(p_hwfn,
3857 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
3858 *p_resc_num,
3859 (*p_resc_num) & ~0x7,
3860 *p_resc_start, (*p_resc_start) & ~0x7);
3861 *p_resc_num &= ~0x7;
3862 *p_resc_start &= ~0x7;
3863 }
3864
3865 return 0;
3866}
3867
3868static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
3869{
3870 int rc;
3871 u8 res_id;
3872
3873 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
3874 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
3875 if (rc)
3876 return rc;
3877 }
3878
3879 return 0;
3880}
3881
3882static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn,
3883 struct qed_ptt *p_ptt)
3884{
3885 struct qed_dev *cdev = p_hwfn->cdev;
3886 u8 native_ppfid_idx;
3887 int rc;
3888
3889 /* Calculation of BB/AH is different for native_ppfid_idx */
3890 if (QED_IS_BB(cdev))
3891 native_ppfid_idx = p_hwfn->rel_pf_id;
3892 else
3893 native_ppfid_idx = p_hwfn->rel_pf_id /
3894 cdev->num_ports_in_engine;
3895
3896 rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);
3897 if (rc != 0 && rc != -EOPNOTSUPP)
3898 return rc;
3899 else if (rc == -EOPNOTSUPP)
3900 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3901
3902 if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {
3903 DP_INFO(p_hwfn,
3904 "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n",
3905 native_ppfid_idx, cdev->ppfid_bitmap);
3906 cdev->ppfid_bitmap = 0x1 << native_ppfid_idx;
3907 }
3908
3909 return 0;
3910}
3911
3912static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3913{
3914 struct qed_resc_unlock_params resc_unlock_params;
3915 struct qed_resc_lock_params resc_lock_params;
3916 bool b_ah = QED_IS_AH(p_hwfn->cdev);
3917 u8 res_id;
3918 int rc;
3919
3920 /* Setting the max values of the soft resources and the following
3921 * resources allocation queries should be atomic. Since several PFs can
3922 * run in parallel - a resource lock is needed.
3923 * If either the resource lock or resource set value commands are not
3924 * supported - skip the the max values setting, release the lock if
3925 * needed, and proceed to the queries. Other failures, including a
3926 * failure to acquire the lock, will cause this function to fail.
3927 */
3928 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
3929 QED_RESC_LOCK_RESC_ALLOC, false);
3930
3931 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
3932 if (rc && rc != -EINVAL) {
3933 return rc;
3934 } else if (rc == -EINVAL) {
3935 DP_INFO(p_hwfn,
3936 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
3937 } else if (!rc && !resc_lock_params.b_granted) {
3938 DP_NOTICE(p_hwfn,
3939 "Failed to acquire the resource lock for the resource allocation commands\n");
3940 return -EBUSY;
3941 } else {
3942 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
3943 if (rc && rc != -EINVAL) {
3944 DP_NOTICE(p_hwfn,
3945 "Failed to set the max values of the soft resources\n");
3946 goto unlock_and_exit;
3947 } else if (rc == -EINVAL) {
3948 DP_INFO(p_hwfn,
3949 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
3950 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
3951 &resc_unlock_params);
3952 if (rc)
3953 DP_INFO(p_hwfn,
3954 "Failed to release the resource lock for the resource allocation commands\n");
3955 }
3956 }
3957
3958 rc = qed_hw_set_resc_info(p_hwfn);
3959 if (rc)
3960 goto unlock_and_exit;
3961
3962 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
3963 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
3964 if (rc)
3965 DP_INFO(p_hwfn,
3966 "Failed to release the resource lock for the resource allocation commands\n");
3967 }
3968
3969 /* PPFID bitmap */
3970 if (IS_LEAD_HWFN(p_hwfn)) {
3971 rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt);
3972 if (rc)
3973 return rc;
3974 }
3975
3976 /* Sanity for ILT */
3977 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
3978 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
3979 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
3980 RESC_START(p_hwfn, QED_ILT),
3981 RESC_END(p_hwfn, QED_ILT) - 1);
3982 return -EINVAL;
3983 }
3984
3985 /* This will also learn the number of SBs from MFW */
3986 if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
3987 return -EINVAL;
3988
3989 qed_hw_set_feat(p_hwfn);
3990
3991 for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
3992 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
3993 qed_hw_get_resc_name(res_id),
3994 RESC_NUM(p_hwfn, res_id),
3995 RESC_START(p_hwfn, res_id));
3996
3997 return 0;
3998
3999unlock_and_exit:
4000 if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
4001 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
4002 return rc;
4003}
4004
4005static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4006{
4007 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fld;
4008 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
4009 struct qed_mcp_link_speed_params *ext_speed;
4010 struct qed_mcp_link_capabilities *p_caps;
4011 struct qed_mcp_link_params *link;
4012 int i;
4013
4014 /* Read global nvm_cfg address */
4015 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
4016
4017 /* Verify MCP has initialized it */
4018 if (!nvm_cfg_addr) {
4019 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
4020 return -EINVAL;
4021 }
4022
4023 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
4024 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
4025
4026 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4027 offsetof(struct nvm_cfg1, glob) +
4028 offsetof(struct nvm_cfg1_glob, core_cfg);
4029
4030 core_cfg = qed_rd(p_hwfn, p_ptt, addr);
4031
4032 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
4033 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
4034 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
4035 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
4036 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
4037 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
4038 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
4039 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
4040 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
4041 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
4042 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
4043 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
4044 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
4045 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1:
4046 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1:
4047 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2:
4048 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2:
4049 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4:
4050 break;
4051 default:
4052 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
4053 break;
4054 }
4055
4056 /* Read default link configuration */
4057 link = &p_hwfn->mcp_info->link_input;
4058 p_caps = &p_hwfn->mcp_info->link_capabilities;
4059 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4060 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
4061 link_temp = qed_rd(p_hwfn, p_ptt,
4062 port_cfg_addr +
4063 offsetof(struct nvm_cfg1_port, speed_cap_mask));
4064 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
4065 link->speed.advertised_speeds = link_temp;
4066
4067 p_caps->speed_capabilities = link->speed.advertised_speeds;
4068
4069 link_temp = qed_rd(p_hwfn, p_ptt,
4070 port_cfg_addr +
4071 offsetof(struct nvm_cfg1_port, link_settings));
4072 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
4073 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
4074 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
4075 link->speed.autoneg = true;
4076 break;
4077 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
4078 link->speed.forced_speed = 1000;
4079 break;
4080 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
4081 link->speed.forced_speed = 10000;
4082 break;
4083 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G:
4084 link->speed.forced_speed = 20000;
4085 break;
4086 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
4087 link->speed.forced_speed = 25000;
4088 break;
4089 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
4090 link->speed.forced_speed = 40000;
4091 break;
4092 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
4093 link->speed.forced_speed = 50000;
4094 break;
4095 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
4096 link->speed.forced_speed = 100000;
4097 break;
4098 default:
4099 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
4100 }
4101
4102 p_caps->default_speed_autoneg = link->speed.autoneg;
4103
4104 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_DRV_FLOW_CONTROL);
4105 link->pause.autoneg = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
4106 link->pause.forced_rx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
4107 link->pause.forced_tx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
4108 link->loopback_mode = 0;
4109
4110 if (p_hwfn->mcp_info->capabilities &
4111 FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) {
4112 switch (GET_MFW_FIELD(link_temp,
4113 NVM_CFG1_PORT_FEC_FORCE_MODE)) {
4114 case NVM_CFG1_PORT_FEC_FORCE_MODE_NONE:
4115 p_caps->fec_default |= QED_FEC_MODE_NONE;
4116 break;
4117 case NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE:
4118 p_caps->fec_default |= QED_FEC_MODE_FIRECODE;
4119 break;
4120 case NVM_CFG1_PORT_FEC_FORCE_MODE_RS:
4121 p_caps->fec_default |= QED_FEC_MODE_RS;
4122 break;
4123 case NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO:
4124 p_caps->fec_default |= QED_FEC_MODE_AUTO;
4125 break;
4126 default:
4127 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4128 "unknown FEC mode in 0x%08x\n", link_temp);
4129 }
4130 } else {
4131 p_caps->fec_default = QED_FEC_MODE_UNSUPPORTED;
4132 }
4133
4134 link->fec = p_caps->fec_default;
4135
4136 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
4137 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
4138 offsetof(struct nvm_cfg1_port, ext_phy));
4139 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
4140 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
4141 p_caps->default_eee = QED_MCP_EEE_ENABLED;
4142 link->eee.enable = true;
4143 switch (link_temp) {
4144 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
4145 p_caps->default_eee = QED_MCP_EEE_DISABLED;
4146 link->eee.enable = false;
4147 break;
4148 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
4149 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
4150 break;
4151 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
4152 p_caps->eee_lpi_timer =
4153 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
4154 break;
4155 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
4156 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
4157 break;
4158 }
4159
4160 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
4161 link->eee.tx_lpi_enable = link->eee.enable;
4162 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
4163 } else {
4164 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
4165 }
4166
4167 if (p_hwfn->mcp_info->capabilities &
4168 FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) {
4169 ext_speed = &link->ext_speed;
4170
4171 link_temp = qed_rd(p_hwfn, p_ptt,
4172 port_cfg_addr +
4173 offsetof(struct nvm_cfg1_port,
4174 extended_speed));
4175
4176 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_EXTENDED_SPEED);
4177 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN)
4178 ext_speed->autoneg = true;
4179
4180 ext_speed->forced_speed = 0;
4181 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G)
4182 ext_speed->forced_speed |= QED_EXT_SPEED_1G;
4183 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G)
4184 ext_speed->forced_speed |= QED_EXT_SPEED_10G;
4185 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G)
4186 ext_speed->forced_speed |= QED_EXT_SPEED_20G;
4187 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G)
4188 ext_speed->forced_speed |= QED_EXT_SPEED_25G;
4189 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G)
4190 ext_speed->forced_speed |= QED_EXT_SPEED_40G;
4191 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R)
4192 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R;
4193 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2)
4194 ext_speed->forced_speed |= QED_EXT_SPEED_50G_R2;
4195 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2)
4196 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R2;
4197 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4)
4198 ext_speed->forced_speed |= QED_EXT_SPEED_100G_R4;
4199 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4)
4200 ext_speed->forced_speed |= QED_EXT_SPEED_100G_P4;
4201
4202 fld = GET_MFW_FIELD(link_temp,
4203 NVM_CFG1_PORT_EXTENDED_SPEED_CAP);
4204
4205 ext_speed->advertised_speeds = 0;
4206 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_RESERVED)
4207 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_RES;
4208 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G)
4209 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_1G;
4210 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G)
4211 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_10G;
4212 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_20G)
4213 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_20G;
4214 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G)
4215 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_25G;
4216 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G)
4217 ext_speed->advertised_speeds |= QED_EXT_SPEED_MASK_40G;
4218 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R)
4219 ext_speed->advertised_speeds |=
4220 QED_EXT_SPEED_MASK_50G_R;
4221 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2)
4222 ext_speed->advertised_speeds |=
4223 QED_EXT_SPEED_MASK_50G_R2;
4224 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2)
4225 ext_speed->advertised_speeds |=
4226 QED_EXT_SPEED_MASK_100G_R2;
4227 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4)
4228 ext_speed->advertised_speeds |=
4229 QED_EXT_SPEED_MASK_100G_R4;
4230 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4)
4231 ext_speed->advertised_speeds |=
4232 QED_EXT_SPEED_MASK_100G_P4;
4233
4234 link_temp = qed_rd(p_hwfn, p_ptt,
4235 port_cfg_addr +
4236 offsetof(struct nvm_cfg1_port,
4237 extended_fec_mode));
4238 link->ext_fec_mode = link_temp;
4239
4240 p_caps->default_ext_speed_caps = ext_speed->advertised_speeds;
4241 p_caps->default_ext_speed = ext_speed->forced_speed;
4242 p_caps->default_ext_autoneg = ext_speed->autoneg;
4243 p_caps->default_ext_fec = link->ext_fec_mode;
4244
4245 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4246 "Read default extended link config: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, FEC: 0x%02x\n",
4247 ext_speed->forced_speed,
4248 ext_speed->advertised_speeds, ext_speed->autoneg,
4249 p_caps->default_ext_fec);
4250 }
4251
4252 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4253 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x, EEE: 0x%02x [0x%08x usec], FEC: 0x%02x\n",
4254 link->speed.forced_speed, link->speed.advertised_speeds,
4255 link->speed.autoneg, link->pause.autoneg,
4256 p_caps->default_eee, p_caps->eee_lpi_timer,
4257 p_caps->fec_default);
4258
4259 if (IS_LEAD_HWFN(p_hwfn)) {
4260 struct qed_dev *cdev = p_hwfn->cdev;
4261
4262 /* Read Multi-function information from shmem */
4263 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4264 offsetof(struct nvm_cfg1, glob) +
4265 offsetof(struct nvm_cfg1_glob, generic_cont0);
4266
4267 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
4268
4269 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
4270 NVM_CFG1_GLOB_MF_MODE_OFFSET;
4271
4272 switch (mf_mode) {
4273 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
4274 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
4275 break;
4276 case NVM_CFG1_GLOB_MF_MODE_UFP:
4277 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4278 BIT(QED_MF_LLH_PROTO_CLSS) |
4279 BIT(QED_MF_UFP_SPECIFIC) |
4280 BIT(QED_MF_8021Q_TAGGING) |
4281 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4282 break;
4283 case NVM_CFG1_GLOB_MF_MODE_BD:
4284 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
4285 BIT(QED_MF_LLH_PROTO_CLSS) |
4286 BIT(QED_MF_8021AD_TAGGING) |
4287 BIT(QED_MF_DONT_ADD_VLAN0_TAG);
4288 break;
4289 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
4290 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4291 BIT(QED_MF_LLH_PROTO_CLSS) |
4292 BIT(QED_MF_LL2_NON_UNICAST) |
4293 BIT(QED_MF_INTER_PF_SWITCH) |
4294 BIT(QED_MF_DISABLE_ARFS);
4295 break;
4296 case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
4297 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
4298 BIT(QED_MF_LLH_PROTO_CLSS) |
4299 BIT(QED_MF_LL2_NON_UNICAST);
4300 if (QED_IS_BB(p_hwfn->cdev))
4301 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
4302 break;
4303 }
4304
4305 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4306 cdev->mf_bits);
4307
4308 /* In CMT the PF is unknown when the GFS block processes the
4309 * packet. Therefore cannot use searcher as it has a per PF
4310 * database, and thus ARFS must be disabled.
4311 *
4312 */
4313 if (QED_IS_CMT(cdev))
4314 cdev->mf_bits |= BIT(QED_MF_DISABLE_ARFS);
4315 }
4316
4317 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
4318 p_hwfn->cdev->mf_bits);
4319
4320 /* Read device capabilities information from shmem */
4321 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4322 offsetof(struct nvm_cfg1, glob) +
4323 offsetof(struct nvm_cfg1_glob, device_capabilities);
4324
4325 device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
4326 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
4327 __set_bit(QED_DEV_CAP_ETH,
4328 &p_hwfn->hw_info.device_capabilities);
4329 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
4330 __set_bit(QED_DEV_CAP_FCOE,
4331 &p_hwfn->hw_info.device_capabilities);
4332 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
4333 __set_bit(QED_DEV_CAP_ISCSI,
4334 &p_hwfn->hw_info.device_capabilities);
4335 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
4336 __set_bit(QED_DEV_CAP_ROCE,
4337 &p_hwfn->hw_info.device_capabilities);
4338
4339 /* Read device serial number information from shmem */
4340 addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
4341 offsetof(struct nvm_cfg1, glob) +
4342 offsetof(struct nvm_cfg1_glob, serial_number);
4343
4344 for (i = 0; i < 4; i++)
4345 p_hwfn->hw_info.part_num[i] = qed_rd(p_hwfn, p_ptt, addr + i * 4);
4346
4347 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
4348}
4349
4350static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4351{
4352 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
4353 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
4354 struct qed_dev *cdev = p_hwfn->cdev;
4355
4356 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
4357
4358 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
4359 * in the other bits are selected.
4360 * Bits 1-15 are for functions 1-15, respectively, and their value is
4361 * '0' only for enabled functions (function 0 always exists and
4362 * enabled).
4363 * In case of CMT, only the "even" functions are enabled, and thus the
4364 * number of functions for both hwfns is learnt from the same bits.
4365 */
4366 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
4367
4368 if (reg_function_hide & 0x1) {
4369 if (QED_IS_BB(cdev)) {
4370 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
4371 num_funcs = 0;
4372 eng_mask = 0xaaaa;
4373 } else {
4374 num_funcs = 1;
4375 eng_mask = 0x5554;
4376 }
4377 } else {
4378 num_funcs = 1;
4379 eng_mask = 0xfffe;
4380 }
4381
4382 /* Get the number of the enabled functions on the engine */
4383 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
4384 while (tmp) {
4385 if (tmp & 0x1)
4386 num_funcs++;
4387 tmp >>= 0x1;
4388 }
4389
4390 /* Get the PF index within the enabled functions */
4391 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
4392 tmp = reg_function_hide & eng_mask & low_pfs_mask;
4393 while (tmp) {
4394 if (tmp & 0x1)
4395 enabled_func_idx--;
4396 tmp >>= 0x1;
4397 }
4398 }
4399
4400 p_hwfn->num_funcs_on_engine = num_funcs;
4401 p_hwfn->enabled_func_idx = enabled_func_idx;
4402
4403 DP_VERBOSE(p_hwfn,
4404 NETIF_MSG_PROBE,
4405 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
4406 p_hwfn->rel_pf_id,
4407 p_hwfn->abs_pf_id,
4408 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
4409}
4410
4411static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4412{
4413 u32 addr, global_offsize, global_addr, port_mode;
4414 struct qed_dev *cdev = p_hwfn->cdev;
4415
4416 /* In CMT there is always only one port */
4417 if (cdev->num_hwfns > 1) {
4418 cdev->num_ports_in_engine = 1;
4419 cdev->num_ports = 1;
4420 return;
4421 }
4422
4423 /* Determine the number of ports per engine */
4424 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
4425 switch (port_mode) {
4426 case 0x0:
4427 cdev->num_ports_in_engine = 1;
4428 break;
4429 case 0x1:
4430 cdev->num_ports_in_engine = 2;
4431 break;
4432 case 0x2:
4433 cdev->num_ports_in_engine = 4;
4434 break;
4435 default:
4436 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode);
4437 cdev->num_ports_in_engine = 1; /* Default to something */
4438 break;
4439 }
4440
4441 /* Get the total number of ports of the device */
4442 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
4443 PUBLIC_GLOBAL);
4444 global_offsize = qed_rd(p_hwfn, p_ptt, addr);
4445 global_addr = SECTION_ADDR(global_offsize, 0);
4446 addr = global_addr + offsetof(struct public_global, max_ports);
4447 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
4448}
4449
4450static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4451{
4452 struct qed_mcp_link_capabilities *p_caps;
4453 u32 eee_status;
4454
4455 p_caps = &p_hwfn->mcp_info->link_capabilities;
4456 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
4457 return;
4458
4459 p_caps->eee_speed_caps = 0;
4460 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
4461 offsetof(struct public_port, eee_status));
4462 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
4463 EEE_SUPPORTED_SPEED_OFFSET;
4464
4465 if (eee_status & EEE_1G_SUPPORTED)
4466 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
4467 if (eee_status & EEE_10G_ADV)
4468 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
4469}
4470
4471static int
4472qed_get_hw_info(struct qed_hwfn *p_hwfn,
4473 struct qed_ptt *p_ptt,
4474 enum qed_pci_personality personality)
4475{
4476 int rc;
4477
4478 /* Since all information is common, only first hwfns should do this */
4479 if (IS_LEAD_HWFN(p_hwfn)) {
4480 rc = qed_iov_hw_info(p_hwfn);
4481 if (rc)
4482 return rc;
4483 }
4484
4485 if (IS_LEAD_HWFN(p_hwfn))
4486 qed_hw_info_port_num(p_hwfn, p_ptt);
4487
4488 qed_mcp_get_capabilities(p_hwfn, p_ptt);
4489
4490 qed_hw_get_nvm_info(p_hwfn, p_ptt);
4491
4492 rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
4493 if (rc)
4494 return rc;
4495
4496 if (qed_mcp_is_init(p_hwfn))
4497 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
4498 p_hwfn->mcp_info->func_info.mac);
4499 else
4500 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
4501
4502 if (qed_mcp_is_init(p_hwfn)) {
4503 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
4504 p_hwfn->hw_info.ovlan =
4505 p_hwfn->mcp_info->func_info.ovlan;
4506
4507 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
4508
4509 qed_get_eee_caps(p_hwfn, p_ptt);
4510
4511 qed_mcp_read_ufp_config(p_hwfn, p_ptt);
4512 }
4513
4514 if (qed_mcp_is_init(p_hwfn)) {
4515 enum qed_pci_personality protocol;
4516
4517 protocol = p_hwfn->mcp_info->func_info.protocol;
4518 p_hwfn->hw_info.personality = protocol;
4519 }
4520
4521 if (QED_IS_ROCE_PERSONALITY(p_hwfn))
4522 p_hwfn->hw_info.multi_tc_roce_en = true;
4523
4524 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
4525 p_hwfn->hw_info.num_active_tc = 1;
4526
4527 qed_get_num_funcs(p_hwfn, p_ptt);
4528
4529 if (qed_mcp_is_init(p_hwfn))
4530 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
4531
4532 return qed_hw_get_resc(p_hwfn, p_ptt);
4533}
4534
4535static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4536{
4537 struct qed_dev *cdev = p_hwfn->cdev;
4538 u16 device_id_mask;
4539 u32 tmp;
4540
4541 /* Read Vendor Id / Device Id */
4542 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
4543 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
4544
4545 /* Determine type */
4546 device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
4547 switch (device_id_mask) {
4548 case QED_DEV_ID_MASK_BB:
4549 cdev->type = QED_DEV_TYPE_BB;
4550 break;
4551 case QED_DEV_ID_MASK_AH:
4552 cdev->type = QED_DEV_TYPE_AH;
4553 break;
4554 default:
4555 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
4556 return -EBUSY;
4557 }
4558
4559 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
4560 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
4561
4562 MASK_FIELD(CHIP_REV, cdev->chip_rev);
4563
4564 /* Learn number of HW-functions */
4565 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
4566
4567 if (tmp & (1 << p_hwfn->rel_pf_id)) {
4568 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
4569 cdev->num_hwfns = 2;
4570 } else {
4571 cdev->num_hwfns = 1;
4572 }
4573
4574 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
4575 MISCS_REG_CHIP_TEST_REG) >> 4;
4576 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
4577 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
4578 MASK_FIELD(CHIP_METAL, cdev->chip_metal);
4579
4580 DP_INFO(cdev->hwfns,
4581 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
4582 QED_IS_BB(cdev) ? "BB" : "AH",
4583 'A' + cdev->chip_rev,
4584 (int)cdev->chip_metal,
4585 cdev->chip_num, cdev->chip_rev,
4586 cdev->chip_bond_id, cdev->chip_metal);
4587
4588 return 0;
4589}
4590
4591static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
4592 void __iomem *p_regview,
4593 void __iomem *p_doorbells,
4594 u64 db_phys_addr,
4595 enum qed_pci_personality personality)
4596{
4597 struct qed_dev *cdev = p_hwfn->cdev;
4598 int rc = 0;
4599
4600 /* Split PCI bars evenly between hwfns */
4601 p_hwfn->regview = p_regview;
4602 p_hwfn->doorbells = p_doorbells;
4603 p_hwfn->db_phys_addr = db_phys_addr;
4604
4605 if (IS_VF(p_hwfn->cdev))
4606 return qed_vf_hw_prepare(p_hwfn);
4607
4608 /* Validate that chip access is feasible */
4609 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
4610 DP_ERR(p_hwfn,
4611 "Reading the ME register returns all Fs; Preventing further chip access\n");
4612 return -EINVAL;
4613 }
4614
4615 get_function_id(p_hwfn);
4616
4617 /* Allocate PTT pool */
4618 rc = qed_ptt_pool_alloc(p_hwfn);
4619 if (rc)
4620 goto err0;
4621
4622 /* Allocate the main PTT */
4623 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
4624
4625 /* First hwfn learns basic information, e.g., number of hwfns */
4626 if (!p_hwfn->my_id) {
4627 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
4628 if (rc)
4629 goto err1;
4630 }
4631
4632 qed_hw_hwfn_prepare(p_hwfn);
4633
4634 /* Initialize MCP structure */
4635 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
4636 if (rc) {
4637 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
4638 goto err1;
4639 }
4640
4641 /* Read the device configuration information from the HW and SHMEM */
4642 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
4643 if (rc) {
4644 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
4645 goto err2;
4646 }
4647
4648 /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
4649 * is called as it sets the ports number in an engine.
4650 */
4651 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) {
4652 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
4653 if (rc)
4654 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
4655 }
4656
4657 /* NVRAM info initialization and population */
4658 if (IS_LEAD_HWFN(p_hwfn)) {
4659 rc = qed_mcp_nvm_info_populate(p_hwfn);
4660 if (rc) {
4661 DP_NOTICE(p_hwfn,
4662 "Failed to populate nvm info shadow\n");
4663 goto err2;
4664 }
4665 }
4666
4667 /* Allocate the init RT array and initialize the init-ops engine */
4668 rc = qed_init_alloc(p_hwfn);
4669 if (rc)
4670 goto err3;
4671
4672 return rc;
4673err3:
4674 if (IS_LEAD_HWFN(p_hwfn))
4675 qed_mcp_nvm_info_free(p_hwfn);
4676err2:
4677 if (IS_LEAD_HWFN(p_hwfn))
4678 qed_iov_free_hw_info(p_hwfn->cdev);
4679 qed_mcp_free(p_hwfn);
4680err1:
4681 qed_hw_hwfn_free(p_hwfn);
4682err0:
4683 return rc;
4684}
4685
4686int qed_hw_prepare(struct qed_dev *cdev,
4687 int personality)
4688{
4689 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4690 int rc;
4691
4692 /* Store the precompiled init data ptrs */
4693 if (IS_PF(cdev))
4694 qed_init_iro_array(cdev);
4695
4696 /* Initialize the first hwfn - will learn number of hwfns */
4697 rc = qed_hw_prepare_single(p_hwfn,
4698 cdev->regview,
4699 cdev->doorbells,
4700 cdev->db_phys_addr,
4701 personality);
4702 if (rc)
4703 return rc;
4704
4705 personality = p_hwfn->hw_info.personality;
4706
4707 /* Initialize the rest of the hwfns */
4708 if (cdev->num_hwfns > 1) {
4709 void __iomem *p_regview, *p_doorbell;
4710 u64 db_phys_addr;
4711 u32 offset;
4712
4713 /* adjust bar offset for second engine */
4714 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4715 BAR_ID_0) / 2;
4716 p_regview = cdev->regview + offset;
4717
4718 offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
4719 BAR_ID_1) / 2;
4720
4721 p_doorbell = cdev->doorbells + offset;
4722
4723 db_phys_addr = cdev->db_phys_addr + offset;
4724
4725 /* prepare second hw function */
4726 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
4727 p_doorbell, db_phys_addr,
4728 personality);
4729
4730 /* in case of error, need to free the previously
4731 * initiliazed hwfn 0.
4732 */
4733 if (rc) {
4734 if (IS_PF(cdev)) {
4735 qed_init_free(p_hwfn);
4736 qed_mcp_nvm_info_free(p_hwfn);
4737 qed_mcp_free(p_hwfn);
4738 qed_hw_hwfn_free(p_hwfn);
4739 }
4740 }
4741 }
4742
4743 return rc;
4744}
4745
4746void qed_hw_remove(struct qed_dev *cdev)
4747{
4748 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
4749 int i;
4750
4751 if (IS_PF(cdev))
4752 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
4753 QED_OV_DRIVER_STATE_NOT_LOADED);
4754
4755 for_each_hwfn(cdev, i) {
4756 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4757
4758 if (IS_VF(cdev)) {
4759 qed_vf_pf_release(p_hwfn);
4760 continue;
4761 }
4762
4763 qed_init_free(p_hwfn);
4764 qed_hw_hwfn_free(p_hwfn);
4765 qed_mcp_free(p_hwfn);
4766 }
4767
4768 qed_iov_free_hw_info(cdev);
4769
4770 qed_mcp_nvm_info_free(p_hwfn);
4771}
4772
4773int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
4774{
4775 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
4776 u16 min, max;
4777
4778 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
4779 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
4780 DP_NOTICE(p_hwfn,
4781 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
4782 src_id, min, max);
4783
4784 return -EINVAL;
4785 }
4786
4787 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
4788
4789 return 0;
4790}
4791
4792int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4793{
4794 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
4795 u8 min, max;
4796
4797 min = (u8)RESC_START(p_hwfn, QED_VPORT);
4798 max = min + RESC_NUM(p_hwfn, QED_VPORT);
4799 DP_NOTICE(p_hwfn,
4800 "vport id [%d] is not valid, available indices [%d - %d]\n",
4801 src_id, min, max);
4802
4803 return -EINVAL;
4804 }
4805
4806 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
4807
4808 return 0;
4809}
4810
4811int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
4812{
4813 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
4814 u8 min, max;
4815
4816 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
4817 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
4818 DP_NOTICE(p_hwfn,
4819 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
4820 src_id, min, max);
4821
4822 return -EINVAL;
4823 }
4824
4825 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
4826
4827 return 0;
4828}
4829
4830static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
4831 u32 hw_addr, void *p_eth_qzone,
4832 size_t eth_qzone_size, u8 timeset)
4833{
4834 struct coalescing_timeset *p_coal_timeset;
4835
4836 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
4837 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
4838 return -EINVAL;
4839 }
4840
4841 p_coal_timeset = p_eth_qzone;
4842 memset(p_eth_qzone, 0, eth_qzone_size);
4843 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
4844 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
4845 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
4846
4847 return 0;
4848}
4849
4850int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
4851{
4852 struct qed_queue_cid *p_cid = p_handle;
4853 struct qed_hwfn *p_hwfn;
4854 struct qed_ptt *p_ptt;
4855 int rc = 0;
4856
4857 p_hwfn = p_cid->p_owner;
4858
4859 if (IS_VF(p_hwfn->cdev))
4860 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
4861
4862 p_ptt = qed_ptt_acquire(p_hwfn);
4863 if (!p_ptt)
4864 return -EAGAIN;
4865
4866 if (rx_coal) {
4867 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
4868 if (rc)
4869 goto out;
4870 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
4871 }
4872
4873 if (tx_coal) {
4874 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
4875 if (rc)
4876 goto out;
4877 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
4878 }
4879out:
4880 qed_ptt_release(p_hwfn, p_ptt);
4881 return rc;
4882}
4883
4884int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
4885 struct qed_ptt *p_ptt,
4886 u16 coalesce, struct qed_queue_cid *p_cid)
4887{
4888 struct ustorm_eth_queue_zone eth_qzone;
4889 u8 timeset, timer_res;
4890 u32 address;
4891 int rc;
4892
4893 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4894 if (coalesce <= 0x7F) {
4895 timer_res = 0;
4896 } else if (coalesce <= 0xFF) {
4897 timer_res = 1;
4898 } else if (coalesce <= 0x1FF) {
4899 timer_res = 2;
4900 } else {
4901 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4902 return -EINVAL;
4903 }
4904 timeset = (u8)(coalesce >> timer_res);
4905
4906 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4907 p_cid->sb_igu_id, false);
4908 if (rc)
4909 goto out;
4910
4911 address = BAR0_MAP_REG_USDM_RAM +
4912 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4913
4914 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4915 sizeof(struct ustorm_eth_queue_zone), timeset);
4916 if (rc)
4917 goto out;
4918
4919out:
4920 return rc;
4921}
4922
4923int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
4924 struct qed_ptt *p_ptt,
4925 u16 coalesce, struct qed_queue_cid *p_cid)
4926{
4927 struct xstorm_eth_queue_zone eth_qzone;
4928 u8 timeset, timer_res;
4929 u32 address;
4930 int rc;
4931
4932 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
4933 if (coalesce <= 0x7F) {
4934 timer_res = 0;
4935 } else if (coalesce <= 0xFF) {
4936 timer_res = 1;
4937 } else if (coalesce <= 0x1FF) {
4938 timer_res = 2;
4939 } else {
4940 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
4941 return -EINVAL;
4942 }
4943 timeset = (u8)(coalesce >> timer_res);
4944
4945 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
4946 p_cid->sb_igu_id, true);
4947 if (rc)
4948 goto out;
4949
4950 address = BAR0_MAP_REG_XSDM_RAM +
4951 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
4952
4953 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone,
4954 sizeof(struct xstorm_eth_queue_zone), timeset);
4955out:
4956 return rc;
4957}
4958
4959/* Calculate final WFQ values for all vports and configure them.
4960 * After this configuration each vport will have
4961 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
4962 */
4963static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4964 struct qed_ptt *p_ptt,
4965 u32 min_pf_rate)
4966{
4967 struct init_qm_vport_params *vport_params;
4968 int i;
4969
4970 vport_params = p_hwfn->qm_info.qm_vport_params;
4971
4972 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4973 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
4974
4975 vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) /
4976 min_pf_rate;
4977 qed_init_vport_wfq(p_hwfn, p_ptt,
4978 vport_params[i].first_tx_pq_id,
4979 vport_params[i].wfq);
4980 }
4981}
4982
4983static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
4984 u32 min_pf_rate)
4985
4986{
4987 int i;
4988
4989 for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
4990 p_hwfn->qm_info.qm_vport_params[i].wfq = 1;
4991}
4992
4993static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
4994 struct qed_ptt *p_ptt,
4995 u32 min_pf_rate)
4996{
4997 struct init_qm_vport_params *vport_params;
4998 int i;
4999
5000 vport_params = p_hwfn->qm_info.qm_vport_params;
5001
5002 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5003 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
5004 qed_init_vport_wfq(p_hwfn, p_ptt,
5005 vport_params[i].first_tx_pq_id,
5006 vport_params[i].wfq);
5007 }
5008}
5009
5010/* This function performs several validations for WFQ
5011 * configuration and required min rate for a given vport
5012 * 1. req_rate must be greater than one percent of min_pf_rate.
5013 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
5014 * rates to get less than one percent of min_pf_rate.
5015 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
5016 */
5017static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
5018 u16 vport_id, u32 req_rate, u32 min_pf_rate)
5019{
5020 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
5021 int non_requested_count = 0, req_count = 0, i, num_vports;
5022
5023 num_vports = p_hwfn->qm_info.num_vports;
5024
5025 /* Accounting for the vports which are configured for WFQ explicitly */
5026 for (i = 0; i < num_vports; i++) {
5027 u32 tmp_speed;
5028
5029 if ((i != vport_id) &&
5030 p_hwfn->qm_info.wfq_data[i].configured) {
5031 req_count++;
5032 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
5033 total_req_min_rate += tmp_speed;
5034 }
5035 }
5036
5037 /* Include current vport data as well */
5038 req_count++;
5039 total_req_min_rate += req_rate;
5040 non_requested_count = num_vports - req_count;
5041
5042 if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
5043 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5044 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5045 vport_id, req_rate, min_pf_rate);
5046 return -EINVAL;
5047 }
5048
5049 if (num_vports > QED_WFQ_UNIT) {
5050 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5051 "Number of vports is greater than %d\n",
5052 QED_WFQ_UNIT);
5053 return -EINVAL;
5054 }
5055
5056 if (total_req_min_rate > min_pf_rate) {
5057 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5058 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
5059 total_req_min_rate, min_pf_rate);
5060 return -EINVAL;
5061 }
5062
5063 total_left_rate = min_pf_rate - total_req_min_rate;
5064
5065 left_rate_per_vp = total_left_rate / non_requested_count;
5066 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) {
5067 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5068 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
5069 left_rate_per_vp, min_pf_rate);
5070 return -EINVAL;
5071 }
5072
5073 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
5074 p_hwfn->qm_info.wfq_data[vport_id].configured = true;
5075
5076 for (i = 0; i < num_vports; i++) {
5077 if (p_hwfn->qm_info.wfq_data[i].configured)
5078 continue;
5079
5080 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
5081 }
5082
5083 return 0;
5084}
5085
5086static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
5087 struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
5088{
5089 struct qed_mcp_link_state *p_link;
5090 int rc = 0;
5091
5092 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
5093
5094 if (!p_link->min_pf_rate) {
5095 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
5096 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
5097 return rc;
5098 }
5099
5100 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
5101
5102 if (!rc)
5103 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
5104 p_link->min_pf_rate);
5105 else
5106 DP_NOTICE(p_hwfn,
5107 "Validation failed while configuring min rate\n");
5108
5109 return rc;
5110}
5111
5112static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
5113 struct qed_ptt *p_ptt,
5114 u32 min_pf_rate)
5115{
5116 bool use_wfq = false;
5117 int rc = 0;
5118 u16 i;
5119
5120 /* Validate all pre configured vports for wfq */
5121 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
5122 u32 rate;
5123
5124 if (!p_hwfn->qm_info.wfq_data[i].configured)
5125 continue;
5126
5127 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
5128 use_wfq = true;
5129
5130 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
5131 if (rc) {
5132 DP_NOTICE(p_hwfn,
5133 "WFQ validation failed while configuring min rate\n");
5134 break;
5135 }
5136 }
5137
5138 if (!rc && use_wfq)
5139 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5140 else
5141 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
5142
5143 return rc;
5144}
5145
5146/* Main API for qed clients to configure vport min rate.
5147 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
5148 * rate - Speed in Mbps needs to be assigned to a given vport.
5149 */
5150int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
5151{
5152 int i, rc = -EINVAL;
5153
5154 /* Currently not supported; Might change in future */
5155 if (cdev->num_hwfns > 1) {
5156 DP_NOTICE(cdev,
5157 "WFQ configuration is not supported for this device\n");
5158 return rc;
5159 }
5160
5161 for_each_hwfn(cdev, i) {
5162 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5163 struct qed_ptt *p_ptt;
5164
5165 p_ptt = qed_ptt_acquire(p_hwfn);
5166 if (!p_ptt)
5167 return -EBUSY;
5168
5169 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
5170
5171 if (rc) {
5172 qed_ptt_release(p_hwfn, p_ptt);
5173 return rc;
5174 }
5175
5176 qed_ptt_release(p_hwfn, p_ptt);
5177 }
5178
5179 return rc;
5180}
5181
5182/* API to configure WFQ from mcp link change */
5183void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
5184 struct qed_ptt *p_ptt, u32 min_pf_rate)
5185{
5186 int i;
5187
5188 if (cdev->num_hwfns > 1) {
5189 DP_VERBOSE(cdev,
5190 NETIF_MSG_LINK,
5191 "WFQ configuration is not supported for this device\n");
5192 return;
5193 }
5194
5195 for_each_hwfn(cdev, i) {
5196 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5197
5198 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
5199 min_pf_rate);
5200 }
5201}
5202
5203int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
5204 struct qed_ptt *p_ptt,
5205 struct qed_mcp_link_state *p_link,
5206 u8 max_bw)
5207{
5208 int rc = 0;
5209
5210 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
5211
5212 if (!p_link->line_speed && (max_bw != 100))
5213 return rc;
5214
5215 p_link->speed = (p_link->line_speed * max_bw) / 100;
5216 p_hwfn->qm_info.pf_rl = p_link->speed;
5217
5218 /* Since the limiter also affects Tx-switched traffic, we don't want it
5219 * to limit such traffic in case there's no actual limit.
5220 * In that case, set limit to imaginary high boundary.
5221 */
5222 if (max_bw == 100)
5223 p_hwfn->qm_info.pf_rl = 100000;
5224
5225 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
5226 p_hwfn->qm_info.pf_rl);
5227
5228 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5229 "Configured MAX bandwidth to be %08x Mb/sec\n",
5230 p_link->speed);
5231
5232 return rc;
5233}
5234
5235/* Main API to configure PF max bandwidth where bw range is [1 - 100] */
5236int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
5237{
5238 int i, rc = -EINVAL;
5239
5240 if (max_bw < 1 || max_bw > 100) {
5241 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
5242 return rc;
5243 }
5244
5245 for_each_hwfn(cdev, i) {
5246 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5247 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5248 struct qed_mcp_link_state *p_link;
5249 struct qed_ptt *p_ptt;
5250
5251 p_link = &p_lead->mcp_info->link_output;
5252
5253 p_ptt = qed_ptt_acquire(p_hwfn);
5254 if (!p_ptt)
5255 return -EBUSY;
5256
5257 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
5258 p_link, max_bw);
5259
5260 qed_ptt_release(p_hwfn, p_ptt);
5261
5262 if (rc)
5263 break;
5264 }
5265
5266 return rc;
5267}
5268
5269int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
5270 struct qed_ptt *p_ptt,
5271 struct qed_mcp_link_state *p_link,
5272 u8 min_bw)
5273{
5274 int rc = 0;
5275
5276 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
5277 p_hwfn->qm_info.pf_wfq = min_bw;
5278
5279 if (!p_link->line_speed)
5280 return rc;
5281
5282 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
5283
5284 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
5285
5286 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
5287 "Configured MIN bandwidth to be %d Mb/sec\n",
5288 p_link->min_pf_rate);
5289
5290 return rc;
5291}
5292
5293/* Main API to configure PF min bandwidth where bw range is [1-100] */
5294int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
5295{
5296 int i, rc = -EINVAL;
5297
5298 if (min_bw < 1 || min_bw > 100) {
5299 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
5300 return rc;
5301 }
5302
5303 for_each_hwfn(cdev, i) {
5304 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
5305 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
5306 struct qed_mcp_link_state *p_link;
5307 struct qed_ptt *p_ptt;
5308
5309 p_link = &p_lead->mcp_info->link_output;
5310
5311 p_ptt = qed_ptt_acquire(p_hwfn);
5312 if (!p_ptt)
5313 return -EBUSY;
5314
5315 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
5316 p_link, min_bw);
5317 if (rc) {
5318 qed_ptt_release(p_hwfn, p_ptt);
5319 return rc;
5320 }
5321
5322 if (p_link->min_pf_rate) {
5323 u32 min_rate = p_link->min_pf_rate;
5324
5325 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
5326 p_ptt,
5327 min_rate);
5328 }
5329
5330 qed_ptt_release(p_hwfn, p_ptt);
5331 }
5332
5333 return rc;
5334}
5335
5336void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
5337{
5338 struct qed_mcp_link_state *p_link;
5339
5340 p_link = &p_hwfn->mcp_info->link_output;
5341
5342 if (p_link->min_pf_rate)
5343 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
5344 p_link->min_pf_rate);
5345
5346 memset(p_hwfn->qm_info.wfq_data, 0,
5347 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
5348}
5349
5350int qed_device_num_ports(struct qed_dev *cdev)
5351{
5352 return cdev->num_ports;
5353}
5354
5355void qed_set_fw_mac_addr(__le16 *fw_msb,
5356 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
5357{
5358 ((u8 *)fw_msb)[0] = mac[1];
5359 ((u8 *)fw_msb)[1] = mac[0];
5360 ((u8 *)fw_mid)[0] = mac[3];
5361 ((u8 *)fw_mid)[1] = mac[2];
5362 ((u8 *)fw_lsb)[0] = mac[5];
5363 ((u8 *)fw_lsb)[1] = mac[4];
5364}
5365
5366static int qed_llh_shadow_remove_all_filters(struct qed_dev *cdev, u8 ppfid)
5367{
5368 struct qed_llh_info *p_llh_info = cdev->p_llh_info;
5369 struct qed_llh_filter_info *p_filters;
5370 int rc;
5371
5372 rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "remove_all");
5373 if (rc)
5374 return rc;
5375
5376 p_filters = p_llh_info->pp_filters[ppfid];
5377 memset(p_filters, 0, NIG_REG_LLH_FUNC_FILTER_EN_SIZE *
5378 sizeof(*p_filters));
5379
5380 return 0;
5381}
5382
5383static void qed_llh_clear_ppfid_filters(struct qed_dev *cdev, u8 ppfid)
5384{
5385 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
5386 struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
5387 u8 filter_idx, abs_ppfid;
5388 int rc = 0;
5389
5390 if (!p_ptt)
5391 return;
5392
5393 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits) &&
5394 !test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
5395 goto out;
5396
5397 rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid);
5398 if (rc)
5399 goto out;
5400
5401 rc = qed_llh_shadow_remove_all_filters(cdev, ppfid);
5402 if (rc)
5403 goto out;
5404
5405 for (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;
5406 filter_idx++) {
5407 rc = qed_llh_remove_filter(p_hwfn, p_ptt,
5408 abs_ppfid, filter_idx);
5409 if (rc)
5410 goto out;
5411 }
5412out:
5413 qed_ptt_release(p_hwfn, p_ptt);
5414}
5415
5416int qed_llh_add_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port)
5417{
5418 return qed_llh_add_protocol_filter(cdev, 0,
5419 QED_LLH_FILTER_TCP_SRC_PORT,
5420 src_port, QED_LLH_DONT_CARE);
5421}
5422
5423void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port)
5424{
5425 qed_llh_remove_protocol_filter(cdev, 0,
5426 QED_LLH_FILTER_TCP_SRC_PORT,
5427 src_port, QED_LLH_DONT_CARE);
5428}
5429
5430int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port)
5431{
5432 return qed_llh_add_protocol_filter(cdev, 0,
5433 QED_LLH_FILTER_TCP_DEST_PORT,
5434 QED_LLH_DONT_CARE, dest_port);
5435}
5436
5437void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port)
5438{
5439 qed_llh_remove_protocol_filter(cdev, 0,
5440 QED_LLH_FILTER_TCP_DEST_PORT,
5441 QED_LLH_DONT_CARE, dest_port);
5442}
5443
5444void qed_llh_clear_all_filters(struct qed_dev *cdev)
5445{
5446 u8 ppfid;
5447
5448 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits) &&
5449 !test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits))
5450 return;
5451
5452 for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++)
5453 qed_llh_clear_ppfid_filters(cdev, ppfid);
5454}