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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4/* Linux PRO/1000 Ethernet Driver main header file */
5
6#ifndef _E1000_H_
7#define _E1000_H_
8
9#include <linux/bitops.h>
10#include <linux/types.h>
11#include <linux/timer.h>
12#include <linux/workqueue.h>
13#include <linux/io.h>
14#include <linux/netdevice.h>
15#include <linux/pci.h>
16#include <linux/crc32.h>
17#include <linux/if_vlan.h>
18#include <linux/timecounter.h>
19#include <linux/net_tstamp.h>
20#include <linux/ptp_clock_kernel.h>
21#include <linux/ptp_classify.h>
22#include <linux/mii.h>
23#include <linux/mdio.h>
24#include <linux/pm_qos.h>
25#include "hw.h"
26
27struct e1000_info;
28
29#define e_dbg(format, arg...) \
30 netdev_dbg(hw->adapter->netdev, format, ## arg)
31#define e_err(format, arg...) \
32 netdev_err(adapter->netdev, format, ## arg)
33#define e_info(format, arg...) \
34 netdev_info(adapter->netdev, format, ## arg)
35#define e_warn(format, arg...) \
36 netdev_warn(adapter->netdev, format, ## arg)
37#define e_notice(format, arg...) \
38 netdev_notice(adapter->netdev, format, ## arg)
39
40/* Interrupt modes, as used by the IntMode parameter */
41#define E1000E_INT_MODE_LEGACY 0
42#define E1000E_INT_MODE_MSI 1
43#define E1000E_INT_MODE_MSIX 2
44
45/* Tx/Rx descriptor defines */
46#define E1000_DEFAULT_TXD 256
47#define E1000_MAX_TXD 4096
48#define E1000_MIN_TXD 64
49
50#define E1000_DEFAULT_RXD 256
51#define E1000_MAX_RXD 4096
52#define E1000_MIN_RXD 64
53
54#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
55#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
56
57#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
58
59/* How many Tx Descriptors do we need to call netif_wake_queue ? */
60/* How many Rx Buffers do we bundle into one write to the hardware ? */
61#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
62
63#define AUTO_ALL_MODES 0
64#define E1000_EEPROM_APME 0x0400
65
66#define E1000_MNG_VLAN_NONE (-1)
67
68#define DEFAULT_JUMBO 9234
69
70/* Time to wait before putting the device into D3 if there's no link (in ms). */
71#define LINK_TIMEOUT 100
72
73/* Count for polling __E1000_RESET condition every 10-20msec.
74 * Experimentation has shown the reset can take approximately 210msec.
75 */
76#define E1000_CHECK_RESET_COUNT 25
77
78#define PCICFG_DESC_RING_STATUS 0xe4
79#define FLUSH_DESC_REQUIRED 0x100
80
81/* in the case of WTHRESH, it appears at least the 82571/2 hardware
82 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
83 * WTHRESH=4, so a setting of 5 gives the most efficient bus
84 * utilization but to avoid possible Tx stalls, set it to 1
85 */
86#define E1000_TXDCTL_DMA_BURST_ENABLE \
87 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
88 E1000_TXDCTL_COUNT_DESC | \
89 (1u << 16) | /* wthresh must be +1 more than desired */\
90 (1u << 8) | /* hthresh */ \
91 0x1f) /* pthresh */
92
93#define E1000_RXDCTL_DMA_BURST_ENABLE \
94 (0x01000000 | /* set descriptor granularity */ \
95 (4u << 16) | /* set writeback threshold */ \
96 (4u << 8) | /* set prefetch threshold */ \
97 0x20) /* set hthresh */
98
99#define E1000_TIDV_FPD BIT(31)
100#define E1000_RDTR_FPD BIT(31)
101
102enum e1000_boards {
103 board_82571,
104 board_82572,
105 board_82573,
106 board_82574,
107 board_82583,
108 board_80003es2lan,
109 board_ich8lan,
110 board_ich9lan,
111 board_ich10lan,
112 board_pchlan,
113 board_pch2lan,
114 board_pch_lpt,
115 board_pch_spt,
116 board_pch_cnp,
117 board_pch_tgp
118};
119
120struct e1000_ps_page {
121 struct page *page;
122 u64 dma; /* must be u64 - written to hw */
123};
124
125/* wrappers around a pointer to a socket buffer,
126 * so a DMA handle can be stored along with the buffer
127 */
128struct e1000_buffer {
129 dma_addr_t dma;
130 struct sk_buff *skb;
131 union {
132 /* Tx */
133 struct {
134 unsigned long time_stamp;
135 u16 length;
136 u16 next_to_watch;
137 unsigned int segs;
138 unsigned int bytecount;
139 u16 mapped_as_page;
140 };
141 /* Rx */
142 struct {
143 /* arrays of page information for packet split */
144 struct e1000_ps_page *ps_pages;
145 struct page *page;
146 };
147 };
148};
149
150struct e1000_ring {
151 struct e1000_adapter *adapter; /* back pointer to adapter */
152 void *desc; /* pointer to ring memory */
153 dma_addr_t dma; /* phys address of ring */
154 unsigned int size; /* length of ring in bytes */
155 unsigned int count; /* number of desc. in ring */
156
157 u16 next_to_use;
158 u16 next_to_clean;
159
160 void __iomem *head;
161 void __iomem *tail;
162
163 /* array of buffer information structs */
164 struct e1000_buffer *buffer_info;
165
166 char name[IFNAMSIZ + 5];
167 u32 ims_val;
168 u32 itr_val;
169 void __iomem *itr_register;
170 int set_itr;
171
172 struct sk_buff *rx_skb_top;
173};
174
175/* PHY register snapshot values */
176struct e1000_phy_regs {
177 u16 bmcr; /* basic mode control register */
178 u16 bmsr; /* basic mode status register */
179 u16 advertise; /* auto-negotiation advertisement */
180 u16 lpa; /* link partner ability register */
181 u16 expansion; /* auto-negotiation expansion reg */
182 u16 ctrl1000; /* 1000BASE-T control register */
183 u16 stat1000; /* 1000BASE-T status register */
184 u16 estatus; /* extended status register */
185};
186
187/* board specific private data structure */
188struct e1000_adapter {
189 struct timer_list watchdog_timer;
190 struct timer_list phy_info_timer;
191 struct timer_list blink_timer;
192
193 struct work_struct reset_task;
194 struct work_struct watchdog_task;
195
196 const struct e1000_info *ei;
197
198 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
199 u32 bd_number;
200 u32 rx_buffer_len;
201 u16 mng_vlan_id;
202 u16 link_speed;
203 u16 link_duplex;
204 u16 eeprom_vers;
205
206 /* track device up/down/testing state */
207 unsigned long state;
208
209 /* Interrupt Throttle Rate */
210 u32 itr;
211 u32 itr_setting;
212 u16 tx_itr;
213 u16 rx_itr;
214
215 /* Tx - one ring per active queue */
216 struct e1000_ring *tx_ring ____cacheline_aligned_in_smp;
217 u32 tx_fifo_limit;
218
219 struct napi_struct napi;
220
221 unsigned int uncorr_errors; /* uncorrectable ECC errors */
222 unsigned int corr_errors; /* correctable ECC errors */
223 unsigned int restart_queue;
224 u32 txd_cmd;
225
226 bool detect_tx_hung;
227 bool tx_hang_recheck;
228 u8 tx_timeout_factor;
229
230 u32 tx_int_delay;
231 u32 tx_abs_int_delay;
232
233 unsigned int total_tx_bytes;
234 unsigned int total_tx_packets;
235 unsigned int total_rx_bytes;
236 unsigned int total_rx_packets;
237
238 /* Tx stats */
239 u64 tpt_old;
240 u64 colc_old;
241 u32 gotc;
242 u64 gotc_old;
243 u32 tx_timeout_count;
244 u32 tx_fifo_head;
245 u32 tx_head_addr;
246 u32 tx_fifo_size;
247 u32 tx_dma_failed;
248 u32 tx_hwtstamp_timeouts;
249 u32 tx_hwtstamp_skipped;
250
251 /* Rx */
252 bool (*clean_rx)(struct e1000_ring *ring, int *work_done,
253 int work_to_do) ____cacheline_aligned_in_smp;
254 void (*alloc_rx_buf)(struct e1000_ring *ring, int cleaned_count,
255 gfp_t gfp);
256 struct e1000_ring *rx_ring;
257
258 u32 rx_int_delay;
259 u32 rx_abs_int_delay;
260
261 /* Rx stats */
262 u64 hw_csum_err;
263 u64 hw_csum_good;
264 u64 rx_hdr_split;
265 u32 gorc;
266 u64 gorc_old;
267 u32 alloc_rx_buff_failed;
268 u32 rx_dma_failed;
269 u32 rx_hwtstamp_cleared;
270
271 unsigned int rx_ps_pages;
272 u16 rx_ps_bsize0;
273 u32 max_frame_size;
274 u32 min_frame_size;
275
276 /* OS defined structs */
277 struct net_device *netdev;
278 struct pci_dev *pdev;
279
280 /* structs defined in e1000_hw.h */
281 struct e1000_hw hw;
282
283 spinlock_t stats64_lock; /* protects statistics counters */
284 struct e1000_hw_stats stats;
285 struct e1000_phy_info phy_info;
286 struct e1000_phy_stats phy_stats;
287
288 /* Snapshot of PHY registers */
289 struct e1000_phy_regs phy_regs;
290
291 struct e1000_ring test_tx_ring;
292 struct e1000_ring test_rx_ring;
293 u32 test_icr;
294
295 u32 msg_enable;
296 unsigned int num_vectors;
297 struct msix_entry *msix_entries;
298 int int_mode;
299 u32 eiac_mask;
300
301 u32 eeprom_wol;
302 u32 wol;
303 u32 pba;
304 u32 max_hw_frame_size;
305
306 bool fc_autoneg;
307
308 unsigned int flags;
309 unsigned int flags2;
310 struct work_struct downshift_task;
311 struct work_struct update_phy_task;
312 struct work_struct print_hang_task;
313
314 int phy_hang_count;
315
316 u16 tx_ring_count;
317 u16 rx_ring_count;
318
319 struct hwtstamp_config hwtstamp_config;
320 struct delayed_work systim_overflow_work;
321 struct sk_buff *tx_hwtstamp_skb;
322 unsigned long tx_hwtstamp_start;
323 struct work_struct tx_hwtstamp_work;
324 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
325 struct cyclecounter cc;
326 struct timecounter tc;
327 struct ptp_clock *ptp_clock;
328 struct ptp_clock_info ptp_clock_info;
329 struct pm_qos_request pm_qos_req;
330 s32 ptp_delta;
331
332 u16 eee_advert;
333};
334
335struct e1000_info {
336 enum e1000_mac_type mac;
337 unsigned int flags;
338 unsigned int flags2;
339 u32 pba;
340 u32 max_hw_frame_size;
341 s32 (*get_variants)(struct e1000_adapter *);
342 const struct e1000_mac_operations *mac_ops;
343 const struct e1000_phy_operations *phy_ops;
344 const struct e1000_nvm_operations *nvm_ops;
345};
346
347s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca);
348
349/* The system time is maintained by a 64-bit counter comprised of the 32-bit
350 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
351 * its resolution) is based on the contents of the TIMINCA register - it
352 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
353 * For the best accuracy, the incperiod should be as small as possible. The
354 * incvalue is scaled by a factor as large as possible (while still fitting
355 * in bits 23:0) so that relatively small clock corrections can be made.
356 *
357 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
358 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
359 * bits to count nanoseconds leaving the rest for fractional nonseconds.
360 */
361#define INCVALUE_96MHZ 125
362#define INCVALUE_SHIFT_96MHZ 17
363#define INCPERIOD_SHIFT_96MHZ 2
364#define INCPERIOD_96MHZ (12 >> INCPERIOD_SHIFT_96MHZ)
365
366#define INCVALUE_25MHZ 40
367#define INCVALUE_SHIFT_25MHZ 18
368#define INCPERIOD_25MHZ 1
369
370#define INCVALUE_24MHZ 125
371#define INCVALUE_SHIFT_24MHZ 14
372#define INCPERIOD_24MHZ 3
373
374#define INCVALUE_38400KHZ 26
375#define INCVALUE_SHIFT_38400KHZ 19
376#define INCPERIOD_38400KHZ 1
377
378/* Another drawback of scaling the incvalue by a large factor is the
379 * 64-bit SYSTIM register overflows more quickly. This is dealt with
380 * by simply reading the clock before it overflows.
381 *
382 * Clock ns bits Overflows after
383 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
384 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
385 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
386 */
387#define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
388#define E1000_MAX_82574_SYSTIM_REREADS 50
389#define E1000_82574_SYSTIM_EPSILON (1ULL << 35ULL)
390
391/* hardware capability, feature, and workaround flags */
392#define FLAG_HAS_AMT BIT(0)
393#define FLAG_HAS_FLASH BIT(1)
394#define FLAG_HAS_HW_VLAN_FILTER BIT(2)
395#define FLAG_HAS_WOL BIT(3)
396/* reserved BIT(4) */
397#define FLAG_HAS_CTRLEXT_ON_LOAD BIT(5)
398#define FLAG_HAS_SWSM_ON_LOAD BIT(6)
399#define FLAG_HAS_JUMBO_FRAMES BIT(7)
400#define FLAG_READ_ONLY_NVM BIT(8)
401#define FLAG_IS_ICH BIT(9)
402#define FLAG_HAS_MSIX BIT(10)
403#define FLAG_HAS_SMART_POWER_DOWN BIT(11)
404#define FLAG_IS_QUAD_PORT_A BIT(12)
405#define FLAG_IS_QUAD_PORT BIT(13)
406#define FLAG_HAS_HW_TIMESTAMP BIT(14)
407#define FLAG_APME_IN_WUC BIT(15)
408#define FLAG_APME_IN_CTRL3 BIT(16)
409#define FLAG_APME_CHECK_PORT_B BIT(17)
410#define FLAG_DISABLE_FC_PAUSE_TIME BIT(18)
411#define FLAG_NO_WAKE_UCAST BIT(19)
412#define FLAG_MNG_PT_ENABLED BIT(20)
413#define FLAG_RESET_OVERWRITES_LAA BIT(21)
414#define FLAG_TARC_SPEED_MODE_BIT BIT(22)
415#define FLAG_TARC_SET_BIT_ZERO BIT(23)
416#define FLAG_RX_NEEDS_RESTART BIT(24)
417#define FLAG_LSC_GIG_SPEED_DROP BIT(25)
418#define FLAG_SMART_POWER_DOWN BIT(26)
419#define FLAG_MSI_ENABLED BIT(27)
420/* reserved BIT(28) */
421#define FLAG_TSO_FORCE BIT(29)
422#define FLAG_RESTART_NOW BIT(30)
423#define FLAG_MSI_TEST_FAILED BIT(31)
424
425#define FLAG2_CRC_STRIPPING BIT(0)
426#define FLAG2_HAS_PHY_WAKEUP BIT(1)
427#define FLAG2_IS_DISCARDING BIT(2)
428#define FLAG2_DISABLE_ASPM_L1 BIT(3)
429#define FLAG2_HAS_PHY_STATS BIT(4)
430#define FLAG2_HAS_EEE BIT(5)
431#define FLAG2_DMA_BURST BIT(6)
432#define FLAG2_DISABLE_ASPM_L0S BIT(7)
433#define FLAG2_DISABLE_AIM BIT(8)
434#define FLAG2_CHECK_PHY_HANG BIT(9)
435#define FLAG2_NO_DISABLE_RX BIT(10)
436#define FLAG2_PCIM2PCI_ARBITER_WA BIT(11)
437#define FLAG2_DFLT_CRC_STRIPPING BIT(12)
438#define FLAG2_CHECK_RX_HWTSTAMP BIT(13)
439#define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14)
440#define FLAG2_ENABLE_S0IX_FLOWS BIT(15)
441
442#define E1000_RX_DESC_PS(R, i) \
443 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
444#define E1000_RX_DESC_EXT(R, i) \
445 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
446#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
447#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
448#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
449
450enum e1000_state_t {
451 __E1000_TESTING,
452 __E1000_RESETTING,
453 __E1000_ACCESS_SHARED_RESOURCE,
454 __E1000_DOWN
455};
456
457enum latency_range {
458 lowest_latency = 0,
459 low_latency = 1,
460 bulk_latency = 2,
461 latency_invalid = 255
462};
463
464extern char e1000e_driver_name[];
465
466void e1000e_check_options(struct e1000_adapter *adapter);
467void e1000e_set_ethtool_ops(struct net_device *netdev);
468
469int e1000e_open(struct net_device *netdev);
470int e1000e_close(struct net_device *netdev);
471void e1000e_up(struct e1000_adapter *adapter);
472void e1000e_down(struct e1000_adapter *adapter, bool reset);
473void e1000e_reinit_locked(struct e1000_adapter *adapter);
474void e1000e_reset(struct e1000_adapter *adapter);
475void e1000e_power_up_phy(struct e1000_adapter *adapter);
476int e1000e_setup_rx_resources(struct e1000_ring *ring);
477int e1000e_setup_tx_resources(struct e1000_ring *ring);
478void e1000e_free_rx_resources(struct e1000_ring *ring);
479void e1000e_free_tx_resources(struct e1000_ring *ring);
480void e1000e_get_stats64(struct net_device *netdev,
481 struct rtnl_link_stats64 *stats);
482void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
483void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
484void e1000e_get_hw_control(struct e1000_adapter *adapter);
485void e1000e_release_hw_control(struct e1000_adapter *adapter);
486void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
487
488extern unsigned int copybreak;
489
490extern const struct e1000_info e1000_82571_info;
491extern const struct e1000_info e1000_82572_info;
492extern const struct e1000_info e1000_82573_info;
493extern const struct e1000_info e1000_82574_info;
494extern const struct e1000_info e1000_82583_info;
495extern const struct e1000_info e1000_ich8_info;
496extern const struct e1000_info e1000_ich9_info;
497extern const struct e1000_info e1000_ich10_info;
498extern const struct e1000_info e1000_pch_info;
499extern const struct e1000_info e1000_pch2_info;
500extern const struct e1000_info e1000_pch_lpt_info;
501extern const struct e1000_info e1000_pch_spt_info;
502extern const struct e1000_info e1000_pch_cnp_info;
503extern const struct e1000_info e1000_pch_tgp_info;
504extern const struct e1000_info e1000_es2_info;
505
506void e1000e_ptp_init(struct e1000_adapter *adapter);
507void e1000e_ptp_remove(struct e1000_adapter *adapter);
508
509u64 e1000e_read_systim(struct e1000_adapter *adapter,
510 struct ptp_system_timestamp *sts);
511
512static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
513{
514 return hw->phy.ops.reset(hw);
515}
516
517static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
518{
519 return hw->phy.ops.read_reg(hw, offset, data);
520}
521
522static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
523{
524 return hw->phy.ops.read_reg_locked(hw, offset, data);
525}
526
527static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
528{
529 return hw->phy.ops.write_reg(hw, offset, data);
530}
531
532static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
533{
534 return hw->phy.ops.write_reg_locked(hw, offset, data);
535}
536
537void e1000e_reload_nvm_generic(struct e1000_hw *hw);
538
539static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
540{
541 if (hw->mac.ops.read_mac_addr)
542 return hw->mac.ops.read_mac_addr(hw);
543
544 return e1000_read_mac_addr_generic(hw);
545}
546
547static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
548{
549 return hw->nvm.ops.validate(hw);
550}
551
552static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
553{
554 return hw->nvm.ops.update(hw);
555}
556
557static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words,
558 u16 *data)
559{
560 return hw->nvm.ops.read(hw, offset, words, data);
561}
562
563static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
564 u16 *data)
565{
566 return hw->nvm.ops.write(hw, offset, words, data);
567}
568
569static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
570{
571 return hw->phy.ops.get_info(hw);
572}
573
574static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
575{
576 return readl(hw->hw_addr + reg);
577}
578
579#define er32(reg) __er32(hw, E1000_##reg)
580
581void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val);
582
583#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
584
585#define e1e_flush() er32(STATUS)
586
587#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
588 (__ew32((a), (reg + ((offset) << 2)), (value)))
589
590#define E1000_READ_REG_ARRAY(a, reg, offset) \
591 (readl((a)->hw_addr + reg + ((offset) << 2)))
592
593#endif /* _E1000_H_ */