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1/**
2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/types.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
27#include <linux/spinlock.h>
28#include <linux/gpio.h>
29#include <plat/usb.h>
30
31#define USBHS_DRIVER_NAME "usbhs-omap"
32#define OMAP_EHCI_DEVICE "ehci-omap"
33#define OMAP_OHCI_DEVICE "ohci-omap3"
34
35/* OMAP USBHOST Register addresses */
36
37/* TLL Register Set */
38#define OMAP_USBTLL_REVISION (0x00)
39#define OMAP_USBTLL_SYSCONFIG (0x10)
40#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
41#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
42#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
43#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
44#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
45
46#define OMAP_USBTLL_SYSSTATUS (0x14)
47#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
48
49#define OMAP_USBTLL_IRQSTATUS (0x18)
50#define OMAP_USBTLL_IRQENABLE (0x1C)
51
52#define OMAP_TLL_SHARED_CONF (0x30)
53#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
54#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
55#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
56#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
57#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
58
59#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
60#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
61#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
62#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
63#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
64#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
65#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
66#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
67
68#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
69#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
70#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
71#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
72#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
73#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
74#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
75#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
76#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
77#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
78
79#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
80#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
81#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
82#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
83#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
84#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
85#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
86#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
87#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
88
89#define OMAP_TLL_CHANNEL_COUNT 3
90#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
91#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
92#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
93
94/* UHH Register Set */
95#define OMAP_UHH_REVISION (0x00)
96#define OMAP_UHH_SYSCONFIG (0x10)
97#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
98#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
99#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
100#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
101#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
102#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
103
104#define OMAP_UHH_SYSSTATUS (0x14)
105#define OMAP_UHH_HOSTCONFIG (0x40)
106#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
107#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
108#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
109#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
110#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
111#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
112#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
113#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
114#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
115#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
116#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
117#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
118
119/* OMAP4-specific defines */
120#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
121#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
122#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
123#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
124#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
125
126#define OMAP4_P1_MODE_CLEAR (3 << 16)
127#define OMAP4_P1_MODE_TLL (1 << 16)
128#define OMAP4_P1_MODE_HSIC (3 << 16)
129#define OMAP4_P2_MODE_CLEAR (3 << 18)
130#define OMAP4_P2_MODE_TLL (1 << 18)
131#define OMAP4_P2_MODE_HSIC (3 << 18)
132
133#define OMAP_REV2_TLL_CHANNEL_COUNT 2
134
135#define OMAP_UHH_DEBUG_CSR (0x44)
136
137/* Values of UHH_REVISION - Note: these are not given in the TRM */
138#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
139#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
140
141#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
142#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
143
144#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
145#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
146#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
147
148
149struct usbhs_hcd_omap {
150 struct clk *usbhost_ick;
151 struct clk *usbhost_hs_fck;
152 struct clk *usbhost_fs_fck;
153 struct clk *xclk60mhsp1_ck;
154 struct clk *xclk60mhsp2_ck;
155 struct clk *utmi_p1_fck;
156 struct clk *usbhost_p1_fck;
157 struct clk *usbtll_p1_fck;
158 struct clk *utmi_p2_fck;
159 struct clk *usbhost_p2_fck;
160 struct clk *usbtll_p2_fck;
161 struct clk *init_60m_fclk;
162 struct clk *usbtll_fck;
163 struct clk *usbtll_ick;
164
165 void __iomem *uhh_base;
166 void __iomem *tll_base;
167
168 struct usbhs_omap_platform_data platdata;
169
170 u32 usbhs_rev;
171 spinlock_t lock;
172 int count;
173};
174/*-------------------------------------------------------------------------*/
175
176const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
177static u64 usbhs_dmamask = ~(u32)0;
178
179/*-------------------------------------------------------------------------*/
180
181static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
182{
183 __raw_writel(val, base + reg);
184}
185
186static inline u32 usbhs_read(void __iomem *base, u32 reg)
187{
188 return __raw_readl(base + reg);
189}
190
191static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
192{
193 __raw_writeb(val, base + reg);
194}
195
196static inline u8 usbhs_readb(void __iomem *base, u8 reg)
197{
198 return __raw_readb(base + reg);
199}
200
201/*-------------------------------------------------------------------------*/
202
203static struct platform_device *omap_usbhs_alloc_child(const char *name,
204 struct resource *res, int num_resources, void *pdata,
205 size_t pdata_size, struct device *dev)
206{
207 struct platform_device *child;
208 int ret;
209
210 child = platform_device_alloc(name, 0);
211
212 if (!child) {
213 dev_err(dev, "platform_device_alloc %s failed\n", name);
214 goto err_end;
215 }
216
217 ret = platform_device_add_resources(child, res, num_resources);
218 if (ret) {
219 dev_err(dev, "platform_device_add_resources failed\n");
220 goto err_alloc;
221 }
222
223 ret = platform_device_add_data(child, pdata, pdata_size);
224 if (ret) {
225 dev_err(dev, "platform_device_add_data failed\n");
226 goto err_alloc;
227 }
228
229 child->dev.dma_mask = &usbhs_dmamask;
230 child->dev.coherent_dma_mask = 0xffffffff;
231 child->dev.parent = dev;
232
233 ret = platform_device_add(child);
234 if (ret) {
235 dev_err(dev, "platform_device_add failed\n");
236 goto err_alloc;
237 }
238
239 return child;
240
241err_alloc:
242 platform_device_put(child);
243
244err_end:
245 return NULL;
246}
247
248static int omap_usbhs_alloc_children(struct platform_device *pdev)
249{
250 struct device *dev = &pdev->dev;
251 struct usbhs_hcd_omap *omap;
252 struct ehci_hcd_omap_platform_data *ehci_data;
253 struct ohci_hcd_omap_platform_data *ohci_data;
254 struct platform_device *ehci;
255 struct platform_device *ohci;
256 struct resource *res;
257 struct resource resources[2];
258 int ret;
259
260 omap = platform_get_drvdata(pdev);
261 ehci_data = omap->platdata.ehci_data;
262 ohci_data = omap->platdata.ohci_data;
263
264 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
265 if (!res) {
266 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
267 ret = -ENODEV;
268 goto err_end;
269 }
270 resources[0] = *res;
271
272 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
273 if (!res) {
274 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
275 ret = -ENODEV;
276 goto err_end;
277 }
278 resources[1] = *res;
279
280 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data,
281 sizeof(*ehci_data), dev);
282
283 if (!ehci) {
284 dev_err(dev, "omap_usbhs_alloc_child failed\n");
285 ret = -ENOMEM;
286 goto err_end;
287 }
288
289 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
290 if (!res) {
291 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
292 ret = -ENODEV;
293 goto err_ehci;
294 }
295 resources[0] = *res;
296
297 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
298 if (!res) {
299 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
300 ret = -ENODEV;
301 goto err_ehci;
302 }
303 resources[1] = *res;
304
305 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data,
306 sizeof(*ohci_data), dev);
307 if (!ohci) {
308 dev_err(dev, "omap_usbhs_alloc_child failed\n");
309 ret = -ENOMEM;
310 goto err_ehci;
311 }
312
313 return 0;
314
315err_ehci:
316 platform_device_unregister(ehci);
317
318err_end:
319 return ret;
320}
321
322/**
323 * usbhs_omap_probe - initialize TI-based HCDs
324 *
325 * Allocates basic resources for this USB host controller.
326 */
327static int __devinit usbhs_omap_probe(struct platform_device *pdev)
328{
329 struct device *dev = &pdev->dev;
330 struct usbhs_omap_platform_data *pdata = dev->platform_data;
331 struct usbhs_hcd_omap *omap;
332 struct resource *res;
333 int ret = 0;
334 int i;
335
336 if (!pdata) {
337 dev_err(dev, "Missing platform data\n");
338 ret = -ENOMEM;
339 goto end_probe;
340 }
341
342 omap = kzalloc(sizeof(*omap), GFP_KERNEL);
343 if (!omap) {
344 dev_err(dev, "Memory allocation failed\n");
345 ret = -ENOMEM;
346 goto end_probe;
347 }
348
349 spin_lock_init(&omap->lock);
350
351 for (i = 0; i < OMAP3_HS_USB_PORTS; i++)
352 omap->platdata.port_mode[i] = pdata->port_mode[i];
353
354 omap->platdata.ehci_data = pdata->ehci_data;
355 omap->platdata.ohci_data = pdata->ohci_data;
356
357 omap->usbhost_ick = clk_get(dev, "usbhost_ick");
358 if (IS_ERR(omap->usbhost_ick)) {
359 ret = PTR_ERR(omap->usbhost_ick);
360 dev_err(dev, "usbhost_ick failed error:%d\n", ret);
361 goto err_end;
362 }
363
364 omap->usbhost_hs_fck = clk_get(dev, "hs_fck");
365 if (IS_ERR(omap->usbhost_hs_fck)) {
366 ret = PTR_ERR(omap->usbhost_hs_fck);
367 dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret);
368 goto err_usbhost_ick;
369 }
370
371 omap->usbhost_fs_fck = clk_get(dev, "fs_fck");
372 if (IS_ERR(omap->usbhost_fs_fck)) {
373 ret = PTR_ERR(omap->usbhost_fs_fck);
374 dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret);
375 goto err_usbhost_hs_fck;
376 }
377
378 omap->usbtll_fck = clk_get(dev, "usbtll_fck");
379 if (IS_ERR(omap->usbtll_fck)) {
380 ret = PTR_ERR(omap->usbtll_fck);
381 dev_err(dev, "usbtll_fck failed error:%d\n", ret);
382 goto err_usbhost_fs_fck;
383 }
384
385 omap->usbtll_ick = clk_get(dev, "usbtll_ick");
386 if (IS_ERR(omap->usbtll_ick)) {
387 ret = PTR_ERR(omap->usbtll_ick);
388 dev_err(dev, "usbtll_ick failed error:%d\n", ret);
389 goto err_usbtll_fck;
390 }
391
392 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk");
393 if (IS_ERR(omap->utmi_p1_fck)) {
394 ret = PTR_ERR(omap->utmi_p1_fck);
395 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
396 goto err_usbtll_ick;
397 }
398
399 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
400 if (IS_ERR(omap->xclk60mhsp1_ck)) {
401 ret = PTR_ERR(omap->xclk60mhsp1_ck);
402 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
403 goto err_utmi_p1_fck;
404 }
405
406 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk");
407 if (IS_ERR(omap->utmi_p2_fck)) {
408 ret = PTR_ERR(omap->utmi_p2_fck);
409 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
410 goto err_xclk60mhsp1_ck;
411 }
412
413 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
414 if (IS_ERR(omap->xclk60mhsp2_ck)) {
415 ret = PTR_ERR(omap->xclk60mhsp2_ck);
416 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
417 goto err_utmi_p2_fck;
418 }
419
420 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk");
421 if (IS_ERR(omap->usbhost_p1_fck)) {
422 ret = PTR_ERR(omap->usbhost_p1_fck);
423 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret);
424 goto err_xclk60mhsp2_ck;
425 }
426
427 omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk");
428 if (IS_ERR(omap->usbtll_p1_fck)) {
429 ret = PTR_ERR(omap->usbtll_p1_fck);
430 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret);
431 goto err_usbhost_p1_fck;
432 }
433
434 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk");
435 if (IS_ERR(omap->usbhost_p2_fck)) {
436 ret = PTR_ERR(omap->usbhost_p2_fck);
437 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret);
438 goto err_usbtll_p1_fck;
439 }
440
441 omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk");
442 if (IS_ERR(omap->usbtll_p2_fck)) {
443 ret = PTR_ERR(omap->usbtll_p2_fck);
444 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret);
445 goto err_usbhost_p2_fck;
446 }
447
448 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
449 if (IS_ERR(omap->init_60m_fclk)) {
450 ret = PTR_ERR(omap->init_60m_fclk);
451 dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
452 goto err_usbtll_p2_fck;
453 }
454
455 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
456 if (!res) {
457 dev_err(dev, "UHH EHCI get resource failed\n");
458 ret = -ENODEV;
459 goto err_init_60m_fclk;
460 }
461
462 omap->uhh_base = ioremap(res->start, resource_size(res));
463 if (!omap->uhh_base) {
464 dev_err(dev, "UHH ioremap failed\n");
465 ret = -ENOMEM;
466 goto err_init_60m_fclk;
467 }
468
469 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll");
470 if (!res) {
471 dev_err(dev, "UHH EHCI get resource failed\n");
472 ret = -ENODEV;
473 goto err_tll;
474 }
475
476 omap->tll_base = ioremap(res->start, resource_size(res));
477 if (!omap->tll_base) {
478 dev_err(dev, "TLL ioremap failed\n");
479 ret = -ENOMEM;
480 goto err_tll;
481 }
482
483 platform_set_drvdata(pdev, omap);
484
485 ret = omap_usbhs_alloc_children(pdev);
486 if (ret) {
487 dev_err(dev, "omap_usbhs_alloc_children failed\n");
488 goto err_alloc;
489 }
490
491 goto end_probe;
492
493err_alloc:
494 iounmap(omap->tll_base);
495
496err_tll:
497 iounmap(omap->uhh_base);
498
499err_init_60m_fclk:
500 clk_put(omap->init_60m_fclk);
501
502err_usbtll_p2_fck:
503 clk_put(omap->usbtll_p2_fck);
504
505err_usbhost_p2_fck:
506 clk_put(omap->usbhost_p2_fck);
507
508err_usbtll_p1_fck:
509 clk_put(omap->usbtll_p1_fck);
510
511err_usbhost_p1_fck:
512 clk_put(omap->usbhost_p1_fck);
513
514err_xclk60mhsp2_ck:
515 clk_put(omap->xclk60mhsp2_ck);
516
517err_utmi_p2_fck:
518 clk_put(omap->utmi_p2_fck);
519
520err_xclk60mhsp1_ck:
521 clk_put(omap->xclk60mhsp1_ck);
522
523err_utmi_p1_fck:
524 clk_put(omap->utmi_p1_fck);
525
526err_usbtll_ick:
527 clk_put(omap->usbtll_ick);
528
529err_usbtll_fck:
530 clk_put(omap->usbtll_fck);
531
532err_usbhost_fs_fck:
533 clk_put(omap->usbhost_fs_fck);
534
535err_usbhost_hs_fck:
536 clk_put(omap->usbhost_hs_fck);
537
538err_usbhost_ick:
539 clk_put(omap->usbhost_ick);
540
541err_end:
542 kfree(omap);
543
544end_probe:
545 return ret;
546}
547
548/**
549 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
550 * @pdev: USB Host Controller being removed
551 *
552 * Reverses the effect of usbhs_omap_probe().
553 */
554static int __devexit usbhs_omap_remove(struct platform_device *pdev)
555{
556 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
557
558 if (omap->count != 0) {
559 dev_err(&pdev->dev,
560 "Either EHCI or OHCI is still using usbhs core\n");
561 return -EBUSY;
562 }
563
564 iounmap(omap->tll_base);
565 iounmap(omap->uhh_base);
566 clk_put(omap->init_60m_fclk);
567 clk_put(omap->usbtll_p2_fck);
568 clk_put(omap->usbhost_p2_fck);
569 clk_put(omap->usbtll_p1_fck);
570 clk_put(omap->usbhost_p1_fck);
571 clk_put(omap->xclk60mhsp2_ck);
572 clk_put(omap->utmi_p2_fck);
573 clk_put(omap->xclk60mhsp1_ck);
574 clk_put(omap->utmi_p1_fck);
575 clk_put(omap->usbtll_ick);
576 clk_put(omap->usbtll_fck);
577 clk_put(omap->usbhost_fs_fck);
578 clk_put(omap->usbhost_hs_fck);
579 clk_put(omap->usbhost_ick);
580 kfree(omap);
581
582 return 0;
583}
584
585static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
586{
587 switch (pmode) {
588 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
589 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
590 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
591 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
592 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
593 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
594 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
595 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
596 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
597 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
598 return true;
599
600 default:
601 return false;
602 }
603}
604
605/*
606 * convert the port-mode enum to a value we can use in the FSLSMODE
607 * field of USBTLL_CHANNEL_CONF
608 */
609static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
610{
611 switch (mode) {
612 case OMAP_USBHS_PORT_MODE_UNUSED:
613 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
614 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
615
616 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
617 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
618
619 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
620 return OMAP_TLL_FSLSMODE_3PIN_PHY;
621
622 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
623 return OMAP_TLL_FSLSMODE_4PIN_PHY;
624
625 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
626 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
627
628 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
629 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
630
631 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
632 return OMAP_TLL_FSLSMODE_3PIN_TLL;
633
634 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
635 return OMAP_TLL_FSLSMODE_4PIN_TLL;
636
637 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
638 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
639
640 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
641 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
642 default:
643 pr_warning("Invalid port mode, using default\n");
644 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
645 }
646}
647
648static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count)
649{
650 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
651 struct usbhs_omap_platform_data *pdata = dev->platform_data;
652 unsigned reg;
653 int i;
654
655 /* Program Common TLL register */
656 reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF);
657 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
658 | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
659 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
660 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
661
662 usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
663
664 /* Enable channels now */
665 for (i = 0; i < tll_channel_count; i++) {
666 reg = usbhs_read(omap->tll_base,
667 OMAP_TLL_CHANNEL_CONF(i));
668
669 if (is_ohci_port(pdata->port_mode[i])) {
670 reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
671 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
672 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
673 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) {
674
675 /* Disable AutoIdle, BitStuffing and use SDR Mode */
676 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
677 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
678 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
679
680 } else
681 continue;
682
683 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
684 usbhs_write(omap->tll_base,
685 OMAP_TLL_CHANNEL_CONF(i), reg);
686
687 usbhs_writeb(omap->tll_base,
688 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
689 }
690}
691
692static int usbhs_enable(struct device *dev)
693{
694 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
695 struct usbhs_omap_platform_data *pdata = &omap->platdata;
696 unsigned long flags = 0;
697 int ret = 0;
698 unsigned long timeout;
699 unsigned reg;
700
701 dev_dbg(dev, "starting TI HSUSB Controller\n");
702 if (!pdata) {
703 dev_dbg(dev, "missing platform_data\n");
704 return -ENODEV;
705 }
706
707 spin_lock_irqsave(&omap->lock, flags);
708 if (omap->count > 0)
709 goto end_count;
710
711 clk_enable(omap->usbhost_ick);
712 clk_enable(omap->usbhost_hs_fck);
713 clk_enable(omap->usbhost_fs_fck);
714 clk_enable(omap->usbtll_fck);
715 clk_enable(omap->usbtll_ick);
716
717 if (pdata->ehci_data->phy_reset) {
718 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) {
719 gpio_request(pdata->ehci_data->reset_gpio_port[0],
720 "USB1 PHY reset");
721 gpio_direction_output
722 (pdata->ehci_data->reset_gpio_port[0], 0);
723 }
724
725 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) {
726 gpio_request(pdata->ehci_data->reset_gpio_port[1],
727 "USB2 PHY reset");
728 gpio_direction_output
729 (pdata->ehci_data->reset_gpio_port[1], 0);
730 }
731
732 /* Hold the PHY in RESET for enough time till DIR is high */
733 udelay(10);
734 }
735
736 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
737 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev);
738
739 /* perform TLL soft reset, and wait until reset is complete */
740 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
741 OMAP_USBTLL_SYSCONFIG_SOFTRESET);
742
743 /* Wait for TLL reset to complete */
744 timeout = jiffies + msecs_to_jiffies(1000);
745 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
746 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
747 cpu_relax();
748
749 if (time_after(jiffies, timeout)) {
750 dev_dbg(dev, "operation timed out\n");
751 ret = -EINVAL;
752 goto err_tll;
753 }
754 }
755
756 dev_dbg(dev, "TLL RESET DONE\n");
757
758 /* (1<<3) = no idle mode only for initial debugging */
759 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
760 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
761 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
762 OMAP_USBTLL_SYSCONFIG_AUTOIDLE);
763
764 /* Put UHH in NoIdle/NoStandby mode */
765 reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG);
766 if (is_omap_usbhs_rev1(omap)) {
767 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
768 | OMAP_UHH_SYSCONFIG_SIDLEMODE
769 | OMAP_UHH_SYSCONFIG_CACTIVITY
770 | OMAP_UHH_SYSCONFIG_MIDLEMODE);
771 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
772
773
774 } else if (is_omap_usbhs_rev2(omap)) {
775 reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR;
776 reg |= OMAP4_UHH_SYSCONFIG_NOIDLE;
777 reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR;
778 reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY;
779 }
780
781 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
782
783 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
784 /* setup ULPI bypass and burst configurations */
785 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
786 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
787 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
788 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
789 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
790
791 if (is_omap_usbhs_rev1(omap)) {
792 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED)
793 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
794 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED)
795 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
796 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED)
797 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
798
799 /* Bypass the TLL module for PHY mode operation */
800 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) {
801 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n");
802 if (is_ehci_phy_mode(pdata->port_mode[0]) ||
803 is_ehci_phy_mode(pdata->port_mode[1]) ||
804 is_ehci_phy_mode(pdata->port_mode[2]))
805 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
806 else
807 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
808 } else {
809 dev_dbg(dev, "OMAP3 ES version > ES2.1\n");
810 if (is_ehci_phy_mode(pdata->port_mode[0]))
811 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
812 else
813 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
814 if (is_ehci_phy_mode(pdata->port_mode[1]))
815 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
816 else
817 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
818 if (is_ehci_phy_mode(pdata->port_mode[2]))
819 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
820 else
821 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
822 }
823 } else if (is_omap_usbhs_rev2(omap)) {
824 /* Clear port mode fields for PHY mode*/
825 reg &= ~OMAP4_P1_MODE_CLEAR;
826 reg &= ~OMAP4_P2_MODE_CLEAR;
827
828 if (is_ehci_phy_mode(pdata->port_mode[0])) {
829 ret = clk_set_parent(omap->utmi_p1_fck,
830 omap->xclk60mhsp1_ck);
831 if (ret != 0) {
832 dev_err(dev, "xclk60mhsp1_ck set parent"
833 "failed error:%d\n", ret);
834 goto err_tll;
835 }
836 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
837 ret = clk_set_parent(omap->utmi_p1_fck,
838 omap->init_60m_fclk);
839 if (ret != 0) {
840 dev_err(dev, "init_60m_fclk set parent"
841 "failed error:%d\n", ret);
842 goto err_tll;
843 }
844 clk_enable(omap->usbhost_p1_fck);
845 clk_enable(omap->usbtll_p1_fck);
846 }
847
848 if (is_ehci_phy_mode(pdata->port_mode[1])) {
849 ret = clk_set_parent(omap->utmi_p2_fck,
850 omap->xclk60mhsp2_ck);
851 if (ret != 0) {
852 dev_err(dev, "xclk60mhsp1_ck set parent"
853 "failed error:%d\n", ret);
854 goto err_tll;
855 }
856 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
857 ret = clk_set_parent(omap->utmi_p2_fck,
858 omap->init_60m_fclk);
859 if (ret != 0) {
860 dev_err(dev, "init_60m_fclk set parent"
861 "failed error:%d\n", ret);
862 goto err_tll;
863 }
864 clk_enable(omap->usbhost_p2_fck);
865 clk_enable(omap->usbtll_p2_fck);
866 }
867
868 clk_enable(omap->utmi_p1_fck);
869 clk_enable(omap->utmi_p2_fck);
870
871 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
872 (is_ohci_port(pdata->port_mode[0])))
873 reg |= OMAP4_P1_MODE_TLL;
874 else if (is_ehci_hsic_mode(pdata->port_mode[0]))
875 reg |= OMAP4_P1_MODE_HSIC;
876
877 if (is_ehci_tll_mode(pdata->port_mode[1]) ||
878 (is_ohci_port(pdata->port_mode[1])))
879 reg |= OMAP4_P2_MODE_TLL;
880 else if (is_ehci_hsic_mode(pdata->port_mode[1]))
881 reg |= OMAP4_P2_MODE_HSIC;
882 }
883
884 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
885 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
886
887 if (is_ehci_tll_mode(pdata->port_mode[0]) ||
888 is_ehci_tll_mode(pdata->port_mode[1]) ||
889 is_ehci_tll_mode(pdata->port_mode[2]) ||
890 (is_ohci_port(pdata->port_mode[0])) ||
891 (is_ohci_port(pdata->port_mode[1])) ||
892 (is_ohci_port(pdata->port_mode[2]))) {
893
894 /* Enable UTMI mode for required TLL channels */
895 if (is_omap_usbhs_rev2(omap))
896 usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT);
897 else
898 usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT);
899 }
900
901 if (pdata->ehci_data->phy_reset) {
902 /* Hold the PHY in RESET for enough time till
903 * PHY is settled and ready
904 */
905 udelay(10);
906
907 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
908 gpio_set_value
909 (pdata->ehci_data->reset_gpio_port[0], 1);
910
911 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
912 gpio_set_value
913 (pdata->ehci_data->reset_gpio_port[1], 1);
914 }
915
916end_count:
917 omap->count++;
918 spin_unlock_irqrestore(&omap->lock, flags);
919 return 0;
920
921err_tll:
922 if (pdata->ehci_data->phy_reset) {
923 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
924 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
925
926 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
927 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
928 }
929
930 clk_disable(omap->usbtll_ick);
931 clk_disable(omap->usbtll_fck);
932 clk_disable(omap->usbhost_fs_fck);
933 clk_disable(omap->usbhost_hs_fck);
934 clk_disable(omap->usbhost_ick);
935 spin_unlock_irqrestore(&omap->lock, flags);
936 return ret;
937}
938
939static void usbhs_disable(struct device *dev)
940{
941 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
942 struct usbhs_omap_platform_data *pdata = &omap->platdata;
943 unsigned long flags = 0;
944 unsigned long timeout;
945
946 dev_dbg(dev, "stopping TI HSUSB Controller\n");
947
948 spin_lock_irqsave(&omap->lock, flags);
949
950 if (omap->count == 0)
951 goto end_disble;
952
953 omap->count--;
954
955 if (omap->count != 0)
956 goto end_disble;
957
958 /* Reset OMAP modules for insmod/rmmod to work */
959 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG,
960 is_omap_usbhs_rev2(omap) ?
961 OMAP4_UHH_SYSCONFIG_SOFTRESET :
962 OMAP_UHH_SYSCONFIG_SOFTRESET);
963
964 timeout = jiffies + msecs_to_jiffies(100);
965 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
966 & (1 << 0))) {
967 cpu_relax();
968
969 if (time_after(jiffies, timeout))
970 dev_dbg(dev, "operation timed out\n");
971 }
972
973 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
974 & (1 << 1))) {
975 cpu_relax();
976
977 if (time_after(jiffies, timeout))
978 dev_dbg(dev, "operation timed out\n");
979 }
980
981 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS)
982 & (1 << 2))) {
983 cpu_relax();
984
985 if (time_after(jiffies, timeout))
986 dev_dbg(dev, "operation timed out\n");
987 }
988
989 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
990
991 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
992 & (1 << 0))) {
993 cpu_relax();
994
995 if (time_after(jiffies, timeout))
996 dev_dbg(dev, "operation timed out\n");
997 }
998
999 if (is_omap_usbhs_rev2(omap)) {
1000 if (is_ehci_tll_mode(pdata->port_mode[0]))
1001 clk_disable(omap->usbtll_p1_fck);
1002 if (is_ehci_tll_mode(pdata->port_mode[1]))
1003 clk_disable(omap->usbtll_p2_fck);
1004 clk_disable(omap->utmi_p2_fck);
1005 clk_disable(omap->utmi_p1_fck);
1006 }
1007
1008 clk_disable(omap->usbtll_ick);
1009 clk_disable(omap->usbtll_fck);
1010 clk_disable(omap->usbhost_fs_fck);
1011 clk_disable(omap->usbhost_hs_fck);
1012 clk_disable(omap->usbhost_ick);
1013
1014 /* The gpio_free migh sleep; so unlock the spinlock */
1015 spin_unlock_irqrestore(&omap->lock, flags);
1016
1017 if (pdata->ehci_data->phy_reset) {
1018 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0]))
1019 gpio_free(pdata->ehci_data->reset_gpio_port[0]);
1020
1021 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1]))
1022 gpio_free(pdata->ehci_data->reset_gpio_port[1]);
1023 }
1024 return;
1025
1026end_disble:
1027 spin_unlock_irqrestore(&omap->lock, flags);
1028}
1029
1030int omap_usbhs_enable(struct device *dev)
1031{
1032 return usbhs_enable(dev->parent);
1033}
1034EXPORT_SYMBOL_GPL(omap_usbhs_enable);
1035
1036void omap_usbhs_disable(struct device *dev)
1037{
1038 usbhs_disable(dev->parent);
1039}
1040EXPORT_SYMBOL_GPL(omap_usbhs_disable);
1041
1042static struct platform_driver usbhs_omap_driver = {
1043 .driver = {
1044 .name = (char *)usbhs_driver_name,
1045 .owner = THIS_MODULE,
1046 },
1047 .remove = __exit_p(usbhs_omap_remove),
1048};
1049
1050MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
1051MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
1052MODULE_LICENSE("GPL v2");
1053MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
1054
1055static int __init omap_usbhs_drvinit(void)
1056{
1057 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
1058}
1059
1060/*
1061 * init before ehci and ohci drivers;
1062 * The usbhs core driver should be initialized much before
1063 * the omap ehci and ohci probe functions are called.
1064 */
1065fs_initcall(omap_usbhs_drvinit);
1066
1067static void __exit omap_usbhs_drvexit(void)
1068{
1069 platform_driver_unregister(&usbhs_omap_driver);
1070}
1071module_exit(omap_usbhs_drvexit);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
4 *
5 * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com
6 * Author: Keshava Munegowda <keshava_mgowda@ti.com>
7 * Author: Roger Quadros <rogerq@ti.com>
8 */
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/slab.h>
13#include <linux/delay.h>
14#include <linux/clk.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/platform_data/usb-omap.h>
19#include <linux/pm_runtime.h>
20#include <linux/of.h>
21#include <linux/of_platform.h>
22#include <linux/err.h>
23
24#include "omap-usb.h"
25
26#define USBHS_DRIVER_NAME "usbhs_omap"
27#define OMAP_EHCI_DEVICE "ehci-omap"
28#define OMAP_OHCI_DEVICE "ohci-omap3"
29
30/* OMAP USBHOST Register addresses */
31
32/* UHH Register Set */
33#define OMAP_UHH_REVISION (0x00)
34#define OMAP_UHH_SYSCONFIG (0x10)
35#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
36#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
37#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
38#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
39#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
40#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
41
42#define OMAP_UHH_SYSSTATUS (0x14)
43#define OMAP_UHH_HOSTCONFIG (0x40)
44#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
45#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
46#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
47#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
48#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
49#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
50#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
51#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
52#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
53#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
54#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
55#define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
56
57/* OMAP4-specific defines */
58#define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
59#define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
60#define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
61#define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
62#define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
63
64#define OMAP4_P1_MODE_CLEAR (3 << 16)
65#define OMAP4_P1_MODE_TLL (1 << 16)
66#define OMAP4_P1_MODE_HSIC (3 << 16)
67#define OMAP4_P2_MODE_CLEAR (3 << 18)
68#define OMAP4_P2_MODE_TLL (1 << 18)
69#define OMAP4_P2_MODE_HSIC (3 << 18)
70
71#define OMAP_UHH_DEBUG_CSR (0x44)
72
73/* Values of UHH_REVISION - Note: these are not given in the TRM */
74#define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
75#define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
76
77#define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
78#define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
79
80#define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
81#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
82#define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
83
84
85struct usbhs_hcd_omap {
86 int nports;
87 struct clk **utmi_clk;
88 struct clk **hsic60m_clk;
89 struct clk **hsic480m_clk;
90
91 struct clk *xclk60mhsp1_ck;
92 struct clk *xclk60mhsp2_ck;
93 struct clk *utmi_p1_gfclk;
94 struct clk *utmi_p2_gfclk;
95 struct clk *init_60m_fclk;
96 struct clk *ehci_logic_fck;
97
98 void __iomem *uhh_base;
99
100 struct usbhs_omap_platform_data *pdata;
101
102 u32 usbhs_rev;
103};
104/*-------------------------------------------------------------------------*/
105
106static const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
107static u64 usbhs_dmamask = DMA_BIT_MASK(32);
108
109/*-------------------------------------------------------------------------*/
110
111static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
112{
113 writel_relaxed(val, base + reg);
114}
115
116static inline u32 usbhs_read(void __iomem *base, u32 reg)
117{
118 return readl_relaxed(base + reg);
119}
120
121/*-------------------------------------------------------------------------*/
122
123/*
124 * Map 'enum usbhs_omap_port_mode' found in <linux/platform_data/usb-omap.h>
125 * to the device tree binding portN-mode found in
126 * 'Documentation/devicetree/bindings/mfd/omap-usb-host.txt'
127 */
128static const char * const port_modes[] = {
129 [OMAP_USBHS_PORT_MODE_UNUSED] = "",
130 [OMAP_EHCI_PORT_MODE_PHY] = "ehci-phy",
131 [OMAP_EHCI_PORT_MODE_TLL] = "ehci-tll",
132 [OMAP_EHCI_PORT_MODE_HSIC] = "ehci-hsic",
133 [OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0] = "ohci-phy-6pin-datse0",
134 [OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM] = "ohci-phy-6pin-dpdm",
135 [OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0] = "ohci-phy-3pin-datse0",
136 [OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM] = "ohci-phy-4pin-dpdm",
137 [OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0] = "ohci-tll-6pin-datse0",
138 [OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM] = "ohci-tll-6pin-dpdm",
139 [OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0] = "ohci-tll-3pin-datse0",
140 [OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM] = "ohci-tll-4pin-dpdm",
141 [OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0] = "ohci-tll-2pin-datse0",
142 [OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM] = "ohci-tll-2pin-dpdm",
143};
144
145static struct platform_device *omap_usbhs_alloc_child(const char *name,
146 struct resource *res, int num_resources, void *pdata,
147 size_t pdata_size, struct device *dev)
148{
149 struct platform_device *child;
150 int ret;
151
152 child = platform_device_alloc(name, 0);
153
154 if (!child) {
155 dev_err(dev, "platform_device_alloc %s failed\n", name);
156 goto err_end;
157 }
158
159 ret = platform_device_add_resources(child, res, num_resources);
160 if (ret) {
161 dev_err(dev, "platform_device_add_resources failed\n");
162 goto err_alloc;
163 }
164
165 ret = platform_device_add_data(child, pdata, pdata_size);
166 if (ret) {
167 dev_err(dev, "platform_device_add_data failed\n");
168 goto err_alloc;
169 }
170
171 child->dev.dma_mask = &usbhs_dmamask;
172 dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
173 child->dev.parent = dev;
174
175 ret = platform_device_add(child);
176 if (ret) {
177 dev_err(dev, "platform_device_add failed\n");
178 goto err_alloc;
179 }
180
181 return child;
182
183err_alloc:
184 platform_device_put(child);
185
186err_end:
187 return NULL;
188}
189
190static int omap_usbhs_alloc_children(struct platform_device *pdev)
191{
192 struct device *dev = &pdev->dev;
193 struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev);
194 struct platform_device *ehci;
195 struct platform_device *ohci;
196 struct resource *res;
197 struct resource resources[2];
198 int ret;
199
200 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
201 if (!res) {
202 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
203 ret = -ENODEV;
204 goto err_end;
205 }
206 resources[0] = *res;
207
208 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
209 if (!res) {
210 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
211 ret = -ENODEV;
212 goto err_end;
213 }
214 resources[1] = *res;
215
216 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
217 sizeof(*pdata), dev);
218
219 if (!ehci) {
220 dev_err(dev, "omap_usbhs_alloc_child failed\n");
221 ret = -ENOMEM;
222 goto err_end;
223 }
224
225 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
226 if (!res) {
227 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
228 ret = -ENODEV;
229 goto err_ehci;
230 }
231 resources[0] = *res;
232
233 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
234 if (!res) {
235 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
236 ret = -ENODEV;
237 goto err_ehci;
238 }
239 resources[1] = *res;
240
241 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
242 sizeof(*pdata), dev);
243 if (!ohci) {
244 dev_err(dev, "omap_usbhs_alloc_child failed\n");
245 ret = -ENOMEM;
246 goto err_ehci;
247 }
248
249 return 0;
250
251err_ehci:
252 platform_device_unregister(ehci);
253
254err_end:
255 return ret;
256}
257
258static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
259{
260 switch (pmode) {
261 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
262 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
263 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
264 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
265 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
266 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
267 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
268 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
269 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
270 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
271 return true;
272
273 default:
274 return false;
275 }
276}
277
278static int usbhs_runtime_resume(struct device *dev)
279{
280 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
281 struct usbhs_omap_platform_data *pdata = omap->pdata;
282 int i, r;
283
284 dev_dbg(dev, "usbhs_runtime_resume\n");
285
286 omap_tll_enable(pdata);
287
288 if (!IS_ERR(omap->ehci_logic_fck))
289 clk_prepare_enable(omap->ehci_logic_fck);
290
291 for (i = 0; i < omap->nports; i++) {
292 switch (pdata->port_mode[i]) {
293 case OMAP_EHCI_PORT_MODE_HSIC:
294 if (!IS_ERR(omap->hsic60m_clk[i])) {
295 r = clk_prepare_enable(omap->hsic60m_clk[i]);
296 if (r) {
297 dev_err(dev,
298 "Can't enable port %d hsic60m clk:%d\n",
299 i, r);
300 }
301 }
302
303 if (!IS_ERR(omap->hsic480m_clk[i])) {
304 r = clk_prepare_enable(omap->hsic480m_clk[i]);
305 if (r) {
306 dev_err(dev,
307 "Can't enable port %d hsic480m clk:%d\n",
308 i, r);
309 }
310 }
311 fallthrough; /* as HSIC mode needs utmi_clk */
312
313 case OMAP_EHCI_PORT_MODE_TLL:
314 if (!IS_ERR(omap->utmi_clk[i])) {
315 r = clk_prepare_enable(omap->utmi_clk[i]);
316 if (r) {
317 dev_err(dev,
318 "Can't enable port %d clk : %d\n",
319 i, r);
320 }
321 }
322 break;
323 default:
324 break;
325 }
326 }
327
328 return 0;
329}
330
331static int usbhs_runtime_suspend(struct device *dev)
332{
333 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
334 struct usbhs_omap_platform_data *pdata = omap->pdata;
335 int i;
336
337 dev_dbg(dev, "usbhs_runtime_suspend\n");
338
339 for (i = 0; i < omap->nports; i++) {
340 switch (pdata->port_mode[i]) {
341 case OMAP_EHCI_PORT_MODE_HSIC:
342 if (!IS_ERR(omap->hsic60m_clk[i]))
343 clk_disable_unprepare(omap->hsic60m_clk[i]);
344
345 if (!IS_ERR(omap->hsic480m_clk[i]))
346 clk_disable_unprepare(omap->hsic480m_clk[i]);
347 fallthrough; /* as utmi_clks were used in HSIC mode */
348
349 case OMAP_EHCI_PORT_MODE_TLL:
350 if (!IS_ERR(omap->utmi_clk[i]))
351 clk_disable_unprepare(omap->utmi_clk[i]);
352 break;
353 default:
354 break;
355 }
356 }
357
358 if (!IS_ERR(omap->ehci_logic_fck))
359 clk_disable_unprepare(omap->ehci_logic_fck);
360
361 omap_tll_disable(pdata);
362
363 return 0;
364}
365
366static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
367 unsigned reg)
368{
369 struct usbhs_omap_platform_data *pdata = omap->pdata;
370 int i;
371
372 for (i = 0; i < omap->nports; i++) {
373 switch (pdata->port_mode[i]) {
374 case OMAP_USBHS_PORT_MODE_UNUSED:
375 reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
376 break;
377 case OMAP_EHCI_PORT_MODE_PHY:
378 if (pdata->single_ulpi_bypass)
379 break;
380
381 if (i == 0)
382 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
383 else
384 reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
385 << (i-1));
386 break;
387 default:
388 if (pdata->single_ulpi_bypass)
389 break;
390
391 if (i == 0)
392 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
393 else
394 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
395 << (i-1);
396 break;
397 }
398 }
399
400 if (pdata->single_ulpi_bypass) {
401 /* bypass ULPI only if none of the ports use PHY mode */
402 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
403
404 for (i = 0; i < omap->nports; i++) {
405 if (is_ehci_phy_mode(pdata->port_mode[i])) {
406 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
407 break;
408 }
409 }
410 }
411
412 return reg;
413}
414
415static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
416 unsigned reg)
417{
418 struct usbhs_omap_platform_data *pdata = omap->pdata;
419 int i;
420
421 for (i = 0; i < omap->nports; i++) {
422 /* Clear port mode fields for PHY mode */
423 reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
424
425 if (is_ehci_tll_mode(pdata->port_mode[i]) ||
426 (is_ohci_port(pdata->port_mode[i])))
427 reg |= OMAP4_P1_MODE_TLL << 2 * i;
428 else if (is_ehci_hsic_mode(pdata->port_mode[i]))
429 reg |= OMAP4_P1_MODE_HSIC << 2 * i;
430 }
431
432 return reg;
433}
434
435static void omap_usbhs_init(struct device *dev)
436{
437 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
438 unsigned reg;
439
440 dev_dbg(dev, "starting TI HSUSB Controller\n");
441
442 pm_runtime_get_sync(dev);
443
444 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
445 /* setup ULPI bypass and burst configurations */
446 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
447 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
448 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
449 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
450 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
451
452 switch (omap->usbhs_rev) {
453 case OMAP_USBHS_REV1:
454 reg = omap_usbhs_rev1_hostconfig(omap, reg);
455 break;
456
457 case OMAP_USBHS_REV2:
458 reg = omap_usbhs_rev2_hostconfig(omap, reg);
459 break;
460
461 default: /* newer revisions */
462 reg = omap_usbhs_rev2_hostconfig(omap, reg);
463 break;
464 }
465
466 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
467 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
468
469 pm_runtime_put_sync(dev);
470}
471
472static int usbhs_omap_get_dt_pdata(struct device *dev,
473 struct usbhs_omap_platform_data *pdata)
474{
475 int ret, i;
476 struct device_node *node = dev->of_node;
477
478 ret = of_property_read_u32(node, "num-ports", &pdata->nports);
479 if (ret)
480 pdata->nports = 0;
481
482 if (pdata->nports > OMAP3_HS_USB_PORTS) {
483 dev_warn(dev, "Too many num_ports <%d> in device tree. Max %d\n",
484 pdata->nports, OMAP3_HS_USB_PORTS);
485 return -ENODEV;
486 }
487
488 /* get port modes */
489 for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
490 char prop[11];
491 const char *mode;
492
493 pdata->port_mode[i] = OMAP_USBHS_PORT_MODE_UNUSED;
494
495 snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
496 ret = of_property_read_string(node, prop, &mode);
497 if (ret < 0)
498 continue;
499
500 /* get 'enum usbhs_omap_port_mode' from port mode string */
501 ret = match_string(port_modes, ARRAY_SIZE(port_modes), mode);
502 if (ret < 0) {
503 dev_warn(dev, "Invalid port%d-mode \"%s\" in device tree\n",
504 i, mode);
505 return -ENODEV;
506 }
507
508 dev_dbg(dev, "port%d-mode: %s -> %d\n", i, mode, ret);
509 pdata->port_mode[i] = ret;
510 }
511
512 /* get flags */
513 pdata->single_ulpi_bypass = of_property_read_bool(node,
514 "single-ulpi-bypass");
515
516 return 0;
517}
518
519static const struct of_device_id usbhs_child_match_table[] = {
520 { .compatible = "ti,ehci-omap", },
521 { .compatible = "ti,ohci-omap3", },
522 { }
523};
524
525/**
526 * usbhs_omap_probe - initialize TI-based HCDs
527 *
528 * Allocates basic resources for this USB host controller.
529 *
530 * @pdev: Pointer to this device's platform device structure
531 */
532static int usbhs_omap_probe(struct platform_device *pdev)
533{
534 struct device *dev = &pdev->dev;
535 struct usbhs_omap_platform_data *pdata = dev_get_platdata(dev);
536 struct usbhs_hcd_omap *omap;
537 struct resource *res;
538 int ret = 0;
539 int i;
540 bool need_logic_fck;
541
542 if (dev->of_node) {
543 /* For DT boot we populate platform data from OF node */
544 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
545 if (!pdata)
546 return -ENOMEM;
547
548 ret = usbhs_omap_get_dt_pdata(dev, pdata);
549 if (ret)
550 return ret;
551
552 dev->platform_data = pdata;
553 }
554
555 if (!pdata) {
556 dev_err(dev, "Missing platform data\n");
557 return -ENODEV;
558 }
559
560 if (pdata->nports > OMAP3_HS_USB_PORTS) {
561 dev_info(dev, "Too many num_ports <%d> in platform_data. Max %d\n",
562 pdata->nports, OMAP3_HS_USB_PORTS);
563 return -ENODEV;
564 }
565
566 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
567 if (!omap) {
568 dev_err(dev, "Memory allocation failed\n");
569 return -ENOMEM;
570 }
571
572 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
573 omap->uhh_base = devm_ioremap_resource(dev, res);
574 if (IS_ERR(omap->uhh_base))
575 return PTR_ERR(omap->uhh_base);
576
577 omap->pdata = pdata;
578
579 /* Initialize the TLL subsystem */
580 omap_tll_init(pdata);
581
582 pm_runtime_enable(dev);
583
584 platform_set_drvdata(pdev, omap);
585 pm_runtime_get_sync(dev);
586
587 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
588
589 /* we need to call runtime suspend before we update omap->nports
590 * to prevent unbalanced clk_disable()
591 */
592 pm_runtime_put_sync(dev);
593
594 /*
595 * If platform data contains nports then use that
596 * else make out number of ports from USBHS revision
597 */
598 if (pdata->nports) {
599 omap->nports = pdata->nports;
600 } else {
601 switch (omap->usbhs_rev) {
602 case OMAP_USBHS_REV1:
603 omap->nports = 3;
604 break;
605 case OMAP_USBHS_REV2:
606 omap->nports = 2;
607 break;
608 default:
609 omap->nports = OMAP3_HS_USB_PORTS;
610 dev_dbg(dev,
611 "USB HOST Rev:0x%x not recognized, assuming %d ports\n",
612 omap->usbhs_rev, omap->nports);
613 break;
614 }
615 pdata->nports = omap->nports;
616 }
617
618 i = sizeof(struct clk *) * omap->nports;
619 omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
620 omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
621 omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
622
623 if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
624 dev_err(dev, "Memory allocation failed\n");
625 ret = -ENOMEM;
626 goto err_mem;
627 }
628
629 /* Set all clocks as invalid to begin with */
630 omap->ehci_logic_fck = ERR_PTR(-ENODEV);
631 omap->init_60m_fclk = ERR_PTR(-ENODEV);
632 omap->utmi_p1_gfclk = ERR_PTR(-ENODEV);
633 omap->utmi_p2_gfclk = ERR_PTR(-ENODEV);
634 omap->xclk60mhsp1_ck = ERR_PTR(-ENODEV);
635 omap->xclk60mhsp2_ck = ERR_PTR(-ENODEV);
636
637 for (i = 0; i < omap->nports; i++) {
638 omap->utmi_clk[i] = ERR_PTR(-ENODEV);
639 omap->hsic480m_clk[i] = ERR_PTR(-ENODEV);
640 omap->hsic60m_clk[i] = ERR_PTR(-ENODEV);
641 }
642
643 /* for OMAP3 i.e. USBHS REV1 */
644 if (omap->usbhs_rev == OMAP_USBHS_REV1) {
645 need_logic_fck = false;
646 for (i = 0; i < omap->nports; i++) {
647 if (is_ehci_phy_mode(pdata->port_mode[i]) ||
648 is_ehci_tll_mode(pdata->port_mode[i]) ||
649 is_ehci_hsic_mode(pdata->port_mode[i]))
650
651 need_logic_fck |= true;
652 }
653
654 if (need_logic_fck) {
655 omap->ehci_logic_fck = devm_clk_get(dev,
656 "usbhost_120m_fck");
657 if (IS_ERR(omap->ehci_logic_fck)) {
658 ret = PTR_ERR(omap->ehci_logic_fck);
659 dev_err(dev, "usbhost_120m_fck failed:%d\n",
660 ret);
661 goto err_mem;
662 }
663 }
664 goto initialize;
665 }
666
667 /* for OMAP4+ i.e. USBHS REV2+ */
668 omap->utmi_p1_gfclk = devm_clk_get(dev, "utmi_p1_gfclk");
669 if (IS_ERR(omap->utmi_p1_gfclk)) {
670 ret = PTR_ERR(omap->utmi_p1_gfclk);
671 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
672 goto err_mem;
673 }
674
675 omap->utmi_p2_gfclk = devm_clk_get(dev, "utmi_p2_gfclk");
676 if (IS_ERR(omap->utmi_p2_gfclk)) {
677 ret = PTR_ERR(omap->utmi_p2_gfclk);
678 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
679 goto err_mem;
680 }
681
682 omap->xclk60mhsp1_ck = devm_clk_get(dev, "refclk_60m_ext_p1");
683 if (IS_ERR(omap->xclk60mhsp1_ck)) {
684 ret = PTR_ERR(omap->xclk60mhsp1_ck);
685 dev_err(dev, "refclk_60m_ext_p1 failed error:%d\n", ret);
686 goto err_mem;
687 }
688
689 omap->xclk60mhsp2_ck = devm_clk_get(dev, "refclk_60m_ext_p2");
690 if (IS_ERR(omap->xclk60mhsp2_ck)) {
691 ret = PTR_ERR(omap->xclk60mhsp2_ck);
692 dev_err(dev, "refclk_60m_ext_p2 failed error:%d\n", ret);
693 goto err_mem;
694 }
695
696 omap->init_60m_fclk = devm_clk_get(dev, "refclk_60m_int");
697 if (IS_ERR(omap->init_60m_fclk)) {
698 ret = PTR_ERR(omap->init_60m_fclk);
699 dev_err(dev, "refclk_60m_int failed error:%d\n", ret);
700 goto err_mem;
701 }
702
703 for (i = 0; i < omap->nports; i++) {
704 char clkname[30];
705
706 /* clock names are indexed from 1*/
707 snprintf(clkname, sizeof(clkname),
708 "usb_host_hs_utmi_p%d_clk", i + 1);
709
710 /* If a clock is not found we won't bail out as not all
711 * platforms have all clocks and we can function without
712 * them
713 */
714 omap->utmi_clk[i] = devm_clk_get(dev, clkname);
715 if (IS_ERR(omap->utmi_clk[i])) {
716 ret = PTR_ERR(omap->utmi_clk[i]);
717 dev_err(dev, "Failed to get clock : %s : %d\n",
718 clkname, ret);
719 goto err_mem;
720 }
721
722 snprintf(clkname, sizeof(clkname),
723 "usb_host_hs_hsic480m_p%d_clk", i + 1);
724 omap->hsic480m_clk[i] = devm_clk_get(dev, clkname);
725 if (IS_ERR(omap->hsic480m_clk[i])) {
726 ret = PTR_ERR(omap->hsic480m_clk[i]);
727 dev_err(dev, "Failed to get clock : %s : %d\n",
728 clkname, ret);
729 goto err_mem;
730 }
731
732 snprintf(clkname, sizeof(clkname),
733 "usb_host_hs_hsic60m_p%d_clk", i + 1);
734 omap->hsic60m_clk[i] = devm_clk_get(dev, clkname);
735 if (IS_ERR(omap->hsic60m_clk[i])) {
736 ret = PTR_ERR(omap->hsic60m_clk[i]);
737 dev_err(dev, "Failed to get clock : %s : %d\n",
738 clkname, ret);
739 goto err_mem;
740 }
741 }
742
743 if (is_ehci_phy_mode(pdata->port_mode[0])) {
744 ret = clk_set_parent(omap->utmi_p1_gfclk,
745 omap->xclk60mhsp1_ck);
746 if (ret != 0) {
747 dev_err(dev, "xclk60mhsp1_ck set parent failed: %d\n",
748 ret);
749 goto err_mem;
750 }
751 } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
752 ret = clk_set_parent(omap->utmi_p1_gfclk,
753 omap->init_60m_fclk);
754 if (ret != 0) {
755 dev_err(dev, "P0 init_60m_fclk set parent failed: %d\n",
756 ret);
757 goto err_mem;
758 }
759 }
760
761 if (is_ehci_phy_mode(pdata->port_mode[1])) {
762 ret = clk_set_parent(omap->utmi_p2_gfclk,
763 omap->xclk60mhsp2_ck);
764 if (ret != 0) {
765 dev_err(dev, "xclk60mhsp2_ck set parent failed: %d\n",
766 ret);
767 goto err_mem;
768 }
769 } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
770 ret = clk_set_parent(omap->utmi_p2_gfclk,
771 omap->init_60m_fclk);
772 if (ret != 0) {
773 dev_err(dev, "P1 init_60m_fclk set parent failed: %d\n",
774 ret);
775 goto err_mem;
776 }
777 }
778
779initialize:
780 omap_usbhs_init(dev);
781
782 if (dev->of_node) {
783 ret = of_platform_populate(dev->of_node,
784 usbhs_child_match_table, NULL, dev);
785
786 if (ret) {
787 dev_err(dev, "Failed to create DT children: %d\n", ret);
788 goto err_mem;
789 }
790
791 } else {
792 ret = omap_usbhs_alloc_children(pdev);
793 if (ret) {
794 dev_err(dev, "omap_usbhs_alloc_children failed: %d\n",
795 ret);
796 goto err_mem;
797 }
798 }
799
800 return 0;
801
802err_mem:
803 pm_runtime_disable(dev);
804
805 return ret;
806}
807
808static int usbhs_omap_remove_child(struct device *dev, void *data)
809{
810 dev_info(dev, "unregistering\n");
811 platform_device_unregister(to_platform_device(dev));
812 return 0;
813}
814
815/**
816 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
817 * @pdev: USB Host Controller being removed
818 *
819 * Reverses the effect of usbhs_omap_probe().
820 */
821static int usbhs_omap_remove(struct platform_device *pdev)
822{
823 pm_runtime_disable(&pdev->dev);
824
825 /* remove children */
826 device_for_each_child(&pdev->dev, NULL, usbhs_omap_remove_child);
827 return 0;
828}
829
830static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
831 .runtime_suspend = usbhs_runtime_suspend,
832 .runtime_resume = usbhs_runtime_resume,
833};
834
835static const struct of_device_id usbhs_omap_dt_ids[] = {
836 { .compatible = "ti,usbhs-host" },
837 { }
838};
839
840MODULE_DEVICE_TABLE(of, usbhs_omap_dt_ids);
841
842
843static struct platform_driver usbhs_omap_driver = {
844 .driver = {
845 .name = usbhs_driver_name,
846 .pm = &usbhsomap_dev_pm_ops,
847 .of_match_table = usbhs_omap_dt_ids,
848 },
849 .probe = usbhs_omap_probe,
850 .remove = usbhs_omap_remove,
851};
852
853MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
854MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
855MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
856MODULE_LICENSE("GPL v2");
857MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
858
859static int omap_usbhs_drvinit(void)
860{
861 return platform_driver_register(&usbhs_omap_driver);
862}
863
864/*
865 * init before ehci and ohci drivers;
866 * The usbhs core driver should be initialized much before
867 * the omap ehci and ohci probe functions are called.
868 * This usbhs core driver should be initialized after
869 * usb tll driver
870 */
871fs_initcall_sync(omap_usbhs_drvinit);
872
873static void omap_usbhs_drvexit(void)
874{
875 platform_driver_unregister(&usbhs_omap_driver);
876}
877module_exit(omap_usbhs_drvexit);