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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Red Hat
4 *
5 * based in parts on udlfb.c:
6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it>
7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
9
10 */
11
12#include <linux/dma-buf.h>
13
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_crtc_helper.h>
16#include <drm/drm_damage_helper.h>
17#include <drm/drm_fourcc.h>
18#include <drm/drm_gem_atomic_helper.h>
19#include <drm/drm_gem_framebuffer_helper.h>
20#include <drm/drm_gem_shmem_helper.h>
21#include <drm/drm_modeset_helper_vtables.h>
22#include <drm/drm_vblank.h>
23
24#include "udl_drv.h"
25
26#define UDL_COLOR_DEPTH_16BPP 0
27
28/*
29 * All DisplayLink bulk operations start with 0xAF, followed by specific code
30 * All operations are written to buffers which then later get sent to device
31 */
32static char *udl_set_register(char *buf, u8 reg, u8 val)
33{
34 *buf++ = 0xAF;
35 *buf++ = 0x20;
36 *buf++ = reg;
37 *buf++ = val;
38 return buf;
39}
40
41static char *udl_vidreg_lock(char *buf)
42{
43 return udl_set_register(buf, 0xFF, 0x00);
44}
45
46static char *udl_vidreg_unlock(char *buf)
47{
48 return udl_set_register(buf, 0xFF, 0xFF);
49}
50
51static char *udl_set_blank_mode(char *buf, u8 mode)
52{
53 return udl_set_register(buf, UDL_REG_BLANK_MODE, mode);
54}
55
56static char *udl_set_color_depth(char *buf, u8 selection)
57{
58 return udl_set_register(buf, 0x00, selection);
59}
60
61static char *udl_set_base16bpp(char *wrptr, u32 base)
62{
63 /* the base pointer is 16 bits wide, 0x20 is hi byte. */
64 wrptr = udl_set_register(wrptr, 0x20, base >> 16);
65 wrptr = udl_set_register(wrptr, 0x21, base >> 8);
66 return udl_set_register(wrptr, 0x22, base);
67}
68
69/*
70 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
71 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
72 */
73static char *udl_set_base8bpp(char *wrptr, u32 base)
74{
75 wrptr = udl_set_register(wrptr, 0x26, base >> 16);
76 wrptr = udl_set_register(wrptr, 0x27, base >> 8);
77 return udl_set_register(wrptr, 0x28, base);
78}
79
80static char *udl_set_register_16(char *wrptr, u8 reg, u16 value)
81{
82 wrptr = udl_set_register(wrptr, reg, value >> 8);
83 return udl_set_register(wrptr, reg+1, value);
84}
85
86/*
87 * This is kind of weird because the controller takes some
88 * register values in a different byte order than other registers.
89 */
90static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value)
91{
92 wrptr = udl_set_register(wrptr, reg, value);
93 return udl_set_register(wrptr, reg+1, value >> 8);
94}
95
96/*
97 * LFSR is linear feedback shift register. The reason we have this is
98 * because the display controller needs to minimize the clock depth of
99 * various counters used in the display path. So this code reverses the
100 * provided value into the lfsr16 value by counting backwards to get
101 * the value that needs to be set in the hardware comparator to get the
102 * same actual count. This makes sense once you read above a couple of
103 * times and think about it from a hardware perspective.
104 */
105static u16 udl_lfsr16(u16 actual_count)
106{
107 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
108
109 while (actual_count--) {
110 lv = ((lv << 1) |
111 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
112 & 0xFFFF;
113 }
114
115 return (u16) lv;
116}
117
118/*
119 * This does LFSR conversion on the value that is to be written.
120 * See LFSR explanation above for more detail.
121 */
122static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
123{
124 return udl_set_register_16(wrptr, reg, udl_lfsr16(value));
125}
126
127/*
128 * This takes a standard fbdev screeninfo struct and all of its monitor mode
129 * details and converts them into the DisplayLink equivalent register commands.
130 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1));
131 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart));
132 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd));
133 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart));
134 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd));
135 ERR(vreg_lfsr16(dev, 0x09, xEndCount));
136 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart));
137 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd));
138 ERR(vreg_big_endian(dev, 0x0F, hPixels));
139 ERR(vreg_lfsr16(dev, 0x11, yEndCount));
140 ERR(vreg_lfsr16(dev, 0x13, vSyncStart));
141 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd));
142 ERR(vreg_big_endian(dev, 0x17, vPixels));
143 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz));
144
145 ERR(vreg(dev, 0x1F, 0));
146
147 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK)));
148 */
149static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode)
150{
151 u16 xds, yds;
152 u16 xde, yde;
153 u16 yec;
154
155 /* x display start */
156 xds = mode->crtc_htotal - mode->crtc_hsync_start;
157 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds);
158 /* x display end */
159 xde = xds + mode->crtc_hdisplay;
160 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde);
161
162 /* y display start */
163 yds = mode->crtc_vtotal - mode->crtc_vsync_start;
164 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds);
165 /* y display end */
166 yde = yds + mode->crtc_vdisplay;
167 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde);
168
169 /* x end count is active + blanking - 1 */
170 wrptr = udl_set_register_lfsr16(wrptr, 0x09,
171 mode->crtc_htotal - 1);
172
173 /* libdlo hardcodes hsync start to 1 */
174 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1);
175
176 /* hsync end is width of sync pulse + 1 */
177 wrptr = udl_set_register_lfsr16(wrptr, 0x0D,
178 mode->crtc_hsync_end - mode->crtc_hsync_start + 1);
179
180 /* hpixels is active pixels */
181 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay);
182
183 /* yendcount is vertical active + vertical blanking */
184 yec = mode->crtc_vtotal;
185 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec);
186
187 /* libdlo hardcodes vsync start to 0 */
188 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0);
189
190 /* vsync end is width of vsync pulse */
191 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start);
192
193 /* vpixels is active pixels */
194 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay);
195
196 wrptr = udl_set_register_16be(wrptr, 0x1B,
197 mode->clock / 5);
198
199 return wrptr;
200}
201
202static char *udl_dummy_render(char *wrptr)
203{
204 *wrptr++ = 0xAF;
205 *wrptr++ = 0x6A; /* copy */
206 *wrptr++ = 0x00; /* from addr */
207 *wrptr++ = 0x00;
208 *wrptr++ = 0x00;
209 *wrptr++ = 0x01; /* one pixel */
210 *wrptr++ = 0x00; /* to address */
211 *wrptr++ = 0x00;
212 *wrptr++ = 0x00;
213 return wrptr;
214}
215
216static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc)
217{
218 struct drm_device *dev = crtc->dev;
219 struct udl_device *udl = to_udl(dev);
220 struct urb *urb;
221 char *buf;
222 int retval;
223
224 if (udl->mode_buf_len == 0) {
225 DRM_ERROR("No mode set\n");
226 return -EINVAL;
227 }
228
229 urb = udl_get_urb(dev);
230 if (!urb)
231 return -ENOMEM;
232
233 buf = (char *)urb->transfer_buffer;
234
235 memcpy(buf, udl->mode_buf, udl->mode_buf_len);
236 retval = udl_submit_urb(dev, urb, udl->mode_buf_len);
237 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len);
238 return retval;
239}
240
241static long udl_log_cpp(unsigned int cpp)
242{
243 if (WARN_ON(!is_power_of_2(cpp)))
244 return -EINVAL;
245 return __ffs(cpp);
246}
247
248static int udl_aligned_damage_clip(struct drm_rect *clip, int x, int y,
249 int width, int height)
250{
251 int x1, x2;
252
253 if (WARN_ON_ONCE(x < 0) ||
254 WARN_ON_ONCE(y < 0) ||
255 WARN_ON_ONCE(width < 0) ||
256 WARN_ON_ONCE(height < 0))
257 return -EINVAL;
258
259 x1 = ALIGN_DOWN(x, sizeof(unsigned long));
260 x2 = ALIGN(width + (x - x1), sizeof(unsigned long)) + x1;
261
262 clip->x1 = x1;
263 clip->y1 = y;
264 clip->x2 = x2;
265 clip->y2 = y + height;
266
267 return 0;
268}
269
270static int udl_handle_damage(struct drm_framebuffer *fb, const struct dma_buf_map *map,
271 int x, int y, int width, int height)
272{
273 struct drm_device *dev = fb->dev;
274 struct dma_buf_attachment *import_attach = fb->obj[0]->import_attach;
275 void *vaddr = map->vaddr; /* TODO: Use mapping abstraction properly */
276 int i, ret, tmp_ret;
277 char *cmd;
278 struct urb *urb;
279 struct drm_rect clip;
280 int log_bpp;
281
282 ret = udl_log_cpp(fb->format->cpp[0]);
283 if (ret < 0)
284 return ret;
285 log_bpp = ret;
286
287 ret = udl_aligned_damage_clip(&clip, x, y, width, height);
288 if (ret)
289 return ret;
290 else if ((clip.x2 > fb->width) || (clip.y2 > fb->height))
291 return -EINVAL;
292
293 if (import_attach) {
294 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
295 DMA_FROM_DEVICE);
296 if (ret)
297 return ret;
298 }
299
300 urb = udl_get_urb(dev);
301 if (!urb) {
302 ret = -ENOMEM;
303 goto out_dma_buf_end_cpu_access;
304 }
305 cmd = urb->transfer_buffer;
306
307 for (i = clip.y1; i < clip.y2; i++) {
308 const int line_offset = fb->pitches[0] * i;
309 const int byte_offset = line_offset + (clip.x1 << log_bpp);
310 const int dev_byte_offset = (fb->width * i + clip.x1) << log_bpp;
311 const int byte_width = (clip.x2 - clip.x1) << log_bpp;
312 ret = udl_render_hline(dev, log_bpp, &urb, (char *)vaddr,
313 &cmd, byte_offset, dev_byte_offset,
314 byte_width);
315 if (ret)
316 goto out_dma_buf_end_cpu_access;
317 }
318
319 if (cmd > (char *)urb->transfer_buffer) {
320 /* Send partial buffer remaining before exiting */
321 int len;
322 if (cmd < (char *)urb->transfer_buffer + urb->transfer_buffer_length)
323 *cmd++ = 0xAF;
324 len = cmd - (char *)urb->transfer_buffer;
325 ret = udl_submit_urb(dev, urb, len);
326 } else {
327 udl_urb_completion(urb);
328 }
329
330 ret = 0;
331
332out_dma_buf_end_cpu_access:
333 if (import_attach) {
334 tmp_ret = dma_buf_end_cpu_access(import_attach->dmabuf,
335 DMA_FROM_DEVICE);
336 if (tmp_ret && !ret)
337 ret = tmp_ret; /* only update ret if not set yet */
338 }
339
340 return ret;
341}
342
343/*
344 * Simple display pipeline
345 */
346
347static const uint32_t udl_simple_display_pipe_formats[] = {
348 DRM_FORMAT_RGB565,
349 DRM_FORMAT_XRGB8888,
350};
351
352static enum drm_mode_status
353udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe,
354 const struct drm_display_mode *mode)
355{
356 return MODE_OK;
357}
358
359static void
360udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe,
361 struct drm_crtc_state *crtc_state,
362 struct drm_plane_state *plane_state)
363{
364 struct drm_crtc *crtc = &pipe->crtc;
365 struct drm_device *dev = crtc->dev;
366 struct drm_framebuffer *fb = plane_state->fb;
367 struct udl_device *udl = to_udl(dev);
368 struct drm_display_mode *mode = &crtc_state->mode;
369 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
370 char *buf;
371 char *wrptr;
372 int color_depth = UDL_COLOR_DEPTH_16BPP;
373
374 buf = (char *)udl->mode_buf;
375
376 /* This first section has to do with setting the base address on the
377 * controller associated with the display. There are 2 base
378 * pointers, currently, we only use the 16 bpp segment.
379 */
380 wrptr = udl_vidreg_lock(buf);
381 wrptr = udl_set_color_depth(wrptr, color_depth);
382 /* set base for 16bpp segment to 0 */
383 wrptr = udl_set_base16bpp(wrptr, 0);
384 /* set base for 8bpp segment to end of fb */
385 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay);
386
387 wrptr = udl_set_vid_cmds(wrptr, mode);
388 wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON);
389 wrptr = udl_vidreg_unlock(wrptr);
390
391 wrptr = udl_dummy_render(wrptr);
392
393 udl->mode_buf_len = wrptr - buf;
394
395 udl_handle_damage(fb, &shadow_plane_state->map[0], 0, 0, fb->width, fb->height);
396
397 if (!crtc_state->mode_changed)
398 return;
399
400 /* enable display */
401 udl_crtc_write_mode_to_hw(crtc);
402}
403
404static void
405udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe)
406{
407 struct drm_crtc *crtc = &pipe->crtc;
408 struct drm_device *dev = crtc->dev;
409 struct urb *urb;
410 char *buf;
411
412 urb = udl_get_urb(dev);
413 if (!urb)
414 return;
415
416 buf = (char *)urb->transfer_buffer;
417 buf = udl_vidreg_lock(buf);
418 buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN);
419 buf = udl_vidreg_unlock(buf);
420 buf = udl_dummy_render(buf);
421
422 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer);
423}
424
425static void
426udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe,
427 struct drm_plane_state *old_plane_state)
428{
429 struct drm_plane_state *state = pipe->plane.state;
430 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
431 struct drm_framebuffer *fb = state->fb;
432 struct drm_rect rect;
433
434 if (!fb)
435 return;
436
437 if (drm_atomic_helper_damage_merged(old_plane_state, state, &rect))
438 udl_handle_damage(fb, &shadow_plane_state->map[0], rect.x1, rect.y1,
439 rect.x2 - rect.x1, rect.y2 - rect.y1);
440}
441
442static const struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = {
443 .mode_valid = udl_simple_display_pipe_mode_valid,
444 .enable = udl_simple_display_pipe_enable,
445 .disable = udl_simple_display_pipe_disable,
446 .update = udl_simple_display_pipe_update,
447 DRM_GEM_SIMPLE_DISPLAY_PIPE_SHADOW_PLANE_FUNCS,
448};
449
450/*
451 * Modesetting
452 */
453
454static const struct drm_mode_config_funcs udl_mode_funcs = {
455 .fb_create = drm_gem_fb_create_with_dirty,
456 .atomic_check = drm_atomic_helper_check,
457 .atomic_commit = drm_atomic_helper_commit,
458};
459
460int udl_modeset_init(struct drm_device *dev)
461{
462 size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
463 struct udl_device *udl = to_udl(dev);
464 struct drm_connector *connector;
465 int ret;
466
467 ret = drmm_mode_config_init(dev);
468 if (ret)
469 return ret;
470
471 dev->mode_config.min_width = 640;
472 dev->mode_config.min_height = 480;
473
474 dev->mode_config.max_width = 2048;
475 dev->mode_config.max_height = 2048;
476
477 dev->mode_config.prefer_shadow = 0;
478 dev->mode_config.preferred_depth = 16;
479
480 dev->mode_config.funcs = &udl_mode_funcs;
481
482 connector = udl_connector_init(dev);
483 if (IS_ERR(connector))
484 return PTR_ERR(connector);
485
486 format_count = ARRAY_SIZE(udl_simple_display_pipe_formats);
487
488 ret = drm_simple_display_pipe_init(dev, &udl->display_pipe,
489 &udl_simple_display_pipe_funcs,
490 udl_simple_display_pipe_formats,
491 format_count, NULL, connector);
492 if (ret)
493 return ret;
494
495 drm_mode_config_reset(dev);
496
497 return 0;
498}