1/*
  2 * Copyright 2010 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs
 23 */
 24
 25#include "drmP.h"
 26#include "nouveau_drv.h"
 27#include "nouveau_hw.h"
 28
 29#include "nv50_display.h"
 30
 31static void nv50_gpio_isr(struct drm_device *dev);
 32static void nv50_gpio_isr_bh(struct work_struct *work);
 33
 34struct nv50_gpio_priv {
 35	struct list_head handlers;
 36	spinlock_t lock;
 37};
 38
 39struct nv50_gpio_handler {
 40	struct drm_device *dev;
 41	struct list_head head;
 42	struct work_struct work;
 43	bool inhibit;
 44
 45	struct dcb_gpio_entry *gpio;
 46
 47	void (*handler)(void *data, int state);
 48	void *data;
 49};
 50
 51static int
 52nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
 53{
 54	const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
 55
 56	if (gpio->line >= 32)
 57		return -EINVAL;
 58
 59	*reg = nv50_gpio_reg[gpio->line >> 3];
 60	*shift = (gpio->line & 7) << 2;
 61	return 0;
 62}
 63
 64int
 65nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
 66{
 67	struct dcb_gpio_entry *gpio;
 68	uint32_t r, s, v;
 69
 70	gpio = nouveau_bios_gpio_entry(dev, tag);
 71	if (!gpio)
 72		return -ENOENT;
 73
 74	if (nv50_gpio_location(gpio, &r, &s))
 75		return -EINVAL;
 76
 77	v = nv_rd32(dev, r) >> (s + 2);
 78	return ((v & 1) == (gpio->state[1] & 1));
 79}
 80
 81int
 82nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
 83{
 84	struct dcb_gpio_entry *gpio;
 85	uint32_t r, s, v;
 86
 87	gpio = nouveau_bios_gpio_entry(dev, tag);
 88	if (!gpio)
 89		return -ENOENT;
 90
 91	if (nv50_gpio_location(gpio, &r, &s))
 92		return -EINVAL;
 93
 94	v  = nv_rd32(dev, r) & ~(0x3 << s);
 95	v |= (gpio->state[state] ^ 2) << s;
 96	nv_wr32(dev, r, v);
 97	return 0;
 98}
 99
100int
101nv50_gpio_irq_register(struct drm_device *dev, enum dcb_gpio_tag tag,
102		       void (*handler)(void *, int), void *data)
103{
104	struct drm_nouveau_private *dev_priv = dev->dev_private;
105	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
106	struct nv50_gpio_priv *priv = pgpio->priv;
107	struct nv50_gpio_handler *gpioh;
108	struct dcb_gpio_entry *gpio;
109	unsigned long flags;
110
111	gpio = nouveau_bios_gpio_entry(dev, tag);
112	if (!gpio)
113		return -ENOENT;
114
115	gpioh = kzalloc(sizeof(*gpioh), GFP_KERNEL);
116	if (!gpioh)
117		return -ENOMEM;
118
119	INIT_WORK(&gpioh->work, nv50_gpio_isr_bh);
120	gpioh->dev  = dev;
121	gpioh->gpio = gpio;
122	gpioh->handler = handler;
123	gpioh->data = data;
124
125	spin_lock_irqsave(&priv->lock, flags);
126	list_add(&gpioh->head, &priv->handlers);
127	spin_unlock_irqrestore(&priv->lock, flags);
128	return 0;
129}
130
131void
132nv50_gpio_irq_unregister(struct drm_device *dev, enum dcb_gpio_tag tag,
133			 void (*handler)(void *, int), void *data)
134{
135	struct drm_nouveau_private *dev_priv = dev->dev_private;
136	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
137	struct nv50_gpio_priv *priv = pgpio->priv;
138	struct nv50_gpio_handler *gpioh, *tmp;
139	struct dcb_gpio_entry *gpio;
140	LIST_HEAD(tofree);
141	unsigned long flags;
142
143	gpio = nouveau_bios_gpio_entry(dev, tag);
144	if (!gpio)
145		return;
146
147	spin_lock_irqsave(&priv->lock, flags);
148	list_for_each_entry_safe(gpioh, tmp, &priv->handlers, head) {
149		if (gpioh->gpio != gpio ||
150		    gpioh->handler != handler ||
151		    gpioh->data != data)
152			continue;
153		list_move(&gpioh->head, &tofree);
154	}
155	spin_unlock_irqrestore(&priv->lock, flags);
156
157	list_for_each_entry_safe(gpioh, tmp, &tofree, head) {
158		flush_work_sync(&gpioh->work);
159		kfree(gpioh);
160	}
161}
162
163bool
164nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
165{
166	struct dcb_gpio_entry *gpio;
167	u32 reg, mask;
168
169	gpio = nouveau_bios_gpio_entry(dev, tag);
170	if (!gpio)
171		return false;
172
173	reg  = gpio->line < 16 ? 0xe050 : 0xe070;
174	mask = 0x00010001 << (gpio->line & 0xf);
175
176	nv_wr32(dev, reg + 4, mask);
177	reg = nv_mask(dev, reg + 0, mask, on ? mask : 0);
178	return (reg & mask) == mask;
179}
180
181static int
182nv50_gpio_create(struct drm_device *dev)
183{
184	struct drm_nouveau_private *dev_priv = dev->dev_private;
185	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
186	struct nv50_gpio_priv *priv;
187
188	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
189	if (!priv)
190		return -ENOMEM;
191
192	INIT_LIST_HEAD(&priv->handlers);
193	spin_lock_init(&priv->lock);
194	pgpio->priv = priv;
195	return 0;
196}
197
198static void
199nv50_gpio_destroy(struct drm_device *dev)
200{
201	struct drm_nouveau_private *dev_priv = dev->dev_private;
202	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
203
204	kfree(pgpio->priv);
205	pgpio->priv = NULL;
206}
207
208int
209nv50_gpio_init(struct drm_device *dev)
210{
211	struct drm_nouveau_private *dev_priv = dev->dev_private;
212	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
213	int ret;
214
215	if (!pgpio->priv) {
216		ret = nv50_gpio_create(dev);
217		if (ret)
218			return ret;
219	}
220
221	/* disable, and ack any pending gpio interrupts */
222	nv_wr32(dev, 0xe050, 0x00000000);
223	nv_wr32(dev, 0xe054, 0xffffffff);
224	if (dev_priv->chipset >= 0x90) {
225		nv_wr32(dev, 0xe070, 0x00000000);
226		nv_wr32(dev, 0xe074, 0xffffffff);
227	}
228
229	nouveau_irq_register(dev, 21, nv50_gpio_isr);
230	return 0;
231}
232
233void
234nv50_gpio_fini(struct drm_device *dev)
235{
236	struct drm_nouveau_private *dev_priv = dev->dev_private;
237
238	nv_wr32(dev, 0xe050, 0x00000000);
239	if (dev_priv->chipset >= 0x90)
240		nv_wr32(dev, 0xe070, 0x00000000);
241	nouveau_irq_unregister(dev, 21);
242
243	nv50_gpio_destroy(dev);
244}
245
246static void
247nv50_gpio_isr_bh(struct work_struct *work)
248{
249	struct nv50_gpio_handler *gpioh =
250		container_of(work, struct nv50_gpio_handler, work);
251	struct drm_nouveau_private *dev_priv = gpioh->dev->dev_private;
252	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
253	struct nv50_gpio_priv *priv = pgpio->priv;
254	unsigned long flags;
255	int state;
256
257	state = pgpio->get(gpioh->dev, gpioh->gpio->tag);
258	if (state < 0)
259		return;
260
261	gpioh->handler(gpioh->data, state);
262
263	spin_lock_irqsave(&priv->lock, flags);
264	gpioh->inhibit = false;
265	spin_unlock_irqrestore(&priv->lock, flags);
266}
267
268static void
269nv50_gpio_isr(struct drm_device *dev)
270{
271	struct drm_nouveau_private *dev_priv = dev->dev_private;
272	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
273	struct nv50_gpio_priv *priv = pgpio->priv;
274	struct nv50_gpio_handler *gpioh;
275	u32 intr0, intr1 = 0;
276	u32 hi, lo, ch;
277
278	intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
279	if (dev_priv->chipset >= 0x90)
280		intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
281
282	hi = (intr0 & 0x0000ffff) | (intr1 << 16);
283	lo = (intr0 >> 16) | (intr1 & 0xffff0000);
284	ch = hi | lo;
285
286	nv_wr32(dev, 0xe054, intr0);
287	if (dev_priv->chipset >= 0x90)
288		nv_wr32(dev, 0xe074, intr1);
289
290	spin_lock(&priv->lock);
291	list_for_each_entry(gpioh, &priv->handlers, head) {
292		if (!(ch & (1 << gpioh->gpio->line)))
293			continue;
294
295		if (gpioh->inhibit)
296			continue;
297		gpioh->inhibit = true;
298
299		schedule_work(&gpioh->work);
300	}
301	spin_unlock(&priv->lock);
302}