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1/*
2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27#include "drmP.h"
28#include "drm_crtc_helper.h"
29
30#include "nouveau_drv.h"
31#include "nouveau_encoder.h"
32#include "nouveau_connector.h"
33#include "nouveau_crtc.h"
34#include "nouveau_hw.h"
35#include "nvreg.h"
36
37#include "i2c/sil164.h"
38
39#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
40 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
41 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
42#define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \
43 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
44 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
45
46static inline bool is_fpc_off(uint32_t fpc)
47{
48 return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
49 FP_TG_CONTROL_OFF);
50}
51
52int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent)
53{
54 /* special case of nv_read_tmds to find crtc associated with an output.
55 * this does not give a correct answer for off-chip dvi, but there's no
56 * use for such an answer anyway
57 */
58 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
59
60 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
61 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
62 return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
63}
64
65void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
66 int head, bool dl)
67{
68 /* The BIOS scripts don't do this for us, sadly
69 * Luckily we do know the values ;-)
70 *
71 * head < 0 indicates we wish to force a setting with the overrideval
72 * (for VT restore etc.)
73 */
74
75 int ramdac = (dcbent->or & OUTPUT_C) >> 2;
76 uint8_t tmds04 = 0x80;
77
78 if (head != ramdac)
79 tmds04 = 0x88;
80
81 if (dcbent->type == OUTPUT_LVDS)
82 tmds04 |= 0x01;
83
84 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
85
86 if (dl) /* dual link */
87 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
88}
89
90void nv04_dfp_disable(struct drm_device *dev, int head)
91{
92 struct drm_nouveau_private *dev_priv = dev->dev_private;
93 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
94
95 if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
96 FP_TG_CONTROL_ON) {
97 /* digital remnants must be cleaned before new crtc
98 * values programmed. delay is time for the vga stuff
99 * to realise it's in control again
100 */
101 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
102 FP_TG_CONTROL_OFF);
103 msleep(50);
104 }
105 /* don't inadvertently turn it on when state written later */
106 crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
107 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
108 ~NV_CIO_CRE_LCD_ROUTE_MASK;
109}
110
111void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
112{
113 struct drm_device *dev = encoder->dev;
114 struct drm_nouveau_private *dev_priv = dev->dev_private;
115 struct drm_crtc *crtc;
116 struct nouveau_crtc *nv_crtc;
117 uint32_t *fpc;
118
119 if (mode == DRM_MODE_DPMS_ON) {
120 nv_crtc = nouveau_crtc(encoder->crtc);
121 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
122
123 if (is_fpc_off(*fpc)) {
124 /* using saved value is ok, as (is_digital && dpms_on &&
125 * fp_control==OFF) is (at present) *only* true when
126 * fpc's most recent change was by below "off" code
127 */
128 *fpc = nv_crtc->dpms_saved_fp_control;
129 }
130
131 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
132 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
133 } else {
134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
135 nv_crtc = nouveau_crtc(crtc);
136 fpc = &dev_priv->mode_reg.crtc_reg[nv_crtc->index].fp_control;
137
138 nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
139 if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
140 nv_crtc->dpms_saved_fp_control = *fpc;
141 /* cut the FP output */
142 *fpc &= ~FP_TG_CONTROL_ON;
143 *fpc |= FP_TG_CONTROL_OFF;
144 NVWriteRAMDAC(dev, nv_crtc->index,
145 NV_PRAMDAC_FP_TG_CONTROL, *fpc);
146 }
147 }
148 }
149}
150
151static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
152{
153 struct drm_device *dev = encoder->dev;
154 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
155 struct drm_encoder *slave;
156
157 if (dcb->type != OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
158 return NULL;
159
160 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
161 * TMDS transmitters at the same I2C address, in the same I2C
162 * bus. This can still work because in that case one of them is
163 * always hard-wired to a reasonable configuration using straps,
164 * and the other one needs to be programmed.
165 *
166 * I don't think there's a way to know which is which, even the
167 * blob programs the one exposed via I2C for *both* heads, so
168 * let's do the same.
169 */
170 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
171 struct dcb_entry *slave_dcb = nouveau_encoder(slave)->dcb;
172
173 if (slave_dcb->type == OUTPUT_TMDS && get_slave_funcs(slave) &&
174 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
175 return slave;
176 }
177
178 return NULL;
179}
180
181static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
182 struct drm_display_mode *mode,
183 struct drm_display_mode *adjusted_mode)
184{
185 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
186 struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
187
188 if (!nv_connector->native_mode ||
189 nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
190 mode->hdisplay > nv_connector->native_mode->hdisplay ||
191 mode->vdisplay > nv_connector->native_mode->vdisplay) {
192 nv_encoder->mode = *adjusted_mode;
193
194 } else {
195 nv_encoder->mode = *nv_connector->native_mode;
196 adjusted_mode->clock = nv_connector->native_mode->clock;
197 }
198
199 return true;
200}
201
202static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
203 struct nouveau_encoder *nv_encoder, int head)
204{
205 struct drm_nouveau_private *dev_priv = dev->dev_private;
206 struct nv04_mode_state *state = &dev_priv->mode_reg;
207 uint32_t bits1618 = nv_encoder->dcb->or & OUTPUT_A ? 0x10000 : 0x40000;
208
209 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
210 return;
211
212 /* SEL_CLK is only used on the primary ramdac
213 * It toggles spread spectrum PLL output and sets the bindings of PLLs
214 * to heads on digital outputs
215 */
216 if (head)
217 state->sel_clk |= bits1618;
218 else
219 state->sel_clk &= ~bits1618;
220
221 /* nv30:
222 * bit 0 NVClk spread spectrum on/off
223 * bit 2 MemClk spread spectrum on/off
224 * bit 4 PixClk1 spread spectrum on/off toggle
225 * bit 6 PixClk2 spread spectrum on/off toggle
226 *
227 * nv40 (observations from bios behaviour and mmio traces):
228 * bits 4&6 as for nv30
229 * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
230 * maybe a different spread mode
231 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
232 * The logic behind turning spread spectrum on/off in the first place,
233 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
234 * entry has the necessary info)
235 */
236 if (nv_encoder->dcb->type == OUTPUT_LVDS && dev_priv->saved_reg.sel_clk & 0xf0) {
237 int shift = (dev_priv->saved_reg.sel_clk & 0x50) ? 0 : 1;
238
239 state->sel_clk &= ~0xf0;
240 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
241 }
242}
243
244static void nv04_dfp_prepare(struct drm_encoder *encoder)
245{
246 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
247 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
248 struct drm_device *dev = encoder->dev;
249 struct drm_nouveau_private *dev_priv = dev->dev_private;
250 int head = nouveau_crtc(encoder->crtc)->index;
251 struct nv04_crtc_reg *crtcstate = dev_priv->mode_reg.crtc_reg;
252 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
253 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
254
255 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
256
257 nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
258
259 *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
260
261 if (nv_two_heads(dev)) {
262 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
263 *cr_lcd |= head ? 0x0 : 0x8;
264 else {
265 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
266 if (nv_encoder->dcb->type == OUTPUT_LVDS)
267 *cr_lcd |= 0x30;
268 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
269 /* avoid being connected to both crtcs */
270 *cr_lcd_oth &= ~0x30;
271 NVWriteVgaCrtc(dev, head ^ 1,
272 NV_CIO_CRE_LCD__INDEX,
273 *cr_lcd_oth);
274 }
275 }
276 }
277}
278
279
280static void nv04_dfp_mode_set(struct drm_encoder *encoder,
281 struct drm_display_mode *mode,
282 struct drm_display_mode *adjusted_mode)
283{
284 struct drm_device *dev = encoder->dev;
285 struct drm_nouveau_private *dev_priv = dev->dev_private;
286 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
287 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
288 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
289 struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
290 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
291 struct drm_display_mode *output_mode = &nv_encoder->mode;
292 uint32_t mode_ratio, panel_ratio;
293
294 NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index);
295 drm_mode_debug_printmodeline(output_mode);
296
297 /* Initialize the FP registers in this CRTC. */
298 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
299 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
300 if (!nv_gf4_disp_arch(dev) ||
301 (output_mode->hsync_start - output_mode->hdisplay) >=
302 dev_priv->vbios.digital_min_front_porch)
303 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
304 else
305 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
306 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
307 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
308 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
309 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
310
311 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
312 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
313 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
314 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
315 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
316 regp->fp_vert_regs[FP_VALID_START] = 0;
317 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
318
319 /* bit26: a bit seen on some g7x, no as yet discernable purpose */
320 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
321 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
322 /* Deal with vsync/hsync polarity */
323 /* LVDS screens do set this, but modes with +ve syncs are very rare */
324 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
325 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
326 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
327 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
328 /* panel scaling first, as native would get set otherwise */
329 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
330 nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */
331 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
332 else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
333 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
334 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
335 else /* gpu needs to scale */
336 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
337 if (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
338 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
339 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
340 output_mode->clock > 165000)
341 regp->fp_control |= (2 << 24);
342 if (nv_encoder->dcb->type == OUTPUT_LVDS) {
343 bool duallink, dummy;
344
345 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
346 &duallink, &dummy);
347 if (duallink)
348 regp->fp_control |= (8 << 28);
349 } else
350 if (output_mode->clock > 165000)
351 regp->fp_control |= (8 << 28);
352
353 regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
354 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
355 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
356 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
357 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
358 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
359 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
360
361 /* We want automatic scaling */
362 regp->fp_debug_1 = 0;
363 /* This can override HTOTAL and VTOTAL */
364 regp->fp_debug_2 = 0;
365
366 /* Use 20.12 fixed point format to avoid floats */
367 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
368 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
369 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
370 * get treated the same as SCALE_FULLSCREEN */
371 if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
372 mode_ratio != panel_ratio) {
373 uint32_t diff, scale;
374 bool divide_by_2 = nv_gf4_disp_arch(dev);
375
376 if (mode_ratio < panel_ratio) {
377 /* vertical needs to expand to glass size (automatic)
378 * horizontal needs to be scaled at vertical scale factor
379 * to maintain aspect */
380
381 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
382 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
383 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
384
385 /* restrict area of screen used, horizontally */
386 diff = output_mode->hdisplay -
387 output_mode->vdisplay * mode_ratio / (1 << 12);
388 regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
389 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
390 }
391
392 if (mode_ratio > panel_ratio) {
393 /* horizontal needs to expand to glass size (automatic)
394 * vertical needs to be scaled at horizontal scale factor
395 * to maintain aspect */
396
397 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
398 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
399 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
400
401 /* restrict area of screen used, vertically */
402 diff = output_mode->vdisplay -
403 (1 << 12) * output_mode->hdisplay / mode_ratio;
404 regp->fp_vert_regs[FP_VALID_START] += diff / 2;
405 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
406 }
407 }
408
409 /* Output property. */
410 if (nv_connector->use_dithering) {
411 if (dev_priv->chipset == 0x11)
412 regp->dither = savep->dither | 0x00010000;
413 else {
414 int i;
415 regp->dither = savep->dither | 0x00000001;
416 for (i = 0; i < 3; i++) {
417 regp->dither_regs[i] = 0xe4e4e4e4;
418 regp->dither_regs[i + 3] = 0x44444444;
419 }
420 }
421 } else {
422 if (dev_priv->chipset != 0x11) {
423 /* reset them */
424 int i;
425 for (i = 0; i < 3; i++) {
426 regp->dither_regs[i] = savep->dither_regs[i];
427 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
428 }
429 }
430 regp->dither = savep->dither;
431 }
432
433 regp->fp_margin_color = 0;
434}
435
436static void nv04_dfp_commit(struct drm_encoder *encoder)
437{
438 struct drm_device *dev = encoder->dev;
439 struct drm_nouveau_private *dev_priv = dev->dev_private;
440 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
441 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
442 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
443 struct dcb_entry *dcbe = nv_encoder->dcb;
444 int head = nouveau_crtc(encoder->crtc)->index;
445 struct drm_encoder *slave_encoder;
446
447 if (dcbe->type == OUTPUT_TMDS)
448 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
449 else if (dcbe->type == OUTPUT_LVDS)
450 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
451
452 /* update fp_control state for any changes made by scripts,
453 * so correct value is written at DPMS on */
454 dev_priv->mode_reg.crtc_reg[head].fp_control =
455 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
456
457 /* This could use refinement for flatpanels, but it should work this way */
458 if (dev_priv->chipset < 0x44)
459 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
460 else
461 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
462
463 /* Init external transmitters */
464 slave_encoder = get_tmds_slave(encoder);
465 if (slave_encoder)
466 get_slave_funcs(slave_encoder)->mode_set(
467 slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
468
469 helper->dpms(encoder, DRM_MODE_DPMS_ON);
470
471 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
472 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
473 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
474}
475
476static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
477{
478#ifdef __powerpc__
479 struct drm_device *dev = encoder->dev;
480
481 /* BIOS scripts usually take care of the backlight, thanks
482 * Apple for your consistency.
483 */
484 if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
485 dev->pci_device == 0x0329) {
486 if (mode == DRM_MODE_DPMS_ON) {
487 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31);
488 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 1);
489 } else {
490 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
491 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 0);
492 }
493 }
494#endif
495}
496
497static inline bool is_powersaving_dpms(int mode)
498{
499 return (mode != DRM_MODE_DPMS_ON);
500}
501
502static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
503{
504 struct drm_device *dev = encoder->dev;
505 struct drm_crtc *crtc = encoder->crtc;
506 struct drm_nouveau_private *dev_priv = dev->dev_private;
507 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
508 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
509
510 if (nv_encoder->last_dpms == mode)
511 return;
512 nv_encoder->last_dpms = mode;
513
514 NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n",
515 mode, nv_encoder->dcb->index);
516
517 if (was_powersaving && is_powersaving_dpms(mode))
518 return;
519
520 if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
521 /* when removing an output, crtc may not be set, but PANEL_OFF
522 * must still be run
523 */
524 int head = crtc ? nouveau_crtc(crtc)->index :
525 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
526
527 if (mode == DRM_MODE_DPMS_ON) {
528 call_lvds_script(dev, nv_encoder->dcb, head,
529 LVDS_PANEL_ON, nv_encoder->mode.clock);
530 } else
531 /* pxclk of 0 is fine for PANEL_OFF, and for a
532 * disconnected LVDS encoder there is no native_mode
533 */
534 call_lvds_script(dev, nv_encoder->dcb, head,
535 LVDS_PANEL_OFF, 0);
536 }
537
538 nv04_dfp_update_backlight(encoder, mode);
539 nv04_dfp_update_fp_control(encoder, mode);
540
541 if (mode == DRM_MODE_DPMS_ON)
542 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
543 else {
544 dev_priv->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
545 dev_priv->mode_reg.sel_clk &= ~0xf0;
546 }
547 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
548}
549
550static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
551{
552 struct drm_device *dev = encoder->dev;
553 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
554
555 if (nv_encoder->last_dpms == mode)
556 return;
557 nv_encoder->last_dpms = mode;
558
559 NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
560 mode, nv_encoder->dcb->index);
561
562 nv04_dfp_update_backlight(encoder, mode);
563 nv04_dfp_update_fp_control(encoder, mode);
564}
565
566static void nv04_dfp_save(struct drm_encoder *encoder)
567{
568 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
569 struct drm_device *dev = encoder->dev;
570
571 if (nv_two_heads(dev))
572 nv_encoder->restore.head =
573 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
574}
575
576static void nv04_dfp_restore(struct drm_encoder *encoder)
577{
578 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
579 struct drm_device *dev = encoder->dev;
580 struct drm_nouveau_private *dev_priv = dev->dev_private;
581 int head = nv_encoder->restore.head;
582
583 if (nv_encoder->dcb->type == OUTPUT_LVDS) {
584 struct nouveau_connector *connector =
585 nouveau_encoder_connector_get(nv_encoder);
586
587 if (connector && connector->native_mode)
588 call_lvds_script(dev, nv_encoder->dcb, head,
589 LVDS_PANEL_ON,
590 connector->native_mode->clock);
591
592 } else if (nv_encoder->dcb->type == OUTPUT_TMDS) {
593 int clock = nouveau_hw_pllvals_to_clk
594 (&dev_priv->saved_reg.crtc_reg[head].pllvals);
595
596 run_tmds_table(dev, nv_encoder->dcb, head, clock);
597 }
598
599 nv_encoder->last_dpms = NV_DPMS_CLEARED;
600}
601
602static void nv04_dfp_destroy(struct drm_encoder *encoder)
603{
604 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
605
606 NV_DEBUG_KMS(encoder->dev, "\n");
607
608 if (get_slave_funcs(encoder))
609 get_slave_funcs(encoder)->destroy(encoder);
610
611 drm_encoder_cleanup(encoder);
612 kfree(nv_encoder);
613}
614
615static void nv04_tmds_slave_init(struct drm_encoder *encoder)
616{
617 struct drm_device *dev = encoder->dev;
618 struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
619 struct nouveau_i2c_chan *i2c = nouveau_i2c_find(dev, 2);
620 struct i2c_board_info info[] = {
621 {
622 .type = "sil164",
623 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
624 .platform_data = &(struct sil164_encoder_params) {
625 SIL164_INPUT_EDGE_RISING
626 }
627 },
628 { }
629 };
630 int type;
631
632 if (!nv_gf4_disp_arch(dev) || !i2c ||
633 get_tmds_slave(encoder))
634 return;
635
636 type = nouveau_i2c_identify(dev, "TMDS transmitter", info, NULL, 2);
637 if (type < 0)
638 return;
639
640 drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
641 &i2c->adapter, &info[type]);
642}
643
644static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
645 .dpms = nv04_lvds_dpms,
646 .save = nv04_dfp_save,
647 .restore = nv04_dfp_restore,
648 .mode_fixup = nv04_dfp_mode_fixup,
649 .prepare = nv04_dfp_prepare,
650 .commit = nv04_dfp_commit,
651 .mode_set = nv04_dfp_mode_set,
652 .detect = NULL,
653};
654
655static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
656 .dpms = nv04_tmds_dpms,
657 .save = nv04_dfp_save,
658 .restore = nv04_dfp_restore,
659 .mode_fixup = nv04_dfp_mode_fixup,
660 .prepare = nv04_dfp_prepare,
661 .commit = nv04_dfp_commit,
662 .mode_set = nv04_dfp_mode_set,
663 .detect = NULL,
664};
665
666static const struct drm_encoder_funcs nv04_dfp_funcs = {
667 .destroy = nv04_dfp_destroy,
668};
669
670int
671nv04_dfp_create(struct drm_connector *connector, struct dcb_entry *entry)
672{
673 const struct drm_encoder_helper_funcs *helper;
674 struct nouveau_encoder *nv_encoder = NULL;
675 struct drm_encoder *encoder;
676 int type;
677
678 switch (entry->type) {
679 case OUTPUT_TMDS:
680 type = DRM_MODE_ENCODER_TMDS;
681 helper = &nv04_tmds_helper_funcs;
682 break;
683 case OUTPUT_LVDS:
684 type = DRM_MODE_ENCODER_LVDS;
685 helper = &nv04_lvds_helper_funcs;
686 break;
687 default:
688 return -EINVAL;
689 }
690
691 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
692 if (!nv_encoder)
693 return -ENOMEM;
694
695 encoder = to_drm_encoder(nv_encoder);
696
697 nv_encoder->dcb = entry;
698 nv_encoder->or = ffs(entry->or) - 1;
699
700 drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type);
701 drm_encoder_helper_add(encoder, helper);
702
703 encoder->possible_crtcs = entry->heads;
704 encoder->possible_clones = 0;
705
706 if (entry->type == OUTPUT_TMDS &&
707 entry->location != DCB_LOC_ON_CHIP)
708 nv04_tmds_slave_init(encoder);
709
710 drm_mode_connector_attach_encoder(connector, encoder);
711 return 0;
712}