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1/*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include "head.h"
23#include "base.h"
24#include "core.h"
25#include "curs.h"
26#include "ovly.h"
27#include "crc.h"
28
29#include <nvif/class.h>
30#include <nvif/event.h>
31#include <nvif/cl0046.h>
32
33#include <drm/drm_atomic.h>
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_vblank.h>
37#include "nouveau_connector.h"
38
39void
40nv50_head_flush_clr(struct nv50_head *head,
41 struct nv50_head_atom *asyh, bool flush)
42{
43 union nv50_head_atom_mask clr = {
44 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
45 };
46 if (clr.crc) nv50_crc_atomic_clr(head);
47 if (clr.olut) head->func->olut_clr(head);
48 if (clr.core) head->func->core_clr(head);
49 if (clr.curs) head->func->curs_clr(head);
50}
51
52void
53nv50_head_flush_set_wndw(struct nv50_head *head, struct nv50_head_atom *asyh)
54{
55 if (asyh->set.curs ) head->func->curs_set(head, asyh);
56 if (asyh->set.olut ) {
57 asyh->olut.offset = nv50_lut_load(&head->olut,
58 asyh->olut.buffer,
59 asyh->state.gamma_lut,
60 asyh->olut.load);
61 head->func->olut_set(head, asyh);
62 }
63}
64
65void
66nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
67{
68 if (asyh->set.view ) head->func->view (head, asyh);
69 if (asyh->set.mode ) head->func->mode (head, asyh);
70 if (asyh->set.core ) head->func->core_set(head, asyh);
71 if (asyh->set.base ) head->func->base (head, asyh);
72 if (asyh->set.ovly ) head->func->ovly (head, asyh);
73 if (asyh->set.dither ) head->func->dither (head, asyh);
74 if (asyh->set.procamp) head->func->procamp (head, asyh);
75 if (asyh->set.crc ) nv50_crc_atomic_set (head, asyh);
76 if (asyh->set.or ) head->func->or (head, asyh);
77}
78
79static void
80nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
81 struct nv50_head_atom *asyh,
82 struct nouveau_conn_atom *asyc)
83{
84 const int vib = asyc->procamp.color_vibrance - 100;
85 const int hue = asyc->procamp.vibrant_hue - 90;
86 const int adj = (vib > 0) ? 50 : 0;
87 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
88 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
89 asyh->set.procamp = true;
90}
91
92static void
93nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
94 struct nv50_head_atom *asyh,
95 struct nouveau_conn_atom *asyc)
96{
97 u32 mode = 0x00;
98
99 if (asyc->dither.mode) {
100 if (asyc->dither.mode == DITHERING_MODE_AUTO) {
101 if (asyh->base.depth > asyh->or.bpc * 3)
102 mode = DITHERING_MODE_DYNAMIC2X2;
103 } else {
104 mode = asyc->dither.mode;
105 }
106
107 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
108 if (asyh->or.bpc >= 8)
109 mode |= DITHERING_DEPTH_8BPC;
110 } else {
111 mode |= asyc->dither.depth;
112 }
113 }
114
115 asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);
116 asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);
117 asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);
118 asyh->set.dither = true;
119}
120
121static void
122nv50_head_atomic_check_view(struct nv50_head_atom *armh,
123 struct nv50_head_atom *asyh,
124 struct nouveau_conn_atom *asyc)
125{
126 struct drm_connector *connector = asyc->state.connector;
127 struct drm_display_mode *omode = &asyh->state.adjusted_mode;
128 struct drm_display_mode *umode = &asyh->state.mode;
129 int mode = asyc->scaler.mode;
130 struct edid *edid;
131 int umode_vdisplay, omode_hdisplay, omode_vdisplay;
132
133 if (connector->edid_blob_ptr)
134 edid = (struct edid *)connector->edid_blob_ptr->data;
135 else
136 edid = NULL;
137
138 if (!asyc->scaler.full) {
139 if (mode == DRM_MODE_SCALE_NONE)
140 omode = umode;
141 } else {
142 /* Non-EDID LVDS/eDP mode. */
143 mode = DRM_MODE_SCALE_FULLSCREEN;
144 }
145
146 /* For the user-specified mode, we must ignore doublescan and
147 * the like, but honor frame packing.
148 */
149 umode_vdisplay = umode->vdisplay;
150 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
151 umode_vdisplay += umode->vtotal;
152 asyh->view.iW = umode->hdisplay;
153 asyh->view.iH = umode_vdisplay;
154 /* For the output mode, we can just use the stock helper. */
155 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
156 asyh->view.oW = omode_hdisplay;
157 asyh->view.oH = omode_vdisplay;
158
159 /* Add overscan compensation if necessary, will keep the aspect
160 * ratio the same as the backend mode unless overridden by the
161 * user setting both hborder and vborder properties.
162 */
163 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
164 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
165 drm_detect_hdmi_monitor(edid)))) {
166 u32 bX = asyc->scaler.underscan.hborder;
167 u32 bY = asyc->scaler.underscan.vborder;
168 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
169
170 if (bX) {
171 asyh->view.oW -= (bX * 2);
172 if (bY) asyh->view.oH -= (bY * 2);
173 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
174 } else {
175 asyh->view.oW -= (asyh->view.oW >> 4) + 32;
176 if (bY) asyh->view.oH -= (bY * 2);
177 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
178 }
179 }
180
181 /* Handle CENTER/ASPECT scaling, taking into account the areas
182 * removed already for overscan compensation.
183 */
184 switch (mode) {
185 case DRM_MODE_SCALE_CENTER:
186 /* NOTE: This will cause scaling when the input is
187 * larger than the output.
188 */
189 asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
190 asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
191 break;
192 case DRM_MODE_SCALE_ASPECT:
193 /* Determine whether the scaling should be on width or on
194 * height. This is done by comparing the aspect ratios of the
195 * sizes. If the output AR is larger than input AR, that means
196 * we want to change the width (letterboxed on the
197 * left/right), otherwise on the height (letterboxed on the
198 * top/bottom).
199 *
200 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
201 * screen will have letterboxes on the left/right. However a
202 * 16:9 (1.777) AR image on that same screen will have
203 * letterboxes on the top/bottom.
204 *
205 * inputAR = iW / iH; outputAR = oW / oH
206 * outputAR > inputAR is equivalent to oW * iH > iW * oH
207 */
208 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
209 /* Recompute output width, i.e. left/right letterbox */
210 u32 r = (asyh->view.iW << 19) / asyh->view.iH;
211 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
212 } else {
213 /* Recompute output height, i.e. top/bottom letterbox */
214 u32 r = (asyh->view.iH << 19) / asyh->view.iW;
215 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
216 }
217 break;
218 default:
219 break;
220 }
221
222 asyh->set.view = true;
223}
224
225static int
226nv50_head_atomic_check_lut(struct nv50_head *head,
227 struct nv50_head_atom *asyh)
228{
229 struct nv50_disp *disp = nv50_disp(head->base.base.dev);
230 struct drm_property_blob *olut = asyh->state.gamma_lut;
231 int size;
232
233 /* Determine whether core output LUT should be enabled. */
234 if (olut) {
235 /* Check if any window(s) have stolen the core output LUT
236 * to as an input LUT for legacy gamma + I8 colour format.
237 */
238 if (asyh->wndw.olut) {
239 /* If any window has stolen the core output LUT,
240 * all of them must.
241 */
242 if (asyh->wndw.olut != asyh->wndw.mask)
243 return -EINVAL;
244 olut = NULL;
245 }
246 }
247
248 if (!olut) {
249 if (!head->func->olut_identity) {
250 asyh->olut.handle = 0;
251 return 0;
252 }
253 size = 0;
254 } else {
255 size = drm_color_lut_size(olut);
256 }
257
258 if (!head->func->olut(head, asyh, size)) {
259 DRM_DEBUG_KMS("Invalid olut\n");
260 return -EINVAL;
261 }
262 asyh->olut.handle = disp->core->chan.vram.handle;
263 asyh->olut.buffer = !asyh->olut.buffer;
264
265 return 0;
266}
267
268static void
269nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
270{
271 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
272 struct nv50_head_mode *m = &asyh->mode;
273 u32 blankus;
274
275 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
276
277 /*
278 * DRM modes are defined in terms of a repeating interval
279 * starting with the active display area. The hardware modes
280 * are defined in terms of a repeating interval starting one
281 * unit (pixel or line) into the sync pulse. So, add bias.
282 */
283
284 m->h.active = mode->crtc_htotal;
285 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
286 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
287 m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
288
289 m->v.active = mode->crtc_vtotal;
290 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
291 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
292 m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
293
294 /*XXX: Safe underestimate, even "0" works */
295 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
296 blankus *= 1000;
297 blankus /= mode->crtc_clock;
298 m->v.blankus = blankus;
299
300 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
301 m->v.blank2e = m->v.active + m->v.blanke;
302 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay;
303 m->v.active = (m->v.active * 2) + 1;
304 m->interlace = true;
305 } else {
306 m->v.blank2e = 0;
307 m->v.blank2s = 1;
308 m->interlace = false;
309 }
310 m->clock = mode->crtc_clock;
311
312 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
313 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
314 asyh->set.or = head->func->or != NULL;
315 asyh->set.mode = true;
316}
317
318static int
319nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
320{
321 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
322 crtc);
323 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
324 crtc);
325 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
326 struct nv50_head *head = nv50_head(crtc);
327 struct nv50_head_atom *armh = nv50_head_atom(old_crtc_state);
328 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
329 struct nouveau_conn_atom *asyc = NULL;
330 struct drm_connector_state *conns;
331 struct drm_connector *conn;
332 int i, ret;
333
334 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
335 if (asyh->state.active) {
336 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
337 if (conns->crtc == crtc) {
338 asyc = nouveau_conn_atom(conns);
339 break;
340 }
341 }
342
343 if (armh->state.active) {
344 if (asyc) {
345 if (asyh->state.mode_changed)
346 asyc->set.scaler = true;
347 if (armh->base.depth != asyh->base.depth)
348 asyc->set.dither = true;
349 }
350 } else {
351 if (asyc)
352 asyc->set.mask = ~0;
353 asyh->set.mask = ~0;
354 asyh->set.or = head->func->or != NULL;
355 }
356
357 if (asyh->state.mode_changed || asyh->state.connectors_changed)
358 nv50_head_atomic_check_mode(head, asyh);
359
360 if (asyh->state.color_mgmt_changed ||
361 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) {
362 int ret = nv50_head_atomic_check_lut(head, asyh);
363 if (ret)
364 return ret;
365
366 asyh->olut.visible = asyh->olut.handle != 0;
367 }
368
369 if (asyc) {
370 if (asyc->set.scaler)
371 nv50_head_atomic_check_view(armh, asyh, asyc);
372 if (asyc->set.dither)
373 nv50_head_atomic_check_dither(armh, asyh, asyc);
374 if (asyc->set.procamp)
375 nv50_head_atomic_check_procamp(armh, asyh, asyc);
376 }
377
378 if (head->func->core_calc) {
379 head->func->core_calc(head, asyh);
380 if (!asyh->core.visible)
381 asyh->olut.visible = false;
382 }
383
384 asyh->set.base = armh->base.cpp != asyh->base.cpp;
385 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
386 } else {
387 asyh->olut.visible = false;
388 asyh->core.visible = false;
389 asyh->curs.visible = false;
390 asyh->base.cpp = 0;
391 asyh->ovly.cpp = 0;
392 }
393
394 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
395 if (asyh->core.visible) {
396 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
397 asyh->set.core = true;
398 } else
399 if (armh->core.visible) {
400 asyh->clr.core = true;
401 }
402
403 if (asyh->curs.visible) {
404 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
405 asyh->set.curs = true;
406 } else
407 if (armh->curs.visible) {
408 asyh->clr.curs = true;
409 }
410
411 if (asyh->olut.visible) {
412 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
413 asyh->set.olut = true;
414 } else
415 if (armh->olut.visible) {
416 asyh->clr.olut = true;
417 }
418 } else {
419 asyh->clr.olut = armh->olut.visible;
420 asyh->clr.core = armh->core.visible;
421 asyh->clr.curs = armh->curs.visible;
422 asyh->set.olut = asyh->olut.visible;
423 asyh->set.core = asyh->core.visible;
424 asyh->set.curs = asyh->curs.visible;
425 }
426
427 ret = nv50_crc_atomic_check_head(head, asyh, armh);
428 if (ret)
429 return ret;
430
431 if (asyh->clr.mask || asyh->set.mask)
432 nv50_atom(asyh->state.state)->lock_core = true;
433 return 0;
434}
435
436static const struct drm_crtc_helper_funcs
437nv50_head_help = {
438 .atomic_check = nv50_head_atomic_check,
439 .get_scanout_position = nouveau_display_scanoutpos,
440};
441
442static void
443nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
444 struct drm_crtc_state *state)
445{
446 struct nv50_head_atom *asyh = nv50_head_atom(state);
447 __drm_atomic_helper_crtc_destroy_state(&asyh->state);
448 kfree(asyh);
449}
450
451static struct drm_crtc_state *
452nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
453{
454 struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
455 struct nv50_head_atom *asyh;
456 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
457 return NULL;
458 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
459 asyh->wndw = armh->wndw;
460 asyh->view = armh->view;
461 asyh->mode = armh->mode;
462 asyh->olut = armh->olut;
463 asyh->core = armh->core;
464 asyh->curs = armh->curs;
465 asyh->base = armh->base;
466 asyh->ovly = armh->ovly;
467 asyh->dither = armh->dither;
468 asyh->procamp = armh->procamp;
469 asyh->crc = armh->crc;
470 asyh->or = armh->or;
471 asyh->dp = armh->dp;
472 asyh->clr.mask = 0;
473 asyh->set.mask = 0;
474 return &asyh->state;
475}
476
477static void
478nv50_head_reset(struct drm_crtc *crtc)
479{
480 struct nv50_head_atom *asyh;
481
482 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
483 return;
484
485 if (crtc->state)
486 nv50_head_atomic_destroy_state(crtc, crtc->state);
487
488 __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
489}
490
491static int
492nv50_head_late_register(struct drm_crtc *crtc)
493{
494 return nv50_head_crc_late_register(nv50_head(crtc));
495}
496
497static void
498nv50_head_destroy(struct drm_crtc *crtc)
499{
500 struct nv50_head *head = nv50_head(crtc);
501
502 nvif_notify_dtor(&head->base.vblank);
503 nv50_lut_fini(&head->olut);
504 drm_crtc_cleanup(crtc);
505 kfree(head);
506}
507
508static const struct drm_crtc_funcs
509nv50_head_func = {
510 .reset = nv50_head_reset,
511 .destroy = nv50_head_destroy,
512 .set_config = drm_atomic_helper_set_config,
513 .page_flip = drm_atomic_helper_page_flip,
514 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
515 .atomic_destroy_state = nv50_head_atomic_destroy_state,
516 .enable_vblank = nouveau_display_vblank_enable,
517 .disable_vblank = nouveau_display_vblank_disable,
518 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
519 .late_register = nv50_head_late_register,
520};
521
522static const struct drm_crtc_funcs
523nvd9_head_func = {
524 .reset = nv50_head_reset,
525 .destroy = nv50_head_destroy,
526 .set_config = drm_atomic_helper_set_config,
527 .page_flip = drm_atomic_helper_page_flip,
528 .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
529 .atomic_destroy_state = nv50_head_atomic_destroy_state,
530 .enable_vblank = nouveau_display_vblank_enable,
531 .disable_vblank = nouveau_display_vblank_disable,
532 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
533 .verify_crc_source = nv50_crc_verify_source,
534 .get_crc_sources = nv50_crc_get_sources,
535 .set_crc_source = nv50_crc_set_source,
536 .late_register = nv50_head_late_register,
537};
538
539static int nv50_head_vblank_handler(struct nvif_notify *notify)
540{
541 struct nouveau_crtc *nv_crtc =
542 container_of(notify, struct nouveau_crtc, vblank);
543
544 if (drm_crtc_handle_vblank(&nv_crtc->base))
545 nv50_crc_handle_vblank(nv50_head(&nv_crtc->base));
546
547 return NVIF_NOTIFY_KEEP;
548}
549
550struct nv50_head *
551nv50_head_create(struct drm_device *dev, int index)
552{
553 struct nouveau_drm *drm = nouveau_drm(dev);
554 struct nv50_disp *disp = nv50_disp(dev);
555 struct nv50_head *head;
556 struct nv50_wndw *base, *ovly, *curs;
557 struct nouveau_crtc *nv_crtc;
558 struct drm_crtc *crtc;
559 const struct drm_crtc_funcs *funcs;
560 int ret;
561
562 head = kzalloc(sizeof(*head), GFP_KERNEL);
563 if (!head)
564 return ERR_PTR(-ENOMEM);
565
566 head->func = disp->core->func->head;
567 head->base.index = index;
568
569 if (disp->disp->object.oclass < GF110_DISP)
570 funcs = &nv50_head_func;
571 else
572 funcs = &nvd9_head_func;
573
574 if (disp->disp->object.oclass < GV100_DISP) {
575 ret = nv50_base_new(drm, head->base.index, &base);
576 ret = nv50_ovly_new(drm, head->base.index, &ovly);
577 } else {
578 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,
579 head->base.index * 2 + 0, &base);
580 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,
581 head->base.index * 2 + 1, &ovly);
582 }
583 if (ret == 0)
584 ret = nv50_curs_new(drm, head->base.index, &curs);
585 if (ret) {
586 kfree(head);
587 return ERR_PTR(ret);
588 }
589
590 nv_crtc = &head->base;
591 crtc = &nv_crtc->base;
592 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
593 funcs, "head-%d", head->base.index);
594 drm_crtc_helper_add(crtc, &nv50_head_help);
595 /* Keep the legacy gamma size at 256 to avoid compatibility issues */
596 drm_mode_crtc_set_gamma_size(crtc, 256);
597 drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,
598 disp->disp->object.oclass >= GF110_DISP,
599 head->func->olut_size);
600
601 if (head->func->olut_set) {
602 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
603 if (ret) {
604 nv50_head_destroy(crtc);
605 return ERR_PTR(ret);
606 }
607 }
608
609 ret = nvif_notify_ctor(&disp->disp->object, "kmsVbl", nv50_head_vblank_handler,
610 false, NV04_DISP_NTFY_VBLANK,
611 &(struct nvif_notify_head_req_v0) {
612 .head = nv_crtc->index,
613 },
614 sizeof(struct nvif_notify_head_req_v0),
615 sizeof(struct nvif_notify_head_rep_v0),
616 &nv_crtc->vblank);
617 if (ret)
618 return ERR_PTR(ret);
619
620 return head;
621}