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1#ifndef A6XX_XML
2#define A6XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
12- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
13- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
14- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
15- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
16- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
17- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
18- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
19- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
20- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
21- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
22- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
23- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
24
25Copyright (C) 2013-2021 by the following authors:
26- Rob Clark <robdclark@gmail.com> (robclark)
27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29Permission is hereby granted, free of charge, to any person obtaining
30a copy of this software and associated documentation files (the
31"Software"), to deal in the Software without restriction, including
32without limitation the rights to use, copy, modify, merge, publish,
33distribute, sublicense, and/or sell copies of the Software, and to
34permit persons to whom the Software is furnished to do so, subject to
35the following conditions:
36
37The above copyright notice and this permission notice (including the
38next paragraph) shall be included in all copies or substantial
39portions of the Software.
40
41THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48*/
49
50
51enum a6xx_tile_mode {
52 TILE6_LINEAR = 0,
53 TILE6_2 = 2,
54 TILE6_3 = 3,
55};
56
57enum a6xx_format {
58 FMT6_A8_UNORM = 2,
59 FMT6_8_UNORM = 3,
60 FMT6_8_SNORM = 4,
61 FMT6_8_UINT = 5,
62 FMT6_8_SINT = 6,
63 FMT6_4_4_4_4_UNORM = 8,
64 FMT6_5_5_5_1_UNORM = 10,
65 FMT6_1_5_5_5_UNORM = 12,
66 FMT6_5_6_5_UNORM = 14,
67 FMT6_8_8_UNORM = 15,
68 FMT6_8_8_SNORM = 16,
69 FMT6_8_8_UINT = 17,
70 FMT6_8_8_SINT = 18,
71 FMT6_L8_A8_UNORM = 19,
72 FMT6_16_UNORM = 21,
73 FMT6_16_SNORM = 22,
74 FMT6_16_FLOAT = 23,
75 FMT6_16_UINT = 24,
76 FMT6_16_SINT = 25,
77 FMT6_8_8_8_UNORM = 33,
78 FMT6_8_8_8_SNORM = 34,
79 FMT6_8_8_8_UINT = 35,
80 FMT6_8_8_8_SINT = 36,
81 FMT6_8_8_8_8_UNORM = 48,
82 FMT6_8_8_8_X8_UNORM = 49,
83 FMT6_8_8_8_8_SNORM = 50,
84 FMT6_8_8_8_8_UINT = 51,
85 FMT6_8_8_8_8_SINT = 52,
86 FMT6_9_9_9_E5_FLOAT = 53,
87 FMT6_10_10_10_2_UNORM = 54,
88 FMT6_10_10_10_2_UNORM_DEST = 55,
89 FMT6_10_10_10_2_SNORM = 57,
90 FMT6_10_10_10_2_UINT = 58,
91 FMT6_10_10_10_2_SINT = 59,
92 FMT6_11_11_10_FLOAT = 66,
93 FMT6_16_16_UNORM = 67,
94 FMT6_16_16_SNORM = 68,
95 FMT6_16_16_FLOAT = 69,
96 FMT6_16_16_UINT = 70,
97 FMT6_16_16_SINT = 71,
98 FMT6_32_UNORM = 72,
99 FMT6_32_SNORM = 73,
100 FMT6_32_FLOAT = 74,
101 FMT6_32_UINT = 75,
102 FMT6_32_SINT = 76,
103 FMT6_32_FIXED = 77,
104 FMT6_16_16_16_UNORM = 88,
105 FMT6_16_16_16_SNORM = 89,
106 FMT6_16_16_16_FLOAT = 90,
107 FMT6_16_16_16_UINT = 91,
108 FMT6_16_16_16_SINT = 92,
109 FMT6_16_16_16_16_UNORM = 96,
110 FMT6_16_16_16_16_SNORM = 97,
111 FMT6_16_16_16_16_FLOAT = 98,
112 FMT6_16_16_16_16_UINT = 99,
113 FMT6_16_16_16_16_SINT = 100,
114 FMT6_32_32_UNORM = 101,
115 FMT6_32_32_SNORM = 102,
116 FMT6_32_32_FLOAT = 103,
117 FMT6_32_32_UINT = 104,
118 FMT6_32_32_SINT = 105,
119 FMT6_32_32_FIXED = 106,
120 FMT6_32_32_32_UNORM = 112,
121 FMT6_32_32_32_SNORM = 113,
122 FMT6_32_32_32_UINT = 114,
123 FMT6_32_32_32_SINT = 115,
124 FMT6_32_32_32_FLOAT = 116,
125 FMT6_32_32_32_FIXED = 117,
126 FMT6_32_32_32_32_UNORM = 128,
127 FMT6_32_32_32_32_SNORM = 129,
128 FMT6_32_32_32_32_FLOAT = 130,
129 FMT6_32_32_32_32_UINT = 131,
130 FMT6_32_32_32_32_SINT = 132,
131 FMT6_32_32_32_32_FIXED = 133,
132 FMT6_G8R8B8R8_422_UNORM = 140,
133 FMT6_R8G8R8B8_422_UNORM = 141,
134 FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
135 FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
136 FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
137 FMT6_8_PLANE_UNORM = 148,
138 FMT6_Z24_UNORM_S8_UINT = 160,
139 FMT6_ETC2_RG11_UNORM = 171,
140 FMT6_ETC2_RG11_SNORM = 172,
141 FMT6_ETC2_R11_UNORM = 173,
142 FMT6_ETC2_R11_SNORM = 174,
143 FMT6_ETC1 = 175,
144 FMT6_ETC2_RGB8 = 176,
145 FMT6_ETC2_RGBA8 = 177,
146 FMT6_ETC2_RGB8A1 = 178,
147 FMT6_DXT1 = 179,
148 FMT6_DXT3 = 180,
149 FMT6_DXT5 = 181,
150 FMT6_RGTC1_UNORM = 183,
151 FMT6_RGTC1_SNORM = 184,
152 FMT6_RGTC2_UNORM = 187,
153 FMT6_RGTC2_SNORM = 188,
154 FMT6_BPTC_UFLOAT = 190,
155 FMT6_BPTC_FLOAT = 191,
156 FMT6_BPTC = 192,
157 FMT6_ASTC_4x4 = 193,
158 FMT6_ASTC_5x4 = 194,
159 FMT6_ASTC_5x5 = 195,
160 FMT6_ASTC_6x5 = 196,
161 FMT6_ASTC_6x6 = 197,
162 FMT6_ASTC_8x5 = 198,
163 FMT6_ASTC_8x6 = 199,
164 FMT6_ASTC_8x8 = 200,
165 FMT6_ASTC_10x5 = 201,
166 FMT6_ASTC_10x6 = 202,
167 FMT6_ASTC_10x8 = 203,
168 FMT6_ASTC_10x10 = 204,
169 FMT6_ASTC_12x10 = 205,
170 FMT6_ASTC_12x12 = 206,
171 FMT6_Z24_UINT_S8_UINT = 234,
172 FMT6_NONE = 255,
173};
174
175enum a6xx_polygon_mode {
176 POLYMODE6_POINTS = 1,
177 POLYMODE6_LINES = 2,
178 POLYMODE6_TRIANGLES = 3,
179};
180
181enum a6xx_depth_format {
182 DEPTH6_NONE = 0,
183 DEPTH6_16 = 1,
184 DEPTH6_24_8 = 2,
185 DEPTH6_32 = 4,
186};
187
188enum a6xx_shader_id {
189 A6XX_TP0_TMO_DATA = 9,
190 A6XX_TP0_SMO_DATA = 10,
191 A6XX_TP0_MIPMAP_BASE_DATA = 11,
192 A6XX_TP1_TMO_DATA = 25,
193 A6XX_TP1_SMO_DATA = 26,
194 A6XX_TP1_MIPMAP_BASE_DATA = 27,
195 A6XX_SP_INST_DATA = 41,
196 A6XX_SP_LB_0_DATA = 42,
197 A6XX_SP_LB_1_DATA = 43,
198 A6XX_SP_LB_2_DATA = 44,
199 A6XX_SP_LB_3_DATA = 45,
200 A6XX_SP_LB_4_DATA = 46,
201 A6XX_SP_LB_5_DATA = 47,
202 A6XX_SP_CB_BINDLESS_DATA = 48,
203 A6XX_SP_CB_LEGACY_DATA = 49,
204 A6XX_SP_UAV_DATA = 50,
205 A6XX_SP_INST_TAG = 51,
206 A6XX_SP_CB_BINDLESS_TAG = 52,
207 A6XX_SP_TMO_UMO_TAG = 53,
208 A6XX_SP_SMO_TAG = 54,
209 A6XX_SP_STATE_DATA = 55,
210 A6XX_HLSQ_CHUNK_CVS_RAM = 73,
211 A6XX_HLSQ_CHUNK_CPS_RAM = 74,
212 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
213 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
214 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
215 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
216 A6XX_HLSQ_CVS_MISC_RAM = 80,
217 A6XX_HLSQ_CPS_MISC_RAM = 81,
218 A6XX_HLSQ_INST_RAM = 82,
219 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
220 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
221 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
222 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
223 A6XX_HLSQ_INST_RAM_TAG = 87,
224 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
225 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
226 A6XX_HLSQ_PWR_REST_RAM = 90,
227 A6XX_HLSQ_PWR_REST_TAG = 91,
228 A6XX_HLSQ_DATAPATH_META = 96,
229 A6XX_HLSQ_FRONTEND_META = 97,
230 A6XX_HLSQ_INDIRECT_META = 98,
231 A6XX_HLSQ_BACKEND_META = 99,
232};
233
234enum a6xx_debugbus_id {
235 A6XX_DBGBUS_CP = 1,
236 A6XX_DBGBUS_RBBM = 2,
237 A6XX_DBGBUS_VBIF = 3,
238 A6XX_DBGBUS_HLSQ = 4,
239 A6XX_DBGBUS_UCHE = 5,
240 A6XX_DBGBUS_DPM = 6,
241 A6XX_DBGBUS_TESS = 7,
242 A6XX_DBGBUS_PC = 8,
243 A6XX_DBGBUS_VFDP = 9,
244 A6XX_DBGBUS_VPC = 10,
245 A6XX_DBGBUS_TSE = 11,
246 A6XX_DBGBUS_RAS = 12,
247 A6XX_DBGBUS_VSC = 13,
248 A6XX_DBGBUS_COM = 14,
249 A6XX_DBGBUS_LRZ = 16,
250 A6XX_DBGBUS_A2D = 17,
251 A6XX_DBGBUS_CCUFCHE = 18,
252 A6XX_DBGBUS_GMU_CX = 19,
253 A6XX_DBGBUS_RBP = 20,
254 A6XX_DBGBUS_DCS = 21,
255 A6XX_DBGBUS_DBGC = 22,
256 A6XX_DBGBUS_CX = 23,
257 A6XX_DBGBUS_GMU_GX = 24,
258 A6XX_DBGBUS_TPFCHE = 25,
259 A6XX_DBGBUS_GBIF_GX = 26,
260 A6XX_DBGBUS_GPC = 29,
261 A6XX_DBGBUS_LARC = 30,
262 A6XX_DBGBUS_HLSQ_SPTP = 31,
263 A6XX_DBGBUS_RB_0 = 32,
264 A6XX_DBGBUS_RB_1 = 33,
265 A6XX_DBGBUS_UCHE_WRAPPER = 36,
266 A6XX_DBGBUS_CCU_0 = 40,
267 A6XX_DBGBUS_CCU_1 = 41,
268 A6XX_DBGBUS_VFD_0 = 56,
269 A6XX_DBGBUS_VFD_1 = 57,
270 A6XX_DBGBUS_VFD_2 = 58,
271 A6XX_DBGBUS_VFD_3 = 59,
272 A6XX_DBGBUS_SP_0 = 64,
273 A6XX_DBGBUS_SP_1 = 65,
274 A6XX_DBGBUS_TPL1_0 = 72,
275 A6XX_DBGBUS_TPL1_1 = 73,
276 A6XX_DBGBUS_TPL1_2 = 74,
277 A6XX_DBGBUS_TPL1_3 = 75,
278};
279
280enum a6xx_cp_perfcounter_select {
281 PERF_CP_ALWAYS_COUNT = 0,
282 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
283 PERF_CP_BUSY_CYCLES = 2,
284 PERF_CP_NUM_PREEMPTIONS = 3,
285 PERF_CP_PREEMPTION_REACTION_DELAY = 4,
286 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
287 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
288 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
289 PERF_CP_PREDICATED_DRAWS_KILLED = 8,
290 PERF_CP_MODE_SWITCH = 9,
291 PERF_CP_ZPASS_DONE = 10,
292 PERF_CP_CONTEXT_DONE = 11,
293 PERF_CP_CACHE_FLUSH = 12,
294 PERF_CP_LONG_PREEMPTIONS = 13,
295 PERF_CP_SQE_I_CACHE_STARVE = 14,
296 PERF_CP_SQE_IDLE = 15,
297 PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
298 PERF_CP_SQE_PM4_STARVE_SDS = 17,
299 PERF_CP_SQE_MRB_STARVE = 18,
300 PERF_CP_SQE_RRB_STARVE = 19,
301 PERF_CP_SQE_VSD_STARVE = 20,
302 PERF_CP_VSD_DECODE_STARVE = 21,
303 PERF_CP_SQE_PIPE_OUT_STALL = 22,
304 PERF_CP_SQE_SYNC_STALL = 23,
305 PERF_CP_SQE_PM4_WFI_STALL = 24,
306 PERF_CP_SQE_SYS_WFI_STALL = 25,
307 PERF_CP_SQE_T4_EXEC = 26,
308 PERF_CP_SQE_LOAD_STATE_EXEC = 27,
309 PERF_CP_SQE_SAVE_SDS_STATE = 28,
310 PERF_CP_SQE_DRAW_EXEC = 29,
311 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
312 PERF_CP_SQE_EXEC_PROFILED = 31,
313 PERF_CP_MEMORY_POOL_EMPTY = 32,
314 PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
315 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
316 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
317 PERF_CP_AHB_STALL_SQE_GMU = 36,
318 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
319 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
320 PERF_CP_CLUSTER0_EMPTY = 39,
321 PERF_CP_CLUSTER1_EMPTY = 40,
322 PERF_CP_CLUSTER2_EMPTY = 41,
323 PERF_CP_CLUSTER3_EMPTY = 42,
324 PERF_CP_CLUSTER4_EMPTY = 43,
325 PERF_CP_CLUSTER5_EMPTY = 44,
326 PERF_CP_PM4_DATA = 45,
327 PERF_CP_PM4_HEADERS = 46,
328 PERF_CP_VBIF_READ_BEATS = 47,
329 PERF_CP_VBIF_WRITE_BEATS = 48,
330 PERF_CP_SQE_INSTR_COUNTER = 49,
331};
332
333enum a6xx_rbbm_perfcounter_select {
334 PERF_RBBM_ALWAYS_COUNT = 0,
335 PERF_RBBM_ALWAYS_ON = 1,
336 PERF_RBBM_TSE_BUSY = 2,
337 PERF_RBBM_RAS_BUSY = 3,
338 PERF_RBBM_PC_DCALL_BUSY = 4,
339 PERF_RBBM_PC_VSD_BUSY = 5,
340 PERF_RBBM_STATUS_MASKED = 6,
341 PERF_RBBM_COM_BUSY = 7,
342 PERF_RBBM_DCOM_BUSY = 8,
343 PERF_RBBM_VBIF_BUSY = 9,
344 PERF_RBBM_VSC_BUSY = 10,
345 PERF_RBBM_TESS_BUSY = 11,
346 PERF_RBBM_UCHE_BUSY = 12,
347 PERF_RBBM_HLSQ_BUSY = 13,
348};
349
350enum a6xx_pc_perfcounter_select {
351 PERF_PC_BUSY_CYCLES = 0,
352 PERF_PC_WORKING_CYCLES = 1,
353 PERF_PC_STALL_CYCLES_VFD = 2,
354 PERF_PC_STALL_CYCLES_TSE = 3,
355 PERF_PC_STALL_CYCLES_VPC = 4,
356 PERF_PC_STALL_CYCLES_UCHE = 5,
357 PERF_PC_STALL_CYCLES_TESS = 6,
358 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
359 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
360 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
361 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
362 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
363 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
364 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
365 PERF_PC_STARVE_CYCLES_DI = 14,
366 PERF_PC_VIS_STREAMS_LOADED = 15,
367 PERF_PC_INSTANCES = 16,
368 PERF_PC_VPC_PRIMITIVES = 17,
369 PERF_PC_DEAD_PRIM = 18,
370 PERF_PC_LIVE_PRIM = 19,
371 PERF_PC_VERTEX_HITS = 20,
372 PERF_PC_IA_VERTICES = 21,
373 PERF_PC_IA_PRIMITIVES = 22,
374 PERF_PC_GS_PRIMITIVES = 23,
375 PERF_PC_HS_INVOCATIONS = 24,
376 PERF_PC_DS_INVOCATIONS = 25,
377 PERF_PC_VS_INVOCATIONS = 26,
378 PERF_PC_GS_INVOCATIONS = 27,
379 PERF_PC_DS_PRIMITIVES = 28,
380 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
381 PERF_PC_3D_DRAWCALLS = 30,
382 PERF_PC_2D_DRAWCALLS = 31,
383 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
384 PERF_TESS_BUSY_CYCLES = 33,
385 PERF_TESS_WORKING_CYCLES = 34,
386 PERF_TESS_STALL_CYCLES_PC = 35,
387 PERF_TESS_STARVE_CYCLES_PC = 36,
388 PERF_PC_TSE_TRANSACTION = 37,
389 PERF_PC_TSE_VERTEX = 38,
390 PERF_PC_TESS_PC_UV_TRANS = 39,
391 PERF_PC_TESS_PC_UV_PATCHES = 40,
392 PERF_PC_TESS_FACTOR_TRANS = 41,
393};
394
395enum a6xx_vfd_perfcounter_select {
396 PERF_VFD_BUSY_CYCLES = 0,
397 PERF_VFD_STALL_CYCLES_UCHE = 1,
398 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
399 PERF_VFD_STALL_CYCLES_SP_INFO = 3,
400 PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
401 PERF_VFD_STARVE_CYCLES_UCHE = 5,
402 PERF_VFD_RBUFFER_FULL = 6,
403 PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
404 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
405 PERF_VFD_NUM_ATTRIBUTES = 9,
406 PERF_VFD_UPPER_SHADER_FIBERS = 10,
407 PERF_VFD_LOWER_SHADER_FIBERS = 11,
408 PERF_VFD_MODE_0_FIBERS = 12,
409 PERF_VFD_MODE_1_FIBERS = 13,
410 PERF_VFD_MODE_2_FIBERS = 14,
411 PERF_VFD_MODE_3_FIBERS = 15,
412 PERF_VFD_MODE_4_FIBERS = 16,
413 PERF_VFD_TOTAL_VERTICES = 17,
414 PERF_VFDP_STALL_CYCLES_VFD = 18,
415 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
416 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
417 PERF_VFDP_STARVE_CYCLES_PC = 21,
418 PERF_VFDP_VS_STAGE_WAVES = 22,
419};
420
421enum a6xx_hlsq_perfcounter_select {
422 PERF_HLSQ_BUSY_CYCLES = 0,
423 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
424 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
425 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
426 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
427 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
428 PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
429 PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
430 PERF_HLSQ_QUADS = 8,
431 PERF_HLSQ_CS_INVOCATIONS = 9,
432 PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
433 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
434 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
435 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
436 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
437 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
438 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
439 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
440 PERF_HLSQ_STALL_CYCLES_VPC = 18,
441 PERF_HLSQ_PIXELS = 19,
442 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
443};
444
445enum a6xx_vpc_perfcounter_select {
446 PERF_VPC_BUSY_CYCLES = 0,
447 PERF_VPC_WORKING_CYCLES = 1,
448 PERF_VPC_STALL_CYCLES_UCHE = 2,
449 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
450 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
451 PERF_VPC_STALL_CYCLES_PC = 5,
452 PERF_VPC_STALL_CYCLES_SP_LM = 6,
453 PERF_VPC_STARVE_CYCLES_SP = 7,
454 PERF_VPC_STARVE_CYCLES_LRZ = 8,
455 PERF_VPC_PC_PRIMITIVES = 9,
456 PERF_VPC_SP_COMPONENTS = 10,
457 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
458 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
459 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
460 PERF_VPC_LM_TRANSACTION = 14,
461 PERF_VPC_STREAMOUT_TRANSACTION = 15,
462 PERF_VPC_VS_BUSY_CYCLES = 16,
463 PERF_VPC_PS_BUSY_CYCLES = 17,
464 PERF_VPC_VS_WORKING_CYCLES = 18,
465 PERF_VPC_PS_WORKING_CYCLES = 19,
466 PERF_VPC_STARVE_CYCLES_RB = 20,
467 PERF_VPC_NUM_VPCRAM_READ_POS = 21,
468 PERF_VPC_WIT_FULL_CYCLES = 22,
469 PERF_VPC_VPCRAM_FULL_CYCLES = 23,
470 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
471 PERF_VPC_NUM_VPCRAM_WRITE = 25,
472 PERF_VPC_NUM_VPCRAM_READ_SO = 26,
473 PERF_VPC_NUM_ATTR_REQ_LM = 27,
474};
475
476enum a6xx_tse_perfcounter_select {
477 PERF_TSE_BUSY_CYCLES = 0,
478 PERF_TSE_CLIPPING_CYCLES = 1,
479 PERF_TSE_STALL_CYCLES_RAS = 2,
480 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
481 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
482 PERF_TSE_STARVE_CYCLES_PC = 5,
483 PERF_TSE_INPUT_PRIM = 6,
484 PERF_TSE_INPUT_NULL_PRIM = 7,
485 PERF_TSE_TRIVAL_REJ_PRIM = 8,
486 PERF_TSE_CLIPPED_PRIM = 9,
487 PERF_TSE_ZERO_AREA_PRIM = 10,
488 PERF_TSE_FACENESS_CULLED_PRIM = 11,
489 PERF_TSE_ZERO_PIXEL_PRIM = 12,
490 PERF_TSE_OUTPUT_NULL_PRIM = 13,
491 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
492 PERF_TSE_CINVOCATION = 15,
493 PERF_TSE_CPRIMITIVES = 16,
494 PERF_TSE_2D_INPUT_PRIM = 17,
495 PERF_TSE_2D_ALIVE_CYCLES = 18,
496 PERF_TSE_CLIP_PLANES = 19,
497};
498
499enum a6xx_ras_perfcounter_select {
500 PERF_RAS_BUSY_CYCLES = 0,
501 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
502 PERF_RAS_STALL_CYCLES_LRZ = 2,
503 PERF_RAS_STARVE_CYCLES_TSE = 3,
504 PERF_RAS_SUPER_TILES = 4,
505 PERF_RAS_8X4_TILES = 5,
506 PERF_RAS_MASKGEN_ACTIVE = 6,
507 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
508 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
509 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
510 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
511 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
512 PERF_RAS_BLOCKS = 12,
513};
514
515enum a6xx_uche_perfcounter_select {
516 PERF_UCHE_BUSY_CYCLES = 0,
517 PERF_UCHE_STALL_CYCLES_ARBITER = 1,
518 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
519 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
520 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
521 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
522 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
523 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
524 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
525 PERF_UCHE_READ_REQUESTS_TP = 9,
526 PERF_UCHE_READ_REQUESTS_VFD = 10,
527 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
528 PERF_UCHE_READ_REQUESTS_LRZ = 12,
529 PERF_UCHE_READ_REQUESTS_SP = 13,
530 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
531 PERF_UCHE_WRITE_REQUESTS_SP = 15,
532 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
533 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
534 PERF_UCHE_EVICTS = 18,
535 PERF_UCHE_BANK_REQ0 = 19,
536 PERF_UCHE_BANK_REQ1 = 20,
537 PERF_UCHE_BANK_REQ2 = 21,
538 PERF_UCHE_BANK_REQ3 = 22,
539 PERF_UCHE_BANK_REQ4 = 23,
540 PERF_UCHE_BANK_REQ5 = 24,
541 PERF_UCHE_BANK_REQ6 = 25,
542 PERF_UCHE_BANK_REQ7 = 26,
543 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
544 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
545 PERF_UCHE_GMEM_READ_BEATS = 29,
546 PERF_UCHE_TPH_REF_FULL = 30,
547 PERF_UCHE_TPH_VICTIM_FULL = 31,
548 PERF_UCHE_TPH_EXT_FULL = 32,
549 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
550 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
551 PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
552 PERF_UCHE_VBIF_READ_BEATS_PC = 36,
553 PERF_UCHE_READ_REQUESTS_PC = 37,
554 PERF_UCHE_RAM_READ_REQ = 38,
555 PERF_UCHE_RAM_WRITE_REQ = 39,
556};
557
558enum a6xx_tp_perfcounter_select {
559 PERF_TP_BUSY_CYCLES = 0,
560 PERF_TP_STALL_CYCLES_UCHE = 1,
561 PERF_TP_LATENCY_CYCLES = 2,
562 PERF_TP_LATENCY_TRANS = 3,
563 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
564 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
565 PERF_TP_L1_CACHELINE_REQUESTS = 6,
566 PERF_TP_L1_CACHELINE_MISSES = 7,
567 PERF_TP_SP_TP_TRANS = 8,
568 PERF_TP_TP_SP_TRANS = 9,
569 PERF_TP_OUTPUT_PIXELS = 10,
570 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
571 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
572 PERF_TP_QUADS_RECEIVED = 13,
573 PERF_TP_QUADS_OFFSET = 14,
574 PERF_TP_QUADS_SHADOW = 15,
575 PERF_TP_QUADS_ARRAY = 16,
576 PERF_TP_QUADS_GRADIENT = 17,
577 PERF_TP_QUADS_1D = 18,
578 PERF_TP_QUADS_2D = 19,
579 PERF_TP_QUADS_BUFFER = 20,
580 PERF_TP_QUADS_3D = 21,
581 PERF_TP_QUADS_CUBE = 22,
582 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
583 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
584 PERF_TP_OUTPUT_PIXELS_POINT = 25,
585 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
586 PERF_TP_OUTPUT_PIXELS_MIP = 27,
587 PERF_TP_OUTPUT_PIXELS_ANISO = 28,
588 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
589 PERF_TP_FLAG_CACHE_REQUESTS = 30,
590 PERF_TP_FLAG_CACHE_MISSES = 31,
591 PERF_TP_L1_5_L2_REQUESTS = 32,
592 PERF_TP_2D_OUTPUT_PIXELS = 33,
593 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
594 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
595 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
596 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
597 PERF_TP_TPA2TPC_TRANS = 38,
598 PERF_TP_L1_MISSES_ASTC_1TILE = 39,
599 PERF_TP_L1_MISSES_ASTC_2TILE = 40,
600 PERF_TP_L1_MISSES_ASTC_4TILE = 41,
601 PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
602 PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
603 PERF_TP_L1_BANK_CONFLICT = 44,
604 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
605 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
606 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
607 PERF_TP_FRONTEND_WORKING_CYCLES = 48,
608 PERF_TP_L1_TAG_WORKING_CYCLES = 49,
609 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
610 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
611 PERF_TP_BACKEND_WORKING_CYCLES = 52,
612 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
613 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
614 PERF_TP_STARVE_CYCLES_SP = 55,
615 PERF_TP_STARVE_CYCLES_UCHE = 56,
616};
617
618enum a6xx_sp_perfcounter_select {
619 PERF_SP_BUSY_CYCLES = 0,
620 PERF_SP_ALU_WORKING_CYCLES = 1,
621 PERF_SP_EFU_WORKING_CYCLES = 2,
622 PERF_SP_STALL_CYCLES_VPC = 3,
623 PERF_SP_STALL_CYCLES_TP = 4,
624 PERF_SP_STALL_CYCLES_UCHE = 5,
625 PERF_SP_STALL_CYCLES_RB = 6,
626 PERF_SP_NON_EXECUTION_CYCLES = 7,
627 PERF_SP_WAVE_CONTEXTS = 8,
628 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
629 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
630 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
631 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
632 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
633 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
634 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
635 PERF_SP_WAVE_CTRL_CYCLES = 16,
636 PERF_SP_WAVE_LOAD_CYCLES = 17,
637 PERF_SP_WAVE_EMIT_CYCLES = 18,
638 PERF_SP_WAVE_NOP_CYCLES = 19,
639 PERF_SP_WAVE_WAIT_CYCLES = 20,
640 PERF_SP_WAVE_FETCH_CYCLES = 21,
641 PERF_SP_WAVE_IDLE_CYCLES = 22,
642 PERF_SP_WAVE_END_CYCLES = 23,
643 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
644 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
645 PERF_SP_WAVE_JOIN_CYCLES = 26,
646 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
647 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
648 PERF_SP_LM_ATOMICS = 29,
649 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
650 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
651 PERF_SP_GM_ATOMICS = 32,
652 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
653 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
654 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
655 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
656 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
657 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
658 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
659 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
660 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
661 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
662 PERF_SP_VS_INSTRUCTIONS = 43,
663 PERF_SP_FS_INSTRUCTIONS = 44,
664 PERF_SP_ADDR_LOCK_COUNT = 45,
665 PERF_SP_UCHE_READ_TRANS = 46,
666 PERF_SP_UCHE_WRITE_TRANS = 47,
667 PERF_SP_EXPORT_VPC_TRANS = 48,
668 PERF_SP_EXPORT_RB_TRANS = 49,
669 PERF_SP_PIXELS_KILLED = 50,
670 PERF_SP_ICL1_REQUESTS = 51,
671 PERF_SP_ICL1_MISSES = 52,
672 PERF_SP_HS_INSTRUCTIONS = 53,
673 PERF_SP_DS_INSTRUCTIONS = 54,
674 PERF_SP_GS_INSTRUCTIONS = 55,
675 PERF_SP_CS_INSTRUCTIONS = 56,
676 PERF_SP_GPR_READ = 57,
677 PERF_SP_GPR_WRITE = 58,
678 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
679 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
680 PERF_SP_LM_BANK_CONFLICTS = 61,
681 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
682 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
683 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
684 PERF_SP_LM_WORKING_CYCLES = 65,
685 PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
686 PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
687 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
688 PERF_SP_STARVE_CYCLES_HLSQ = 69,
689 PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
690 PERF_SP_WORKING_EU = 71,
691 PERF_SP_ANY_EU_WORKING = 72,
692 PERF_SP_WORKING_EU_FS_STAGE = 73,
693 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
694 PERF_SP_WORKING_EU_VS_STAGE = 75,
695 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
696 PERF_SP_WORKING_EU_CS_STAGE = 77,
697 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
698 PERF_SP_GPR_READ_PREFETCH = 79,
699 PERF_SP_GPR_READ_CONFLICT = 80,
700 PERF_SP_GPR_WRITE_CONFLICT = 81,
701 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
702 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
703 PERF_SP_EXECUTABLE_WAVES = 84,
704};
705
706enum a6xx_rb_perfcounter_select {
707 PERF_RB_BUSY_CYCLES = 0,
708 PERF_RB_STALL_CYCLES_HLSQ = 1,
709 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
710 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
711 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
712 PERF_RB_STARVE_CYCLES_SP = 5,
713 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
714 PERF_RB_STARVE_CYCLES_CCU = 7,
715 PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
716 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
717 PERF_RB_Z_WORKLOAD = 10,
718 PERF_RB_HLSQ_ACTIVE = 11,
719 PERF_RB_Z_READ = 12,
720 PERF_RB_Z_WRITE = 13,
721 PERF_RB_C_READ = 14,
722 PERF_RB_C_WRITE = 15,
723 PERF_RB_TOTAL_PASS = 16,
724 PERF_RB_Z_PASS = 17,
725 PERF_RB_Z_FAIL = 18,
726 PERF_RB_S_FAIL = 19,
727 PERF_RB_BLENDED_FXP_COMPONENTS = 20,
728 PERF_RB_BLENDED_FP16_COMPONENTS = 21,
729 PERF_RB_PS_INVOCATIONS = 22,
730 PERF_RB_2D_ALIVE_CYCLES = 23,
731 PERF_RB_2D_STALL_CYCLES_A2D = 24,
732 PERF_RB_2D_STARVE_CYCLES_SRC = 25,
733 PERF_RB_2D_STARVE_CYCLES_SP = 26,
734 PERF_RB_2D_STARVE_CYCLES_DST = 27,
735 PERF_RB_2D_VALID_PIXELS = 28,
736 PERF_RB_3D_PIXELS = 29,
737 PERF_RB_BLENDER_WORKING_CYCLES = 30,
738 PERF_RB_ZPROC_WORKING_CYCLES = 31,
739 PERF_RB_CPROC_WORKING_CYCLES = 32,
740 PERF_RB_SAMPLER_WORKING_CYCLES = 33,
741 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
742 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
743 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
744 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
745 PERF_RB_STALL_CYCLES_VPC = 38,
746 PERF_RB_2D_INPUT_TRANS = 39,
747 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
748 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
749 PERF_RB_BLENDED_FP32_COMPONENTS = 42,
750 PERF_RB_COLOR_PIX_TILES = 43,
751 PERF_RB_STALL_CYCLES_CCU = 44,
752 PERF_RB_EARLY_Z_ARB3_GRANT = 45,
753 PERF_RB_LATE_Z_ARB3_GRANT = 46,
754 PERF_RB_EARLY_Z_SKIP_GRANT = 47,
755};
756
757enum a6xx_vsc_perfcounter_select {
758 PERF_VSC_BUSY_CYCLES = 0,
759 PERF_VSC_WORKING_CYCLES = 1,
760 PERF_VSC_STALL_CYCLES_UCHE = 2,
761 PERF_VSC_EOT_NUM = 3,
762 PERF_VSC_INPUT_TILES = 4,
763};
764
765enum a6xx_ccu_perfcounter_select {
766 PERF_CCU_BUSY_CYCLES = 0,
767 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
768 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
769 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
770 PERF_CCU_DEPTH_BLOCKS = 4,
771 PERF_CCU_COLOR_BLOCKS = 5,
772 PERF_CCU_DEPTH_BLOCK_HIT = 6,
773 PERF_CCU_COLOR_BLOCK_HIT = 7,
774 PERF_CCU_PARTIAL_BLOCK_READ = 8,
775 PERF_CCU_GMEM_READ = 9,
776 PERF_CCU_GMEM_WRITE = 10,
777 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
778 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
779 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
780 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
781 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
782 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
783 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
784 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
785 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
786 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
787 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
788 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
789 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
790 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
791 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
792 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
793 PERF_CCU_2D_RD_REQ = 27,
794 PERF_CCU_2D_WR_REQ = 28,
795};
796
797enum a6xx_lrz_perfcounter_select {
798 PERF_LRZ_BUSY_CYCLES = 0,
799 PERF_LRZ_STARVE_CYCLES_RAS = 1,
800 PERF_LRZ_STALL_CYCLES_RB = 2,
801 PERF_LRZ_STALL_CYCLES_VSC = 3,
802 PERF_LRZ_STALL_CYCLES_VPC = 4,
803 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
804 PERF_LRZ_STALL_CYCLES_UCHE = 6,
805 PERF_LRZ_LRZ_READ = 7,
806 PERF_LRZ_LRZ_WRITE = 8,
807 PERF_LRZ_READ_LATENCY = 9,
808 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
809 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
810 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
811 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
812 PERF_LRZ_FULL_8X8_TILES = 14,
813 PERF_LRZ_PARTIAL_8X8_TILES = 15,
814 PERF_LRZ_TILE_KILLED = 16,
815 PERF_LRZ_TOTAL_PIXEL = 17,
816 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
817 PERF_LRZ_FULLY_COVERED_TILES = 19,
818 PERF_LRZ_PARTIAL_COVERED_TILES = 20,
819 PERF_LRZ_FEEDBACK_ACCEPT = 21,
820 PERF_LRZ_FEEDBACK_DISCARD = 22,
821 PERF_LRZ_FEEDBACK_STALL = 23,
822 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
823 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
824 PERF_LRZ_STALL_CYCLES_VC = 26,
825 PERF_LRZ_RAS_MASK_TRANS = 27,
826};
827
828enum a6xx_cmp_perfcounter_select {
829 PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
830 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
831 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
832 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
833 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
834 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
835 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
836 PERF_CMPDECMP_VBIF_READ_DATA = 7,
837 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
838 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
839 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
840 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
841 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
842 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
843 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
844 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
845 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
846 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
847 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
848 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
849 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
850 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
851 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
852 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
853 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
854 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
855 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
856 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
857 PERF_CMPDECMP_2D_RD_DATA = 28,
858 PERF_CMPDECMP_2D_WR_DATA = 29,
859 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
860 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
861 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
862 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
863 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
864 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
865 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
866 PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
867 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
868 PERF_CMPDECMP_2D_PIXELS = 39,
869};
870
871enum a6xx_2d_ifmt {
872 R2D_UNORM8 = 16,
873 R2D_INT32 = 7,
874 R2D_INT16 = 6,
875 R2D_INT8 = 5,
876 R2D_FLOAT32 = 4,
877 R2D_FLOAT16 = 3,
878 R2D_UNORM8_SRGB = 1,
879 R2D_RAW = 0,
880};
881
882enum a6xx_ztest_mode {
883 A6XX_EARLY_Z = 0,
884 A6XX_LATE_Z = 1,
885 A6XX_EARLY_LRZ_LATE_Z = 2,
886};
887
888enum a6xx_rotation {
889 ROTATE_0 = 0,
890 ROTATE_90 = 1,
891 ROTATE_180 = 2,
892 ROTATE_270 = 3,
893 ROTATE_HFLIP = 4,
894 ROTATE_VFLIP = 5,
895};
896
897enum a6xx_tess_spacing {
898 TESS_EQUAL = 0,
899 TESS_FRACTIONAL_ODD = 2,
900 TESS_FRACTIONAL_EVEN = 3,
901};
902
903enum a6xx_tess_output {
904 TESS_POINTS = 0,
905 TESS_LINES = 1,
906 TESS_CW_TRIS = 2,
907 TESS_CCW_TRIS = 3,
908};
909
910enum a6xx_threadsize {
911 THREAD64 = 0,
912 THREAD128 = 1,
913};
914
915enum a6xx_tex_filter {
916 A6XX_TEX_NEAREST = 0,
917 A6XX_TEX_LINEAR = 1,
918 A6XX_TEX_ANISO = 2,
919 A6XX_TEX_CUBIC = 3,
920};
921
922enum a6xx_tex_clamp {
923 A6XX_TEX_REPEAT = 0,
924 A6XX_TEX_CLAMP_TO_EDGE = 1,
925 A6XX_TEX_MIRROR_REPEAT = 2,
926 A6XX_TEX_CLAMP_TO_BORDER = 3,
927 A6XX_TEX_MIRROR_CLAMP = 4,
928};
929
930enum a6xx_tex_aniso {
931 A6XX_TEX_ANISO_1 = 0,
932 A6XX_TEX_ANISO_2 = 1,
933 A6XX_TEX_ANISO_4 = 2,
934 A6XX_TEX_ANISO_8 = 3,
935 A6XX_TEX_ANISO_16 = 4,
936};
937
938enum a6xx_reduction_mode {
939 A6XX_REDUCTION_MODE_AVERAGE = 0,
940 A6XX_REDUCTION_MODE_MIN = 1,
941 A6XX_REDUCTION_MODE_MAX = 2,
942};
943
944enum a6xx_tex_swiz {
945 A6XX_TEX_X = 0,
946 A6XX_TEX_Y = 1,
947 A6XX_TEX_Z = 2,
948 A6XX_TEX_W = 3,
949 A6XX_TEX_ZERO = 4,
950 A6XX_TEX_ONE = 5,
951};
952
953enum a6xx_tex_type {
954 A6XX_TEX_1D = 0,
955 A6XX_TEX_2D = 1,
956 A6XX_TEX_CUBE = 2,
957 A6XX_TEX_3D = 3,
958};
959
960#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
961#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
962#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
963#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
964#define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
965#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
966#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
967#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
968#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
969#define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
970#define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
971#define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
972#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
973#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
974#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
975#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
976#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
977#define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
978#define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
979#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
980#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
981#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
982#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
983#define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
984#define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
985#define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
986#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
987#define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
988#define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
989#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
990#define REG_A6XX_CP_RB_BASE 0x00000800
991
992#define REG_A6XX_CP_RB_BASE_HI 0x00000801
993
994#define REG_A6XX_CP_RB_CNTL 0x00000802
995
996#define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804
997
998#define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805
999
1000#define REG_A6XX_CP_RB_RPTR 0x00000806
1001
1002#define REG_A6XX_CP_RB_WPTR 0x00000807
1003
1004#define REG_A6XX_CP_SQE_CNTL 0x00000808
1005
1006#define REG_A6XX_CP_CP2GMU_STATUS 0x00000812
1007#define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
1008
1009#define REG_A6XX_CP_HW_FAULT 0x00000821
1010
1011#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
1012
1013#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1014
1015#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
1016
1017#define REG_A6XX_CP_MISC_CNTL 0x00000840
1018
1019#define REG_A6XX_CP_APRIV_CNTL 0x00000844
1020
1021#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
1022#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff
1023#define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0
1024static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val)
1025{
1026 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK;
1027}
1028#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00
1029#define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8
1030static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val)
1031{
1032 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK;
1033}
1034#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
1035#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
1036static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
1037{
1038 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
1039}
1040#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
1041#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
1042static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
1043{
1044 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
1045}
1046
1047#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
1048#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff
1049#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
1050static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
1051{
1052 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
1053}
1054#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
1055#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
1056static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
1057{
1058 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
1059}
1060
1061#define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
1062
1063#define REG_A6XX_CP_CHICKEN_DBG 0x00000841
1064
1065#define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
1066
1067#define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
1068
1069#define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
1070
1071static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1072
1073static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1074
1075static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1076
1077static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1078#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
1079#define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
1080static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1081{
1082 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1083}
1084#define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
1085#define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
1086static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1087{
1088 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1089}
1090#define A6XX_CP_PROTECT_REG_READ 0x80000000
1091
1092#define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
1093
1094#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1
1095
1096#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2
1097
1098#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3
1099
1100#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4
1101
1102#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5
1103
1104#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6
1105
1106#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7
1107
1108#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8
1109
1110static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
1111
1112#define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900
1113
1114#define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901
1115
1116#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
1117
1118#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
1119
1120#define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
1121
1122#define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
1123
1124#define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
1125
1126#define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
1127
1128#define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
1129
1130#define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
1131
1132#define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
1133
1134#define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
1135
1136#define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
1137
1138#define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
1139
1140#define REG_A6XX_CP_IB1_BASE 0x00000928
1141
1142#define REG_A6XX_CP_IB1_BASE_HI 0x00000929
1143
1144#define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
1145
1146#define REG_A6XX_CP_IB2_BASE 0x0000092b
1147
1148#define REG_A6XX_CP_IB2_BASE_HI 0x0000092c
1149
1150#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
1151
1152#define REG_A6XX_CP_SDS_BASE 0x0000092e
1153
1154#define REG_A6XX_CP_SDS_BASE_HI 0x0000092f
1155
1156#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
1157
1158#define REG_A6XX_CP_MRB_BASE 0x00000931
1159
1160#define REG_A6XX_CP_MRB_BASE_HI 0x00000932
1161
1162#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
1163
1164#define REG_A6XX_CP_VSD_BASE 0x00000934
1165
1166#define REG_A6XX_CP_VSD_BASE_HI 0x00000935
1167
1168#define REG_A6XX_CP_MRB_DWORDS 0x00000946
1169
1170#define REG_A6XX_CP_VSD_DWORDS 0x00000947
1171
1172#define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949
1173#define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000
1174#define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16
1175static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val)
1176{
1177 return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK;
1178}
1179
1180#define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a
1181#define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000
1182#define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16
1183static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val)
1184{
1185 return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK;
1186}
1187
1188#define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c
1189#define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000
1190#define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16
1191static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val)
1192{
1193 return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK;
1194}
1195
1196#define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980
1197
1198#define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981
1199
1200#define REG_A6XX_CP_AHB_CNTL 0x0000098d
1201
1202#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1203
1204#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1205
1206#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
1207
1208#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
1209
1210#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1211
1212#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
1213
1214#define REG_A6XX_RBBM_STATUS 0x00000210
1215#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
1216#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
1217#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
1218#define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
1219#define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
1220#define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
1221#define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
1222#define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
1223#define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
1224#define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
1225#define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
1226#define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
1227#define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
1228#define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
1229#define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
1230#define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
1231#define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
1232#define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
1233#define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
1234#define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
1235#define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
1236#define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
1237#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
1238#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
1239
1240#define REG_A6XX_RBBM_STATUS3 0x00000213
1241#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
1242
1243#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1244
1245static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
1246
1247static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1248
1249static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
1250
1251static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
1252
1253static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
1254
1255static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
1256
1257static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
1258
1259static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
1260
1261static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
1262
1263static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
1264
1265static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
1266
1267static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
1268
1269static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
1270
1271static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
1272
1273static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
1274
1275static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
1276
1277#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1278
1279#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1280
1281#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1282
1283#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1284
1285#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1286
1287#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1288
1289#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1290
1291static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
1292
1293#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1294
1295#define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1296
1297#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
1298
1299#define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
1300
1301#define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542
1302
1303#define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543
1304
1305#define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544
1306
1307#define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545
1308
1309#define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546
1310
1311#define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547
1312
1313#define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548
1314
1315#define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549
1316
1317#define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a
1318
1319#define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b
1320
1321#define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c
1322
1323#define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d
1324
1325#define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e
1326
1327#define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f
1328
1329#define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550
1330
1331#define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551
1332
1333#define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552
1334
1335#define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553
1336
1337#define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554
1338
1339#define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555
1340
1341#define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1342
1343#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1344
1345#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1346
1347#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1348
1349#define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1350
1351#define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1352
1353#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
1354
1355#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
1356
1357#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c
1358#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001
1359
1360#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
1361
1362#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
1363
1364#define REG_A6XX_RBBM_INT_0_MASK 0x00000038
1365
1366#define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
1367
1368#define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
1369
1370#define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
1371
1372#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1373
1374#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1375
1376#define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
1377
1378#define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
1379
1380#define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
1381
1382#define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
1383
1384#define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
1385
1386#define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
1387
1388#define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
1389
1390#define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
1391
1392#define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
1393
1394#define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
1395
1396#define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
1397
1398#define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
1399
1400#define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
1401
1402#define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
1403
1404#define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
1405
1406#define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
1407
1408#define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
1409
1410#define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
1411
1412#define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
1413
1414#define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
1415
1416#define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
1417
1418#define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
1419
1420#define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
1421
1422#define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
1423
1424#define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
1425
1426#define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
1427
1428#define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
1429
1430#define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
1431
1432#define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
1433
1434#define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
1435
1436#define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
1437
1438#define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
1439
1440#define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
1441
1442#define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
1443
1444#define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
1445
1446#define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
1447
1448#define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
1449
1450#define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
1451
1452#define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
1453
1454#define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
1455
1456#define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
1457
1458#define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
1459
1460#define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
1461
1462#define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
1463
1464#define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
1465
1466#define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
1467
1468#define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
1469
1470#define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
1471
1472#define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
1473
1474#define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
1475
1476#define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
1477
1478#define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
1479
1480#define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
1481
1482#define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
1483
1484#define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
1485
1486#define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
1487
1488#define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
1489
1490#define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
1491
1492#define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
1493
1494#define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
1495
1496#define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
1497
1498#define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
1499
1500#define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
1501
1502#define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
1503
1504#define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
1505
1506#define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
1507
1508#define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
1509
1510#define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
1511
1512#define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
1513
1514#define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
1515
1516#define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
1517
1518#define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
1519
1520#define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
1521
1522#define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
1523
1524#define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
1525
1526#define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
1527
1528#define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
1529
1530#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
1531
1532#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
1533
1534#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
1535
1536#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
1537
1538#define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
1539
1540#define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
1541
1542#define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
1543
1544#define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
1545
1546#define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
1547
1548#define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
1549
1550#define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
1551
1552#define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
1553
1554#define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
1555
1556#define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
1557
1558#define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
1559
1560#define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
1561
1562#define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
1563
1564#define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
1565
1566#define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
1567
1568#define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
1569
1570#define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
1571
1572#define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
1573
1574#define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
1575
1576#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
1577
1578#define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
1579
1580#define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
1581
1582#define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
1583
1584#define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
1585
1586#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
1587
1588#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
1589
1590#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
1591
1592#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
1593
1594#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
1595
1596#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
1597
1598#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
1599
1600#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
1601
1602#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
1603#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
1604#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
1605static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
1606{
1607 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
1608}
1609#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
1610#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
1611static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
1612{
1613 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
1614}
1615
1616#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
1617#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
1618#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
1619static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
1620{
1621 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
1622}
1623#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
1624#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
1625static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
1626{
1627 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
1628}
1629#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
1630#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
1631static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
1632{
1633 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
1634}
1635
1636#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
1637#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
1638#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
1639static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
1640{
1641 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
1642}
1643
1644#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
1645
1646#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
1647
1648#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
1649
1650#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
1651
1652#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
1653
1654#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
1655
1656#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
1657
1658#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
1659
1660#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
1661#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
1662#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
1663static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
1664{
1665 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
1666}
1667#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
1668#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
1669static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
1670{
1671 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
1672}
1673#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
1674#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
1675static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
1676{
1677 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
1678}
1679#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
1680#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
1681static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
1682{
1683 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
1684}
1685#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
1686#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
1687static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
1688{
1689 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
1690}
1691#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
1692#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
1693static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
1694{
1695 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
1696}
1697#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
1698#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
1699static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
1700{
1701 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
1702}
1703#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
1704#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
1705static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
1706{
1707 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
1708}
1709
1710#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
1711#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
1712#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
1713static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
1714{
1715 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
1716}
1717#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
1718#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
1719static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
1720{
1721 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
1722}
1723#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
1724#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
1725static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
1726{
1727 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
1728}
1729#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
1730#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
1731static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
1732{
1733 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
1734}
1735#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
1736#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
1737static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
1738{
1739 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
1740}
1741#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
1742#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
1743static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
1744{
1745 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
1746}
1747#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
1748#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
1749static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
1750{
1751 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
1752}
1753#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
1754#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
1755static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
1756{
1757 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
1758}
1759
1760#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
1761
1762#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
1763
1764static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
1765
1766#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
1767
1768#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
1769
1770#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
1771
1772#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
1773
1774#define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05
1775
1776#define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06
1777
1778#define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07
1779
1780#define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08
1781
1782#define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09
1783
1784#define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a
1785
1786#define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b
1787
1788#define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c
1789
1790#define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d
1791
1792#define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e
1793
1794#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
1795
1796#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
1797
1798#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
1799#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
1800#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
1801static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
1802{
1803 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
1804}
1805
1806static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
1807
1808#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
1809
1810#define REG_A6XX_VBIF_VERSION 0x00003000
1811
1812#define REG_A6XX_VBIF_CLKON 0x00003001
1813#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
1814
1815#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1816
1817#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
1818
1819#define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
1820
1821#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
1822
1823#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
1824
1825#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
1826#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
1827#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
1828static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
1829{
1830 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
1831}
1832
1833#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
1834
1835#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
1836#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
1837#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
1838static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
1839{
1840 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
1841}
1842
1843#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
1844
1845#define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
1846
1847#define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
1848
1849#define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
1850
1851#define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
1852
1853#define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
1854
1855#define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
1856
1857#define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
1858
1859#define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
1860
1861#define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
1862
1863#define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
1864
1865#define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
1866
1867#define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
1868
1869#define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
1870
1871#define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
1872
1873#define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
1874
1875#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
1876
1877#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
1878
1879#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1880
1881#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1882
1883#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1884
1885#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1886
1887#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
1888
1889#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
1890
1891#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
1892
1893#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
1894
1895#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
1896
1897#define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
1898
1899#define REG_A6XX_GBIF_HALT 0x00003c45
1900
1901#define REG_A6XX_GBIF_HALT_ACK 0x00003c46
1902
1903#define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
1904
1905#define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
1906
1907#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
1908
1909#define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
1910
1911#define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
1912
1913#define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
1914
1915#define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
1916
1917#define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
1918
1919#define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
1920
1921#define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
1922
1923#define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
1924
1925#define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
1926
1927#define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
1928
1929#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
1930
1931#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
1932
1933#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
1934
1935#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
1936
1937#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
1938#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
1939#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1940static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1941{
1942 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
1943}
1944#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
1945#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
1946static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1947{
1948 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
1949}
1950
1951#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
1952
1953#define REG_A6XX_VSC_BIN_COUNT 0x00000c06
1954#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
1955#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
1956static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
1957{
1958 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
1959}
1960#define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
1961#define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
1962static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
1963{
1964 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
1965}
1966
1967static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1968
1969static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1970#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1971#define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1972static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1973{
1974 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
1975}
1976#define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1977#define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1978static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1979{
1980 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1981}
1982#define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
1983#define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1984static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1985{
1986 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
1987}
1988#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
1989#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
1990static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1991{
1992 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
1993}
1994
1995#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
1996
1997#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
1998
1999#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2000
2001#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2002
2003#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
2004
2005#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
2006
2007static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2008
2009static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2010
2011static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2012
2013static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2014
2015static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2016
2017static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2018
2019#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
2020
2021#define REG_A6XX_GRAS_CL_CNTL 0x00008000
2022#define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001
2023#define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002
2024#define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004
2025#define A6XX_GRAS_CL_CNTL_UNK5 0x00000020
2026#define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2027#define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080
2028#define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100
2029#define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200
2030
2031#define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001
2032#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2033#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
2034static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2035{
2036 return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2037}
2038#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2039#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
2040static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2041{
2042 return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2043}
2044
2045#define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002
2046#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2047#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0
2048static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
2049{
2050 return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
2051}
2052#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2053#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8
2054static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
2055{
2056 return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
2057}
2058
2059#define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003
2060#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2061#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0
2062static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
2063{
2064 return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
2065}
2066#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2067#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8
2068static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
2069{
2070 return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
2071}
2072
2073#define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004
2074
2075#define REG_A6XX_GRAS_CNTL 0x00008005
2076#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2077#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2078#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2079#define A6XX_GRAS_CNTL_SIZE 0x00000008
2080#define A6XX_GRAS_CNTL_UNK4 0x00000010
2081#define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020
2082#define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
2083#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
2084static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2085{
2086 return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
2087}
2088
2089#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
2090#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff
2091#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2092static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2093{
2094 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2095}
2096#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00
2097#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2098static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2099{
2100 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2101}
2102
2103static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2104
2105static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2106#define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
2107#define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
2108static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
2109{
2110 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
2111}
2112
2113static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
2114#define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
2115#define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
2116static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
2117{
2118 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
2119}
2120
2121static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
2122#define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
2123#define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
2124static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
2125{
2126 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
2127}
2128
2129static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
2130#define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
2131#define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
2132static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
2133{
2134 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
2135}
2136
2137static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
2138#define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
2139#define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
2140static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
2141{
2142 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
2143}
2144
2145static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
2146#define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
2147#define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
2148static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
2149{
2150 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
2151}
2152
2153static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2154
2155static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2156#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
2157#define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0
2158static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
2159{
2160 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
2161}
2162
2163static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
2164#define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff
2165#define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0
2166static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
2167{
2168 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
2169}
2170
2171#define REG_A6XX_GRAS_SU_CNTL 0x00008090
2172#define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2173#define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2174#define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2175#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2176#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2177static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2178{
2179 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2180}
2181#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2182#define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
2183#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
2184static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2185{
2186 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2187}
2188#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2189#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
2190#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
2191static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2192{
2193 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2194}
2195#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
2196#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
2197#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
2198#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
2199static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
2200{
2201 return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
2202}
2203
2204#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2205#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2206#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2207static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2208{
2209 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2210}
2211#define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2212#define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2213static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2214{
2215 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2216}
2217
2218#define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
2219#define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff
2220#define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
2221static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2222{
2223 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2224}
2225
2226#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
2227#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
2228#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
2229static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
2230{
2231 return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
2232}
2233
2234#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
2235#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2236#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2237static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2238{
2239 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2240}
2241
2242#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
2243#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2244#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2245static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2246{
2247 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2248}
2249
2250#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
2251#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2252#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2253static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2254{
2255 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2256}
2257
2258#define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
2259#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2260#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2261static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2262{
2263 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2264}
2265#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008
2266#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
2267static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
2268{
2269 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
2270}
2271
2272#define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099
2273
2274#define REG_A6XX_GRAS_UNKNOWN_809A 0x0000809a
2275
2276#define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b
2277#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001
2278#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002
2279
2280#define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c
2281#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001
2282#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002
2283
2284#define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d
2285#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001
2286#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002
2287
2288#define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
2289
2290#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
2291#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f
2292#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
2293static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2294{
2295 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2296}
2297#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00
2298#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
2299static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2300{
2301 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2302}
2303#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000
2304#define A6XX_GRAS_BIN_CONTROL_UNK19__MASK 0x00080000
2305#define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT 19
2306static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val)
2307{
2308 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK;
2309}
2310#define A6XX_GRAS_BIN_CONTROL_UNK20__MASK 0x00100000
2311#define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT 20
2312static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val)
2313{
2314 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK;
2315}
2316#define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000
2317#define A6XX_GRAS_BIN_CONTROL_UNK22__MASK 0x0fc00000
2318#define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT 22
2319static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val)
2320{
2321 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK;
2322}
2323
2324#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
2325#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2326#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2327static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2328{
2329 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2330}
2331#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
2332#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2
2333static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
2334{
2335 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
2336}
2337#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
2338#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3
2339static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
2340{
2341 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
2342}
2343
2344#define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
2345#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2346#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2347static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2348{
2349 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2350}
2351#define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2352
2353#define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4
2354#define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001
2355#define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
2356
2357#define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5
2358#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
2359#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
2360static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
2361{
2362 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
2363}
2364#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
2365#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
2366static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
2367{
2368 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
2369}
2370#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
2371#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
2372static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
2373{
2374 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
2375}
2376#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
2377#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
2378static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
2379{
2380 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
2381}
2382#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
2383#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
2384static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
2385{
2386 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
2387}
2388#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
2389#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
2390static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
2391{
2392 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
2393}
2394#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
2395#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
2396static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
2397{
2398 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
2399}
2400#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
2401#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
2402static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
2403{
2404 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
2405}
2406
2407#define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
2408#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
2409#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
2410static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
2411{
2412 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
2413}
2414#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
2415#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
2416static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
2417{
2418 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
2419}
2420#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
2421#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
2422static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
2423{
2424 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
2425}
2426#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
2427#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
2428static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
2429{
2430 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
2431}
2432#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
2433#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
2434static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
2435{
2436 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
2437}
2438#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
2439#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
2440static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
2441{
2442 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
2443}
2444#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
2445#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
2446static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
2447{
2448 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
2449}
2450#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
2451#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
2452static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
2453{
2454 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
2455}
2456
2457#define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
2458
2459static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2460
2461static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2462#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff
2463#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
2464static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2465{
2466 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2467}
2468#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000
2469#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
2470static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2471{
2472 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2473}
2474
2475static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
2476#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff
2477#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
2478static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2479{
2480 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2481}
2482#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000
2483#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
2484static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2485{
2486 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2487}
2488
2489static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2490
2491static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2492#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff
2493#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0
2494static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
2495{
2496 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
2497}
2498#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000
2499#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16
2500static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
2501{
2502 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
2503}
2504
2505static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
2506#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff
2507#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0
2508static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
2509{
2510 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
2511}
2512#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000
2513#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16
2514static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
2515{
2516 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
2517}
2518
2519#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
2520#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff
2521#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2522static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2523{
2524 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2525}
2526#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000
2527#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2528static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2529{
2530 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2531}
2532
2533#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
2534#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff
2535#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2536static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2537{
2538 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2539}
2540#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000
2541#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2542static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2543{
2544 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2545}
2546
2547#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
2548#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2549#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2550#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2551#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
2552#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
2553#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
2554#define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0
2555#define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6
2556static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
2557{
2558 return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
2559}
2560
2561#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
2562
2563#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
2564#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
2565#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
2566static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
2567{
2568 return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
2569}
2570
2571#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
2572#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
2573#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
2574static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
2575{
2576 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
2577}
2578
2579#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
2580#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff
2581#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
2582static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
2583{
2584 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
2585}
2586#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
2587#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
2588static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
2589{
2590 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
2591}
2592
2593#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
2594#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
2595#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
2596static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
2597{
2598 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
2599}
2600
2601#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
2602#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
2603
2604#define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a
2605#define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff
2606#define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0
2607static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val)
2608{
2609 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK;
2610}
2611#define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000
2612#define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16
2613static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val)
2614{
2615 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK;
2616}
2617#define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000
2618#define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28
2619static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val)
2620{
2621 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK;
2622}
2623
2624#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
2625
2626#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
2627#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
2628#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
2629static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
2630{
2631 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
2632}
2633#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK 0x00000078
2634#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT 3
2635static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val)
2636{
2637 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK;
2638}
2639#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
2640#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
2641#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
2642static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
2643{
2644 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
2645}
2646#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
2647#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000
2648#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17
2649static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
2650{
2651 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
2652}
2653#define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000
2654#define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000
2655#define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20
2656static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
2657{
2658 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
2659}
2660#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
2661#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
2662static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
2663{
2664 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
2665}
2666#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK 0x20000000
2667#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT 29
2668static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val)
2669{
2670 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK;
2671}
2672
2673#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
2674
2675#define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
2676
2677#define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
2678
2679#define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
2680
2681#define REG_A6XX_GRAS_2D_DST_TL 0x00008405
2682#define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff
2683#define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
2684static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
2685{
2686 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
2687}
2688#define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000
2689#define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
2690static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
2691{
2692 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
2693}
2694
2695#define REG_A6XX_GRAS_2D_DST_BR 0x00008406
2696#define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff
2697#define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
2698static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
2699{
2700 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
2701}
2702#define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000
2703#define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
2704static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
2705{
2706 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
2707}
2708
2709#define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407
2710
2711#define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408
2712
2713#define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409
2714
2715#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a
2716#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff
2717#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0
2718static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
2719{
2720 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
2721}
2722#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000
2723#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16
2724static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
2725{
2726 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
2727}
2728
2729#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b
2730#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff
2731#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0
2732static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
2733{
2734 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
2735}
2736#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000
2737#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16
2738static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
2739{
2740 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
2741}
2742
2743#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
2744
2745#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
2746
2747static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
2748
2749static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
2750
2751static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
2752
2753#define REG_A6XX_RB_BIN_CONTROL 0x00008800
2754#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
2755#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
2756static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
2757{
2758 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
2759}
2760#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
2761#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
2762static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
2763{
2764 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
2765}
2766#define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000
2767#define A6XX_RB_BIN_CONTROL_UNK19__MASK 0x00080000
2768#define A6XX_RB_BIN_CONTROL_UNK19__SHIFT 19
2769static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val)
2770{
2771 return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK;
2772}
2773#define A6XX_RB_BIN_CONTROL_UNK20__MASK 0x00100000
2774#define A6XX_RB_BIN_CONTROL_UNK20__SHIFT 20
2775static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val)
2776{
2777 return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK;
2778}
2779#define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000
2780#define A6XX_RB_BIN_CONTROL_UNK22__MASK 0x07c00000
2781#define A6XX_RB_BIN_CONTROL_UNK22__SHIFT 22
2782static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val)
2783{
2784 return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK;
2785}
2786
2787#define REG_A6XX_RB_RENDER_CNTL 0x00008801
2788#define A6XX_RB_RENDER_CNTL_UNK3 0x00000008
2789#define A6XX_RB_RENDER_CNTL_UNK4 0x00000010
2790#define A6XX_RB_RENDER_CNTL_UNK5__MASK 0x00000060
2791#define A6XX_RB_RENDER_CNTL_UNK5__SHIFT 5
2792static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val)
2793{
2794 return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK;
2795}
2796#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
2797#define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00001f00
2798#define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8
2799static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
2800{
2801 return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
2802}
2803#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2804#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2805#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2806static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2807{
2808 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2809}
2810
2811#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
2812#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2813#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2814static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2815{
2816 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2817}
2818#define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
2819#define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2
2820static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
2821{
2822 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
2823}
2824#define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
2825#define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3
2826static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
2827{
2828 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
2829}
2830
2831#define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
2832#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2833#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2834static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2835{
2836 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2837}
2838#define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2839
2840#define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804
2841#define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001
2842#define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
2843
2844#define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805
2845#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
2846#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
2847static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
2848{
2849 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
2850}
2851#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
2852#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
2853static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
2854{
2855 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
2856}
2857#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
2858#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
2859static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
2860{
2861 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
2862}
2863#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
2864#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
2865static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
2866{
2867 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
2868}
2869#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
2870#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
2871static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
2872{
2873 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
2874}
2875#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
2876#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
2877static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
2878{
2879 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
2880}
2881#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
2882#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
2883static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
2884{
2885 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
2886}
2887#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
2888#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
2889static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
2890{
2891 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
2892}
2893
2894#define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
2895#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
2896#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
2897static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
2898{
2899 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
2900}
2901#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
2902#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
2903static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
2904{
2905 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
2906}
2907#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
2908#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
2909static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
2910{
2911 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
2912}
2913#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
2914#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
2915static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
2916{
2917 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
2918}
2919#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
2920#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
2921static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
2922{
2923 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
2924}
2925#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
2926#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
2927static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
2928{
2929 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
2930}
2931#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
2932#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
2933static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
2934{
2935 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
2936}
2937#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
2938#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
2939static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
2940{
2941 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
2942}
2943
2944#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
2945#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
2946#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
2947#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
2948#define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008
2949#define A6XX_RB_RENDER_CONTROL0_UNK4 0x00000010
2950#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020
2951#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
2952#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
2953static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
2954{
2955 return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
2956}
2957#define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
2958
2959#define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
2960#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
2961#define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002
2962#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
2963#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
2964#define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010
2965#define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020
2966#define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
2967#define A6XX_RB_RENDER_CONTROL1_UNK7 0x00000080
2968#define A6XX_RB_RENDER_CONTROL1_UNK8 0x00000100
2969
2970#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
2971#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
2972#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
2973#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
2974#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008
2975
2976#define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
2977#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
2978#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
2979static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
2980{
2981 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
2982}
2983
2984#define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
2985#define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2986#define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2987static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
2988{
2989 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
2990}
2991#define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
2992#define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
2993static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
2994{
2995 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
2996}
2997#define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
2998#define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
2999static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3000{
3001 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3002}
3003#define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3004#define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
3005static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3006{
3007 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3008}
3009#define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3010#define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
3011static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3012{
3013 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3014}
3015#define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3016#define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
3017static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3018{
3019 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3020}
3021#define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3022#define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
3023static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3024{
3025 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3026}
3027#define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3028#define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
3029static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3030{
3031 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3032}
3033
3034#define REG_A6XX_RB_DITHER_CNTL 0x0000880e
3035#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
3036#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
3037static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3038{
3039 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3040}
3041#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
3042#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
3043static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3044{
3045 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3046}
3047#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
3048#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
3049static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3050{
3051 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3052}
3053#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
3054#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
3055static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3056{
3057 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3058}
3059#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
3060#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
3061static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3062{
3063 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3064}
3065#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
3066#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
3067static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3068{
3069 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3070}
3071#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
3072#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
3073static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3074{
3075 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3076}
3077#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
3078#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
3079static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3080{
3081 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3082}
3083
3084#define REG_A6XX_RB_SRGB_CNTL 0x0000880f
3085#define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
3086#define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
3087#define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
3088#define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
3089#define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
3090#define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
3091#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
3092#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
3093
3094#define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
3095#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3096
3097#define REG_A6XX_RB_UNKNOWN_8811 0x00008811
3098
3099#define REG_A6XX_RB_UNKNOWN_8818 0x00008818
3100
3101#define REG_A6XX_RB_UNKNOWN_8819 0x00008819
3102
3103#define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
3104
3105#define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
3106
3107#define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
3108
3109#define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
3110
3111#define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
3112
3113static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3114
3115static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3116#define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
3117#define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
3118#define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3119#define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3120#define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
3121static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3122{
3123 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3124}
3125#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3126#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
3127static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3128{
3129 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3130}
3131
3132static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3133#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3134#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
3135static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3136{
3137 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3138}
3139#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3140#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
3141static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3142{
3143 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3144}
3145#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3146#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
3147static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3148{
3149 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3150}
3151#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3152#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
3153static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3154{
3155 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3156}
3157#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3158#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3159static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3160{
3161 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3162}
3163#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3164#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
3165static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3166{
3167 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3168}
3169
3170static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3171#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3172#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
3173static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
3174{
3175 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3176}
3177#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3178#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
3179static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3180{
3181 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3182}
3183#define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400
3184#define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10
3185static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
3186{
3187 return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
3188}
3189#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3190#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
3191static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3192{
3193 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3194}
3195
3196static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3197#define A6XX_RB_MRT_PITCH__MASK 0x0000ffff
3198#define A6XX_RB_MRT_PITCH__SHIFT 0
3199static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3200{
3201 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3202}
3203
3204static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3205#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff
3206#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3207static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3208{
3209 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3210}
3211
3212static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3213#define A6XX_RB_MRT_BASE__MASK 0xffffffff
3214#define A6XX_RB_MRT_BASE__SHIFT 0
3215static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3216{
3217 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3218}
3219
3220static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3221#define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000
3222#define A6XX_RB_MRT_BASE_GMEM__SHIFT 12
3223static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
3224{
3225 return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
3226}
3227
3228#define REG_A6XX_RB_BLEND_RED_F32 0x00008860
3229#define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
3230#define A6XX_RB_BLEND_RED_F32__SHIFT 0
3231static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3232{
3233 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3234}
3235
3236#define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
3237#define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3238#define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
3239static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3240{
3241 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3242}
3243
3244#define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
3245#define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3246#define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
3247static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3248{
3249 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3250}
3251
3252#define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
3253#define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3254#define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
3255static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3256{
3257 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3258}
3259
3260#define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
3261#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3262#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
3263static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3264{
3265 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3266}
3267#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3268#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3269#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
3270static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3271{
3272 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3273}
3274
3275#define REG_A6XX_RB_BLEND_CNTL 0x00008865
3276#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3277#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
3278static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3279{
3280 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3281}
3282#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3283#define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
3284#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3285#define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800
3286#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3287#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
3288static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3289{
3290 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3291}
3292
3293#define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
3294#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
3295#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
3296static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
3297{
3298 return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
3299}
3300
3301#define REG_A6XX_RB_DEPTH_CNTL 0x00008871
3302#define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
3303#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3304#define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3305#define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
3306static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3307{
3308 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3309}
3310#define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020
3311#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
3312#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
3313
3314#define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
3315#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3316#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
3317static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
3318{
3319 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3320}
3321#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018
3322#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
3323static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
3324{
3325 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
3326}
3327
3328#define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
3329#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff
3330#define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
3331static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3332{
3333 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
3334}
3335
3336#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
3337#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff
3338#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
3339static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3340{
3341 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3342}
3343
3344#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
3345#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
3346#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
3347static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
3348{
3349 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
3350}
3351
3352#define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
3353#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000
3354#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12
3355static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
3356{
3357 return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
3358}
3359
3360#define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878
3361#define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff
3362#define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0
3363static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
3364{
3365 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
3366}
3367
3368#define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879
3369#define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff
3370#define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0
3371static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
3372{
3373 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
3374}
3375
3376#define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
3377#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3378#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3379#define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3380#define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3381#define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
3382static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3383{
3384 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
3385}
3386#define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3387#define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
3388static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3389{
3390 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
3391}
3392#define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3393#define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
3394static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3395{
3396 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3397}
3398#define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3399#define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
3400static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3401{
3402 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3403}
3404#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3405#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
3406static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3407{
3408 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3409}
3410#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3411#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
3412static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3413{
3414 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3415}
3416#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3417#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
3418static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3419{
3420 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3421}
3422#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3423#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
3424static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3425{
3426 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3427}
3428
3429#define REG_A6XX_RB_STENCIL_INFO 0x00008881
3430#define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3431#define A6XX_RB_STENCIL_INFO_UNK1 0x00000002
3432
3433#define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
3434#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff
3435#define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
3436static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3437{
3438 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3439}
3440
3441#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
3442#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff
3443#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
3444static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3445{
3446 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3447}
3448
3449#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
3450#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
3451#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
3452static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
3453{
3454 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
3455}
3456
3457#define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
3458#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000
3459#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12
3460static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
3461{
3462 return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
3463}
3464
3465#define REG_A6XX_RB_STENCILREF 0x00008887
3466#define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
3467#define A6XX_RB_STENCILREF_REF__SHIFT 0
3468static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3469{
3470 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3471}
3472#define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
3473#define A6XX_RB_STENCILREF_BFREF__SHIFT 8
3474static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
3475{
3476 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
3477}
3478
3479#define REG_A6XX_RB_STENCILMASK 0x00008888
3480#define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
3481#define A6XX_RB_STENCILMASK_MASK__SHIFT 0
3482static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3483{
3484 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3485}
3486#define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
3487#define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
3488static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
3489{
3490 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
3491}
3492
3493#define REG_A6XX_RB_STENCILWRMASK 0x00008889
3494#define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
3495#define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
3496static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3497{
3498 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3499}
3500#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
3501#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
3502static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
3503{
3504 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
3505}
3506
3507#define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
3508#define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff
3509#define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
3510static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3511{
3512 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3513}
3514#define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000
3515#define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
3516static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3517{
3518 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3519}
3520
3521#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
3522#define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001
3523#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3524
3525#define REG_A6XX_RB_LRZ_CNTL 0x00008898
3526#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
3527
3528#define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0
3529#define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff
3530#define A6XX_RB_Z_CLAMP_MIN__SHIFT 0
3531static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
3532{
3533 return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
3534}
3535
3536#define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1
3537#define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff
3538#define A6XX_RB_Z_CLAMP_MAX__SHIFT 0
3539static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
3540{
3541 return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
3542}
3543
3544#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
3545#define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff
3546#define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0
3547static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
3548{
3549 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
3550}
3551#define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000
3552#define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16
3553static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
3554{
3555 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
3556}
3557
3558#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
3559#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff
3560#define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
3561static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
3562{
3563 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
3564}
3565#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000
3566#define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
3567static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
3568{
3569 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
3570}
3571
3572#define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
3573#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff
3574#define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
3575static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
3576{
3577 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
3578}
3579#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000
3580#define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
3581static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
3582{
3583 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3584}
3585
3586#define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
3587#define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f
3588#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
3589static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
3590{
3591 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
3592}
3593#define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00
3594#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
3595static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
3596{
3597 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
3598}
3599
3600#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
3601#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff
3602#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
3603static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
3604{
3605 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
3606}
3607#define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000
3608#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
3609static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
3610{
3611 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
3612}
3613
3614#define REG_A6XX_RB_MSAA_CNTL 0x000088d5
3615#define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018
3616#define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3
3617static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3618{
3619 return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
3620}
3621
3622#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
3623#define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000
3624#define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12
3625static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
3626{
3627 return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
3628}
3629
3630#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
3631#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
3632#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
3633static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3634{
3635 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3636}
3637#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
3638#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
3639#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
3640static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3641{
3642 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
3643}
3644#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
3645#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
3646static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3647{
3648 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
3649}
3650#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
3651#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
3652static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
3653{
3654 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
3655}
3656#define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000
3657
3658#define REG_A6XX_RB_BLIT_DST 0x000088d8
3659#define A6XX_RB_BLIT_DST__MASK 0xffffffff
3660#define A6XX_RB_BLIT_DST__SHIFT 0
3661static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
3662{
3663 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
3664}
3665
3666#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
3667#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
3668#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
3669static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
3670{
3671 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
3672}
3673
3674#define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
3675#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff
3676#define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
3677static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3678{
3679 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3680}
3681
3682#define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
3683#define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff
3684#define A6XX_RB_BLIT_FLAG_DST__SHIFT 0
3685static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
3686{
3687 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
3688}
3689
3690#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
3691#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
3692#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
3693static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
3694{
3695 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
3696}
3697#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800
3698#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
3699static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
3700{
3701 return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
3702}
3703
3704#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
3705
3706#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
3707
3708#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
3709
3710#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
3711
3712#define REG_A6XX_RB_BLIT_INFO 0x000088e3
3713#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
3714#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
3715#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
3716#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
3717#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
3718#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
3719static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
3720{
3721 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
3722}
3723#define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300
3724#define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8
3725static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val)
3726{
3727 return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK;
3728}
3729#define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000
3730#define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12
3731static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val)
3732{
3733 return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK;
3734}
3735
3736#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
3737
3738#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1
3739#define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff
3740#define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0
3741static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
3742{
3743 return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
3744}
3745
3746#define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3
3747#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
3748#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
3749static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3750{
3751 return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
3752}
3753#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800
3754#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3755static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3756{
3757 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3758}
3759
3760#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
3761
3762#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
3763#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
3764#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
3765static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
3766{
3767 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
3768}
3769
3770#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
3771#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f
3772#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
3773static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3774{
3775 return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
3776}
3777#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700
3778#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8
3779static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
3780{
3781 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
3782}
3783#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800
3784#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3785static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3786{
3787 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3788}
3789
3790static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3791
3792static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
3793#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
3794#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
3795static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
3796{
3797 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
3798}
3799
3800static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
3801#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
3802#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
3803static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
3804{
3805 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
3806}
3807#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
3808#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
3809static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3810{
3811 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
3812}
3813
3814#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
3815#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
3816#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
3817static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
3818{
3819 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
3820}
3821
3822#define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
3823#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
3824#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
3825static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
3826{
3827 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
3828}
3829#define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK 0x00000078
3830#define A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT 3
3831static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val)
3832{
3833 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK3__MASK;
3834}
3835#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
3836#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
3837#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
3838static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
3839{
3840 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3841}
3842#define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
3843#define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000
3844#define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17
3845static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
3846{
3847 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
3848}
3849#define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000
3850#define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000
3851#define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20
3852static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
3853{
3854 return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
3855}
3856#define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
3857#define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24
3858static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
3859{
3860 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
3861}
3862#define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK 0x20000000
3863#define A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT 29
3864static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val)
3865{
3866 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK29__MASK;
3867}
3868
3869#define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01
3870
3871#define REG_A6XX_RB_2D_DST_INFO 0x00008c17
3872#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3873#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3874static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
3875{
3876 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
3877}
3878#define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
3879#define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
3880static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
3881{
3882 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
3883}
3884#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3885#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3886static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3887{
3888 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
3889}
3890#define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
3891#define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
3892#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
3893#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
3894static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3895{
3896 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
3897}
3898#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
3899#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
3900#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
3901#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
3902#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
3903#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
3904#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
3905#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
3906#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
3907static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
3908{
3909 return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
3910}
3911#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
3912
3913#define REG_A6XX_RB_2D_DST 0x00008c18
3914#define A6XX_RB_2D_DST__MASK 0xffffffff
3915#define A6XX_RB_2D_DST__SHIFT 0
3916static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
3917{
3918 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
3919}
3920
3921#define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a
3922#define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff
3923#define A6XX_RB_2D_DST_PITCH__SHIFT 0
3924static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
3925{
3926 return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
3927}
3928
3929#define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b
3930#define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff
3931#define A6XX_RB_2D_DST_PLANE1__SHIFT 0
3932static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
3933{
3934 return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
3935}
3936
3937#define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d
3938#define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff
3939#define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0
3940static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
3941{
3942 return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
3943}
3944
3945#define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
3946#define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff
3947#define A6XX_RB_2D_DST_PLANE2__SHIFT 0
3948static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
3949{
3950 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
3951}
3952
3953#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
3954#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
3955#define A6XX_RB_2D_DST_FLAGS__SHIFT 0
3956static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
3957{
3958 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
3959}
3960
3961#define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
3962#define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff
3963#define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
3964static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
3965{
3966 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
3967}
3968
3969#define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23
3970#define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff
3971#define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0
3972static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
3973{
3974 return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
3975}
3976
3977#define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25
3978#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff
3979#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0
3980static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
3981{
3982 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
3983}
3984
3985#define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
3986
3987#define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
3988
3989#define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
3990
3991#define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
3992
3993#define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
3994
3995#define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04
3996
3997#define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
3998
3999#define REG_A6XX_RB_CCU_CNTL 0x00008e07
4000#define A6XX_RB_CCU_CNTL_OFFSET__MASK 0xff800000
4001#define A6XX_RB_CCU_CNTL_OFFSET__SHIFT 23
4002static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val)
4003{
4004 return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK;
4005}
4006#define A6XX_RB_CCU_CNTL_GMEM 0x00400000
4007#define A6XX_RB_CCU_CNTL_UNK2 0x00000004
4008
4009#define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
4010#define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001
4011#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
4012#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
4013static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
4014{
4015 return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
4016}
4017#define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
4018#define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010
4019#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400
4020#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10
4021static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
4022{
4023 return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
4024}
4025#define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800
4026#define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000
4027#define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12
4028static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4029{
4030 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4031}
4032
4033static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
4034
4035static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
4036
4037#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4038
4039static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
4040
4041#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4042
4043#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
4044
4045#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
4046
4047#define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
4048#define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff
4049#define A6XX_RB_UNKNOWN_8E51__SHIFT 0
4050static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
4051{
4052 return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
4053}
4054
4055#define REG_A6XX_VPC_UNKNOWN_9100 0x00009100
4056
4057#define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101
4058#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4059#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0
4060static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4061{
4062 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
4063}
4064#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4065#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
4066static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4067{
4068 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4069}
4070#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4071#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
4072static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4073{
4074 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4075}
4076
4077#define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102
4078#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4079#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0
4080static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4081{
4082 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
4083}
4084#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4085#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
4086static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4087{
4088 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4089}
4090#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4091#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
4092static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4093{
4094 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4095}
4096
4097#define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103
4098#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4099#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0
4100static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4101{
4102 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
4103}
4104#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4105#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
4106static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4107{
4108 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4109}
4110#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4111#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
4112static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4113{
4114 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4115}
4116
4117#define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104
4118#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4119#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0
4120static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
4121{
4122 return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
4123}
4124#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4125#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8
4126static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
4127{
4128 return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
4129}
4130
4131#define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105
4132#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4133#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0
4134static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
4135{
4136 return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
4137}
4138#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4139#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8
4140static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
4141{
4142 return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
4143}
4144
4145#define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106
4146#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4147#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0
4148static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
4149{
4150 return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
4151}
4152#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4153#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8
4154static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4155{
4156 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4157}
4158
4159#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4160#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
4161#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
4162
4163#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4164#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
4165#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
4166static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4167{
4168 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4169}
4170
4171static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4172
4173static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4174
4175static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4176
4177static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4178
4179#define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
4180
4181#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
4182
4183static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4184
4185static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4186
4187#define REG_A6XX_VPC_SO_CNTL 0x00009216
4188#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
4189#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
4190static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
4191{
4192 return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
4193}
4194#define A6XX_VPC_SO_CNTL_RESET 0x00010000
4195
4196#define REG_A6XX_VPC_SO_PROG 0x00009217
4197#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
4198#define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
4199static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4200{
4201 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4202}
4203#define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
4204#define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
4205static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
4206{
4207 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
4208}
4209#define A6XX_VPC_SO_PROG_A_EN 0x00000800
4210#define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
4211#define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
4212static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
4213{
4214 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
4215}
4216#define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
4217#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
4218static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4219{
4220 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4221}
4222#define A6XX_VPC_SO_PROG_B_EN 0x00800000
4223
4224#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4225#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4226#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
4227static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4228{
4229 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4230}
4231
4232static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4233
4234static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4235#define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff
4236#define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0
4237static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4238{
4239 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4240}
4241
4242static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4243#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
4244#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
4245static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4246{
4247 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4248}
4249
4250static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }
4251
4252static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
4253#define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc
4254#define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2
4255static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
4256{
4257 return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
4258}
4259
4260static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
4261#define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff
4262#define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0
4263static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
4264{
4265 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
4266}
4267
4268#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
4269#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
4270
4271#define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
4272
4273#define REG_A6XX_VPC_VS_PACK 0x00009301
4274#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4275#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0
4276static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
4277{
4278 return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
4279}
4280#define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00
4281#define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8
4282static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
4283{
4284 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
4285}
4286#define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000
4287#define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16
4288static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
4289{
4290 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
4291}
4292#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
4293#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
4294static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
4295{
4296 return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
4297}
4298
4299#define REG_A6XX_VPC_GS_PACK 0x00009302
4300#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4301#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0
4302static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
4303{
4304 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
4305}
4306#define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00
4307#define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8
4308static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
4309{
4310 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
4311}
4312#define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000
4313#define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16
4314static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
4315{
4316 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
4317}
4318#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
4319#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
4320static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
4321{
4322 return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
4323}
4324
4325#define REG_A6XX_VPC_DS_PACK 0x00009303
4326#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4327#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0
4328static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
4329{
4330 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
4331}
4332#define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00
4333#define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8
4334static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
4335{
4336 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
4337}
4338#define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000
4339#define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16
4340static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
4341{
4342 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
4343}
4344#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
4345#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
4346static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
4347{
4348 return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
4349}
4350
4351#define REG_A6XX_VPC_CNTL_0 0x00009304
4352#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
4353#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
4354static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
4355{
4356 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
4357}
4358#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
4359#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
4360static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
4361{
4362 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
4363}
4364#define A6XX_VPC_CNTL_0_VARYING 0x00010000
4365#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
4366#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
4367static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
4368{
4369 return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
4370}
4371
4372#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
4373#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
4374#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
4375static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
4376{
4377 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
4378}
4379#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
4380#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
4381static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
4382{
4383 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
4384}
4385#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
4386#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
4387static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
4388{
4389 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
4390}
4391#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
4392#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
4393static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
4394{
4395 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
4396}
4397#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
4398#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
4399static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
4400{
4401 return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
4402}
4403
4404#define REG_A6XX_VPC_SO_DISABLE 0x00009306
4405#define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
4406
4407#define REG_A6XX_VPC_UNKNOWN_9600 0x00009600
4408
4409#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
4410
4411#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
4412
4413#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
4414
4415static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
4416
4417#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
4418
4419#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
4420#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
4421#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
4422static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
4423{
4424 return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
4425}
4426#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
4427#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
4428static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
4429{
4430 return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
4431}
4432
4433#define REG_A6XX_PC_TESS_CNTL 0x00009802
4434#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
4435#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
4436static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
4437{
4438 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
4439}
4440#define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c
4441#define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2
4442static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
4443{
4444 return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
4445}
4446
4447#define REG_A6XX_PC_RESTART_INDEX 0x00009803
4448
4449#define REG_A6XX_PC_MODE_CNTL 0x00009804
4450
4451#define REG_A6XX_PC_UNKNOWN_9805 0x00009805
4452
4453#define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806
4454
4455#define REG_A6XX_PC_DRAW_CMD 0x00009840
4456#define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff
4457#define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0
4458static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
4459{
4460 return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
4461}
4462
4463#define REG_A6XX_PC_DISPATCH_CMD 0x00009841
4464#define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
4465#define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0
4466static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
4467{
4468 return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
4469}
4470
4471#define REG_A6XX_PC_EVENT_CMD 0x00009842
4472#define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000
4473#define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16
4474static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
4475{
4476 return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
4477}
4478#define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
4479#define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
4480static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
4481{
4482 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
4483}
4484
4485#define REG_A6XX_PC_MARKER 0x00009880
4486
4487#define REG_A6XX_PC_POLYGON_MODE 0x00009981
4488#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
4489#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
4490static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4491{
4492 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
4493}
4494
4495#define REG_A6XX_PC_RASTER_CNTL 0x00009980
4496#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
4497#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
4498static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
4499{
4500 return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
4501}
4502#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
4503
4504#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
4505#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
4506#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
4507#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
4508#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
4509
4510#define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01
4511#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
4512#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
4513static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4514{
4515 return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4516}
4517#define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100
4518#define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200
4519#define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400
4520#define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800
4521#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
4522#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16
4523static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
4524{
4525 return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
4526}
4527
4528#define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02
4529#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
4530#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
4531static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4532{
4533 return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4534}
4535#define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100
4536#define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200
4537#define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400
4538#define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800
4539#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
4540#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16
4541static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
4542{
4543 return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
4544}
4545
4546#define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03
4547
4548#define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04
4549#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
4550#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
4551static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
4552{
4553 return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
4554}
4555#define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100
4556#define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200
4557#define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400
4558#define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800
4559#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
4560#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16
4561static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
4562{
4563 return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
4564}
4565
4566#define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05
4567#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
4568#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
4569static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
4570{
4571 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
4572}
4573#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
4574#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
4575static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
4576{
4577 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
4578}
4579#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
4580#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
4581static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
4582{
4583 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
4584}
4585#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000
4586#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18
4587static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
4588{
4589 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
4590}
4591
4592#define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
4593#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
4594#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
4595static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
4596{
4597 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
4598}
4599
4600#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
4601#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
4602#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
4603#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
4604#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
4605static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4606{
4607 return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
4608}
4609
4610#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
4611
4612#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
4613#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
4614#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
4615static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
4616{
4617 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
4618}
4619#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
4620#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
4621static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
4622{
4623 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
4624}
4625
4626#define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
4627
4628#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
4629
4630#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
4631
4632#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
4633
4634#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
4635
4636#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
4637#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
4638#define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0
4639static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
4640{
4641 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
4642}
4643
4644#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
4645#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
4646#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
4647static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
4648{
4649 return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
4650}
4651#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
4652#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
4653static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
4654{
4655 return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
4656}
4657#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
4658#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
4659static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
4660{
4661 return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
4662}
4663#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
4664#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
4665static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
4666{
4667 return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
4668}
4669#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
4670#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
4671static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
4672{
4673 return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
4674}
4675#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
4676#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
4677
4678#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
4679
4680#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
4681
4682#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
4683#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
4684#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
4685static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
4686{
4687 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
4688}
4689#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000
4690#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16
4691static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
4692{
4693 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
4694}
4695#define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000
4696#define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22
4697static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
4698{
4699 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
4700}
4701
4702#define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12
4703#define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff
4704#define A6XX_PC_BIN_PRIM_STRM__SHIFT 0
4705static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
4706{
4707 return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
4708}
4709
4710#define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
4711#define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff
4712#define A6XX_PC_BIN_DRAW_STRM__SHIFT 0
4713static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
4714{
4715 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
4716}
4717
4718#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
4719#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
4720
4721static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
4722
4723#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
4724
4725#define REG_A6XX_VFD_CONTROL_0 0x0000a000
4726#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
4727#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
4728static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
4729{
4730 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
4731}
4732#define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00
4733#define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8
4734static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
4735{
4736 return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
4737}
4738
4739#define REG_A6XX_VFD_CONTROL_1 0x0000a001
4740#define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
4741#define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
4742static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
4743{
4744 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
4745}
4746#define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
4747#define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
4748static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
4749{
4750 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
4751}
4752#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
4753#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
4754static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
4755{
4756 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
4757}
4758#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
4759#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
4760static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
4761{
4762 return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
4763}
4764
4765#define REG_A6XX_VFD_CONTROL_2 0x0000a002
4766#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
4767#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
4768static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
4769{
4770 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
4771}
4772#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
4773#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
4774static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
4775{
4776 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
4777}
4778
4779#define REG_A6XX_VFD_CONTROL_3 0x0000a003
4780#define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff
4781#define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0
4782static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val)
4783{
4784 return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK;
4785}
4786#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
4787#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
4788static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
4789{
4790 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
4791}
4792#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
4793#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
4794static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
4795{
4796 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
4797}
4798#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
4799#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
4800static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
4801{
4802 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
4803}
4804
4805#define REG_A6XX_VFD_CONTROL_4 0x0000a004
4806#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
4807#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
4808static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
4809{
4810 return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
4811}
4812
4813#define REG_A6XX_VFD_CONTROL_5 0x0000a005
4814#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
4815#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
4816static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
4817{
4818 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
4819}
4820#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
4821#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
4822static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
4823{
4824 return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
4825}
4826
4827#define REG_A6XX_VFD_CONTROL_6 0x0000a006
4828#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
4829
4830#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
4831#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
4832#define A6XX_VFD_MODE_CNTL_UNK1 0x00000002
4833#define A6XX_VFD_MODE_CNTL_UNK2 0x00000004
4834
4835#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
4836#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
4837#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
4838#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
4839#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
4840static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
4841{
4842 return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
4843}
4844
4845#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
4846#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
4847#define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
4848
4849#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
4850
4851#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
4852
4853static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4854
4855static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
4856#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
4857#define A6XX_VFD_FETCH_BASE__SHIFT 0
4858static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
4859{
4860 return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
4861}
4862
4863static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
4864
4865static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
4866
4867static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4868
4869static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
4870#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
4871#define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
4872static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
4873{
4874 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
4875}
4876#define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0
4877#define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5
4878static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
4879{
4880 return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
4881}
4882#define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
4883#define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
4884#define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
4885static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
4886{
4887 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
4888}
4889#define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
4890#define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
4891static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
4892{
4893 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
4894}
4895#define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
4896#define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
4897
4898static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
4899
4900static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4901
4902static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
4903#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
4904#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
4905static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
4906{
4907 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
4908}
4909#define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
4910#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
4911static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
4912{
4913 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
4914}
4915
4916#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
4917
4918#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
4919
4920static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
4921
4922#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
4923#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
4924#define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000
4925#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
4926#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
4927static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
4928{
4929 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
4930}
4931#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
4932#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
4933static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4934{
4935 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4936}
4937#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
4938#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
4939static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4940{
4941 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4942}
4943#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
4944#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
4945#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
4946static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4947{
4948 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4949}
4950
4951#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
4952
4953#define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802
4954#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
4955#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0
4956static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
4957{
4958 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
4959}
4960#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
4961#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
4962static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
4963{
4964 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
4965}
4966
4967static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4968
4969static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
4970#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
4971#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
4972static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4973{
4974 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
4975}
4976#define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
4977#define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
4978static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4979{
4980 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4981}
4982#define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
4983#define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
4984static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4985{
4986 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
4987}
4988#define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
4989#define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
4990static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4991{
4992 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4993}
4994
4995static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4996
4997static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
4998#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
4999#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
5000static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
5001{
5002 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
5003}
5004#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5005#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
5006static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
5007{
5008 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
5009}
5010#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5011#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
5012static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
5013{
5014 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
5015}
5016#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5017#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
5018static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
5019{
5020 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5021}
5022
5023#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
5024
5025#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
5026#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
5027#define A6XX_SP_VS_OBJ_START__SHIFT 0
5028static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
5029{
5030 return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
5031}
5032
5033#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
5034#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5035#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5036static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5037{
5038 return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5039}
5040#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5041#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5042static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5043{
5044 return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5045}
5046
5047#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
5048#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
5049#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
5050static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
5051{
5052 return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
5053}
5054
5055#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
5056#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5057#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5058static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5059{
5060 return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5061}
5062#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5063
5064#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5065
5066#define REG_A6XX_SP_VS_CONFIG 0x0000a823
5067#define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
5068#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
5069#define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
5070#define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
5071#define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
5072#define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
5073#define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
5074static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
5075{
5076 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
5077}
5078#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
5079#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
5080static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
5081{
5082 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5083}
5084#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
5085#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
5086static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5087{
5088 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
5089}
5090
5091#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5092
5093#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
5094#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5095#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5096static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5097{
5098 return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK;
5099}
5100
5101#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5102#define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000
5103#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
5104#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
5105static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5106{
5107 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
5108}
5109#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5110#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5111static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5112{
5113 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5114}
5115#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5116#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5117static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5118{
5119 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5120}
5121#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
5122#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5123#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5124static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5125{
5126 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5127}
5128
5129#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
5130
5131#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
5132
5133#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
5134
5135#define REG_A6XX_SP_HS_OBJ_START 0x0000a834
5136#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
5137#define A6XX_SP_HS_OBJ_START__SHIFT 0
5138static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
5139{
5140 return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
5141}
5142
5143#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
5144#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5145#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5146static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5147{
5148 return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5149}
5150#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5151#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5152static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5153{
5154 return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5155}
5156
5157#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
5158#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
5159#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
5160static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
5161{
5162 return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
5163}
5164
5165#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
5166#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5167#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5168static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5169{
5170 return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5171}
5172#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5173
5174#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5175
5176#define REG_A6XX_SP_HS_CONFIG 0x0000a83b
5177#define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
5178#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
5179#define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
5180#define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
5181#define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
5182#define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
5183#define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
5184static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
5185{
5186 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
5187}
5188#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
5189#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
5190static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
5191{
5192 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5193}
5194#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
5195#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
5196static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5197{
5198 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
5199}
5200
5201#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5202
5203#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
5204#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5205#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5206static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5207{
5208 return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK;
5209}
5210
5211#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5212#define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000
5213#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
5214#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
5215static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5216{
5217 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
5218}
5219#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5220#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5221static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5222{
5223 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5224}
5225#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5226#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5227static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5228{
5229 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5230}
5231#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
5232#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5233#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5234static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5235{
5236 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5237}
5238
5239#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
5240
5241#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5242#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5243#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0
5244static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5245{
5246 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5247}
5248#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5249#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
5250static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5251{
5252 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5253}
5254
5255static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5256
5257static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5258#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
5259#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
5260static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5261{
5262 return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
5263}
5264#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5265#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
5266static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
5267{
5268 return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
5269}
5270#define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
5271#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
5272static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
5273{
5274 return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
5275}
5276#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5277#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
5278static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
5279{
5280 return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
5281}
5282
5283static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5284
5285static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5286#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5287#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
5288static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
5289{
5290 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
5291}
5292#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5293#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
5294static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
5295{
5296 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
5297}
5298#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5299#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
5300static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
5301{
5302 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
5303}
5304#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5305#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
5306static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5307{
5308 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5309}
5310
5311#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
5312
5313#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
5314#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
5315#define A6XX_SP_DS_OBJ_START__SHIFT 0
5316static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
5317{
5318 return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
5319}
5320
5321#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
5322#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5323#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5324static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5325{
5326 return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5327}
5328#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5329#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5330static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5331{
5332 return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5333}
5334
5335#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
5336#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
5337#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
5338static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
5339{
5340 return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
5341}
5342
5343#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
5344#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5345#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5346static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5347{
5348 return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5349}
5350#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5351
5352#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5353
5354#define REG_A6XX_SP_DS_CONFIG 0x0000a863
5355#define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
5356#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
5357#define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
5358#define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
5359#define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
5360#define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
5361#define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
5362static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
5363{
5364 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
5365}
5366#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
5367#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
5368static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
5369{
5370 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5371}
5372#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
5373#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
5374static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5375{
5376 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
5377}
5378
5379#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5380
5381#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
5382#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5383#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5384static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5385{
5386 return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK;
5387}
5388
5389#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5390#define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000
5391#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
5392#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
5393static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5394{
5395 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
5396}
5397#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5398#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5399static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5400{
5401 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5402}
5403#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5404#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5405static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5406{
5407 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5408}
5409#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
5410#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5411#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5412static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5413{
5414 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5415}
5416
5417#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5418
5419#define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
5420
5421#define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873
5422#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5423#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0
5424static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
5425{
5426 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
5427}
5428#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5429#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
5430static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5431{
5432 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5433}
5434
5435static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5436
5437static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5438#define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff
5439#define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
5440static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
5441{
5442 return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
5443}
5444#define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5445#define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8
5446static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
5447{
5448 return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
5449}
5450#define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000
5451#define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
5452static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
5453{
5454 return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
5455}
5456#define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5457#define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24
5458static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
5459{
5460 return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
5461}
5462
5463static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5464
5465static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5466#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5467#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
5468static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
5469{
5470 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
5471}
5472#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5473#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
5474static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
5475{
5476 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
5477}
5478#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5479#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
5480static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
5481{
5482 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
5483}
5484#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5485#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
5486static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
5487{
5488 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
5489}
5490
5491#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
5492
5493#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
5494#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
5495#define A6XX_SP_GS_OBJ_START__SHIFT 0
5496static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
5497{
5498 return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
5499}
5500
5501#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
5502#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5503#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5504static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5505{
5506 return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5507}
5508#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5509#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5510static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5511{
5512 return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5513}
5514
5515#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
5516#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
5517#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
5518static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
5519{
5520 return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
5521}
5522
5523#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
5524#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5525#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5526static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5527{
5528 return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5529}
5530#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5531
5532#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
5533
5534#define REG_A6XX_SP_GS_CONFIG 0x0000a894
5535#define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
5536#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
5537#define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
5538#define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
5539#define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
5540#define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
5541#define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
5542static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
5543{
5544 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
5545}
5546#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
5547#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
5548static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
5549{
5550 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
5551}
5552#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
5553#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
5554static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
5555{
5556 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
5557}
5558
5559#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
5560
5561#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
5562#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5563#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5564static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5565{
5566 return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK;
5567}
5568
5569#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
5570#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
5571#define A6XX_SP_VS_TEX_SAMP__SHIFT 0
5572static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
5573{
5574 return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
5575}
5576
5577#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
5578#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
5579#define A6XX_SP_HS_TEX_SAMP__SHIFT 0
5580static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
5581{
5582 return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
5583}
5584
5585#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
5586#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
5587#define A6XX_SP_DS_TEX_SAMP__SHIFT 0
5588static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
5589{
5590 return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
5591}
5592
5593#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
5594#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
5595#define A6XX_SP_GS_TEX_SAMP__SHIFT 0
5596static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
5597{
5598 return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
5599}
5600
5601#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
5602#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
5603#define A6XX_SP_VS_TEX_CONST__SHIFT 0
5604static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
5605{
5606 return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
5607}
5608
5609#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
5610#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
5611#define A6XX_SP_HS_TEX_CONST__SHIFT 0
5612static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
5613{
5614 return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
5615}
5616
5617#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
5618#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
5619#define A6XX_SP_DS_TEX_CONST__SHIFT 0
5620static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
5621{
5622 return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
5623}
5624
5625#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
5626#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
5627#define A6XX_SP_GS_TEX_CONST__SHIFT 0
5628static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
5629{
5630 return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
5631}
5632
5633#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
5634#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5635#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
5636static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
5637{
5638 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
5639}
5640#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
5641#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
5642#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
5643#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
5644#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
5645#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
5646#define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000
5647#define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27
5648static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val)
5649{
5650 return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK;
5651}
5652#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
5653#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
5654#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
5655static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5656{
5657 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
5658}
5659#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5660#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5661static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5662{
5663 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5664}
5665#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5666#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5667static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5668{
5669 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5670}
5671#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
5672#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5673#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5674static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5675{
5676 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
5677}
5678
5679#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
5680
5681#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
5682
5683#define REG_A6XX_SP_FS_OBJ_START 0x0000a983
5684#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
5685#define A6XX_SP_FS_OBJ_START__SHIFT 0
5686static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
5687{
5688 return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
5689}
5690
5691#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
5692#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5693#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5694static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5695{
5696 return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5697}
5698#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5699#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
5700static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5701{
5702 return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5703}
5704
5705#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
5706#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
5707#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
5708static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
5709{
5710 return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
5711}
5712
5713#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
5714#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5715#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
5716static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5717{
5718 return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5719}
5720#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5721
5722#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
5723#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
5724#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
5725static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
5726{
5727 return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
5728}
5729#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
5730#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
5731#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
5732
5733#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
5734#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
5735#define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
5736#define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
5737#define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
5738#define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
5739#define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
5740#define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
5741#define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
5742
5743#define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
5744#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
5745#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
5746static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
5747{
5748 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
5749}
5750#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
5751#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
5752static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
5753{
5754 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
5755}
5756#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
5757#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
5758static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
5759{
5760 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
5761}
5762#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
5763#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
5764static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
5765{
5766 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
5767}
5768#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
5769#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
5770static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
5771{
5772 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
5773}
5774#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
5775#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
5776static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
5777{
5778 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
5779}
5780#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
5781#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
5782static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
5783{
5784 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
5785}
5786#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
5787#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
5788static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
5789{
5790 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
5791}
5792
5793#define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
5794#define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
5795#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
5796#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
5797static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
5798{
5799 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
5800}
5801#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
5802#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
5803static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
5804{
5805 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
5806}
5807#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000
5808#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24
5809static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
5810{
5811 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
5812}
5813
5814#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
5815#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
5816#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
5817static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
5818{
5819 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
5820}
5821
5822static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5823
5824static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
5825#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
5826#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
5827static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
5828{
5829 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
5830}
5831#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
5832
5833static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
5834
5835static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
5836#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
5837#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
5838static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
5839{
5840 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
5841}
5842#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
5843#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
5844#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
5845
5846#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
5847#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
5848#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
5849static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
5850{
5851 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
5852}
5853#define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008
5854#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0
5855#define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4
5856static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val)
5857{
5858 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK;
5859}
5860#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000
5861#define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12
5862static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val)
5863{
5864 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK;
5865}
5866
5867static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
5868
5869static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
5870#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
5871#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
5872static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
5873{
5874 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
5875}
5876#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780
5877#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
5878static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
5879{
5880 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
5881}
5882#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800
5883#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11
5884static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
5885{
5886 return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
5887}
5888#define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000
5889#define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16
5890static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
5891{
5892 return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
5893}
5894#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000
5895#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22
5896static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
5897{
5898 return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
5899}
5900#define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000
5901#define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000
5902#define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27
5903static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val)
5904{
5905 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
5906}
5907
5908static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
5909
5910static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
5911#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
5912#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
5913static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
5914{
5915 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
5916}
5917#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
5918#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
5919static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
5920{
5921 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
5922}
5923
5924#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
5925
5926#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
5927
5928#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
5929#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
5930#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
5931static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
5932{
5933 return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK;
5934}
5935
5936#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
5937#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
5938#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
5939static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
5940{
5941 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
5942}
5943#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
5944#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
5945#define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000
5946#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
5947#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
5948#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
5949static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5950{
5951 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
5952}
5953#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5954#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
5955static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5956{
5957 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5958}
5959#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5960#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
5961static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5962{
5963 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5964}
5965#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
5966#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5967#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
5968static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5969{
5970 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
5971}
5972
5973#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
5974#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
5975#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
5976static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
5977{
5978 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
5979}
5980#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
5981#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
5982
5983#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
5984
5985#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
5986
5987#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
5988#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
5989#define A6XX_SP_CS_OBJ_START__SHIFT 0
5990static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
5991{
5992 return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
5993}
5994
5995#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
5996#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5997#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
5998static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5999{
6000 return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6001}
6002#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6003#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
6004static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6005{
6006 return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6007}
6008
6009#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
6010#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
6011#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
6012static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
6013{
6014 return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
6015}
6016
6017#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
6018#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6019#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
6020static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6021{
6022 return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6023}
6024#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6025
6026#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6027
6028#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
6029#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
6030#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
6031#define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
6032#define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
6033#define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
6034#define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
6035#define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
6036static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6037{
6038 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6039}
6040#define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
6041#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
6042static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6043{
6044 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6045}
6046#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
6047#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
6048static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6049{
6050 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6051}
6052
6053#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6054
6055#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
6056#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
6057#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
6058static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
6059{
6060 return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK;
6061}
6062
6063#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
6064#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
6065#define A6XX_SP_FS_TEX_SAMP__SHIFT 0
6066static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
6067{
6068 return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
6069}
6070
6071#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
6072#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
6073#define A6XX_SP_CS_TEX_SAMP__SHIFT 0
6074static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
6075{
6076 return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
6077}
6078
6079#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
6080#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
6081#define A6XX_SP_FS_TEX_CONST__SHIFT 0
6082static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
6083{
6084 return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
6085}
6086
6087#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
6088#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
6089#define A6XX_SP_CS_TEX_CONST__SHIFT 0
6090static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
6091{
6092 return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
6093}
6094
6095static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6096
6097static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6098
6099#define REG_A6XX_SP_CS_IBO 0x0000a9f2
6100#define A6XX_SP_CS_IBO__MASK 0xffffffff
6101#define A6XX_SP_CS_IBO__SHIFT 0
6102static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
6103{
6104 return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
6105}
6106
6107#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6108
6109#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
6110#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
6111#define A6XX_SP_MODE_CONTROL_UNK1 0x00000002
6112#define A6XX_SP_MODE_CONTROL_UNK2 0x00000004
6113#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
6114
6115#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6116#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
6117#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
6118#define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
6119#define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
6120#define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
6121#define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
6122#define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
6123static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
6124{
6125 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
6126}
6127#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
6128#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
6129static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
6130{
6131 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6132}
6133#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
6134#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
6135static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6136{
6137 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6138}
6139
6140#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
6141
6142static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6143
6144static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6145
6146#define REG_A6XX_SP_IBO 0x0000ab1a
6147#define A6XX_SP_IBO__MASK 0xffffffff
6148#define A6XX_SP_IBO__SHIFT 0
6149static inline uint32_t A6XX_SP_IBO(uint32_t val)
6150{
6151 return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
6152}
6153
6154#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6155
6156#define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
6157#define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
6158#define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
6159#define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004
6160#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
6161#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3
6162static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
6163{
6164 return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
6165}
6166#define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800
6167#define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000
6168#define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
6169static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6170{
6171 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6172}
6173
6174#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
6175
6176#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
6177
6178#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
6179
6180#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
6181
6182#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
6183#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
6184
6185#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
6186#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
6187#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
6188#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
6189#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
6190#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
6191#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
6192
6193static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
6194
6195#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6196#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6197#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6198static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6199{
6200 return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
6201}
6202
6203#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6204
6205#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6206
6207#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
6208
6209#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
6210
6211#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6212#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
6213#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
6214static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6215{
6216 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6217}
6218#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
6219#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
6220static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
6221{
6222 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
6223}
6224
6225#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
6226#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
6227#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
6228static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6229{
6230 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
6231}
6232#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6233
6234#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6235#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6236#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
6237static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6238{
6239 return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
6240}
6241
6242#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6243#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
6244#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
6245
6246#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
6247#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
6248#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
6249static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
6250{
6251 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
6252}
6253#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
6254#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
6255static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
6256{
6257 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
6258}
6259#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
6260#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
6261static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
6262{
6263 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
6264}
6265#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
6266#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
6267static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
6268{
6269 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
6270}
6271#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
6272#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
6273static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
6274{
6275 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
6276}
6277#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
6278#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
6279static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
6280{
6281 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
6282}
6283#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
6284#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
6285static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
6286{
6287 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
6288}
6289#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
6290#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
6291static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
6292{
6293 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
6294}
6295
6296#define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306
6297#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
6298#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
6299static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
6300{
6301 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
6302}
6303#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
6304#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
6305static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
6306{
6307 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
6308}
6309#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
6310#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
6311static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
6312{
6313 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
6314}
6315#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
6316#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
6317static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
6318{
6319 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
6320}
6321#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
6322#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
6323static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
6324{
6325 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
6326}
6327#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
6328#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
6329static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
6330{
6331 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
6332}
6333#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
6334#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
6335static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
6336{
6337 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
6338}
6339#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
6340#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
6341static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6342{
6343 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6344}
6345
6346#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
6347#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
6348#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
6349static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
6350{
6351 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
6352}
6353#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6354#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
6355static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
6356{
6357 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
6358}
6359
6360#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
6361
6362#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
6363#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
6364#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
6365static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
6366{
6367 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
6368}
6369#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
6370#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
6371static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
6372{
6373 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
6374}
6375#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
6376#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
6377static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
6378{
6379 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
6380}
6381#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
6382#define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
6383#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
6384#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
6385static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6386{
6387 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6388}
6389#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6390#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
6391#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6392#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
6393#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6394#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
6395#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6396#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
6397#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
6398static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
6399{
6400 return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
6401}
6402#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
6403
6404#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
6405#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
6406#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
6407static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
6408{
6409 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
6410}
6411#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
6412#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
6413static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
6414{
6415 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
6416}
6417
6418#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
6419#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
6420#define A6XX_SP_PS_2D_SRC__SHIFT 0
6421static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
6422{
6423 return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
6424}
6425
6426#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
6427#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
6428#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
6429static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
6430{
6431 return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
6432}
6433#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
6434#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
6435static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
6436{
6437 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
6438}
6439
6440#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
6441#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
6442#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
6443static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
6444{
6445 return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
6446}
6447
6448#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
6449#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
6450#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
6451static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
6452{
6453 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
6454}
6455
6456#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
6457#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
6458#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
6459static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
6460{
6461 return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
6462}
6463
6464#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
6465#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
6466#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
6467static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
6468{
6469 return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
6470}
6471
6472#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
6473#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
6474#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
6475static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
6476{
6477 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
6478}
6479
6480#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
6481
6482#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
6483
6484#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
6485
6486#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
6487
6488#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
6489#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
6490#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
6491static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
6492{
6493 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
6494}
6495#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6496#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
6497static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
6498{
6499 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
6500}
6501
6502#define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600
6503
6504#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
6505
6506#define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
6507
6508#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
6509#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
6510#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
6511#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
6512static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
6513{
6514 return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
6515}
6516#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
6517#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
6518#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
6519static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
6520{
6521 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
6522}
6523#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
6524#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
6525static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
6526{
6527 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
6528}
6529
6530#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
6531
6532#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
6533
6534#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
6535
6536#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
6537
6538#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
6539
6540#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
6541
6542static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
6543
6544#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
6545#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
6546#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
6547static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
6548{
6549 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
6550}
6551#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
6552
6553#define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
6554#define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
6555#define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
6556static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
6557{
6558 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
6559}
6560#define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
6561
6562#define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
6563#define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
6564#define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
6565static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
6566{
6567 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
6568}
6569#define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
6570
6571#define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
6572#define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
6573#define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
6574static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
6575{
6576 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
6577}
6578#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
6579
6580#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
6581
6582#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
6583#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
6584#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
6585static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
6586{
6587 return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
6588}
6589
6590#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
6591
6592#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
6593#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
6594#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
6595static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
6596{
6597 return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
6598}
6599#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
6600#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
6601#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
6602static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
6603{
6604 return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
6605}
6606
6607#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
6608
6609#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
6610
6611#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
6612#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
6613#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
6614static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
6615{
6616 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
6617}
6618#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
6619#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
6620static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
6621{
6622 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
6623}
6624#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
6625#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
6626static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
6627{
6628 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
6629}
6630#define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
6631#define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
6632static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
6633{
6634 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
6635}
6636
6637#define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
6638#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
6639#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
6640static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
6641{
6642 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
6643}
6644#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
6645#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
6646static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
6647{
6648 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
6649}
6650#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
6651#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
6652static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
6653{
6654 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
6655}
6656#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
6657#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
6658static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
6659{
6660 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
6661}
6662
6663#define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
6664#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
6665#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
6666static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
6667{
6668 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
6669}
6670#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
6671#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
6672static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
6673{
6674 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
6675}
6676#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
6677#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
6678static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
6679{
6680 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
6681}
6682#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
6683#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
6684static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
6685{
6686 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
6687}
6688
6689#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
6690#define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff
6691#define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0
6692static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val)
6693{
6694 return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK;
6695}
6696#define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00
6697#define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8
6698static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val)
6699{
6700 return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK;
6701}
6702
6703#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
6704#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
6705#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
6706static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
6707{
6708 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
6709}
6710#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
6711
6712#define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
6713#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
6714#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
6715static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
6716{
6717 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
6718}
6719#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
6720#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
6721static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
6722{
6723 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
6724}
6725#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
6726#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
6727static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
6728{
6729 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
6730}
6731#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
6732#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
6733static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
6734{
6735 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
6736}
6737
6738#define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
6739#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
6740#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
6741static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
6742{
6743 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
6744}
6745
6746#define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
6747#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
6748#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
6749static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
6750{
6751 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
6752}
6753
6754#define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
6755#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
6756#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
6757static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
6758{
6759 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
6760}
6761
6762#define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
6763#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
6764#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
6765static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
6766{
6767 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
6768}
6769
6770#define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
6771#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
6772#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
6773static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
6774{
6775 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
6776}
6777
6778#define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
6779#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
6780#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
6781static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
6782{
6783 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
6784}
6785
6786#define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
6787#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
6788#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
6789static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
6790{
6791 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
6792}
6793#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
6794#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
6795static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
6796{
6797 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
6798}
6799#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
6800#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
6801static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
6802{
6803 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
6804}
6805#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6806#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
6807static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
6808{
6809 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
6810}
6811
6812#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
6813#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
6814#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
6815static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
6816{
6817 return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
6818}
6819#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
6820#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
6821#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
6822static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
6823{
6824 return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
6825}
6826#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
6827
6828#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
6829
6830#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
6831
6832#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
6833
6834#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
6835
6836#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
6837#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
6838#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
6839static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
6840{
6841 return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
6842}
6843
6844#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
6845
6846static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6847
6848static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
6849
6850#define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00
6851#define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff
6852#define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0
6853static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
6854{
6855 return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
6856}
6857
6858#define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01
6859#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
6860#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0
6861static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
6862{
6863 return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
6864}
6865
6866#define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02
6867#define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000
6868#define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16
6869static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
6870{
6871 return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
6872}
6873#define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f
6874#define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0
6875static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
6876{
6877 return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
6878}
6879
6880#define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08
6881#define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001
6882#define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002
6883#define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004
6884#define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008
6885#define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010
6886#define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020
6887#define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040
6888#define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080
6889#define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000
6890#define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100
6891#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00
6892#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9
6893static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
6894{
6895 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
6896}
6897#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000
6898#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14
6899static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
6900{
6901 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
6902}
6903
6904#define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
6905#define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
6906#define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
6907static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
6908{
6909 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
6910}
6911#define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
6912
6913#define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11
6914#define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001
6915
6916static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
6917
6918static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
6919
6920#define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80
6921#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
6922#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8
6923static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
6924{
6925 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
6926}
6927#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f
6928#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0
6929static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
6930{
6931 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
6932}
6933
6934#define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
6935
6936#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
6937
6938#define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04
6939
6940#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
6941
6942#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
6943
6944static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
6945
6946#define REG_A6XX_CP_EVENT_START 0x0000d600
6947#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
6948#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
6949static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
6950{
6951 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
6952}
6953
6954#define REG_A6XX_CP_EVENT_END 0x0000d601
6955#define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff
6956#define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0
6957static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
6958{
6959 return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
6960}
6961
6962#define REG_A6XX_CP_2D_EVENT_START 0x0000d700
6963#define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff
6964#define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0
6965static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
6966{
6967 return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
6968}
6969
6970#define REG_A6XX_CP_2D_EVENT_END 0x0000d701
6971#define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff
6972#define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0
6973static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
6974{
6975 return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
6976}
6977
6978#define REG_A6XX_TEX_SAMP_0 0x00000000
6979#define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
6980#define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
6981#define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
6982static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
6983{
6984 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
6985}
6986#define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
6987#define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
6988static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
6989{
6990 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
6991}
6992#define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
6993#define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
6994static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
6995{
6996 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
6997}
6998#define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
6999#define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
7000static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
7001{
7002 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
7003}
7004#define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
7005#define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
7006static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
7007{
7008 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
7009}
7010#define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
7011#define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
7012static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
7013{
7014 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
7015}
7016#define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
7017#define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
7018static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
7019{
7020 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
7021}
7022
7023#define REG_A6XX_TEX_SAMP_1 0x00000001
7024#define A6XX_TEX_SAMP_1_UNK0 0x00000001
7025#define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
7026#define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
7027static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
7028{
7029 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
7030}
7031#define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
7032#define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
7033#define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
7034#define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
7035#define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
7036static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
7037{
7038 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
7039}
7040#define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
7041#define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
7042static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
7043{
7044 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
7045}
7046
7047#define REG_A6XX_TEX_SAMP_2 0x00000002
7048#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
7049#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
7050static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7051{
7052 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7053}
7054#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7055#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
7056#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
7057static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
7058{
7059 return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
7060}
7061
7062#define REG_A6XX_TEX_SAMP_3 0x00000003
7063
7064#define REG_A6XX_TEX_CONST_0 0x00000000
7065#define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
7066#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
7067static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
7068{
7069 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
7070}
7071#define A6XX_TEX_CONST_0_SRGB 0x00000004
7072#define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
7073#define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
7074static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
7075{
7076 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
7077}
7078#define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
7079#define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
7080static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
7081{
7082 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
7083}
7084#define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
7085#define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
7086static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
7087{
7088 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
7089}
7090#define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
7091#define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
7092static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
7093{
7094 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
7095}
7096#define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
7097#define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
7098static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
7099{
7100 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
7101}
7102#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000
7103#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000
7104#define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
7105#define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
7106static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
7107{
7108 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
7109}
7110#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
7111#define A6XX_TEX_CONST_0_FMT__SHIFT 22
7112static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
7113{
7114 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
7115}
7116#define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
7117#define A6XX_TEX_CONST_0_SWAP__SHIFT 30
7118static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
7119{
7120 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
7121}
7122
7123#define REG_A6XX_TEX_CONST_1 0x00000001
7124#define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
7125#define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
7126static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
7127{
7128 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
7129}
7130#define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
7131#define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
7132static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
7133{
7134 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
7135}
7136
7137#define REG_A6XX_TEX_CONST_2 0x00000002
7138#define A6XX_TEX_CONST_2_UNK4 0x00000010
7139#define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
7140#define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
7141static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
7142{
7143 return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
7144}
7145#define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
7146#define A6XX_TEX_CONST_2_PITCH__SHIFT 7
7147static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
7148{
7149 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
7150}
7151#define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000
7152#define A6XX_TEX_CONST_2_TYPE__SHIFT 29
7153static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
7154{
7155 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
7156}
7157#define A6XX_TEX_CONST_2_UNK31 0x80000000
7158
7159#define REG_A6XX_TEX_CONST_3 0x00000003
7160#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
7161#define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
7162static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
7163{
7164 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
7165}
7166#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
7167#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
7168static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
7169{
7170 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
7171}
7172#define A6XX_TEX_CONST_3_TILE_ALL 0x08000000
7173#define A6XX_TEX_CONST_3_FLAG 0x10000000
7174
7175#define REG_A6XX_TEX_CONST_4 0x00000004
7176#define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
7177#define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
7178static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
7179{
7180 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
7181}
7182
7183#define REG_A6XX_TEX_CONST_5 0x00000005
7184#define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
7185#define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
7186static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
7187{
7188 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
7189}
7190#define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
7191#define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
7192static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
7193{
7194 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
7195}
7196
7197#define REG_A6XX_TEX_CONST_6 0x00000006
7198#define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00
7199#define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8
7200static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
7201{
7202 return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
7203}
7204
7205#define REG_A6XX_TEX_CONST_7 0x00000007
7206#define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
7207#define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
7208static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
7209{
7210 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
7211}
7212
7213#define REG_A6XX_TEX_CONST_8 0x00000008
7214#define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
7215#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
7216static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
7217{
7218 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
7219}
7220
7221#define REG_A6XX_TEX_CONST_9 0x00000009
7222#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
7223#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
7224static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7225{
7226 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7227}
7228
7229#define REG_A6XX_TEX_CONST_10 0x0000000a
7230#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
7231#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
7232static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
7233{
7234 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
7235}
7236#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00
7237#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8
7238static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
7239{
7240 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
7241}
7242#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000
7243#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12
7244static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
7245{
7246 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
7247}
7248
7249#define REG_A6XX_TEX_CONST_11 0x0000000b
7250
7251#define REG_A6XX_TEX_CONST_12 0x0000000c
7252
7253#define REG_A6XX_TEX_CONST_13 0x0000000d
7254
7255#define REG_A6XX_TEX_CONST_14 0x0000000e
7256
7257#define REG_A6XX_TEX_CONST_15 0x0000000f
7258
7259#define REG_A6XX_IBO_0 0x00000000
7260#define A6XX_IBO_0_TILE_MODE__MASK 0x00000003
7261#define A6XX_IBO_0_TILE_MODE__SHIFT 0
7262static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)
7263{
7264 return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK;
7265}
7266#define A6XX_IBO_0_FMT__MASK 0x3fc00000
7267#define A6XX_IBO_0_FMT__SHIFT 22
7268static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val)
7269{
7270 return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
7271}
7272
7273#define REG_A6XX_IBO_1 0x00000001
7274#define A6XX_IBO_1_WIDTH__MASK 0x00007fff
7275#define A6XX_IBO_1_WIDTH__SHIFT 0
7276static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
7277{
7278 return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
7279}
7280#define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000
7281#define A6XX_IBO_1_HEIGHT__SHIFT 15
7282static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
7283{
7284 return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
7285}
7286
7287#define REG_A6XX_IBO_2 0x00000002
7288#define A6XX_IBO_2_UNK4 0x00000010
7289#define A6XX_IBO_2_PITCH__MASK 0x1fffff80
7290#define A6XX_IBO_2_PITCH__SHIFT 7
7291static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
7292{
7293 return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
7294}
7295#define A6XX_IBO_2_TYPE__MASK 0x60000000
7296#define A6XX_IBO_2_TYPE__SHIFT 29
7297static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
7298{
7299 return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
7300}
7301#define A6XX_IBO_2_UNK31 0x80000000
7302
7303#define REG_A6XX_IBO_3 0x00000003
7304#define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff
7305#define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0
7306static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
7307{
7308 return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
7309}
7310#define A6XX_IBO_3_UNK27 0x08000000
7311#define A6XX_IBO_3_FLAG 0x10000000
7312
7313#define REG_A6XX_IBO_4 0x00000004
7314#define A6XX_IBO_4_BASE_LO__MASK 0xffffffff
7315#define A6XX_IBO_4_BASE_LO__SHIFT 0
7316static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
7317{
7318 return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
7319}
7320
7321#define REG_A6XX_IBO_5 0x00000005
7322#define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff
7323#define A6XX_IBO_5_BASE_HI__SHIFT 0
7324static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
7325{
7326 return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
7327}
7328#define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000
7329#define A6XX_IBO_5_DEPTH__SHIFT 17
7330static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
7331{
7332 return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
7333}
7334
7335#define REG_A6XX_IBO_6 0x00000006
7336
7337#define REG_A6XX_IBO_7 0x00000007
7338
7339#define REG_A6XX_IBO_8 0x00000008
7340
7341#define REG_A6XX_IBO_9 0x00000009
7342#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
7343#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
7344static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7345{
7346 return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7347}
7348
7349#define REG_A6XX_IBO_10 0x0000000a
7350#define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
7351#define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0
7352static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
7353{
7354 return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
7355}
7356
7357#define REG_A6XX_UBO_0 0x00000000
7358#define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
7359#define A6XX_UBO_0_BASE_LO__SHIFT 0
7360static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
7361{
7362 return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
7363}
7364
7365#define REG_A6XX_UBO_1 0x00000001
7366#define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
7367#define A6XX_UBO_1_BASE_HI__SHIFT 0
7368static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
7369{
7370 return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
7371}
7372#define A6XX_UBO_1_SIZE__MASK 0xfffe0000
7373#define A6XX_UBO_1_SIZE__SHIFT 17
7374static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
7375{
7376 return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
7377}
7378
7379#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
7380
7381#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
7382
7383#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
7384
7385#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
7386
7387#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
7388
7389#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
7390
7391#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
7392
7393#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
7394
7395#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
7396
7397#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
7398
7399#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
7400
7401#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
7402
7403#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
7404
7405#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
7406
7407#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
7408
7409#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
7410
7411#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
7412
7413#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
7414
7415#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
7416
7417#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
7418
7419#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
7420
7421#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
7422
7423#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
7424
7425#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
7426
7427#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
7428
7429#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
7430
7431#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
7432
7433#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
7434#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
7435#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
7436static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
7437{
7438 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
7439}
7440#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
7441#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
7442static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
7443{
7444 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
7445}
7446
7447#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
7448
7449#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
7450
7451#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
7452
7453#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
7454#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
7455#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
7456static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
7457{
7458 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
7459}
7460#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
7461#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
7462static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
7463{
7464 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
7465}
7466#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
7467#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
7468static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
7469{
7470 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
7471}
7472
7473#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
7474#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
7475#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
7476static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
7477{
7478 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
7479}
7480
7481#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
7482
7483#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
7484
7485#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
7486
7487#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
7488
7489#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
7490
7491#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
7492
7493#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
7494
7495#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
7496
7497#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
7498#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
7499#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
7500static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
7501{
7502 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
7503}
7504#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
7505#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
7506static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
7507{
7508 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
7509}
7510#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
7511#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
7512static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
7513{
7514 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
7515}
7516#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
7517#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
7518static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
7519{
7520 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
7521}
7522#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
7523#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
7524static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
7525{
7526 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
7527}
7528#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
7529#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
7530static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
7531{
7532 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
7533}
7534#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
7535#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
7536static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
7537{
7538 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
7539}
7540#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
7541#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
7542static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
7543{
7544 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
7545}
7546
7547#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
7548#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
7549#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
7550static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
7551{
7552 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
7553}
7554#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
7555#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
7556static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
7557{
7558 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
7559}
7560#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
7561#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
7562static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
7563{
7564 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
7565}
7566#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
7567#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
7568static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
7569{
7570 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
7571}
7572#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
7573#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
7574static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
7575{
7576 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
7577}
7578#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
7579#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
7580static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
7581{
7582 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
7583}
7584#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
7585#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
7586static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
7587{
7588 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
7589}
7590#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
7591#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
7592static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
7593{
7594 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
7595}
7596
7597#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
7598
7599#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
7600
7601#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
7602
7603#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
7604
7605
7606#endif /* A6XX_XML */