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  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2015 MediaTek Inc.
  4 * Authors:
  5 *	YT Shen <yt.shen@mediatek.com>
  6 *	CK Hu <ck.hu@mediatek.com>
  7 */
  8
  9#include <linux/clk.h>
 10#include <linux/of.h>
 11#include <linux/of_address.h>
 12#include <linux/of_platform.h>
 13#include <linux/platform_device.h>
 14#include <linux/soc/mediatek/mtk-cmdq.h>
 15#include <drm/drm_print.h>
 16
 17#include "mtk_disp_drv.h"
 18#include "mtk_drm_drv.h"
 19#include "mtk_drm_plane.h"
 20#include "mtk_drm_ddp_comp.h"
 21#include "mtk_drm_crtc.h"
 22
 23#define DISP_OD_EN				0x0000
 24#define DISP_OD_INTEN				0x0008
 25#define DISP_OD_INTSTA				0x000c
 26#define DISP_OD_CFG				0x0020
 27#define DISP_OD_SIZE				0x0030
 28#define DISP_DITHER_5				0x0114
 29#define DISP_DITHER_7				0x011c
 30#define DISP_DITHER_15				0x013c
 31#define DISP_DITHER_16				0x0140
 32
 33#define DISP_REG_UFO_START			0x0000
 34
 35#define DISP_AAL_EN				0x0000
 36#define DISP_AAL_SIZE				0x0030
 37#define DISP_AAL_OUTPUT_SIZE			0x04d8
 38
 39#define DISP_DITHER_EN				0x0000
 40#define DITHER_EN				BIT(0)
 41#define DISP_DITHER_CFG				0x0020
 42#define DITHER_RELAY_MODE			BIT(0)
 43#define DITHER_ENGINE_EN			BIT(1)
 44#define DISP_DITHER_SIZE			0x0030
 45
 46#define LUT_10BIT_MASK				0x03ff
 47
 48#define OD_RELAYMODE				BIT(0)
 49
 50#define UFO_BYPASS				BIT(2)
 51
 52#define AAL_EN					BIT(0)
 53
 54#define DISP_DITHERING				BIT(2)
 55#define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)
 56#define DITHER_OVFLW_BIT_R(x)			(((x) & 0x7) << 24)
 57#define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)
 58#define DITHER_ADD_RSHIFT_R(x)			(((x) & 0x7) << 16)
 59#define DITHER_NEW_BIT_MODE			BIT(0)
 60#define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)
 61#define DITHER_OVFLW_BIT_B(x)			(((x) & 0x7) << 24)
 62#define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)
 63#define DITHER_ADD_RSHIFT_B(x)			(((x) & 0x7) << 16)
 64#define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 65#define DITHER_OVFLW_BIT_G(x)			(((x) & 0x7) << 8)
 66#define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 67#define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)
 68
 69struct mtk_ddp_comp_dev {
 70	struct clk *clk;
 71	void __iomem *regs;
 72	struct cmdq_client_reg cmdq_reg;
 73};
 74
 75void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 76		   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
 77		   unsigned int offset)
 78{
 79#if IS_REACHABLE(CONFIG_MTK_CMDQ)
 80	if (cmdq_pkt)
 81		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
 82			       cmdq_reg->offset + offset, value);
 83	else
 84#endif
 85		writel(value, regs + offset);
 86}
 87
 88void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 89			   struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
 90			   unsigned int offset)
 91{
 92#if IS_REACHABLE(CONFIG_MTK_CMDQ)
 93	if (cmdq_pkt)
 94		cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
 95			       cmdq_reg->offset + offset, value);
 96	else
 97#endif
 98		writel_relaxed(value, regs + offset);
 99}
100
101void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
102			struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
103			unsigned int offset, unsigned int mask)
104{
105#if IS_REACHABLE(CONFIG_MTK_CMDQ)
106	if (cmdq_pkt) {
107		cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
108				    cmdq_reg->offset + offset, value, mask);
109	} else {
110#endif
111		u32 tmp = readl(regs + offset);
112
113		tmp = (tmp & ~mask) | (value & mask);
114		writel(tmp, regs + offset);
115#if IS_REACHABLE(CONFIG_MTK_CMDQ)
116	}
117#endif
118}
119
120static int mtk_ddp_clk_enable(struct device *dev)
121{
122	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
123
124	return clk_prepare_enable(priv->clk);
125}
126
127static void mtk_ddp_clk_disable(struct device *dev)
128{
129	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
130
131	clk_disable_unprepare(priv->clk);
132}
133
134void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
135			   unsigned int bpc, unsigned int cfg,
136			   unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
137{
138	/* If bpc equal to 0, the dithering function didn't be enabled */
139	if (bpc == 0)
140		return;
141
142	if (bpc >= MTK_MIN_BPC) {
143		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
144		mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
145		mtk_ddp_write(cmdq_pkt,
146			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
147			      DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
148			      DITHER_NEW_BIT_MODE,
149			      cmdq_reg, regs, DISP_DITHER_15);
150		mtk_ddp_write(cmdq_pkt,
151			      DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
152			      DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
153			      DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
154			      DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
155			      cmdq_reg, regs, DISP_DITHER_16);
156		mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
157	}
158}
159
160static void mtk_dither_set(struct device *dev, unsigned int bpc,
161		    unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
162{
163	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
164
165	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
166			      DISP_DITHERING, cmdq_pkt);
167}
168
169static void mtk_od_config(struct device *dev, unsigned int w,
170			  unsigned int h, unsigned int vrefresh,
171			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
172{
173	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
174
175	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE);
176	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG);
177	mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
178}
179
180static void mtk_od_start(struct device *dev)
181{
182	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
183
184	writel(1, priv->regs + DISP_OD_EN);
185}
186
187static void mtk_ufoe_start(struct device *dev)
188{
189	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
190
191	writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
192}
193
194static void mtk_aal_config(struct device *dev, unsigned int w,
195			   unsigned int h, unsigned int vrefresh,
196			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
197{
198	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
199
200	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
201	mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_OUTPUT_SIZE);
202}
203
204static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
205{
206	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
207
208	mtk_gamma_set_common(priv->regs, state);
209}
210
211static void mtk_aal_start(struct device *dev)
212{
213	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
214
215	writel(AAL_EN, priv->regs + DISP_AAL_EN);
216}
217
218static void mtk_aal_stop(struct device *dev)
219{
220	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
221
222	writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
223}
224
225static void mtk_dither_config(struct device *dev, unsigned int w,
226			      unsigned int h, unsigned int vrefresh,
227			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
228{
229	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
230
231	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
232	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
233	mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
234			      DITHER_ENGINE_EN, cmdq_pkt);
235}
236
237static void mtk_dither_start(struct device *dev)
238{
239	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
240
241	writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
242}
243
244static void mtk_dither_stop(struct device *dev)
245{
246	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
247
248	writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
249}
250
251static const struct mtk_ddp_comp_funcs ddp_aal = {
252	.clk_enable = mtk_ddp_clk_enable,
253	.clk_disable = mtk_ddp_clk_disable,
254	.gamma_set = mtk_aal_gamma_set,
255	.config = mtk_aal_config,
256	.start = mtk_aal_start,
257	.stop = mtk_aal_stop,
258};
259
260static const struct mtk_ddp_comp_funcs ddp_ccorr = {
261	.clk_enable = mtk_ccorr_clk_enable,
262	.clk_disable = mtk_ccorr_clk_disable,
263	.config = mtk_ccorr_config,
264	.start = mtk_ccorr_start,
265	.stop = mtk_ccorr_stop,
266	.ctm_set = mtk_ccorr_ctm_set,
267};
268
269static const struct mtk_ddp_comp_funcs ddp_color = {
270	.clk_enable = mtk_color_clk_enable,
271	.clk_disable = mtk_color_clk_disable,
272	.config = mtk_color_config,
273	.start = mtk_color_start,
274};
275
276static const struct mtk_ddp_comp_funcs ddp_dither = {
277	.clk_enable = mtk_ddp_clk_enable,
278	.clk_disable = mtk_ddp_clk_disable,
279	.config = mtk_dither_config,
280	.start = mtk_dither_start,
281	.stop = mtk_dither_stop,
282};
283
284static const struct mtk_ddp_comp_funcs ddp_dpi = {
285	.start = mtk_dpi_start,
286	.stop = mtk_dpi_stop,
287};
288
289static const struct mtk_ddp_comp_funcs ddp_dsi = {
290	.start = mtk_dsi_ddp_start,
291	.stop = mtk_dsi_ddp_stop,
292};
293
294static const struct mtk_ddp_comp_funcs ddp_gamma = {
295	.clk_enable = mtk_gamma_clk_enable,
296	.clk_disable = mtk_gamma_clk_disable,
297	.gamma_set = mtk_gamma_set,
298	.config = mtk_gamma_config,
299	.start = mtk_gamma_start,
300	.stop = mtk_gamma_stop,
301};
302
303static const struct mtk_ddp_comp_funcs ddp_od = {
304	.clk_enable = mtk_ddp_clk_enable,
305	.clk_disable = mtk_ddp_clk_disable,
306	.config = mtk_od_config,
307	.start = mtk_od_start,
308};
309
310static const struct mtk_ddp_comp_funcs ddp_ovl = {
311	.clk_enable = mtk_ovl_clk_enable,
312	.clk_disable = mtk_ovl_clk_disable,
313	.config = mtk_ovl_config,
314	.start = mtk_ovl_start,
315	.stop = mtk_ovl_stop,
316	.enable_vblank = mtk_ovl_enable_vblank,
317	.disable_vblank = mtk_ovl_disable_vblank,
318	.supported_rotations = mtk_ovl_supported_rotations,
319	.layer_nr = mtk_ovl_layer_nr,
320	.layer_check = mtk_ovl_layer_check,
321	.layer_config = mtk_ovl_layer_config,
322	.bgclr_in_on = mtk_ovl_bgclr_in_on,
323	.bgclr_in_off = mtk_ovl_bgclr_in_off,
324};
325
326static const struct mtk_ddp_comp_funcs ddp_rdma = {
327	.clk_enable = mtk_rdma_clk_enable,
328	.clk_disable = mtk_rdma_clk_disable,
329	.config = mtk_rdma_config,
330	.start = mtk_rdma_start,
331	.stop = mtk_rdma_stop,
332	.enable_vblank = mtk_rdma_enable_vblank,
333	.disable_vblank = mtk_rdma_disable_vblank,
334	.layer_nr = mtk_rdma_layer_nr,
335	.layer_config = mtk_rdma_layer_config,
336};
337
338static const struct mtk_ddp_comp_funcs ddp_ufoe = {
339	.clk_enable = mtk_ddp_clk_enable,
340	.clk_disable = mtk_ddp_clk_disable,
341	.start = mtk_ufoe_start,
342};
343
344static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
345	[MTK_DISP_OVL] = "ovl",
346	[MTK_DISP_OVL_2L] = "ovl-2l",
347	[MTK_DISP_RDMA] = "rdma",
348	[MTK_DISP_WDMA] = "wdma",
349	[MTK_DISP_COLOR] = "color",
350	[MTK_DISP_CCORR] = "ccorr",
351	[MTK_DISP_AAL] = "aal",
352	[MTK_DISP_GAMMA] = "gamma",
353	[MTK_DISP_DITHER] = "dither",
354	[MTK_DISP_UFOE] = "ufoe",
355	[MTK_DSI] = "dsi",
356	[MTK_DPI] = "dpi",
357	[MTK_DISP_PWM] = "pwm",
358	[MTK_DISP_MUTEX] = "mutex",
359	[MTK_DISP_OD] = "od",
360	[MTK_DISP_BLS] = "bls",
361};
362
363struct mtk_ddp_comp_match {
364	enum mtk_ddp_comp_type type;
365	int alias_id;
366	const struct mtk_ddp_comp_funcs *funcs;
367};
368
369static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
370	[DDP_COMPONENT_AAL0]	= { MTK_DISP_AAL,	0, &ddp_aal },
371	[DDP_COMPONENT_AAL1]	= { MTK_DISP_AAL,	1, &ddp_aal },
372	[DDP_COMPONENT_BLS]	= { MTK_DISP_BLS,	0, NULL },
373	[DDP_COMPONENT_CCORR]	= { MTK_DISP_CCORR,	0, &ddp_ccorr },
374	[DDP_COMPONENT_COLOR0]	= { MTK_DISP_COLOR,	0, &ddp_color },
375	[DDP_COMPONENT_COLOR1]	= { MTK_DISP_COLOR,	1, &ddp_color },
376	[DDP_COMPONENT_DITHER]	= { MTK_DISP_DITHER,	0, &ddp_dither },
377	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, &ddp_dpi },
378	[DDP_COMPONENT_DPI1]	= { MTK_DPI,		1, &ddp_dpi },
379	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, &ddp_dsi },
380	[DDP_COMPONENT_DSI1]	= { MTK_DSI,		1, &ddp_dsi },
381	[DDP_COMPONENT_DSI2]	= { MTK_DSI,		2, &ddp_dsi },
382	[DDP_COMPONENT_DSI3]	= { MTK_DSI,		3, &ddp_dsi },
383	[DDP_COMPONENT_GAMMA]	= { MTK_DISP_GAMMA,	0, &ddp_gamma },
384	[DDP_COMPONENT_OD0]	= { MTK_DISP_OD,	0, &ddp_od },
385	[DDP_COMPONENT_OD1]	= { MTK_DISP_OD,	1, &ddp_od },
386	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, &ddp_ovl },
387	[DDP_COMPONENT_OVL1]	= { MTK_DISP_OVL,	1, &ddp_ovl },
388	[DDP_COMPONENT_OVL_2L0]	= { MTK_DISP_OVL_2L,	0, &ddp_ovl },
389	[DDP_COMPONENT_OVL_2L1]	= { MTK_DISP_OVL_2L,	1, &ddp_ovl },
390	[DDP_COMPONENT_PWM0]	= { MTK_DISP_PWM,	0, NULL },
391	[DDP_COMPONENT_PWM1]	= { MTK_DISP_PWM,	1, NULL },
392	[DDP_COMPONENT_PWM2]	= { MTK_DISP_PWM,	2, NULL },
393	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0, &ddp_rdma },
394	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1, &ddp_rdma },
395	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2, &ddp_rdma },
396	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
397	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
398	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
399};
400
401static bool mtk_drm_find_comp_in_ddp(struct device *dev,
402				     const enum mtk_ddp_comp_id *path,
403				     unsigned int path_len,
404				     struct mtk_ddp_comp *ddp_comp)
405{
406	unsigned int i;
407
408	if (path == NULL)
409		return false;
410
411	for (i = 0U; i < path_len; i++)
412		if (dev == ddp_comp[path[i]].dev)
413			return true;
414
415	return false;
416}
417
418int mtk_ddp_comp_get_id(struct device_node *node,
419			enum mtk_ddp_comp_type comp_type)
420{
421	int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
422	int i;
423
424	for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
425		if (comp_type == mtk_ddp_matches[i].type &&
426		    (id < 0 || id == mtk_ddp_matches[i].alias_id))
427			return i;
428	}
429
430	return -EINVAL;
431}
432
433unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
434						struct device *dev)
435{
436	struct mtk_drm_private *private = drm->dev_private;
437	unsigned int ret = 0;
438
439	if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
440				     private->ddp_comp))
441		ret = BIT(0);
442	else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
443					  private->data->ext_len, private->ddp_comp))
444		ret = BIT(1);
445	else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
446					  private->data->third_len, private->ddp_comp))
447		ret = BIT(2);
448	else
449		DRM_INFO("Failed to find comp in ddp table\n");
450
451	return ret;
452}
453
454static int mtk_ddp_get_larb_dev(struct device_node *node, struct mtk_ddp_comp *comp,
455				struct device *dev)
456{
457	struct device_node *larb_node;
458	struct platform_device *larb_pdev;
459
460	larb_node = of_parse_phandle(node, "mediatek,larb", 0);
461	if (!larb_node) {
462		dev_err(dev, "Missing mediadek,larb phandle in %pOF node\n", node);
463		return -EINVAL;
464	}
465
466	larb_pdev = of_find_device_by_node(larb_node);
467	if (!larb_pdev) {
468		dev_warn(dev, "Waiting for larb device %pOF\n", larb_node);
469		of_node_put(larb_node);
470		return -EPROBE_DEFER;
471	}
472	of_node_put(larb_node);
473	comp->larb_dev = &larb_pdev->dev;
474
475	return 0;
476}
477
478int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
479		      enum mtk_ddp_comp_id comp_id)
480{
481	struct platform_device *comp_pdev;
482	enum mtk_ddp_comp_type type;
483	struct mtk_ddp_comp_dev *priv;
484	int ret;
485
486	if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
487		return -EINVAL;
488
489	type = mtk_ddp_matches[comp_id].type;
490
491	comp->id = comp_id;
492	comp->funcs = mtk_ddp_matches[comp_id].funcs;
493	comp_pdev = of_find_device_by_node(node);
494	if (!comp_pdev) {
495		DRM_INFO("Waiting for device %s\n", node->full_name);
496		return -EPROBE_DEFER;
497	}
498	comp->dev = &comp_pdev->dev;
499
500	/* Only DMA capable components need the LARB property */
501	if (type == MTK_DISP_OVL ||
502	    type == MTK_DISP_OVL_2L ||
503	    type == MTK_DISP_RDMA ||
504	    type == MTK_DISP_WDMA) {
505		ret = mtk_ddp_get_larb_dev(node, comp, comp->dev);
506		if (ret)
507			return ret;
508	}
509
510	if (type == MTK_DISP_BLS ||
511	    type == MTK_DISP_CCORR ||
512	    type == MTK_DISP_COLOR ||
513	    type == MTK_DISP_GAMMA ||
514	    type == MTK_DPI ||
515	    type == MTK_DSI ||
516	    type == MTK_DISP_OVL ||
517	    type == MTK_DISP_OVL_2L ||
518	    type == MTK_DISP_PWM ||
519	    type == MTK_DISP_RDMA)
520		return 0;
521
522	priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
523	if (!priv)
524		return -ENOMEM;
525
526	priv->regs = of_iomap(node, 0);
527	priv->clk = of_clk_get(node, 0);
528	if (IS_ERR(priv->clk))
529		return PTR_ERR(priv->clk);
530
531#if IS_REACHABLE(CONFIG_MTK_CMDQ)
532	ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
533	if (ret)
534		dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
535#endif
536
537	platform_set_drvdata(comp_pdev, priv);
538
539	return 0;
540}