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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
30#include <linux/debugfs.h>
31#include <linux/slab.h>
32#include "drmP.h"
33#include "drm.h"
34#include "intel_drv.h"
35#include "intel_ringbuffer.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
38
39#define DRM_I915_RING_DEBUG 1
40
41
42#if defined(CONFIG_DEBUG_FS)
43
44enum {
45 ACTIVE_LIST,
46 FLUSHING_LIST,
47 INACTIVE_LIST,
48 PINNED_LIST,
49 DEFERRED_FREE_LIST,
50};
51
52static const char *yesno(int v)
53{
54 return v ? "yes" : "no";
55}
56
57static int i915_capabilities(struct seq_file *m, void *data)
58{
59 struct drm_info_node *node = (struct drm_info_node *) m->private;
60 struct drm_device *dev = node->minor->dev;
61 const struct intel_device_info *info = INTEL_INFO(dev);
62
63 seq_printf(m, "gen: %d\n", info->gen);
64#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
65 B(is_mobile);
66 B(is_i85x);
67 B(is_i915g);
68 B(is_i945gm);
69 B(is_g33);
70 B(need_gfx_hws);
71 B(is_g4x);
72 B(is_pineview);
73 B(is_broadwater);
74 B(is_crestline);
75 B(has_fbc);
76 B(has_pipe_cxsr);
77 B(has_hotplug);
78 B(cursor_needs_physical);
79 B(has_overlay);
80 B(overlay_needs_physical);
81 B(supports_tv);
82 B(has_bsd_ring);
83 B(has_blt_ring);
84#undef B
85
86 return 0;
87}
88
89static const char *get_pin_flag(struct drm_i915_gem_object *obj)
90{
91 if (obj->user_pin_count > 0)
92 return "P";
93 else if (obj->pin_count > 0)
94 return "p";
95 else
96 return " ";
97}
98
99static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
100{
101 switch (obj->tiling_mode) {
102 default:
103 case I915_TILING_NONE: return " ";
104 case I915_TILING_X: return "X";
105 case I915_TILING_Y: return "Y";
106 }
107}
108
109static const char *cache_level_str(int type)
110{
111 switch (type) {
112 case I915_CACHE_NONE: return " uncached";
113 case I915_CACHE_LLC: return " snooped (LLC)";
114 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
115 default: return "";
116 }
117}
118
119static void
120describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
121{
122 seq_printf(m, "%p: %s%s %8zd %04x %04x %d %d%s%s%s",
123 &obj->base,
124 get_pin_flag(obj),
125 get_tiling_flag(obj),
126 obj->base.size,
127 obj->base.read_domains,
128 obj->base.write_domain,
129 obj->last_rendering_seqno,
130 obj->last_fenced_seqno,
131 cache_level_str(obj->cache_level),
132 obj->dirty ? " dirty" : "",
133 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
134 if (obj->base.name)
135 seq_printf(m, " (name: %d)", obj->base.name);
136 if (obj->fence_reg != I915_FENCE_REG_NONE)
137 seq_printf(m, " (fence: %d)", obj->fence_reg);
138 if (obj->gtt_space != NULL)
139 seq_printf(m, " (gtt offset: %08x, size: %08x)",
140 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
141 if (obj->pin_mappable || obj->fault_mappable) {
142 char s[3], *t = s;
143 if (obj->pin_mappable)
144 *t++ = 'p';
145 if (obj->fault_mappable)
146 *t++ = 'f';
147 *t = '\0';
148 seq_printf(m, " (%s mappable)", s);
149 }
150 if (obj->ring != NULL)
151 seq_printf(m, " (%s)", obj->ring->name);
152}
153
154static int i915_gem_object_list_info(struct seq_file *m, void *data)
155{
156 struct drm_info_node *node = (struct drm_info_node *) m->private;
157 uintptr_t list = (uintptr_t) node->info_ent->data;
158 struct list_head *head;
159 struct drm_device *dev = node->minor->dev;
160 drm_i915_private_t *dev_priv = dev->dev_private;
161 struct drm_i915_gem_object *obj;
162 size_t total_obj_size, total_gtt_size;
163 int count, ret;
164
165 ret = mutex_lock_interruptible(&dev->struct_mutex);
166 if (ret)
167 return ret;
168
169 switch (list) {
170 case ACTIVE_LIST:
171 seq_printf(m, "Active:\n");
172 head = &dev_priv->mm.active_list;
173 break;
174 case INACTIVE_LIST:
175 seq_printf(m, "Inactive:\n");
176 head = &dev_priv->mm.inactive_list;
177 break;
178 case PINNED_LIST:
179 seq_printf(m, "Pinned:\n");
180 head = &dev_priv->mm.pinned_list;
181 break;
182 case FLUSHING_LIST:
183 seq_printf(m, "Flushing:\n");
184 head = &dev_priv->mm.flushing_list;
185 break;
186 case DEFERRED_FREE_LIST:
187 seq_printf(m, "Deferred free:\n");
188 head = &dev_priv->mm.deferred_free_list;
189 break;
190 default:
191 mutex_unlock(&dev->struct_mutex);
192 return -EINVAL;
193 }
194
195 total_obj_size = total_gtt_size = count = 0;
196 list_for_each_entry(obj, head, mm_list) {
197 seq_printf(m, " ");
198 describe_obj(m, obj);
199 seq_printf(m, "\n");
200 total_obj_size += obj->base.size;
201 total_gtt_size += obj->gtt_space->size;
202 count++;
203 }
204 mutex_unlock(&dev->struct_mutex);
205
206 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
207 count, total_obj_size, total_gtt_size);
208 return 0;
209}
210
211#define count_objects(list, member) do { \
212 list_for_each_entry(obj, list, member) { \
213 size += obj->gtt_space->size; \
214 ++count; \
215 if (obj->map_and_fenceable) { \
216 mappable_size += obj->gtt_space->size; \
217 ++mappable_count; \
218 } \
219 } \
220} while(0)
221
222static int i915_gem_object_info(struct seq_file *m, void* data)
223{
224 struct drm_info_node *node = (struct drm_info_node *) m->private;
225 struct drm_device *dev = node->minor->dev;
226 struct drm_i915_private *dev_priv = dev->dev_private;
227 u32 count, mappable_count;
228 size_t size, mappable_size;
229 struct drm_i915_gem_object *obj;
230 int ret;
231
232 ret = mutex_lock_interruptible(&dev->struct_mutex);
233 if (ret)
234 return ret;
235
236 seq_printf(m, "%u objects, %zu bytes\n",
237 dev_priv->mm.object_count,
238 dev_priv->mm.object_memory);
239
240 size = count = mappable_size = mappable_count = 0;
241 count_objects(&dev_priv->mm.gtt_list, gtt_list);
242 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
243 count, mappable_count, size, mappable_size);
244
245 size = count = mappable_size = mappable_count = 0;
246 count_objects(&dev_priv->mm.active_list, mm_list);
247 count_objects(&dev_priv->mm.flushing_list, mm_list);
248 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
249 count, mappable_count, size, mappable_size);
250
251 size = count = mappable_size = mappable_count = 0;
252 count_objects(&dev_priv->mm.pinned_list, mm_list);
253 seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
254 count, mappable_count, size, mappable_size);
255
256 size = count = mappable_size = mappable_count = 0;
257 count_objects(&dev_priv->mm.inactive_list, mm_list);
258 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
259 count, mappable_count, size, mappable_size);
260
261 size = count = mappable_size = mappable_count = 0;
262 count_objects(&dev_priv->mm.deferred_free_list, mm_list);
263 seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
264 count, mappable_count, size, mappable_size);
265
266 size = count = mappable_size = mappable_count = 0;
267 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
268 if (obj->fault_mappable) {
269 size += obj->gtt_space->size;
270 ++count;
271 }
272 if (obj->pin_mappable) {
273 mappable_size += obj->gtt_space->size;
274 ++mappable_count;
275 }
276 }
277 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
278 mappable_count, mappable_size);
279 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
280 count, size);
281
282 seq_printf(m, "%zu [%zu] gtt total\n",
283 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
284
285 mutex_unlock(&dev->struct_mutex);
286
287 return 0;
288}
289
290static int i915_gem_gtt_info(struct seq_file *m, void* data)
291{
292 struct drm_info_node *node = (struct drm_info_node *) m->private;
293 struct drm_device *dev = node->minor->dev;
294 struct drm_i915_private *dev_priv = dev->dev_private;
295 struct drm_i915_gem_object *obj;
296 size_t total_obj_size, total_gtt_size;
297 int count, ret;
298
299 ret = mutex_lock_interruptible(&dev->struct_mutex);
300 if (ret)
301 return ret;
302
303 total_obj_size = total_gtt_size = count = 0;
304 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
305 seq_printf(m, " ");
306 describe_obj(m, obj);
307 seq_printf(m, "\n");
308 total_obj_size += obj->base.size;
309 total_gtt_size += obj->gtt_space->size;
310 count++;
311 }
312
313 mutex_unlock(&dev->struct_mutex);
314
315 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
316 count, total_obj_size, total_gtt_size);
317
318 return 0;
319}
320
321
322static int i915_gem_pageflip_info(struct seq_file *m, void *data)
323{
324 struct drm_info_node *node = (struct drm_info_node *) m->private;
325 struct drm_device *dev = node->minor->dev;
326 unsigned long flags;
327 struct intel_crtc *crtc;
328
329 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
330 const char pipe = pipe_name(crtc->pipe);
331 const char plane = plane_name(crtc->plane);
332 struct intel_unpin_work *work;
333
334 spin_lock_irqsave(&dev->event_lock, flags);
335 work = crtc->unpin_work;
336 if (work == NULL) {
337 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
338 pipe, plane);
339 } else {
340 if (!work->pending) {
341 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
342 pipe, plane);
343 } else {
344 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
345 pipe, plane);
346 }
347 if (work->enable_stall_check)
348 seq_printf(m, "Stall check enabled, ");
349 else
350 seq_printf(m, "Stall check waiting for page flip ioctl, ");
351 seq_printf(m, "%d prepares\n", work->pending);
352
353 if (work->old_fb_obj) {
354 struct drm_i915_gem_object *obj = work->old_fb_obj;
355 if (obj)
356 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
357 }
358 if (work->pending_flip_obj) {
359 struct drm_i915_gem_object *obj = work->pending_flip_obj;
360 if (obj)
361 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
362 }
363 }
364 spin_unlock_irqrestore(&dev->event_lock, flags);
365 }
366
367 return 0;
368}
369
370static int i915_gem_request_info(struct seq_file *m, void *data)
371{
372 struct drm_info_node *node = (struct drm_info_node *) m->private;
373 struct drm_device *dev = node->minor->dev;
374 drm_i915_private_t *dev_priv = dev->dev_private;
375 struct drm_i915_gem_request *gem_request;
376 int ret, count;
377
378 ret = mutex_lock_interruptible(&dev->struct_mutex);
379 if (ret)
380 return ret;
381
382 count = 0;
383 if (!list_empty(&dev_priv->ring[RCS].request_list)) {
384 seq_printf(m, "Render requests:\n");
385 list_for_each_entry(gem_request,
386 &dev_priv->ring[RCS].request_list,
387 list) {
388 seq_printf(m, " %d @ %d\n",
389 gem_request->seqno,
390 (int) (jiffies - gem_request->emitted_jiffies));
391 }
392 count++;
393 }
394 if (!list_empty(&dev_priv->ring[VCS].request_list)) {
395 seq_printf(m, "BSD requests:\n");
396 list_for_each_entry(gem_request,
397 &dev_priv->ring[VCS].request_list,
398 list) {
399 seq_printf(m, " %d @ %d\n",
400 gem_request->seqno,
401 (int) (jiffies - gem_request->emitted_jiffies));
402 }
403 count++;
404 }
405 if (!list_empty(&dev_priv->ring[BCS].request_list)) {
406 seq_printf(m, "BLT requests:\n");
407 list_for_each_entry(gem_request,
408 &dev_priv->ring[BCS].request_list,
409 list) {
410 seq_printf(m, " %d @ %d\n",
411 gem_request->seqno,
412 (int) (jiffies - gem_request->emitted_jiffies));
413 }
414 count++;
415 }
416 mutex_unlock(&dev->struct_mutex);
417
418 if (count == 0)
419 seq_printf(m, "No requests\n");
420
421 return 0;
422}
423
424static void i915_ring_seqno_info(struct seq_file *m,
425 struct intel_ring_buffer *ring)
426{
427 if (ring->get_seqno) {
428 seq_printf(m, "Current sequence (%s): %d\n",
429 ring->name, ring->get_seqno(ring));
430 seq_printf(m, "Waiter sequence (%s): %d\n",
431 ring->name, ring->waiting_seqno);
432 seq_printf(m, "IRQ sequence (%s): %d\n",
433 ring->name, ring->irq_seqno);
434 }
435}
436
437static int i915_gem_seqno_info(struct seq_file *m, void *data)
438{
439 struct drm_info_node *node = (struct drm_info_node *) m->private;
440 struct drm_device *dev = node->minor->dev;
441 drm_i915_private_t *dev_priv = dev->dev_private;
442 int ret, i;
443
444 ret = mutex_lock_interruptible(&dev->struct_mutex);
445 if (ret)
446 return ret;
447
448 for (i = 0; i < I915_NUM_RINGS; i++)
449 i915_ring_seqno_info(m, &dev_priv->ring[i]);
450
451 mutex_unlock(&dev->struct_mutex);
452
453 return 0;
454}
455
456
457static int i915_interrupt_info(struct seq_file *m, void *data)
458{
459 struct drm_info_node *node = (struct drm_info_node *) m->private;
460 struct drm_device *dev = node->minor->dev;
461 drm_i915_private_t *dev_priv = dev->dev_private;
462 int ret, i, pipe;
463
464 ret = mutex_lock_interruptible(&dev->struct_mutex);
465 if (ret)
466 return ret;
467
468 if (!HAS_PCH_SPLIT(dev)) {
469 seq_printf(m, "Interrupt enable: %08x\n",
470 I915_READ(IER));
471 seq_printf(m, "Interrupt identity: %08x\n",
472 I915_READ(IIR));
473 seq_printf(m, "Interrupt mask: %08x\n",
474 I915_READ(IMR));
475 for_each_pipe(pipe)
476 seq_printf(m, "Pipe %c stat: %08x\n",
477 pipe_name(pipe),
478 I915_READ(PIPESTAT(pipe)));
479 } else {
480 seq_printf(m, "North Display Interrupt enable: %08x\n",
481 I915_READ(DEIER));
482 seq_printf(m, "North Display Interrupt identity: %08x\n",
483 I915_READ(DEIIR));
484 seq_printf(m, "North Display Interrupt mask: %08x\n",
485 I915_READ(DEIMR));
486 seq_printf(m, "South Display Interrupt enable: %08x\n",
487 I915_READ(SDEIER));
488 seq_printf(m, "South Display Interrupt identity: %08x\n",
489 I915_READ(SDEIIR));
490 seq_printf(m, "South Display Interrupt mask: %08x\n",
491 I915_READ(SDEIMR));
492 seq_printf(m, "Graphics Interrupt enable: %08x\n",
493 I915_READ(GTIER));
494 seq_printf(m, "Graphics Interrupt identity: %08x\n",
495 I915_READ(GTIIR));
496 seq_printf(m, "Graphics Interrupt mask: %08x\n",
497 I915_READ(GTIMR));
498 }
499 seq_printf(m, "Interrupts received: %d\n",
500 atomic_read(&dev_priv->irq_received));
501 for (i = 0; i < I915_NUM_RINGS; i++) {
502 if (IS_GEN6(dev) || IS_GEN7(dev)) {
503 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
504 dev_priv->ring[i].name,
505 I915_READ_IMR(&dev_priv->ring[i]));
506 }
507 i915_ring_seqno_info(m, &dev_priv->ring[i]);
508 }
509 mutex_unlock(&dev->struct_mutex);
510
511 return 0;
512}
513
514static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
515{
516 struct drm_info_node *node = (struct drm_info_node *) m->private;
517 struct drm_device *dev = node->minor->dev;
518 drm_i915_private_t *dev_priv = dev->dev_private;
519 int i, ret;
520
521 ret = mutex_lock_interruptible(&dev->struct_mutex);
522 if (ret)
523 return ret;
524
525 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
526 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
527 for (i = 0; i < dev_priv->num_fence_regs; i++) {
528 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
529
530 seq_printf(m, "Fenced object[%2d] = ", i);
531 if (obj == NULL)
532 seq_printf(m, "unused");
533 else
534 describe_obj(m, obj);
535 seq_printf(m, "\n");
536 }
537
538 mutex_unlock(&dev->struct_mutex);
539 return 0;
540}
541
542static int i915_hws_info(struct seq_file *m, void *data)
543{
544 struct drm_info_node *node = (struct drm_info_node *) m->private;
545 struct drm_device *dev = node->minor->dev;
546 drm_i915_private_t *dev_priv = dev->dev_private;
547 struct intel_ring_buffer *ring;
548 const volatile u32 __iomem *hws;
549 int i;
550
551 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
552 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
553 if (hws == NULL)
554 return 0;
555
556 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
557 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
558 i * 4,
559 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
560 }
561 return 0;
562}
563
564static void i915_dump_object(struct seq_file *m,
565 struct io_mapping *mapping,
566 struct drm_i915_gem_object *obj)
567{
568 int page, page_count, i;
569
570 page_count = obj->base.size / PAGE_SIZE;
571 for (page = 0; page < page_count; page++) {
572 u32 *mem = io_mapping_map_wc(mapping,
573 obj->gtt_offset + page * PAGE_SIZE);
574 for (i = 0; i < PAGE_SIZE; i += 4)
575 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
576 io_mapping_unmap(mem);
577 }
578}
579
580static int i915_batchbuffer_info(struct seq_file *m, void *data)
581{
582 struct drm_info_node *node = (struct drm_info_node *) m->private;
583 struct drm_device *dev = node->minor->dev;
584 drm_i915_private_t *dev_priv = dev->dev_private;
585 struct drm_i915_gem_object *obj;
586 int ret;
587
588 ret = mutex_lock_interruptible(&dev->struct_mutex);
589 if (ret)
590 return ret;
591
592 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
593 if (obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) {
594 seq_printf(m, "--- gtt_offset = 0x%08x\n", obj->gtt_offset);
595 i915_dump_object(m, dev_priv->mm.gtt_mapping, obj);
596 }
597 }
598
599 mutex_unlock(&dev->struct_mutex);
600 return 0;
601}
602
603static int i915_ringbuffer_data(struct seq_file *m, void *data)
604{
605 struct drm_info_node *node = (struct drm_info_node *) m->private;
606 struct drm_device *dev = node->minor->dev;
607 drm_i915_private_t *dev_priv = dev->dev_private;
608 struct intel_ring_buffer *ring;
609 int ret;
610
611 ret = mutex_lock_interruptible(&dev->struct_mutex);
612 if (ret)
613 return ret;
614
615 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
616 if (!ring->obj) {
617 seq_printf(m, "No ringbuffer setup\n");
618 } else {
619 const u8 __iomem *virt = ring->virtual_start;
620 uint32_t off;
621
622 for (off = 0; off < ring->size; off += 4) {
623 uint32_t *ptr = (uint32_t *)(virt + off);
624 seq_printf(m, "%08x : %08x\n", off, *ptr);
625 }
626 }
627 mutex_unlock(&dev->struct_mutex);
628
629 return 0;
630}
631
632static int i915_ringbuffer_info(struct seq_file *m, void *data)
633{
634 struct drm_info_node *node = (struct drm_info_node *) m->private;
635 struct drm_device *dev = node->minor->dev;
636 drm_i915_private_t *dev_priv = dev->dev_private;
637 struct intel_ring_buffer *ring;
638
639 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
640 if (ring->size == 0)
641 return 0;
642
643 seq_printf(m, "Ring %s:\n", ring->name);
644 seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
645 seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
646 seq_printf(m, " Size : %08x\n", ring->size);
647 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
648 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
649 if (IS_GEN6(dev)) {
650 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
651 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
652 }
653 seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
654 seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
655
656 return 0;
657}
658
659static const char *ring_str(int ring)
660{
661 switch (ring) {
662 case RING_RENDER: return " render";
663 case RING_BSD: return " bsd";
664 case RING_BLT: return " blt";
665 default: return "";
666 }
667}
668
669static const char *pin_flag(int pinned)
670{
671 if (pinned > 0)
672 return " P";
673 else if (pinned < 0)
674 return " p";
675 else
676 return "";
677}
678
679static const char *tiling_flag(int tiling)
680{
681 switch (tiling) {
682 default:
683 case I915_TILING_NONE: return "";
684 case I915_TILING_X: return " X";
685 case I915_TILING_Y: return " Y";
686 }
687}
688
689static const char *dirty_flag(int dirty)
690{
691 return dirty ? " dirty" : "";
692}
693
694static const char *purgeable_flag(int purgeable)
695{
696 return purgeable ? " purgeable" : "";
697}
698
699static void print_error_buffers(struct seq_file *m,
700 const char *name,
701 struct drm_i915_error_buffer *err,
702 int count)
703{
704 seq_printf(m, "%s [%d]:\n", name, count);
705
706 while (count--) {
707 seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s",
708 err->gtt_offset,
709 err->size,
710 err->read_domains,
711 err->write_domain,
712 err->seqno,
713 pin_flag(err->pinned),
714 tiling_flag(err->tiling),
715 dirty_flag(err->dirty),
716 purgeable_flag(err->purgeable),
717 ring_str(err->ring),
718 cache_level_str(err->cache_level));
719
720 if (err->name)
721 seq_printf(m, " (name: %d)", err->name);
722 if (err->fence_reg != I915_FENCE_REG_NONE)
723 seq_printf(m, " (fence: %d)", err->fence_reg);
724
725 seq_printf(m, "\n");
726 err++;
727 }
728}
729
730static int i915_error_state(struct seq_file *m, void *unused)
731{
732 struct drm_info_node *node = (struct drm_info_node *) m->private;
733 struct drm_device *dev = node->minor->dev;
734 drm_i915_private_t *dev_priv = dev->dev_private;
735 struct drm_i915_error_state *error;
736 unsigned long flags;
737 int i, page, offset, elt;
738
739 spin_lock_irqsave(&dev_priv->error_lock, flags);
740 if (!dev_priv->first_error) {
741 seq_printf(m, "no error state collected\n");
742 goto out;
743 }
744
745 error = dev_priv->first_error;
746
747 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
748 error->time.tv_usec);
749 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
750 seq_printf(m, "EIR: 0x%08x\n", error->eir);
751 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
752 if (INTEL_INFO(dev)->gen >= 6) {
753 seq_printf(m, "ERROR: 0x%08x\n", error->error);
754 seq_printf(m, "Blitter command stream:\n");
755 seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
756 seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
757 seq_printf(m, " IPEHR: 0x%08x\n", error->bcs_ipehr);
758 seq_printf(m, " INSTDONE: 0x%08x\n", error->bcs_instdone);
759 seq_printf(m, " seqno: 0x%08x\n", error->bcs_seqno);
760 seq_printf(m, "Video (BSD) command stream:\n");
761 seq_printf(m, " ACTHD: 0x%08x\n", error->vcs_acthd);
762 seq_printf(m, " IPEIR: 0x%08x\n", error->vcs_ipeir);
763 seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr);
764 seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone);
765 seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno);
766 }
767 seq_printf(m, "Render command stream:\n");
768 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
769 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir);
770 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
771 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
772 if (INTEL_INFO(dev)->gen >= 4) {
773 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
774 seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
775 }
776 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm);
777 seq_printf(m, " seqno: 0x%08x\n", error->seqno);
778
779 for (i = 0; i < dev_priv->num_fence_regs; i++)
780 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
781
782 if (error->active_bo)
783 print_error_buffers(m, "Active",
784 error->active_bo,
785 error->active_bo_count);
786
787 if (error->pinned_bo)
788 print_error_buffers(m, "Pinned",
789 error->pinned_bo,
790 error->pinned_bo_count);
791
792 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
793 if (error->batchbuffer[i]) {
794 struct drm_i915_error_object *obj = error->batchbuffer[i];
795
796 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
797 dev_priv->ring[i].name,
798 obj->gtt_offset);
799 offset = 0;
800 for (page = 0; page < obj->page_count; page++) {
801 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
802 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
803 offset += 4;
804 }
805 }
806 }
807 }
808
809 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
810 if (error->ringbuffer[i]) {
811 struct drm_i915_error_object *obj = error->ringbuffer[i];
812 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
813 dev_priv->ring[i].name,
814 obj->gtt_offset);
815 offset = 0;
816 for (page = 0; page < obj->page_count; page++) {
817 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
818 seq_printf(m, "%08x : %08x\n",
819 offset,
820 obj->pages[page][elt]);
821 offset += 4;
822 }
823 }
824 }
825 }
826
827 if (error->overlay)
828 intel_overlay_print_error_state(m, error->overlay);
829
830 if (error->display)
831 intel_display_print_error_state(m, dev, error->display);
832
833out:
834 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
835
836 return 0;
837}
838
839static int i915_rstdby_delays(struct seq_file *m, void *unused)
840{
841 struct drm_info_node *node = (struct drm_info_node *) m->private;
842 struct drm_device *dev = node->minor->dev;
843 drm_i915_private_t *dev_priv = dev->dev_private;
844 u16 crstanddelay = I915_READ16(CRSTANDVID);
845
846 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
847
848 return 0;
849}
850
851static int i915_cur_delayinfo(struct seq_file *m, void *unused)
852{
853 struct drm_info_node *node = (struct drm_info_node *) m->private;
854 struct drm_device *dev = node->minor->dev;
855 drm_i915_private_t *dev_priv = dev->dev_private;
856 int ret;
857
858 if (IS_GEN5(dev)) {
859 u16 rgvswctl = I915_READ16(MEMSWCTL);
860 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
861
862 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
863 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
864 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
865 MEMSTAT_VID_SHIFT);
866 seq_printf(m, "Current P-state: %d\n",
867 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
868 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
869 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
870 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
871 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
872 u32 rpstat;
873 u32 rpupei, rpcurup, rpprevup;
874 u32 rpdownei, rpcurdown, rpprevdown;
875 int max_freq;
876
877 /* RPSTAT1 is in the GT power well */
878 ret = mutex_lock_interruptible(&dev->struct_mutex);
879 if (ret)
880 return ret;
881
882 gen6_gt_force_wake_get(dev_priv);
883
884 rpstat = I915_READ(GEN6_RPSTAT1);
885 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
886 rpcurup = I915_READ(GEN6_RP_CUR_UP);
887 rpprevup = I915_READ(GEN6_RP_PREV_UP);
888 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
889 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
890 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
891
892 gen6_gt_force_wake_put(dev_priv);
893 mutex_unlock(&dev->struct_mutex);
894
895 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
896 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
897 seq_printf(m, "Render p-state ratio: %d\n",
898 (gt_perf_status & 0xff00) >> 8);
899 seq_printf(m, "Render p-state VID: %d\n",
900 gt_perf_status & 0xff);
901 seq_printf(m, "Render p-state limit: %d\n",
902 rp_state_limits & 0xff);
903 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
904 GEN6_CAGF_SHIFT) * 50);
905 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
906 GEN6_CURICONT_MASK);
907 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
908 GEN6_CURBSYTAVG_MASK);
909 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
910 GEN6_CURBSYTAVG_MASK);
911 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
912 GEN6_CURIAVG_MASK);
913 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
914 GEN6_CURBSYTAVG_MASK);
915 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
916 GEN6_CURBSYTAVG_MASK);
917
918 max_freq = (rp_state_cap & 0xff0000) >> 16;
919 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
920 max_freq * 50);
921
922 max_freq = (rp_state_cap & 0xff00) >> 8;
923 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
924 max_freq * 50);
925
926 max_freq = rp_state_cap & 0xff;
927 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
928 max_freq * 50);
929 } else {
930 seq_printf(m, "no P-state info available\n");
931 }
932
933 return 0;
934}
935
936static int i915_delayfreq_table(struct seq_file *m, void *unused)
937{
938 struct drm_info_node *node = (struct drm_info_node *) m->private;
939 struct drm_device *dev = node->minor->dev;
940 drm_i915_private_t *dev_priv = dev->dev_private;
941 u32 delayfreq;
942 int i;
943
944 for (i = 0; i < 16; i++) {
945 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
946 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
947 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
948 }
949
950 return 0;
951}
952
953static inline int MAP_TO_MV(int map)
954{
955 return 1250 - (map * 25);
956}
957
958static int i915_inttoext_table(struct seq_file *m, void *unused)
959{
960 struct drm_info_node *node = (struct drm_info_node *) m->private;
961 struct drm_device *dev = node->minor->dev;
962 drm_i915_private_t *dev_priv = dev->dev_private;
963 u32 inttoext;
964 int i;
965
966 for (i = 1; i <= 32; i++) {
967 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
968 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
969 }
970
971 return 0;
972}
973
974static int i915_drpc_info(struct seq_file *m, void *unused)
975{
976 struct drm_info_node *node = (struct drm_info_node *) m->private;
977 struct drm_device *dev = node->minor->dev;
978 drm_i915_private_t *dev_priv = dev->dev_private;
979 u32 rgvmodectl = I915_READ(MEMMODECTL);
980 u32 rstdbyctl = I915_READ(RSTDBYCTL);
981 u16 crstandvid = I915_READ16(CRSTANDVID);
982
983 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
984 "yes" : "no");
985 seq_printf(m, "Boost freq: %d\n",
986 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
987 MEMMODE_BOOST_FREQ_SHIFT);
988 seq_printf(m, "HW control enabled: %s\n",
989 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
990 seq_printf(m, "SW control enabled: %s\n",
991 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
992 seq_printf(m, "Gated voltage change: %s\n",
993 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
994 seq_printf(m, "Starting frequency: P%d\n",
995 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
996 seq_printf(m, "Max P-state: P%d\n",
997 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
998 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
999 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1000 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1001 seq_printf(m, "Render standby enabled: %s\n",
1002 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1003 seq_printf(m, "Current RS state: ");
1004 switch (rstdbyctl & RSX_STATUS_MASK) {
1005 case RSX_STATUS_ON:
1006 seq_printf(m, "on\n");
1007 break;
1008 case RSX_STATUS_RC1:
1009 seq_printf(m, "RC1\n");
1010 break;
1011 case RSX_STATUS_RC1E:
1012 seq_printf(m, "RC1E\n");
1013 break;
1014 case RSX_STATUS_RS1:
1015 seq_printf(m, "RS1\n");
1016 break;
1017 case RSX_STATUS_RS2:
1018 seq_printf(m, "RS2 (RC6)\n");
1019 break;
1020 case RSX_STATUS_RS3:
1021 seq_printf(m, "RC3 (RC6+)\n");
1022 break;
1023 default:
1024 seq_printf(m, "unknown\n");
1025 break;
1026 }
1027
1028 return 0;
1029}
1030
1031static int i915_fbc_status(struct seq_file *m, void *unused)
1032{
1033 struct drm_info_node *node = (struct drm_info_node *) m->private;
1034 struct drm_device *dev = node->minor->dev;
1035 drm_i915_private_t *dev_priv = dev->dev_private;
1036
1037 if (!I915_HAS_FBC(dev)) {
1038 seq_printf(m, "FBC unsupported on this chipset\n");
1039 return 0;
1040 }
1041
1042 if (intel_fbc_enabled(dev)) {
1043 seq_printf(m, "FBC enabled\n");
1044 } else {
1045 seq_printf(m, "FBC disabled: ");
1046 switch (dev_priv->no_fbc_reason) {
1047 case FBC_NO_OUTPUT:
1048 seq_printf(m, "no outputs");
1049 break;
1050 case FBC_STOLEN_TOO_SMALL:
1051 seq_printf(m, "not enough stolen memory");
1052 break;
1053 case FBC_UNSUPPORTED_MODE:
1054 seq_printf(m, "mode not supported");
1055 break;
1056 case FBC_MODE_TOO_LARGE:
1057 seq_printf(m, "mode too large");
1058 break;
1059 case FBC_BAD_PLANE:
1060 seq_printf(m, "FBC unsupported on plane");
1061 break;
1062 case FBC_NOT_TILED:
1063 seq_printf(m, "scanout buffer not tiled");
1064 break;
1065 case FBC_MULTIPLE_PIPES:
1066 seq_printf(m, "multiple pipes are enabled");
1067 break;
1068 case FBC_MODULE_PARAM:
1069 seq_printf(m, "disabled per module param (default off)");
1070 break;
1071 default:
1072 seq_printf(m, "unknown reason");
1073 }
1074 seq_printf(m, "\n");
1075 }
1076 return 0;
1077}
1078
1079static int i915_sr_status(struct seq_file *m, void *unused)
1080{
1081 struct drm_info_node *node = (struct drm_info_node *) m->private;
1082 struct drm_device *dev = node->minor->dev;
1083 drm_i915_private_t *dev_priv = dev->dev_private;
1084 bool sr_enabled = false;
1085
1086 if (HAS_PCH_SPLIT(dev))
1087 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1088 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1089 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1090 else if (IS_I915GM(dev))
1091 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1092 else if (IS_PINEVIEW(dev))
1093 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1094
1095 seq_printf(m, "self-refresh: %s\n",
1096 sr_enabled ? "enabled" : "disabled");
1097
1098 return 0;
1099}
1100
1101static int i915_emon_status(struct seq_file *m, void *unused)
1102{
1103 struct drm_info_node *node = (struct drm_info_node *) m->private;
1104 struct drm_device *dev = node->minor->dev;
1105 drm_i915_private_t *dev_priv = dev->dev_private;
1106 unsigned long temp, chipset, gfx;
1107 int ret;
1108
1109 ret = mutex_lock_interruptible(&dev->struct_mutex);
1110 if (ret)
1111 return ret;
1112
1113 temp = i915_mch_val(dev_priv);
1114 chipset = i915_chipset_val(dev_priv);
1115 gfx = i915_gfx_val(dev_priv);
1116 mutex_unlock(&dev->struct_mutex);
1117
1118 seq_printf(m, "GMCH temp: %ld\n", temp);
1119 seq_printf(m, "Chipset power: %ld\n", chipset);
1120 seq_printf(m, "GFX power: %ld\n", gfx);
1121 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1122
1123 return 0;
1124}
1125
1126static int i915_ring_freq_table(struct seq_file *m, void *unused)
1127{
1128 struct drm_info_node *node = (struct drm_info_node *) m->private;
1129 struct drm_device *dev = node->minor->dev;
1130 drm_i915_private_t *dev_priv = dev->dev_private;
1131 int ret;
1132 int gpu_freq, ia_freq;
1133
1134 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1135 seq_printf(m, "unsupported on this chipset\n");
1136 return 0;
1137 }
1138
1139 ret = mutex_lock_interruptible(&dev->struct_mutex);
1140 if (ret)
1141 return ret;
1142
1143 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1144
1145 for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
1146 gpu_freq++) {
1147 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1148 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1149 GEN6_PCODE_READ_MIN_FREQ_TABLE);
1150 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
1151 GEN6_PCODE_READY) == 0, 10)) {
1152 DRM_ERROR("pcode read of freq table timed out\n");
1153 continue;
1154 }
1155 ia_freq = I915_READ(GEN6_PCODE_DATA);
1156 seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1157 }
1158
1159 mutex_unlock(&dev->struct_mutex);
1160
1161 return 0;
1162}
1163
1164static int i915_gfxec(struct seq_file *m, void *unused)
1165{
1166 struct drm_info_node *node = (struct drm_info_node *) m->private;
1167 struct drm_device *dev = node->minor->dev;
1168 drm_i915_private_t *dev_priv = dev->dev_private;
1169
1170 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1171
1172 return 0;
1173}
1174
1175static int i915_opregion(struct seq_file *m, void *unused)
1176{
1177 struct drm_info_node *node = (struct drm_info_node *) m->private;
1178 struct drm_device *dev = node->minor->dev;
1179 drm_i915_private_t *dev_priv = dev->dev_private;
1180 struct intel_opregion *opregion = &dev_priv->opregion;
1181 int ret;
1182
1183 ret = mutex_lock_interruptible(&dev->struct_mutex);
1184 if (ret)
1185 return ret;
1186
1187 if (opregion->header)
1188 seq_write(m, opregion->header, OPREGION_SIZE);
1189
1190 mutex_unlock(&dev->struct_mutex);
1191
1192 return 0;
1193}
1194
1195static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1196{
1197 struct drm_info_node *node = (struct drm_info_node *) m->private;
1198 struct drm_device *dev = node->minor->dev;
1199 drm_i915_private_t *dev_priv = dev->dev_private;
1200 struct intel_fbdev *ifbdev;
1201 struct intel_framebuffer *fb;
1202 int ret;
1203
1204 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1205 if (ret)
1206 return ret;
1207
1208 ifbdev = dev_priv->fbdev;
1209 fb = to_intel_framebuffer(ifbdev->helper.fb);
1210
1211 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1212 fb->base.width,
1213 fb->base.height,
1214 fb->base.depth,
1215 fb->base.bits_per_pixel);
1216 describe_obj(m, fb->obj);
1217 seq_printf(m, "\n");
1218
1219 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1220 if (&fb->base == ifbdev->helper.fb)
1221 continue;
1222
1223 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1224 fb->base.width,
1225 fb->base.height,
1226 fb->base.depth,
1227 fb->base.bits_per_pixel);
1228 describe_obj(m, fb->obj);
1229 seq_printf(m, "\n");
1230 }
1231
1232 mutex_unlock(&dev->mode_config.mutex);
1233
1234 return 0;
1235}
1236
1237static int i915_context_status(struct seq_file *m, void *unused)
1238{
1239 struct drm_info_node *node = (struct drm_info_node *) m->private;
1240 struct drm_device *dev = node->minor->dev;
1241 drm_i915_private_t *dev_priv = dev->dev_private;
1242 int ret;
1243
1244 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1245 if (ret)
1246 return ret;
1247
1248 if (dev_priv->pwrctx) {
1249 seq_printf(m, "power context ");
1250 describe_obj(m, dev_priv->pwrctx);
1251 seq_printf(m, "\n");
1252 }
1253
1254 if (dev_priv->renderctx) {
1255 seq_printf(m, "render context ");
1256 describe_obj(m, dev_priv->renderctx);
1257 seq_printf(m, "\n");
1258 }
1259
1260 mutex_unlock(&dev->mode_config.mutex);
1261
1262 return 0;
1263}
1264
1265static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1266{
1267 struct drm_info_node *node = (struct drm_info_node *) m->private;
1268 struct drm_device *dev = node->minor->dev;
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270
1271 seq_printf(m, "forcewake count = %d\n",
1272 atomic_read(&dev_priv->forcewake_count));
1273
1274 return 0;
1275}
1276
1277static int
1278i915_wedged_open(struct inode *inode,
1279 struct file *filp)
1280{
1281 filp->private_data = inode->i_private;
1282 return 0;
1283}
1284
1285static ssize_t
1286i915_wedged_read(struct file *filp,
1287 char __user *ubuf,
1288 size_t max,
1289 loff_t *ppos)
1290{
1291 struct drm_device *dev = filp->private_data;
1292 drm_i915_private_t *dev_priv = dev->dev_private;
1293 char buf[80];
1294 int len;
1295
1296 len = snprintf(buf, sizeof (buf),
1297 "wedged : %d\n",
1298 atomic_read(&dev_priv->mm.wedged));
1299
1300 if (len > sizeof (buf))
1301 len = sizeof (buf);
1302
1303 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1304}
1305
1306static ssize_t
1307i915_wedged_write(struct file *filp,
1308 const char __user *ubuf,
1309 size_t cnt,
1310 loff_t *ppos)
1311{
1312 struct drm_device *dev = filp->private_data;
1313 char buf[20];
1314 int val = 1;
1315
1316 if (cnt > 0) {
1317 if (cnt > sizeof (buf) - 1)
1318 return -EINVAL;
1319
1320 if (copy_from_user(buf, ubuf, cnt))
1321 return -EFAULT;
1322 buf[cnt] = 0;
1323
1324 val = simple_strtoul(buf, NULL, 0);
1325 }
1326
1327 DRM_INFO("Manually setting wedged to %d\n", val);
1328 i915_handle_error(dev, val);
1329
1330 return cnt;
1331}
1332
1333static const struct file_operations i915_wedged_fops = {
1334 .owner = THIS_MODULE,
1335 .open = i915_wedged_open,
1336 .read = i915_wedged_read,
1337 .write = i915_wedged_write,
1338 .llseek = default_llseek,
1339};
1340
1341static int
1342i915_max_freq_open(struct inode *inode,
1343 struct file *filp)
1344{
1345 filp->private_data = inode->i_private;
1346 return 0;
1347}
1348
1349static ssize_t
1350i915_max_freq_read(struct file *filp,
1351 char __user *ubuf,
1352 size_t max,
1353 loff_t *ppos)
1354{
1355 struct drm_device *dev = filp->private_data;
1356 drm_i915_private_t *dev_priv = dev->dev_private;
1357 char buf[80];
1358 int len;
1359
1360 len = snprintf(buf, sizeof (buf),
1361 "max freq: %d\n", dev_priv->max_delay * 50);
1362
1363 if (len > sizeof (buf))
1364 len = sizeof (buf);
1365
1366 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1367}
1368
1369static ssize_t
1370i915_max_freq_write(struct file *filp,
1371 const char __user *ubuf,
1372 size_t cnt,
1373 loff_t *ppos)
1374{
1375 struct drm_device *dev = filp->private_data;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 char buf[20];
1378 int val = 1;
1379
1380 if (cnt > 0) {
1381 if (cnt > sizeof (buf) - 1)
1382 return -EINVAL;
1383
1384 if (copy_from_user(buf, ubuf, cnt))
1385 return -EFAULT;
1386 buf[cnt] = 0;
1387
1388 val = simple_strtoul(buf, NULL, 0);
1389 }
1390
1391 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1392
1393 /*
1394 * Turbo will still be enabled, but won't go above the set value.
1395 */
1396 dev_priv->max_delay = val / 50;
1397
1398 gen6_set_rps(dev, val / 50);
1399
1400 return cnt;
1401}
1402
1403static const struct file_operations i915_max_freq_fops = {
1404 .owner = THIS_MODULE,
1405 .open = i915_max_freq_open,
1406 .read = i915_max_freq_read,
1407 .write = i915_max_freq_write,
1408 .llseek = default_llseek,
1409};
1410
1411static int
1412i915_cache_sharing_open(struct inode *inode,
1413 struct file *filp)
1414{
1415 filp->private_data = inode->i_private;
1416 return 0;
1417}
1418
1419static ssize_t
1420i915_cache_sharing_read(struct file *filp,
1421 char __user *ubuf,
1422 size_t max,
1423 loff_t *ppos)
1424{
1425 struct drm_device *dev = filp->private_data;
1426 drm_i915_private_t *dev_priv = dev->dev_private;
1427 char buf[80];
1428 u32 snpcr;
1429 int len;
1430
1431 mutex_lock(&dev_priv->dev->struct_mutex);
1432 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1433 mutex_unlock(&dev_priv->dev->struct_mutex);
1434
1435 len = snprintf(buf, sizeof (buf),
1436 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1437 GEN6_MBC_SNPCR_SHIFT);
1438
1439 if (len > sizeof (buf))
1440 len = sizeof (buf);
1441
1442 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1443}
1444
1445static ssize_t
1446i915_cache_sharing_write(struct file *filp,
1447 const char __user *ubuf,
1448 size_t cnt,
1449 loff_t *ppos)
1450{
1451 struct drm_device *dev = filp->private_data;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 char buf[20];
1454 u32 snpcr;
1455 int val = 1;
1456
1457 if (cnt > 0) {
1458 if (cnt > sizeof (buf) - 1)
1459 return -EINVAL;
1460
1461 if (copy_from_user(buf, ubuf, cnt))
1462 return -EFAULT;
1463 buf[cnt] = 0;
1464
1465 val = simple_strtoul(buf, NULL, 0);
1466 }
1467
1468 if (val < 0 || val > 3)
1469 return -EINVAL;
1470
1471 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1472
1473 /* Update the cache sharing policy here as well */
1474 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1475 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1476 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1477 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1478
1479 return cnt;
1480}
1481
1482static const struct file_operations i915_cache_sharing_fops = {
1483 .owner = THIS_MODULE,
1484 .open = i915_cache_sharing_open,
1485 .read = i915_cache_sharing_read,
1486 .write = i915_cache_sharing_write,
1487 .llseek = default_llseek,
1488};
1489
1490/* As the drm_debugfs_init() routines are called before dev->dev_private is
1491 * allocated we need to hook into the minor for release. */
1492static int
1493drm_add_fake_info_node(struct drm_minor *minor,
1494 struct dentry *ent,
1495 const void *key)
1496{
1497 struct drm_info_node *node;
1498
1499 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1500 if (node == NULL) {
1501 debugfs_remove(ent);
1502 return -ENOMEM;
1503 }
1504
1505 node->minor = minor;
1506 node->dent = ent;
1507 node->info_ent = (void *) key;
1508 list_add(&node->list, &minor->debugfs_nodes.list);
1509
1510 return 0;
1511}
1512
1513static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
1514{
1515 struct drm_device *dev = minor->dev;
1516 struct dentry *ent;
1517
1518 ent = debugfs_create_file("i915_wedged",
1519 S_IRUGO | S_IWUSR,
1520 root, dev,
1521 &i915_wedged_fops);
1522 if (IS_ERR(ent))
1523 return PTR_ERR(ent);
1524
1525 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
1526}
1527
1528static int i915_forcewake_open(struct inode *inode, struct file *file)
1529{
1530 struct drm_device *dev = inode->i_private;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 int ret;
1533
1534 if (!IS_GEN6(dev))
1535 return 0;
1536
1537 ret = mutex_lock_interruptible(&dev->struct_mutex);
1538 if (ret)
1539 return ret;
1540 gen6_gt_force_wake_get(dev_priv);
1541 mutex_unlock(&dev->struct_mutex);
1542
1543 return 0;
1544}
1545
1546int i915_forcewake_release(struct inode *inode, struct file *file)
1547{
1548 struct drm_device *dev = inode->i_private;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550
1551 if (!IS_GEN6(dev))
1552 return 0;
1553
1554 /*
1555 * It's bad that we can potentially hang userspace if struct_mutex gets
1556 * forever stuck. However, if we cannot acquire this lock it means that
1557 * almost certainly the driver has hung, is not unload-able. Therefore
1558 * hanging here is probably a minor inconvenience not to be seen my
1559 * almost every user.
1560 */
1561 mutex_lock(&dev->struct_mutex);
1562 gen6_gt_force_wake_put(dev_priv);
1563 mutex_unlock(&dev->struct_mutex);
1564
1565 return 0;
1566}
1567
1568static const struct file_operations i915_forcewake_fops = {
1569 .owner = THIS_MODULE,
1570 .open = i915_forcewake_open,
1571 .release = i915_forcewake_release,
1572};
1573
1574static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1575{
1576 struct drm_device *dev = minor->dev;
1577 struct dentry *ent;
1578
1579 ent = debugfs_create_file("i915_forcewake_user",
1580 S_IRUSR,
1581 root, dev,
1582 &i915_forcewake_fops);
1583 if (IS_ERR(ent))
1584 return PTR_ERR(ent);
1585
1586 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
1587}
1588
1589static int i915_max_freq_create(struct dentry *root, struct drm_minor *minor)
1590{
1591 struct drm_device *dev = minor->dev;
1592 struct dentry *ent;
1593
1594 ent = debugfs_create_file("i915_max_freq",
1595 S_IRUGO | S_IWUSR,
1596 root, dev,
1597 &i915_max_freq_fops);
1598 if (IS_ERR(ent))
1599 return PTR_ERR(ent);
1600
1601 return drm_add_fake_info_node(minor, ent, &i915_max_freq_fops);
1602}
1603
1604static int i915_cache_sharing_create(struct dentry *root, struct drm_minor *minor)
1605{
1606 struct drm_device *dev = minor->dev;
1607 struct dentry *ent;
1608
1609 ent = debugfs_create_file("i915_cache_sharing",
1610 S_IRUGO | S_IWUSR,
1611 root, dev,
1612 &i915_cache_sharing_fops);
1613 if (IS_ERR(ent))
1614 return PTR_ERR(ent);
1615
1616 return drm_add_fake_info_node(minor, ent, &i915_cache_sharing_fops);
1617}
1618
1619static struct drm_info_list i915_debugfs_list[] = {
1620 {"i915_capabilities", i915_capabilities, 0},
1621 {"i915_gem_objects", i915_gem_object_info, 0},
1622 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1623 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
1624 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
1625 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
1626 {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
1627 {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
1628 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1629 {"i915_gem_request", i915_gem_request_info, 0},
1630 {"i915_gem_seqno", i915_gem_seqno_info, 0},
1631 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1632 {"i915_gem_interrupt", i915_interrupt_info, 0},
1633 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1634 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1635 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1636 {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1637 {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1638 {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1639 {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1640 {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1641 {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
1642 {"i915_batchbuffers", i915_batchbuffer_info, 0},
1643 {"i915_error_state", i915_error_state, 0},
1644 {"i915_rstdby_delays", i915_rstdby_delays, 0},
1645 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1646 {"i915_delayfreq_table", i915_delayfreq_table, 0},
1647 {"i915_inttoext_table", i915_inttoext_table, 0},
1648 {"i915_drpc_info", i915_drpc_info, 0},
1649 {"i915_emon_status", i915_emon_status, 0},
1650 {"i915_ring_freq_table", i915_ring_freq_table, 0},
1651 {"i915_gfxec", i915_gfxec, 0},
1652 {"i915_fbc_status", i915_fbc_status, 0},
1653 {"i915_sr_status", i915_sr_status, 0},
1654 {"i915_opregion", i915_opregion, 0},
1655 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1656 {"i915_context_status", i915_context_status, 0},
1657 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
1658};
1659#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1660
1661int i915_debugfs_init(struct drm_minor *minor)
1662{
1663 int ret;
1664
1665 ret = i915_wedged_create(minor->debugfs_root, minor);
1666 if (ret)
1667 return ret;
1668
1669 ret = i915_forcewake_create(minor->debugfs_root, minor);
1670 if (ret)
1671 return ret;
1672 ret = i915_max_freq_create(minor->debugfs_root, minor);
1673 if (ret)
1674 return ret;
1675 ret = i915_cache_sharing_create(minor->debugfs_root, minor);
1676 if (ret)
1677 return ret;
1678
1679 return drm_debugfs_create_files(i915_debugfs_list,
1680 I915_DEBUGFS_ENTRIES,
1681 minor->debugfs_root, minor);
1682}
1683
1684void i915_debugfs_cleanup(struct drm_minor *minor)
1685{
1686 drm_debugfs_remove_files(i915_debugfs_list,
1687 I915_DEBUGFS_ENTRIES, minor);
1688 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
1689 1, minor);
1690 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1691 1, minor);
1692 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
1693 1, minor);
1694 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
1695 1, minor);
1696}
1697
1698#endif /* CONFIG_DEBUG_FS */
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/sched/mm.h>
30#include <linux/sort.h>
31
32#include <drm/drm_debugfs.h>
33
34#include "gem/i915_gem_context.h"
35#include "gt/intel_gt_buffer_pool.h"
36#include "gt/intel_gt_clock_utils.h"
37#include "gt/intel_gt.h"
38#include "gt/intel_gt_pm.h"
39#include "gt/intel_gt_requests.h"
40#include "gt/intel_reset.h"
41#include "gt/intel_rc6.h"
42#include "gt/intel_rps.h"
43#include "gt/intel_sseu_debugfs.h"
44
45#include "i915_debugfs.h"
46#include "i915_debugfs_params.h"
47#include "i915_irq.h"
48#include "i915_scheduler.h"
49#include "i915_trace.h"
50#include "intel_pm.h"
51#include "intel_sideband.h"
52
53static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
54{
55 return to_i915(node->minor->dev);
56}
57
58static int i915_capabilities(struct seq_file *m, void *data)
59{
60 struct drm_i915_private *i915 = node_to_i915(m->private);
61 struct drm_printer p = drm_seq_file_printer(m);
62
63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
64
65 intel_device_info_print_static(INTEL_INFO(i915), &p);
66 intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
67 intel_gt_info_print(&i915->gt.info, &p);
68 intel_driver_caps_print(&i915->caps, &p);
69
70 kernel_param_lock(THIS_MODULE);
71 i915_params_dump(&i915->params, &p);
72 kernel_param_unlock(THIS_MODULE);
73
74 return 0;
75}
76
77static char get_tiling_flag(struct drm_i915_gem_object *obj)
78{
79 switch (i915_gem_object_get_tiling(obj)) {
80 default:
81 case I915_TILING_NONE: return ' ';
82 case I915_TILING_X: return 'X';
83 case I915_TILING_Y: return 'Y';
84 }
85}
86
87static char get_global_flag(struct drm_i915_gem_object *obj)
88{
89 return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
90}
91
92static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
93{
94 return obj->mm.mapping ? 'M' : ' ';
95}
96
97static const char *
98stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
99{
100 size_t x = 0;
101
102 switch (page_sizes) {
103 case 0:
104 return "";
105 case I915_GTT_PAGE_SIZE_4K:
106 return "4K";
107 case I915_GTT_PAGE_SIZE_64K:
108 return "64K";
109 case I915_GTT_PAGE_SIZE_2M:
110 return "2M";
111 default:
112 if (!buf)
113 return "M";
114
115 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
116 x += snprintf(buf + x, len - x, "2M, ");
117 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
118 x += snprintf(buf + x, len - x, "64K, ");
119 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
120 x += snprintf(buf + x, len - x, "4K, ");
121 buf[x-2] = '\0';
122
123 return buf;
124 }
125}
126
127static const char *stringify_vma_type(const struct i915_vma *vma)
128{
129 if (i915_vma_is_ggtt(vma))
130 return "ggtt";
131
132 if (i915_vma_is_dpt(vma))
133 return "dpt";
134
135 return "ppgtt";
136}
137
138void
139i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
140{
141 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
142 struct intel_engine_cs *engine;
143 struct i915_vma *vma;
144 int pin_count = 0;
145
146 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
147 &obj->base,
148 get_tiling_flag(obj),
149 get_global_flag(obj),
150 get_pin_mapped_flag(obj),
151 obj->base.size / 1024,
152 obj->read_domains,
153 obj->write_domain,
154 i915_cache_level_str(dev_priv, obj->cache_level),
155 obj->mm.dirty ? " dirty" : "",
156 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
157 if (obj->base.name)
158 seq_printf(m, " (name: %d)", obj->base.name);
159
160 spin_lock(&obj->vma.lock);
161 list_for_each_entry(vma, &obj->vma.list, obj_link) {
162 if (!drm_mm_node_allocated(&vma->node))
163 continue;
164
165 spin_unlock(&obj->vma.lock);
166
167 if (i915_vma_is_pinned(vma))
168 pin_count++;
169
170 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
171 stringify_vma_type(vma),
172 vma->node.start, vma->node.size,
173 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
174 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
175 switch (vma->ggtt_view.type) {
176 case I915_GGTT_VIEW_NORMAL:
177 seq_puts(m, ", normal");
178 break;
179
180 case I915_GGTT_VIEW_PARTIAL:
181 seq_printf(m, ", partial [%08llx+%x]",
182 vma->ggtt_view.partial.offset << PAGE_SHIFT,
183 vma->ggtt_view.partial.size << PAGE_SHIFT);
184 break;
185
186 case I915_GGTT_VIEW_ROTATED:
187 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
188 vma->ggtt_view.rotated.plane[0].width,
189 vma->ggtt_view.rotated.plane[0].height,
190 vma->ggtt_view.rotated.plane[0].src_stride,
191 vma->ggtt_view.rotated.plane[0].dst_stride,
192 vma->ggtt_view.rotated.plane[0].offset,
193 vma->ggtt_view.rotated.plane[1].width,
194 vma->ggtt_view.rotated.plane[1].height,
195 vma->ggtt_view.rotated.plane[1].src_stride,
196 vma->ggtt_view.rotated.plane[1].dst_stride,
197 vma->ggtt_view.rotated.plane[1].offset);
198 break;
199
200 case I915_GGTT_VIEW_REMAPPED:
201 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
202 vma->ggtt_view.remapped.plane[0].width,
203 vma->ggtt_view.remapped.plane[0].height,
204 vma->ggtt_view.remapped.plane[0].src_stride,
205 vma->ggtt_view.remapped.plane[0].dst_stride,
206 vma->ggtt_view.remapped.plane[0].offset,
207 vma->ggtt_view.remapped.plane[1].width,
208 vma->ggtt_view.remapped.plane[1].height,
209 vma->ggtt_view.remapped.plane[1].src_stride,
210 vma->ggtt_view.remapped.plane[1].dst_stride,
211 vma->ggtt_view.remapped.plane[1].offset);
212 break;
213
214 default:
215 MISSING_CASE(vma->ggtt_view.type);
216 break;
217 }
218 }
219 if (vma->fence)
220 seq_printf(m, " , fence: %d", vma->fence->id);
221 seq_puts(m, ")");
222
223 spin_lock(&obj->vma.lock);
224 }
225 spin_unlock(&obj->vma.lock);
226
227 seq_printf(m, " (pinned x %d)", pin_count);
228 if (i915_gem_object_is_stolen(obj))
229 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
230 if (i915_gem_object_is_framebuffer(obj))
231 seq_printf(m, " (fb)");
232
233 engine = i915_gem_object_last_write_engine(obj);
234 if (engine)
235 seq_printf(m, " (%s)", engine->name);
236}
237
238static int i915_gem_object_info(struct seq_file *m, void *data)
239{
240 struct drm_i915_private *i915 = node_to_i915(m->private);
241 struct intel_memory_region *mr;
242 enum intel_region_id id;
243
244 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
245 i915->mm.shrink_count,
246 atomic_read(&i915->mm.free_count),
247 i915->mm.shrink_memory);
248 for_each_memory_region(mr, i915, id)
249 seq_printf(m, "%s: total:%pa, available:%pa bytes\n",
250 mr->name, &mr->total, &mr->avail);
251
252 return 0;
253}
254
255#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
256static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
257 size_t count, loff_t *pos)
258{
259 struct i915_gpu_coredump *error;
260 ssize_t ret;
261 void *buf;
262
263 error = file->private_data;
264 if (!error)
265 return 0;
266
267 /* Bounce buffer required because of kernfs __user API convenience. */
268 buf = kmalloc(count, GFP_KERNEL);
269 if (!buf)
270 return -ENOMEM;
271
272 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
273 if (ret <= 0)
274 goto out;
275
276 if (!copy_to_user(ubuf, buf, ret))
277 *pos += ret;
278 else
279 ret = -EFAULT;
280
281out:
282 kfree(buf);
283 return ret;
284}
285
286static int gpu_state_release(struct inode *inode, struct file *file)
287{
288 i915_gpu_coredump_put(file->private_data);
289 return 0;
290}
291
292static int i915_gpu_info_open(struct inode *inode, struct file *file)
293{
294 struct drm_i915_private *i915 = inode->i_private;
295 struct i915_gpu_coredump *gpu;
296 intel_wakeref_t wakeref;
297
298 gpu = NULL;
299 with_intel_runtime_pm(&i915->runtime_pm, wakeref)
300 gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
301 if (IS_ERR(gpu))
302 return PTR_ERR(gpu);
303
304 file->private_data = gpu;
305 return 0;
306}
307
308static const struct file_operations i915_gpu_info_fops = {
309 .owner = THIS_MODULE,
310 .open = i915_gpu_info_open,
311 .read = gpu_state_read,
312 .llseek = default_llseek,
313 .release = gpu_state_release,
314};
315
316static ssize_t
317i915_error_state_write(struct file *filp,
318 const char __user *ubuf,
319 size_t cnt,
320 loff_t *ppos)
321{
322 struct i915_gpu_coredump *error = filp->private_data;
323
324 if (!error)
325 return 0;
326
327 drm_dbg(&error->i915->drm, "Resetting error state\n");
328 i915_reset_error_state(error->i915);
329
330 return cnt;
331}
332
333static int i915_error_state_open(struct inode *inode, struct file *file)
334{
335 struct i915_gpu_coredump *error;
336
337 error = i915_first_error_state(inode->i_private);
338 if (IS_ERR(error))
339 return PTR_ERR(error);
340
341 file->private_data = error;
342 return 0;
343}
344
345static const struct file_operations i915_error_state_fops = {
346 .owner = THIS_MODULE,
347 .open = i915_error_state_open,
348 .read = gpu_state_read,
349 .write = i915_error_state_write,
350 .llseek = default_llseek,
351 .release = gpu_state_release,
352};
353#endif
354
355static int i915_frequency_info(struct seq_file *m, void *unused)
356{
357 struct drm_i915_private *dev_priv = node_to_i915(m->private);
358 struct intel_uncore *uncore = &dev_priv->uncore;
359 struct intel_rps *rps = &dev_priv->gt.rps;
360 intel_wakeref_t wakeref;
361
362 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
363
364 if (GRAPHICS_VER(dev_priv) == 5) {
365 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
366 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
367
368 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
369 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
370 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
371 MEMSTAT_VID_SHIFT);
372 seq_printf(m, "Current P-state: %d\n",
373 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
374 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
375 u32 rpmodectl, freq_sts;
376
377 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
378 seq_printf(m, "Video Turbo Mode: %s\n",
379 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
380 seq_printf(m, "HW control enabled: %s\n",
381 yesno(rpmodectl & GEN6_RP_ENABLE));
382 seq_printf(m, "SW control enabled: %s\n",
383 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
384 GEN6_RP_MEDIA_SW_MODE));
385
386 vlv_punit_get(dev_priv);
387 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
388 vlv_punit_put(dev_priv);
389
390 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
391 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
392
393 seq_printf(m, "actual GPU freq: %d MHz\n",
394 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
395
396 seq_printf(m, "current GPU freq: %d MHz\n",
397 intel_gpu_freq(rps, rps->cur_freq));
398
399 seq_printf(m, "max GPU freq: %d MHz\n",
400 intel_gpu_freq(rps, rps->max_freq));
401
402 seq_printf(m, "min GPU freq: %d MHz\n",
403 intel_gpu_freq(rps, rps->min_freq));
404
405 seq_printf(m, "idle GPU freq: %d MHz\n",
406 intel_gpu_freq(rps, rps->idle_freq));
407
408 seq_printf(m,
409 "efficient (RPe) frequency: %d MHz\n",
410 intel_gpu_freq(rps, rps->efficient_freq));
411 } else if (GRAPHICS_VER(dev_priv) >= 6) {
412 u32 rp_state_limits;
413 u32 gt_perf_status;
414 u32 rp_state_cap;
415 u32 rpmodectl, rpinclimit, rpdeclimit;
416 u32 rpstat, cagf, reqf;
417 u32 rpupei, rpcurup, rpprevup;
418 u32 rpdownei, rpcurdown, rpprevdown;
419 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
420 int max_freq;
421
422 rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS);
423 if (IS_GEN9_LP(dev_priv)) {
424 rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP);
425 gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS);
426 } else {
427 rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP);
428 gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS);
429 }
430
431 /* RPSTAT1 is in the GT power well */
432 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
433
434 reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ);
435 if (GRAPHICS_VER(dev_priv) >= 9)
436 reqf >>= 23;
437 else {
438 reqf &= ~GEN6_TURBO_DISABLE;
439 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
440 reqf >>= 24;
441 else
442 reqf >>= 25;
443 }
444 reqf = intel_gpu_freq(rps, reqf);
445
446 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
447 rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD);
448 rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD);
449
450 rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1);
451 rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
452 rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
453 rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
454 rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
455 rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
456 rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
457 cagf = intel_rps_read_actual_frequency(rps);
458
459 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
460
461 if (GRAPHICS_VER(dev_priv) >= 11) {
462 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
463 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
464 /*
465 * The equivalent to the PM ISR & IIR cannot be read
466 * without affecting the current state of the system
467 */
468 pm_isr = 0;
469 pm_iir = 0;
470 } else if (GRAPHICS_VER(dev_priv) >= 8) {
471 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2));
472 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2));
473 pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2));
474 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2));
475 } else {
476 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER);
477 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR);
478 pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR);
479 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
480 }
481 pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK);
482
483 seq_printf(m, "Video Turbo Mode: %s\n",
484 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
485 seq_printf(m, "HW control enabled: %s\n",
486 yesno(rpmodectl & GEN6_RP_ENABLE));
487 seq_printf(m, "SW control enabled: %s\n",
488 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
489 GEN6_RP_MEDIA_SW_MODE));
490
491 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
492 pm_ier, pm_imr, pm_mask);
493 if (GRAPHICS_VER(dev_priv) <= 10)
494 seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
495 pm_isr, pm_iir);
496 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
497 rps->pm_intrmsk_mbz);
498 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
499 seq_printf(m, "Render p-state ratio: %d\n",
500 (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
501 seq_printf(m, "Render p-state VID: %d\n",
502 gt_perf_status & 0xff);
503 seq_printf(m, "Render p-state limit: %d\n",
504 rp_state_limits & 0xff);
505 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
506 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
507 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
508 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
509 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
510 seq_printf(m, "CAGF: %dMHz\n", cagf);
511 seq_printf(m, "RP CUR UP EI: %d (%lldns)\n",
512 rpupei,
513 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei));
514 seq_printf(m, "RP CUR UP: %d (%lldun)\n",
515 rpcurup,
516 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup));
517 seq_printf(m, "RP PREV UP: %d (%lldns)\n",
518 rpprevup,
519 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup));
520 seq_printf(m, "Up threshold: %d%%\n",
521 rps->power.up_threshold);
522
523 seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n",
524 rpdownei,
525 intel_gt_pm_interval_to_ns(&dev_priv->gt,
526 rpdownei));
527 seq_printf(m, "RP CUR DOWN: %d (%lldns)\n",
528 rpcurdown,
529 intel_gt_pm_interval_to_ns(&dev_priv->gt,
530 rpcurdown));
531 seq_printf(m, "RP PREV DOWN: %d (%lldns)\n",
532 rpprevdown,
533 intel_gt_pm_interval_to_ns(&dev_priv->gt,
534 rpprevdown));
535 seq_printf(m, "Down threshold: %d%%\n",
536 rps->power.down_threshold);
537
538 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
539 rp_state_cap >> 16) & 0xff;
540 max_freq *= (IS_GEN9_BC(dev_priv) ||
541 GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
542 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
543 intel_gpu_freq(rps, max_freq));
544
545 max_freq = (rp_state_cap & 0xff00) >> 8;
546 max_freq *= (IS_GEN9_BC(dev_priv) ||
547 GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
548 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
549 intel_gpu_freq(rps, max_freq));
550
551 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
552 rp_state_cap >> 0) & 0xff;
553 max_freq *= (IS_GEN9_BC(dev_priv) ||
554 GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
555 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
556 intel_gpu_freq(rps, max_freq));
557 seq_printf(m, "Max overclocked frequency: %dMHz\n",
558 intel_gpu_freq(rps, rps->max_freq));
559
560 seq_printf(m, "Current freq: %d MHz\n",
561 intel_gpu_freq(rps, rps->cur_freq));
562 seq_printf(m, "Actual freq: %d MHz\n", cagf);
563 seq_printf(m, "Idle freq: %d MHz\n",
564 intel_gpu_freq(rps, rps->idle_freq));
565 seq_printf(m, "Min freq: %d MHz\n",
566 intel_gpu_freq(rps, rps->min_freq));
567 seq_printf(m, "Boost freq: %d MHz\n",
568 intel_gpu_freq(rps, rps->boost_freq));
569 seq_printf(m, "Max freq: %d MHz\n",
570 intel_gpu_freq(rps, rps->max_freq));
571 seq_printf(m,
572 "efficient (RPe) frequency: %d MHz\n",
573 intel_gpu_freq(rps, rps->efficient_freq));
574 } else {
575 seq_puts(m, "no P-state info available\n");
576 }
577
578 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
579 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
580 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
581
582 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
583 return 0;
584}
585
586static const char *swizzle_string(unsigned swizzle)
587{
588 switch (swizzle) {
589 case I915_BIT_6_SWIZZLE_NONE:
590 return "none";
591 case I915_BIT_6_SWIZZLE_9:
592 return "bit9";
593 case I915_BIT_6_SWIZZLE_9_10:
594 return "bit9/bit10";
595 case I915_BIT_6_SWIZZLE_9_11:
596 return "bit9/bit11";
597 case I915_BIT_6_SWIZZLE_9_10_11:
598 return "bit9/bit10/bit11";
599 case I915_BIT_6_SWIZZLE_9_17:
600 return "bit9/bit17";
601 case I915_BIT_6_SWIZZLE_9_10_17:
602 return "bit9/bit10/bit17";
603 case I915_BIT_6_SWIZZLE_UNKNOWN:
604 return "unknown";
605 }
606
607 return "bug";
608}
609
610static int i915_swizzle_info(struct seq_file *m, void *data)
611{
612 struct drm_i915_private *dev_priv = node_to_i915(m->private);
613 struct intel_uncore *uncore = &dev_priv->uncore;
614 intel_wakeref_t wakeref;
615
616 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
617 swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
618 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
619 swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
620
621 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
622 seq_puts(m, "L-shaped memory detected\n");
623
624 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
625 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
626 return 0;
627
628 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
629
630 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
631 seq_printf(m, "DDC = 0x%08x\n",
632 intel_uncore_read(uncore, DCC));
633 seq_printf(m, "DDC2 = 0x%08x\n",
634 intel_uncore_read(uncore, DCC2));
635 seq_printf(m, "C0DRB3 = 0x%04x\n",
636 intel_uncore_read16(uncore, C0DRB3_BW));
637 seq_printf(m, "C1DRB3 = 0x%04x\n",
638 intel_uncore_read16(uncore, C1DRB3_BW));
639 } else if (INTEL_GEN(dev_priv) >= 6) {
640 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
641 intel_uncore_read(uncore, MAD_DIMM_C0));
642 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
643 intel_uncore_read(uncore, MAD_DIMM_C1));
644 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
645 intel_uncore_read(uncore, MAD_DIMM_C2));
646 seq_printf(m, "TILECTL = 0x%08x\n",
647 intel_uncore_read(uncore, TILECTL));
648 if (GRAPHICS_VER(dev_priv) >= 8)
649 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
650 intel_uncore_read(uncore, GAMTARBMODE));
651 else
652 seq_printf(m, "ARB_MODE = 0x%08x\n",
653 intel_uncore_read(uncore, ARB_MODE));
654 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
655 intel_uncore_read(uncore, DISP_ARB_CTL));
656 }
657
658 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
659
660 return 0;
661}
662
663static int i915_rps_boost_info(struct seq_file *m, void *data)
664{
665 struct drm_i915_private *dev_priv = node_to_i915(m->private);
666 struct intel_rps *rps = &dev_priv->gt.rps;
667
668 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
669 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
670 seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
671 seq_printf(m, "Boosts outstanding? %d\n",
672 atomic_read(&rps->num_waiters));
673 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
674 seq_printf(m, "Frequency requested %d, actual %d\n",
675 intel_gpu_freq(rps, rps->cur_freq),
676 intel_rps_read_actual_frequency(rps));
677 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
678 intel_gpu_freq(rps, rps->min_freq),
679 intel_gpu_freq(rps, rps->min_freq_softlimit),
680 intel_gpu_freq(rps, rps->max_freq_softlimit),
681 intel_gpu_freq(rps, rps->max_freq));
682 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
683 intel_gpu_freq(rps, rps->idle_freq),
684 intel_gpu_freq(rps, rps->efficient_freq),
685 intel_gpu_freq(rps, rps->boost_freq));
686
687 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
688
689 return 0;
690}
691
692static int i915_runtime_pm_status(struct seq_file *m, void *unused)
693{
694 struct drm_i915_private *dev_priv = node_to_i915(m->private);
695 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
696
697 if (!HAS_RUNTIME_PM(dev_priv))
698 seq_puts(m, "Runtime power management not supported\n");
699
700 seq_printf(m, "Runtime power status: %s\n",
701 enableddisabled(!dev_priv->power_domains.init_wakeref));
702
703 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
704 seq_printf(m, "IRQs disabled: %s\n",
705 yesno(!intel_irqs_enabled(dev_priv)));
706#ifdef CONFIG_PM
707 seq_printf(m, "Usage count: %d\n",
708 atomic_read(&dev_priv->drm.dev->power.usage_count));
709#else
710 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
711#endif
712 seq_printf(m, "PCI device power state: %s [%d]\n",
713 pci_power_name(pdev->current_state),
714 pdev->current_state);
715
716 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
717 struct drm_printer p = drm_seq_file_printer(m);
718
719 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
720 }
721
722 return 0;
723}
724
725static int i915_engine_info(struct seq_file *m, void *unused)
726{
727 struct drm_i915_private *i915 = node_to_i915(m->private);
728 struct intel_engine_cs *engine;
729 intel_wakeref_t wakeref;
730 struct drm_printer p;
731
732 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
733
734 seq_printf(m, "GT awake? %s [%d], %llums\n",
735 yesno(i915->gt.awake),
736 atomic_read(&i915->gt.wakeref.count),
737 ktime_to_ms(intel_gt_get_awake_time(&i915->gt)));
738 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
739 i915->gt.clock_frequency,
740 i915->gt.clock_period_ns);
741
742 p = drm_seq_file_printer(m);
743 for_each_uabi_engine(engine, i915)
744 intel_engine_dump(engine, &p, "%s\n", engine->name);
745
746 intel_gt_show_timelines(&i915->gt, &p, i915_request_show_with_schedule);
747
748 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
749
750 return 0;
751}
752
753static int i915_wa_registers(struct seq_file *m, void *unused)
754{
755 struct drm_i915_private *i915 = node_to_i915(m->private);
756 struct intel_engine_cs *engine;
757
758 for_each_uabi_engine(engine, i915) {
759 const struct i915_wa_list *wal = &engine->ctx_wa_list;
760 const struct i915_wa *wa;
761 unsigned int count;
762
763 count = wal->count;
764 if (!count)
765 continue;
766
767 seq_printf(m, "%s: Workarounds applied: %u\n",
768 engine->name, count);
769
770 for (wa = wal->list; count--; wa++)
771 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
772 i915_mmio_reg_offset(wa->reg),
773 wa->set, wa->clr);
774
775 seq_printf(m, "\n");
776 }
777
778 return 0;
779}
780
781static int
782i915_wedged_get(void *data, u64 *val)
783{
784 struct drm_i915_private *i915 = data;
785 int ret = intel_gt_terminally_wedged(&i915->gt);
786
787 switch (ret) {
788 case -EIO:
789 *val = 1;
790 return 0;
791 case 0:
792 *val = 0;
793 return 0;
794 default:
795 return ret;
796 }
797}
798
799static int
800i915_wedged_set(void *data, u64 val)
801{
802 struct drm_i915_private *i915 = data;
803
804 /* Flush any previous reset before applying for a new one */
805 wait_event(i915->gt.reset.queue,
806 !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
807
808 intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
809 "Manually set wedged engine mask = %llx", val);
810 return 0;
811}
812
813DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
814 i915_wedged_get, i915_wedged_set,
815 "%llu\n");
816
817static int
818i915_perf_noa_delay_set(void *data, u64 val)
819{
820 struct drm_i915_private *i915 = data;
821
822 /*
823 * This would lead to infinite waits as we're doing timestamp
824 * difference on the CS with only 32bits.
825 */
826 if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX)
827 return -EINVAL;
828
829 atomic64_set(&i915->perf.noa_programming_delay, val);
830 return 0;
831}
832
833static int
834i915_perf_noa_delay_get(void *data, u64 *val)
835{
836 struct drm_i915_private *i915 = data;
837
838 *val = atomic64_read(&i915->perf.noa_programming_delay);
839 return 0;
840}
841
842DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
843 i915_perf_noa_delay_get,
844 i915_perf_noa_delay_set,
845 "%llu\n");
846
847#define DROP_UNBOUND BIT(0)
848#define DROP_BOUND BIT(1)
849#define DROP_RETIRE BIT(2)
850#define DROP_ACTIVE BIT(3)
851#define DROP_FREED BIT(4)
852#define DROP_SHRINK_ALL BIT(5)
853#define DROP_IDLE BIT(6)
854#define DROP_RESET_ACTIVE BIT(7)
855#define DROP_RESET_SEQNO BIT(8)
856#define DROP_RCU BIT(9)
857#define DROP_ALL (DROP_UNBOUND | \
858 DROP_BOUND | \
859 DROP_RETIRE | \
860 DROP_ACTIVE | \
861 DROP_FREED | \
862 DROP_SHRINK_ALL |\
863 DROP_IDLE | \
864 DROP_RESET_ACTIVE | \
865 DROP_RESET_SEQNO | \
866 DROP_RCU)
867static int
868i915_drop_caches_get(void *data, u64 *val)
869{
870 *val = DROP_ALL;
871
872 return 0;
873}
874static int
875gt_drop_caches(struct intel_gt *gt, u64 val)
876{
877 int ret;
878
879 if (val & DROP_RESET_ACTIVE &&
880 wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT))
881 intel_gt_set_wedged(gt);
882
883 if (val & DROP_RETIRE)
884 intel_gt_retire_requests(gt);
885
886 if (val & (DROP_IDLE | DROP_ACTIVE)) {
887 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
888 if (ret)
889 return ret;
890 }
891
892 if (val & DROP_IDLE) {
893 ret = intel_gt_pm_wait_for_idle(gt);
894 if (ret)
895 return ret;
896 }
897
898 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
899 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
900
901 if (val & DROP_FREED)
902 intel_gt_flush_buffer_pool(gt);
903
904 return 0;
905}
906
907static int
908i915_drop_caches_set(void *data, u64 val)
909{
910 struct drm_i915_private *i915 = data;
911 int ret;
912
913 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
914 val, val & DROP_ALL);
915
916 ret = gt_drop_caches(&i915->gt, val);
917 if (ret)
918 return ret;
919
920 fs_reclaim_acquire(GFP_KERNEL);
921 if (val & DROP_BOUND)
922 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
923
924 if (val & DROP_UNBOUND)
925 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
926
927 if (val & DROP_SHRINK_ALL)
928 i915_gem_shrink_all(i915);
929 fs_reclaim_release(GFP_KERNEL);
930
931 if (val & DROP_RCU)
932 rcu_barrier();
933
934 if (val & DROP_FREED)
935 i915_gem_drain_freed_objects(i915);
936
937 return 0;
938}
939
940DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
941 i915_drop_caches_get, i915_drop_caches_set,
942 "0x%08llx\n");
943
944static int i915_sseu_status(struct seq_file *m, void *unused)
945{
946 struct drm_i915_private *i915 = node_to_i915(m->private);
947 struct intel_gt *gt = &i915->gt;
948
949 return intel_sseu_status(m, gt);
950}
951
952static int i915_forcewake_open(struct inode *inode, struct file *file)
953{
954 struct drm_i915_private *i915 = inode->i_private;
955 struct intel_gt *gt = &i915->gt;
956
957 atomic_inc(>->user_wakeref);
958 intel_gt_pm_get(gt);
959 if (GRAPHICS_VER(i915) >= 6)
960 intel_uncore_forcewake_user_get(gt->uncore);
961
962 return 0;
963}
964
965static int i915_forcewake_release(struct inode *inode, struct file *file)
966{
967 struct drm_i915_private *i915 = inode->i_private;
968 struct intel_gt *gt = &i915->gt;
969
970 if (GRAPHICS_VER(i915) >= 6)
971 intel_uncore_forcewake_user_put(&i915->uncore);
972 intel_gt_pm_put(gt);
973 atomic_dec(>->user_wakeref);
974
975 return 0;
976}
977
978static const struct file_operations i915_forcewake_fops = {
979 .owner = THIS_MODULE,
980 .open = i915_forcewake_open,
981 .release = i915_forcewake_release,
982};
983
984static const struct drm_info_list i915_debugfs_list[] = {
985 {"i915_capabilities", i915_capabilities, 0},
986 {"i915_gem_objects", i915_gem_object_info, 0},
987 {"i915_frequency_info", i915_frequency_info, 0},
988 {"i915_swizzle_info", i915_swizzle_info, 0},
989 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
990 {"i915_engine_info", i915_engine_info, 0},
991 {"i915_wa_registers", i915_wa_registers, 0},
992 {"i915_sseu_status", i915_sseu_status, 0},
993 {"i915_rps_boost_info", i915_rps_boost_info, 0},
994};
995#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
996
997static const struct i915_debugfs_files {
998 const char *name;
999 const struct file_operations *fops;
1000} i915_debugfs_files[] = {
1001 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
1002 {"i915_wedged", &i915_wedged_fops},
1003 {"i915_gem_drop_caches", &i915_drop_caches_fops},
1004#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1005 {"i915_error_state", &i915_error_state_fops},
1006 {"i915_gpu_info", &i915_gpu_info_fops},
1007#endif
1008};
1009
1010void i915_debugfs_register(struct drm_i915_private *dev_priv)
1011{
1012 struct drm_minor *minor = dev_priv->drm.primary;
1013 int i;
1014
1015 i915_debugfs_params(dev_priv);
1016
1017 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
1018 to_i915(minor->dev), &i915_forcewake_fops);
1019 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
1020 debugfs_create_file(i915_debugfs_files[i].name,
1021 S_IRUGO | S_IWUSR,
1022 minor->debugfs_root,
1023 to_i915(minor->dev),
1024 i915_debugfs_files[i].fops);
1025 }
1026
1027 drm_debugfs_create_files(i915_debugfs_list,
1028 I915_DEBUGFS_ENTRIES,
1029 minor->debugfs_root, minor);
1030}