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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "cikd.h"
27#include "atom.h"
28#include "amdgpu_atombios.h"
29#include "amdgpu_dpm.h"
30#include "kv_dpm.h"
31#include "gfx_v7_0.h"
32#include <linux/seq_file.h>
33
34#include "smu/smu_7_0_0_d.h"
35#include "smu/smu_7_0_0_sh_mask.h"
36
37#include "gca/gfx_7_2_d.h"
38#include "gca/gfx_7_2_sh_mask.h"
39
40#define KV_MAX_DEEPSLEEP_DIVIDER_ID 5
41#define KV_MINIMUM_ENGINE_CLOCK 800
42#define SMC_RAM_END 0x40000
43
44static const struct amd_pm_funcs kv_dpm_funcs;
45
46static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47static int kv_enable_nb_dpm(struct amdgpu_device *adev,
48 bool enable);
49static void kv_init_graphics_levels(struct amdgpu_device *adev);
50static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53static void kv_enable_new_levels(struct amdgpu_device *adev);
54static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
55 struct amdgpu_ps *new_rps);
56static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57static int kv_set_enabled_levels(struct amdgpu_device *adev);
58static int kv_force_dpm_highest(struct amdgpu_device *adev);
59static int kv_force_dpm_lowest(struct amdgpu_device *adev);
60static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
61 struct amdgpu_ps *new_rps,
62 struct amdgpu_ps *old_rps);
63static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
64 int min_temp, int max_temp);
65static int kv_init_fps_limits(struct amdgpu_device *adev);
66
67static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
68static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
69
70
71static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
72 struct sumo_vid_mapping_table *vid_mapping_table,
73 u32 vid_2bit)
74{
75 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
77 u32 i;
78
79 if (vddc_sclk_table && vddc_sclk_table->count) {
80 if (vid_2bit < vddc_sclk_table->count)
81 return vddc_sclk_table->entries[vid_2bit].v;
82 else
83 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
84 } else {
85 for (i = 0; i < vid_mapping_table->num_entries; i++) {
86 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
87 return vid_mapping_table->entries[i].vid_7bit;
88 }
89 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
90 }
91}
92
93static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
94 struct sumo_vid_mapping_table *vid_mapping_table,
95 u32 vid_7bit)
96{
97 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
98 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
99 u32 i;
100
101 if (vddc_sclk_table && vddc_sclk_table->count) {
102 for (i = 0; i < vddc_sclk_table->count; i++) {
103 if (vddc_sclk_table->entries[i].v == vid_7bit)
104 return i;
105 }
106 return vddc_sclk_table->count - 1;
107 } else {
108 for (i = 0; i < vid_mapping_table->num_entries; i++) {
109 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
110 return vid_mapping_table->entries[i].vid_2bit;
111 }
112
113 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
114 }
115}
116
117static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
118{
119/* This bit selects who handles display phy powergating.
120 * Clear the bit to let atom handle it.
121 * Set it to let the driver handle it.
122 * For now we just let atom handle it.
123 */
124#if 0
125 u32 v = RREG32(mmDOUT_SCRATCH3);
126
127 if (enable)
128 v |= 0x4;
129 else
130 v &= 0xFFFFFFFB;
131
132 WREG32(mmDOUT_SCRATCH3, v);
133#endif
134}
135
136static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
137 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
138 ATOM_AVAILABLE_SCLK_LIST *table)
139{
140 u32 i;
141 u32 n = 0;
142 u32 prev_sclk = 0;
143
144 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
145 if (table[i].ulSupportedSCLK > prev_sclk) {
146 sclk_voltage_mapping_table->entries[n].sclk_frequency =
147 table[i].ulSupportedSCLK;
148 sclk_voltage_mapping_table->entries[n].vid_2bit =
149 table[i].usVoltageIndex;
150 prev_sclk = table[i].ulSupportedSCLK;
151 n++;
152 }
153 }
154
155 sclk_voltage_mapping_table->num_max_dpm_entries = n;
156}
157
158static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
159 struct sumo_vid_mapping_table *vid_mapping_table,
160 ATOM_AVAILABLE_SCLK_LIST *table)
161{
162 u32 i, j;
163
164 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
165 if (table[i].ulSupportedSCLK != 0) {
166 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
167 table[i].usVoltageID;
168 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
169 table[i].usVoltageIndex;
170 }
171 }
172
173 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
174 if (vid_mapping_table->entries[i].vid_7bit == 0) {
175 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
176 if (vid_mapping_table->entries[j].vid_7bit != 0) {
177 vid_mapping_table->entries[i] =
178 vid_mapping_table->entries[j];
179 vid_mapping_table->entries[j].vid_7bit = 0;
180 break;
181 }
182 }
183
184 if (j == SUMO_MAX_NUMBER_VOLTAGES)
185 break;
186 }
187 }
188
189 vid_mapping_table->num_entries = i;
190}
191
192#if 0
193static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
194{
195 { 0, 4, 1 },
196 { 1, 4, 1 },
197 { 2, 5, 1 },
198 { 3, 4, 2 },
199 { 4, 1, 1 },
200 { 5, 5, 2 },
201 { 6, 6, 1 },
202 { 7, 9, 2 },
203 { 0xffffffff }
204};
205
206static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
207{
208 { 0, 4, 1 },
209 { 0xffffffff }
210};
211
212static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
213{
214 { 0, 4, 1 },
215 { 0xffffffff }
216};
217
218static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
219{
220 { 0, 4, 1 },
221 { 0xffffffff }
222};
223
224static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
225{
226 { 0, 4, 1 },
227 { 0xffffffff }
228};
229
230static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
231{
232 { 0, 4, 1 },
233 { 1, 4, 1 },
234 { 2, 5, 1 },
235 { 3, 4, 1 },
236 { 4, 1, 1 },
237 { 5, 5, 1 },
238 { 6, 6, 1 },
239 { 7, 9, 1 },
240 { 8, 4, 1 },
241 { 9, 2, 1 },
242 { 10, 3, 1 },
243 { 11, 6, 1 },
244 { 12, 8, 2 },
245 { 13, 1, 1 },
246 { 14, 2, 1 },
247 { 15, 3, 1 },
248 { 16, 1, 1 },
249 { 17, 4, 1 },
250 { 18, 3, 1 },
251 { 19, 1, 1 },
252 { 20, 8, 1 },
253 { 21, 5, 1 },
254 { 22, 1, 1 },
255 { 23, 1, 1 },
256 { 24, 4, 1 },
257 { 27, 6, 1 },
258 { 28, 1, 1 },
259 { 0xffffffff }
260};
261
262static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
263{
264 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
265};
266
267static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
268{
269 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
270};
271
272static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
273{
274 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
275};
276
277static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
278{
279 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
280};
281
282static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
283{
284 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
285};
286
287static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
288{
289 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
290};
291#endif
292
293static const struct kv_pt_config_reg didt_config_kv[] =
294{
295 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
296 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
297 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
298 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
299 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
300 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
301 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
302 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
303 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
304 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
305 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
306 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
307 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
308 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
309 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
310 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
311 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
312 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
313 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
314 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
315 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
316 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
317 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
318 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
319 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
320 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
321 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
322 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
323 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
324 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
325 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
326 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
327 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
328 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
329 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
330 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
331 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
332 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
333 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
334 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
335 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
336 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
337 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
338 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
339 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
340 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
341 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
342 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
343 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
344 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
345 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
346 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
347 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
348 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
349 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
350 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
351 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
352 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
353 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
354 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
355 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
356 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
357 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
358 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
359 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
360 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
361 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
362 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
363 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
364 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
365 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
366 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
367 { 0xFFFFFFFF }
368};
369
370static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
371{
372 struct kv_ps *ps = rps->ps_priv;
373
374 return ps;
375}
376
377static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
378{
379 struct kv_power_info *pi = adev->pm.dpm.priv;
380
381 return pi;
382}
383
384#if 0
385static void kv_program_local_cac_table(struct amdgpu_device *adev,
386 const struct kv_lcac_config_values *local_cac_table,
387 const struct kv_lcac_config_reg *local_cac_reg)
388{
389 u32 i, count, data;
390 const struct kv_lcac_config_values *values = local_cac_table;
391
392 while (values->block_id != 0xffffffff) {
393 count = values->signal_id;
394 for (i = 0; i < count; i++) {
395 data = ((values->block_id << local_cac_reg->block_shift) &
396 local_cac_reg->block_mask);
397 data |= ((i << local_cac_reg->signal_shift) &
398 local_cac_reg->signal_mask);
399 data |= ((values->t << local_cac_reg->t_shift) &
400 local_cac_reg->t_mask);
401 data |= ((1 << local_cac_reg->enable_shift) &
402 local_cac_reg->enable_mask);
403 WREG32_SMC(local_cac_reg->cntl, data);
404 }
405 values++;
406 }
407}
408#endif
409
410static int kv_program_pt_config_registers(struct amdgpu_device *adev,
411 const struct kv_pt_config_reg *cac_config_regs)
412{
413 const struct kv_pt_config_reg *config_regs = cac_config_regs;
414 u32 data;
415 u32 cache = 0;
416
417 if (config_regs == NULL)
418 return -EINVAL;
419
420 while (config_regs->offset != 0xFFFFFFFF) {
421 if (config_regs->type == KV_CONFIGREG_CACHE) {
422 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
423 } else {
424 switch (config_regs->type) {
425 case KV_CONFIGREG_SMC_IND:
426 data = RREG32_SMC(config_regs->offset);
427 break;
428 case KV_CONFIGREG_DIDT_IND:
429 data = RREG32_DIDT(config_regs->offset);
430 break;
431 default:
432 data = RREG32(config_regs->offset);
433 break;
434 }
435
436 data &= ~config_regs->mask;
437 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
438 data |= cache;
439 cache = 0;
440
441 switch (config_regs->type) {
442 case KV_CONFIGREG_SMC_IND:
443 WREG32_SMC(config_regs->offset, data);
444 break;
445 case KV_CONFIGREG_DIDT_IND:
446 WREG32_DIDT(config_regs->offset, data);
447 break;
448 default:
449 WREG32(config_regs->offset, data);
450 break;
451 }
452 }
453 config_regs++;
454 }
455
456 return 0;
457}
458
459static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
460{
461 struct kv_power_info *pi = kv_get_pi(adev);
462 u32 data;
463
464 if (pi->caps_sq_ramping) {
465 data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
466 if (enable)
467 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
468 else
469 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
470 WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
471 }
472
473 if (pi->caps_db_ramping) {
474 data = RREG32_DIDT(ixDIDT_DB_CTRL0);
475 if (enable)
476 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
477 else
478 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
479 WREG32_DIDT(ixDIDT_DB_CTRL0, data);
480 }
481
482 if (pi->caps_td_ramping) {
483 data = RREG32_DIDT(ixDIDT_TD_CTRL0);
484 if (enable)
485 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
486 else
487 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
488 WREG32_DIDT(ixDIDT_TD_CTRL0, data);
489 }
490
491 if (pi->caps_tcp_ramping) {
492 data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
493 if (enable)
494 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
495 else
496 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
497 WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
498 }
499}
500
501static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
502{
503 struct kv_power_info *pi = kv_get_pi(adev);
504 int ret;
505
506 if (pi->caps_sq_ramping ||
507 pi->caps_db_ramping ||
508 pi->caps_td_ramping ||
509 pi->caps_tcp_ramping) {
510 amdgpu_gfx_rlc_enter_safe_mode(adev);
511
512 if (enable) {
513 ret = kv_program_pt_config_registers(adev, didt_config_kv);
514 if (ret) {
515 amdgpu_gfx_rlc_exit_safe_mode(adev);
516 return ret;
517 }
518 }
519
520 kv_do_enable_didt(adev, enable);
521
522 amdgpu_gfx_rlc_exit_safe_mode(adev);
523 }
524
525 return 0;
526}
527
528#if 0
529static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
530{
531 struct kv_power_info *pi = kv_get_pi(adev);
532
533 if (pi->caps_cac) {
534 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
535 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
536 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
537
538 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
539 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
540 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
541
542 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
543 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
544 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
545
546 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
547 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
548 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
549
550 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
551 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
552 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
553
554 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
555 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
556 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
557 }
558}
559#endif
560
561static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
562{
563 struct kv_power_info *pi = kv_get_pi(adev);
564 int ret = 0;
565
566 if (pi->caps_cac) {
567 if (enable) {
568 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
569 if (ret)
570 pi->cac_enabled = false;
571 else
572 pi->cac_enabled = true;
573 } else if (pi->cac_enabled) {
574 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
575 pi->cac_enabled = false;
576 }
577 }
578
579 return ret;
580}
581
582static int kv_process_firmware_header(struct amdgpu_device *adev)
583{
584 struct kv_power_info *pi = kv_get_pi(adev);
585 u32 tmp;
586 int ret;
587
588 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
589 offsetof(SMU7_Firmware_Header, DpmTable),
590 &tmp, pi->sram_end);
591
592 if (ret == 0)
593 pi->dpm_table_start = tmp;
594
595 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
596 offsetof(SMU7_Firmware_Header, SoftRegisters),
597 &tmp, pi->sram_end);
598
599 if (ret == 0)
600 pi->soft_regs_start = tmp;
601
602 return ret;
603}
604
605static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
606{
607 struct kv_power_info *pi = kv_get_pi(adev);
608 int ret;
609
610 pi->graphics_voltage_change_enable = 1;
611
612 ret = amdgpu_kv_copy_bytes_to_smc(adev,
613 pi->dpm_table_start +
614 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
615 &pi->graphics_voltage_change_enable,
616 sizeof(u8), pi->sram_end);
617
618 return ret;
619}
620
621static int kv_set_dpm_interval(struct amdgpu_device *adev)
622{
623 struct kv_power_info *pi = kv_get_pi(adev);
624 int ret;
625
626 pi->graphics_interval = 1;
627
628 ret = amdgpu_kv_copy_bytes_to_smc(adev,
629 pi->dpm_table_start +
630 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
631 &pi->graphics_interval,
632 sizeof(u8), pi->sram_end);
633
634 return ret;
635}
636
637static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
638{
639 struct kv_power_info *pi = kv_get_pi(adev);
640 int ret;
641
642 ret = amdgpu_kv_copy_bytes_to_smc(adev,
643 pi->dpm_table_start +
644 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
645 &pi->graphics_boot_level,
646 sizeof(u8), pi->sram_end);
647
648 return ret;
649}
650
651static void kv_program_vc(struct amdgpu_device *adev)
652{
653 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
654}
655
656static void kv_clear_vc(struct amdgpu_device *adev)
657{
658 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
659}
660
661static int kv_set_divider_value(struct amdgpu_device *adev,
662 u32 index, u32 sclk)
663{
664 struct kv_power_info *pi = kv_get_pi(adev);
665 struct atom_clock_dividers dividers;
666 int ret;
667
668 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
669 sclk, false, ÷rs);
670 if (ret)
671 return ret;
672
673 pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
674 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
675
676 return 0;
677}
678
679static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
680 u16 voltage)
681{
682 return 6200 - (voltage * 25);
683}
684
685static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
686 u32 vid_2bit)
687{
688 struct kv_power_info *pi = kv_get_pi(adev);
689 u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
690 &pi->sys_info.vid_mapping_table,
691 vid_2bit);
692
693 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
694}
695
696
697static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
698{
699 struct kv_power_info *pi = kv_get_pi(adev);
700
701 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
702 pi->graphics_level[index].MinVddNb =
703 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
704
705 return 0;
706}
707
708static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
709{
710 struct kv_power_info *pi = kv_get_pi(adev);
711
712 pi->graphics_level[index].AT = cpu_to_be16((u16)at);
713
714 return 0;
715}
716
717static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
718 u32 index, bool enable)
719{
720 struct kv_power_info *pi = kv_get_pi(adev);
721
722 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
723}
724
725static void kv_start_dpm(struct amdgpu_device *adev)
726{
727 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
728
729 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
730 WREG32_SMC(ixGENERAL_PWRMGT, tmp);
731
732 amdgpu_kv_smc_dpm_enable(adev, true);
733}
734
735static void kv_stop_dpm(struct amdgpu_device *adev)
736{
737 amdgpu_kv_smc_dpm_enable(adev, false);
738}
739
740static void kv_start_am(struct amdgpu_device *adev)
741{
742 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
743
744 sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
745 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
746 sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
747
748 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
749}
750
751static void kv_reset_am(struct amdgpu_device *adev)
752{
753 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
754
755 sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
756 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
757
758 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
759}
760
761static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
762{
763 return amdgpu_kv_notify_message_to_smu(adev, freeze ?
764 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
765}
766
767static int kv_force_lowest_valid(struct amdgpu_device *adev)
768{
769 return kv_force_dpm_lowest(adev);
770}
771
772static int kv_unforce_levels(struct amdgpu_device *adev)
773{
774 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
775 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
776 else
777 return kv_set_enabled_levels(adev);
778}
779
780static int kv_update_sclk_t(struct amdgpu_device *adev)
781{
782 struct kv_power_info *pi = kv_get_pi(adev);
783 u32 low_sclk_interrupt_t = 0;
784 int ret = 0;
785
786 if (pi->caps_sclk_throttle_low_notification) {
787 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
788
789 ret = amdgpu_kv_copy_bytes_to_smc(adev,
790 pi->dpm_table_start +
791 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
792 (u8 *)&low_sclk_interrupt_t,
793 sizeof(u32), pi->sram_end);
794 }
795 return ret;
796}
797
798static int kv_program_bootup_state(struct amdgpu_device *adev)
799{
800 struct kv_power_info *pi = kv_get_pi(adev);
801 u32 i;
802 struct amdgpu_clock_voltage_dependency_table *table =
803 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
804
805 if (table && table->count) {
806 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
807 if (table->entries[i].clk == pi->boot_pl.sclk)
808 break;
809 }
810
811 pi->graphics_boot_level = (u8)i;
812 kv_dpm_power_level_enable(adev, i, true);
813 } else {
814 struct sumo_sclk_voltage_mapping_table *table =
815 &pi->sys_info.sclk_voltage_mapping_table;
816
817 if (table->num_max_dpm_entries == 0)
818 return -EINVAL;
819
820 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
821 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
822 break;
823 }
824
825 pi->graphics_boot_level = (u8)i;
826 kv_dpm_power_level_enable(adev, i, true);
827 }
828 return 0;
829}
830
831static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
832{
833 struct kv_power_info *pi = kv_get_pi(adev);
834 int ret;
835
836 pi->graphics_therm_throttle_enable = 1;
837
838 ret = amdgpu_kv_copy_bytes_to_smc(adev,
839 pi->dpm_table_start +
840 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
841 &pi->graphics_therm_throttle_enable,
842 sizeof(u8), pi->sram_end);
843
844 return ret;
845}
846
847static int kv_upload_dpm_settings(struct amdgpu_device *adev)
848{
849 struct kv_power_info *pi = kv_get_pi(adev);
850 int ret;
851
852 ret = amdgpu_kv_copy_bytes_to_smc(adev,
853 pi->dpm_table_start +
854 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
855 (u8 *)&pi->graphics_level,
856 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
857 pi->sram_end);
858
859 if (ret)
860 return ret;
861
862 ret = amdgpu_kv_copy_bytes_to_smc(adev,
863 pi->dpm_table_start +
864 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
865 &pi->graphics_dpm_level_count,
866 sizeof(u8), pi->sram_end);
867
868 return ret;
869}
870
871static u32 kv_get_clock_difference(u32 a, u32 b)
872{
873 return (a >= b) ? a - b : b - a;
874}
875
876static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
877{
878 struct kv_power_info *pi = kv_get_pi(adev);
879 u32 value;
880
881 if (pi->caps_enable_dfs_bypass) {
882 if (kv_get_clock_difference(clk, 40000) < 200)
883 value = 3;
884 else if (kv_get_clock_difference(clk, 30000) < 200)
885 value = 2;
886 else if (kv_get_clock_difference(clk, 20000) < 200)
887 value = 7;
888 else if (kv_get_clock_difference(clk, 15000) < 200)
889 value = 6;
890 else if (kv_get_clock_difference(clk, 10000) < 200)
891 value = 8;
892 else
893 value = 0;
894 } else {
895 value = 0;
896 }
897
898 return value;
899}
900
901static int kv_populate_uvd_table(struct amdgpu_device *adev)
902{
903 struct kv_power_info *pi = kv_get_pi(adev);
904 struct amdgpu_uvd_clock_voltage_dependency_table *table =
905 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
906 struct atom_clock_dividers dividers;
907 int ret;
908 u32 i;
909
910 if (table == NULL || table->count == 0)
911 return 0;
912
913 pi->uvd_level_count = 0;
914 for (i = 0; i < table->count; i++) {
915 if (pi->high_voltage_t &&
916 (pi->high_voltage_t < table->entries[i].v))
917 break;
918
919 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
920 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
921 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
922
923 pi->uvd_level[i].VClkBypassCntl =
924 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
925 pi->uvd_level[i].DClkBypassCntl =
926 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
927
928 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
929 table->entries[i].vclk, false, ÷rs);
930 if (ret)
931 return ret;
932 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
933
934 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
935 table->entries[i].dclk, false, ÷rs);
936 if (ret)
937 return ret;
938 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
939
940 pi->uvd_level_count++;
941 }
942
943 ret = amdgpu_kv_copy_bytes_to_smc(adev,
944 pi->dpm_table_start +
945 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
946 (u8 *)&pi->uvd_level_count,
947 sizeof(u8), pi->sram_end);
948 if (ret)
949 return ret;
950
951 pi->uvd_interval = 1;
952
953 ret = amdgpu_kv_copy_bytes_to_smc(adev,
954 pi->dpm_table_start +
955 offsetof(SMU7_Fusion_DpmTable, UVDInterval),
956 &pi->uvd_interval,
957 sizeof(u8), pi->sram_end);
958 if (ret)
959 return ret;
960
961 ret = amdgpu_kv_copy_bytes_to_smc(adev,
962 pi->dpm_table_start +
963 offsetof(SMU7_Fusion_DpmTable, UvdLevel),
964 (u8 *)&pi->uvd_level,
965 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
966 pi->sram_end);
967
968 return ret;
969
970}
971
972static int kv_populate_vce_table(struct amdgpu_device *adev)
973{
974 struct kv_power_info *pi = kv_get_pi(adev);
975 int ret;
976 u32 i;
977 struct amdgpu_vce_clock_voltage_dependency_table *table =
978 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
979 struct atom_clock_dividers dividers;
980
981 if (table == NULL || table->count == 0)
982 return 0;
983
984 pi->vce_level_count = 0;
985 for (i = 0; i < table->count; i++) {
986 if (pi->high_voltage_t &&
987 pi->high_voltage_t < table->entries[i].v)
988 break;
989
990 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
991 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
992
993 pi->vce_level[i].ClkBypassCntl =
994 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
995
996 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
997 table->entries[i].evclk, false, ÷rs);
998 if (ret)
999 return ret;
1000 pi->vce_level[i].Divider = (u8)dividers.post_div;
1001
1002 pi->vce_level_count++;
1003 }
1004
1005 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1006 pi->dpm_table_start +
1007 offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
1008 (u8 *)&pi->vce_level_count,
1009 sizeof(u8),
1010 pi->sram_end);
1011 if (ret)
1012 return ret;
1013
1014 pi->vce_interval = 1;
1015
1016 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1017 pi->dpm_table_start +
1018 offsetof(SMU7_Fusion_DpmTable, VCEInterval),
1019 (u8 *)&pi->vce_interval,
1020 sizeof(u8),
1021 pi->sram_end);
1022 if (ret)
1023 return ret;
1024
1025 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1026 pi->dpm_table_start +
1027 offsetof(SMU7_Fusion_DpmTable, VceLevel),
1028 (u8 *)&pi->vce_level,
1029 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
1030 pi->sram_end);
1031
1032 return ret;
1033}
1034
1035static int kv_populate_samu_table(struct amdgpu_device *adev)
1036{
1037 struct kv_power_info *pi = kv_get_pi(adev);
1038 struct amdgpu_clock_voltage_dependency_table *table =
1039 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1040 struct atom_clock_dividers dividers;
1041 int ret;
1042 u32 i;
1043
1044 if (table == NULL || table->count == 0)
1045 return 0;
1046
1047 pi->samu_level_count = 0;
1048 for (i = 0; i < table->count; i++) {
1049 if (pi->high_voltage_t &&
1050 pi->high_voltage_t < table->entries[i].v)
1051 break;
1052
1053 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1054 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1055
1056 pi->samu_level[i].ClkBypassCntl =
1057 (u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1058
1059 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1060 table->entries[i].clk, false, ÷rs);
1061 if (ret)
1062 return ret;
1063 pi->samu_level[i].Divider = (u8)dividers.post_div;
1064
1065 pi->samu_level_count++;
1066 }
1067
1068 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1069 pi->dpm_table_start +
1070 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
1071 (u8 *)&pi->samu_level_count,
1072 sizeof(u8),
1073 pi->sram_end);
1074 if (ret)
1075 return ret;
1076
1077 pi->samu_interval = 1;
1078
1079 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1080 pi->dpm_table_start +
1081 offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
1082 (u8 *)&pi->samu_interval,
1083 sizeof(u8),
1084 pi->sram_end);
1085 if (ret)
1086 return ret;
1087
1088 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1089 pi->dpm_table_start +
1090 offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1091 (u8 *)&pi->samu_level,
1092 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1093 pi->sram_end);
1094 if (ret)
1095 return ret;
1096
1097 return ret;
1098}
1099
1100
1101static int kv_populate_acp_table(struct amdgpu_device *adev)
1102{
1103 struct kv_power_info *pi = kv_get_pi(adev);
1104 struct amdgpu_clock_voltage_dependency_table *table =
1105 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1106 struct atom_clock_dividers dividers;
1107 int ret;
1108 u32 i;
1109
1110 if (table == NULL || table->count == 0)
1111 return 0;
1112
1113 pi->acp_level_count = 0;
1114 for (i = 0; i < table->count; i++) {
1115 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1116 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1117
1118 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1119 table->entries[i].clk, false, ÷rs);
1120 if (ret)
1121 return ret;
1122 pi->acp_level[i].Divider = (u8)dividers.post_div;
1123
1124 pi->acp_level_count++;
1125 }
1126
1127 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1128 pi->dpm_table_start +
1129 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1130 (u8 *)&pi->acp_level_count,
1131 sizeof(u8),
1132 pi->sram_end);
1133 if (ret)
1134 return ret;
1135
1136 pi->acp_interval = 1;
1137
1138 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1139 pi->dpm_table_start +
1140 offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1141 (u8 *)&pi->acp_interval,
1142 sizeof(u8),
1143 pi->sram_end);
1144 if (ret)
1145 return ret;
1146
1147 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1148 pi->dpm_table_start +
1149 offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1150 (u8 *)&pi->acp_level,
1151 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1152 pi->sram_end);
1153 if (ret)
1154 return ret;
1155
1156 return ret;
1157}
1158
1159static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
1160{
1161 struct kv_power_info *pi = kv_get_pi(adev);
1162 u32 i;
1163 struct amdgpu_clock_voltage_dependency_table *table =
1164 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1165
1166 if (table && table->count) {
1167 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1168 if (pi->caps_enable_dfs_bypass) {
1169 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1170 pi->graphics_level[i].ClkBypassCntl = 3;
1171 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1172 pi->graphics_level[i].ClkBypassCntl = 2;
1173 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1174 pi->graphics_level[i].ClkBypassCntl = 7;
1175 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1176 pi->graphics_level[i].ClkBypassCntl = 6;
1177 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1178 pi->graphics_level[i].ClkBypassCntl = 8;
1179 else
1180 pi->graphics_level[i].ClkBypassCntl = 0;
1181 } else {
1182 pi->graphics_level[i].ClkBypassCntl = 0;
1183 }
1184 }
1185 } else {
1186 struct sumo_sclk_voltage_mapping_table *table =
1187 &pi->sys_info.sclk_voltage_mapping_table;
1188 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1189 if (pi->caps_enable_dfs_bypass) {
1190 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1191 pi->graphics_level[i].ClkBypassCntl = 3;
1192 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1193 pi->graphics_level[i].ClkBypassCntl = 2;
1194 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1195 pi->graphics_level[i].ClkBypassCntl = 7;
1196 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1197 pi->graphics_level[i].ClkBypassCntl = 6;
1198 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1199 pi->graphics_level[i].ClkBypassCntl = 8;
1200 else
1201 pi->graphics_level[i].ClkBypassCntl = 0;
1202 } else {
1203 pi->graphics_level[i].ClkBypassCntl = 0;
1204 }
1205 }
1206 }
1207}
1208
1209static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
1210{
1211 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1212 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1213}
1214
1215static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
1216{
1217 struct kv_power_info *pi = kv_get_pi(adev);
1218
1219 pi->acp_boot_level = 0xff;
1220}
1221
1222static void kv_update_current_ps(struct amdgpu_device *adev,
1223 struct amdgpu_ps *rps)
1224{
1225 struct kv_ps *new_ps = kv_get_ps(rps);
1226 struct kv_power_info *pi = kv_get_pi(adev);
1227
1228 pi->current_rps = *rps;
1229 pi->current_ps = *new_ps;
1230 pi->current_rps.ps_priv = &pi->current_ps;
1231 adev->pm.dpm.current_ps = &pi->current_rps;
1232}
1233
1234static void kv_update_requested_ps(struct amdgpu_device *adev,
1235 struct amdgpu_ps *rps)
1236{
1237 struct kv_ps *new_ps = kv_get_ps(rps);
1238 struct kv_power_info *pi = kv_get_pi(adev);
1239
1240 pi->requested_rps = *rps;
1241 pi->requested_ps = *new_ps;
1242 pi->requested_rps.ps_priv = &pi->requested_ps;
1243 adev->pm.dpm.requested_ps = &pi->requested_rps;
1244}
1245
1246static void kv_dpm_enable_bapm(void *handle, bool enable)
1247{
1248 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249 struct kv_power_info *pi = kv_get_pi(adev);
1250 int ret;
1251
1252 if (pi->bapm_enable) {
1253 ret = amdgpu_kv_smc_bapm_enable(adev, enable);
1254 if (ret)
1255 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1256 }
1257}
1258
1259static int kv_dpm_enable(struct amdgpu_device *adev)
1260{
1261 struct kv_power_info *pi = kv_get_pi(adev);
1262 int ret;
1263
1264 ret = kv_process_firmware_header(adev);
1265 if (ret) {
1266 DRM_ERROR("kv_process_firmware_header failed\n");
1267 return ret;
1268 }
1269 kv_init_fps_limits(adev);
1270 kv_init_graphics_levels(adev);
1271 ret = kv_program_bootup_state(adev);
1272 if (ret) {
1273 DRM_ERROR("kv_program_bootup_state failed\n");
1274 return ret;
1275 }
1276 kv_calculate_dfs_bypass_settings(adev);
1277 ret = kv_upload_dpm_settings(adev);
1278 if (ret) {
1279 DRM_ERROR("kv_upload_dpm_settings failed\n");
1280 return ret;
1281 }
1282 ret = kv_populate_uvd_table(adev);
1283 if (ret) {
1284 DRM_ERROR("kv_populate_uvd_table failed\n");
1285 return ret;
1286 }
1287 ret = kv_populate_vce_table(adev);
1288 if (ret) {
1289 DRM_ERROR("kv_populate_vce_table failed\n");
1290 return ret;
1291 }
1292 ret = kv_populate_samu_table(adev);
1293 if (ret) {
1294 DRM_ERROR("kv_populate_samu_table failed\n");
1295 return ret;
1296 }
1297 ret = kv_populate_acp_table(adev);
1298 if (ret) {
1299 DRM_ERROR("kv_populate_acp_table failed\n");
1300 return ret;
1301 }
1302 kv_program_vc(adev);
1303#if 0
1304 kv_initialize_hardware_cac_manager(adev);
1305#endif
1306 kv_start_am(adev);
1307 if (pi->enable_auto_thermal_throttling) {
1308 ret = kv_enable_auto_thermal_throttling(adev);
1309 if (ret) {
1310 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1311 return ret;
1312 }
1313 }
1314 ret = kv_enable_dpm_voltage_scaling(adev);
1315 if (ret) {
1316 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1317 return ret;
1318 }
1319 ret = kv_set_dpm_interval(adev);
1320 if (ret) {
1321 DRM_ERROR("kv_set_dpm_interval failed\n");
1322 return ret;
1323 }
1324 ret = kv_set_dpm_boot_state(adev);
1325 if (ret) {
1326 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1327 return ret;
1328 }
1329 ret = kv_enable_ulv(adev, true);
1330 if (ret) {
1331 DRM_ERROR("kv_enable_ulv failed\n");
1332 return ret;
1333 }
1334 kv_start_dpm(adev);
1335 ret = kv_enable_didt(adev, true);
1336 if (ret) {
1337 DRM_ERROR("kv_enable_didt failed\n");
1338 return ret;
1339 }
1340 ret = kv_enable_smc_cac(adev, true);
1341 if (ret) {
1342 DRM_ERROR("kv_enable_smc_cac failed\n");
1343 return ret;
1344 }
1345
1346 kv_reset_acp_boot_level(adev);
1347
1348 ret = amdgpu_kv_smc_bapm_enable(adev, false);
1349 if (ret) {
1350 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1351 return ret;
1352 }
1353
1354 if (adev->irq.installed &&
1355 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
1356 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
1357 if (ret) {
1358 DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1359 return ret;
1360 }
1361 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1362 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1363 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1364 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1365 }
1366
1367 return ret;
1368}
1369
1370static void kv_dpm_disable(struct amdgpu_device *adev)
1371{
1372 struct kv_power_info *pi = kv_get_pi(adev);
1373
1374 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1375 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1376 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1377 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1378
1379 amdgpu_kv_smc_bapm_enable(adev, false);
1380
1381 if (adev->asic_type == CHIP_MULLINS)
1382 kv_enable_nb_dpm(adev, false);
1383
1384 /* powerup blocks */
1385 kv_dpm_powergate_acp(adev, false);
1386 kv_dpm_powergate_samu(adev, false);
1387 if (pi->caps_vce_pg) /* power on the VCE block */
1388 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1389 if (pi->caps_uvd_pg) /* power on the UVD block */
1390 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1391
1392 kv_enable_smc_cac(adev, false);
1393 kv_enable_didt(adev, false);
1394 kv_clear_vc(adev);
1395 kv_stop_dpm(adev);
1396 kv_enable_ulv(adev, false);
1397 kv_reset_am(adev);
1398
1399 kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1400}
1401
1402#if 0
1403static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1404 u16 reg_offset, u32 value)
1405{
1406 struct kv_power_info *pi = kv_get_pi(adev);
1407
1408 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1409 (u8 *)&value, sizeof(u16), pi->sram_end);
1410}
1411
1412static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1413 u16 reg_offset, u32 *value)
1414{
1415 struct kv_power_info *pi = kv_get_pi(adev);
1416
1417 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1418 value, pi->sram_end);
1419}
1420#endif
1421
1422static void kv_init_sclk_t(struct amdgpu_device *adev)
1423{
1424 struct kv_power_info *pi = kv_get_pi(adev);
1425
1426 pi->low_sclk_interrupt_t = 0;
1427}
1428
1429static int kv_init_fps_limits(struct amdgpu_device *adev)
1430{
1431 struct kv_power_info *pi = kv_get_pi(adev);
1432 int ret = 0;
1433
1434 if (pi->caps_fps) {
1435 u16 tmp;
1436
1437 tmp = 45;
1438 pi->fps_high_t = cpu_to_be16(tmp);
1439 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1440 pi->dpm_table_start +
1441 offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1442 (u8 *)&pi->fps_high_t,
1443 sizeof(u16), pi->sram_end);
1444
1445 tmp = 30;
1446 pi->fps_low_t = cpu_to_be16(tmp);
1447
1448 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1449 pi->dpm_table_start +
1450 offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1451 (u8 *)&pi->fps_low_t,
1452 sizeof(u16), pi->sram_end);
1453
1454 }
1455 return ret;
1456}
1457
1458static void kv_init_powergate_state(struct amdgpu_device *adev)
1459{
1460 struct kv_power_info *pi = kv_get_pi(adev);
1461
1462 pi->uvd_power_gated = false;
1463 pi->vce_power_gated = false;
1464 pi->samu_power_gated = false;
1465 pi->acp_power_gated = false;
1466
1467}
1468
1469static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1470{
1471 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1472 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1473}
1474
1475static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1476{
1477 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1478 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1479}
1480
1481static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
1482{
1483 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1484 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1485}
1486
1487static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
1488{
1489 return amdgpu_kv_notify_message_to_smu(adev, enable ?
1490 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1491}
1492
1493static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1494{
1495 struct kv_power_info *pi = kv_get_pi(adev);
1496 struct amdgpu_uvd_clock_voltage_dependency_table *table =
1497 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1498 int ret;
1499 u32 mask;
1500
1501 if (!gate) {
1502 if (table->count)
1503 pi->uvd_boot_level = table->count - 1;
1504 else
1505 pi->uvd_boot_level = 0;
1506
1507 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1508 mask = 1 << pi->uvd_boot_level;
1509 } else {
1510 mask = 0x1f;
1511 }
1512
1513 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1514 pi->dpm_table_start +
1515 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1516 (uint8_t *)&pi->uvd_boot_level,
1517 sizeof(u8), pi->sram_end);
1518 if (ret)
1519 return ret;
1520
1521 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1522 PPSMC_MSG_UVDDPM_SetEnabledMask,
1523 mask);
1524 }
1525
1526 return kv_enable_uvd_dpm(adev, !gate);
1527}
1528
1529static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
1530{
1531 u8 i;
1532 struct amdgpu_vce_clock_voltage_dependency_table *table =
1533 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1534
1535 for (i = 0; i < table->count; i++) {
1536 if (table->entries[i].evclk >= evclk)
1537 break;
1538 }
1539
1540 return i;
1541}
1542
1543static int kv_update_vce_dpm(struct amdgpu_device *adev,
1544 struct amdgpu_ps *amdgpu_new_state,
1545 struct amdgpu_ps *amdgpu_current_state)
1546{
1547 struct kv_power_info *pi = kv_get_pi(adev);
1548 struct amdgpu_vce_clock_voltage_dependency_table *table =
1549 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1550 int ret;
1551
1552 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1553 if (pi->caps_stable_p_state)
1554 pi->vce_boot_level = table->count - 1;
1555 else
1556 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
1557
1558 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1559 pi->dpm_table_start +
1560 offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1561 (u8 *)&pi->vce_boot_level,
1562 sizeof(u8),
1563 pi->sram_end);
1564 if (ret)
1565 return ret;
1566
1567 if (pi->caps_stable_p_state)
1568 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1569 PPSMC_MSG_VCEDPM_SetEnabledMask,
1570 (1 << pi->vce_boot_level));
1571 kv_enable_vce_dpm(adev, true);
1572 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1573 kv_enable_vce_dpm(adev, false);
1574 }
1575
1576 return 0;
1577}
1578
1579static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
1580{
1581 struct kv_power_info *pi = kv_get_pi(adev);
1582 struct amdgpu_clock_voltage_dependency_table *table =
1583 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1584 int ret;
1585
1586 if (!gate) {
1587 if (pi->caps_stable_p_state)
1588 pi->samu_boot_level = table->count - 1;
1589 else
1590 pi->samu_boot_level = 0;
1591
1592 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1593 pi->dpm_table_start +
1594 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1595 (u8 *)&pi->samu_boot_level,
1596 sizeof(u8),
1597 pi->sram_end);
1598 if (ret)
1599 return ret;
1600
1601 if (pi->caps_stable_p_state)
1602 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1603 PPSMC_MSG_SAMUDPM_SetEnabledMask,
1604 (1 << pi->samu_boot_level));
1605 }
1606
1607 return kv_enable_samu_dpm(adev, !gate);
1608}
1609
1610static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
1611{
1612 u8 i;
1613 struct amdgpu_clock_voltage_dependency_table *table =
1614 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1615
1616 for (i = 0; i < table->count; i++) {
1617 if (table->entries[i].clk >= 0) /* XXX */
1618 break;
1619 }
1620
1621 if (i >= table->count)
1622 i = table->count - 1;
1623
1624 return i;
1625}
1626
1627static void kv_update_acp_boot_level(struct amdgpu_device *adev)
1628{
1629 struct kv_power_info *pi = kv_get_pi(adev);
1630 u8 acp_boot_level;
1631
1632 if (!pi->caps_stable_p_state) {
1633 acp_boot_level = kv_get_acp_boot_level(adev);
1634 if (acp_boot_level != pi->acp_boot_level) {
1635 pi->acp_boot_level = acp_boot_level;
1636 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1637 PPSMC_MSG_ACPDPM_SetEnabledMask,
1638 (1 << pi->acp_boot_level));
1639 }
1640 }
1641}
1642
1643static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
1644{
1645 struct kv_power_info *pi = kv_get_pi(adev);
1646 struct amdgpu_clock_voltage_dependency_table *table =
1647 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1648 int ret;
1649
1650 if (!gate) {
1651 if (pi->caps_stable_p_state)
1652 pi->acp_boot_level = table->count - 1;
1653 else
1654 pi->acp_boot_level = kv_get_acp_boot_level(adev);
1655
1656 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1657 pi->dpm_table_start +
1658 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1659 (u8 *)&pi->acp_boot_level,
1660 sizeof(u8),
1661 pi->sram_end);
1662 if (ret)
1663 return ret;
1664
1665 if (pi->caps_stable_p_state)
1666 amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1667 PPSMC_MSG_ACPDPM_SetEnabledMask,
1668 (1 << pi->acp_boot_level));
1669 }
1670
1671 return kv_enable_acp_dpm(adev, !gate);
1672}
1673
1674static void kv_dpm_powergate_uvd(void *handle, bool gate)
1675{
1676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1677 struct kv_power_info *pi = kv_get_pi(adev);
1678
1679 pi->uvd_power_gated = gate;
1680
1681 if (gate) {
1682 /* stop the UVD block */
1683 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1684 AMD_PG_STATE_GATE);
1685 kv_update_uvd_dpm(adev, gate);
1686 if (pi->caps_uvd_pg)
1687 /* power off the UVD block */
1688 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1689 } else {
1690 if (pi->caps_uvd_pg)
1691 /* power on the UVD block */
1692 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1693 /* re-init the UVD block */
1694 kv_update_uvd_dpm(adev, gate);
1695
1696 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1697 AMD_PG_STATE_UNGATE);
1698 }
1699}
1700
1701static void kv_dpm_powergate_vce(void *handle, bool gate)
1702{
1703 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1704 struct kv_power_info *pi = kv_get_pi(adev);
1705
1706 pi->vce_power_gated = gate;
1707
1708 if (gate) {
1709 /* stop the VCE block */
1710 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1711 AMD_PG_STATE_GATE);
1712 kv_enable_vce_dpm(adev, false);
1713 if (pi->caps_vce_pg) /* power off the VCE block */
1714 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1715 } else {
1716 if (pi->caps_vce_pg) /* power on the VCE block */
1717 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1718 kv_enable_vce_dpm(adev, true);
1719 /* re-init the VCE block */
1720 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1721 AMD_PG_STATE_UNGATE);
1722 }
1723}
1724
1725
1726static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
1727{
1728 struct kv_power_info *pi = kv_get_pi(adev);
1729
1730 if (pi->samu_power_gated == gate)
1731 return;
1732
1733 pi->samu_power_gated = gate;
1734
1735 if (gate) {
1736 kv_update_samu_dpm(adev, true);
1737 if (pi->caps_samu_pg)
1738 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
1739 } else {
1740 if (pi->caps_samu_pg)
1741 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
1742 kv_update_samu_dpm(adev, false);
1743 }
1744}
1745
1746static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
1747{
1748 struct kv_power_info *pi = kv_get_pi(adev);
1749
1750 if (pi->acp_power_gated == gate)
1751 return;
1752
1753 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
1754 return;
1755
1756 pi->acp_power_gated = gate;
1757
1758 if (gate) {
1759 kv_update_acp_dpm(adev, true);
1760 if (pi->caps_acp_pg)
1761 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
1762 } else {
1763 if (pi->caps_acp_pg)
1764 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
1765 kv_update_acp_dpm(adev, false);
1766 }
1767}
1768
1769static void kv_set_valid_clock_range(struct amdgpu_device *adev,
1770 struct amdgpu_ps *new_rps)
1771{
1772 struct kv_ps *new_ps = kv_get_ps(new_rps);
1773 struct kv_power_info *pi = kv_get_pi(adev);
1774 u32 i;
1775 struct amdgpu_clock_voltage_dependency_table *table =
1776 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1777
1778 if (table && table->count) {
1779 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1780 if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1781 (i == (pi->graphics_dpm_level_count - 1))) {
1782 pi->lowest_valid = i;
1783 break;
1784 }
1785 }
1786
1787 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1788 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1789 break;
1790 }
1791 pi->highest_valid = i;
1792
1793 if (pi->lowest_valid > pi->highest_valid) {
1794 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1795 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1796 pi->highest_valid = pi->lowest_valid;
1797 else
1798 pi->lowest_valid = pi->highest_valid;
1799 }
1800 } else {
1801 struct sumo_sclk_voltage_mapping_table *table =
1802 &pi->sys_info.sclk_voltage_mapping_table;
1803
1804 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1805 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1806 i == (int)(pi->graphics_dpm_level_count - 1)) {
1807 pi->lowest_valid = i;
1808 break;
1809 }
1810 }
1811
1812 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1813 if (table->entries[i].sclk_frequency <=
1814 new_ps->levels[new_ps->num_levels - 1].sclk)
1815 break;
1816 }
1817 pi->highest_valid = i;
1818
1819 if (pi->lowest_valid > pi->highest_valid) {
1820 if ((new_ps->levels[0].sclk -
1821 table->entries[pi->highest_valid].sclk_frequency) >
1822 (table->entries[pi->lowest_valid].sclk_frequency -
1823 new_ps->levels[new_ps->num_levels -1].sclk))
1824 pi->highest_valid = pi->lowest_valid;
1825 else
1826 pi->lowest_valid = pi->highest_valid;
1827 }
1828 }
1829}
1830
1831static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev,
1832 struct amdgpu_ps *new_rps)
1833{
1834 struct kv_ps *new_ps = kv_get_ps(new_rps);
1835 struct kv_power_info *pi = kv_get_pi(adev);
1836 int ret = 0;
1837 u8 clk_bypass_cntl;
1838
1839 if (pi->caps_enable_dfs_bypass) {
1840 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1841 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1842 ret = amdgpu_kv_copy_bytes_to_smc(adev,
1843 (pi->dpm_table_start +
1844 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1845 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1846 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1847 &clk_bypass_cntl,
1848 sizeof(u8), pi->sram_end);
1849 }
1850
1851 return ret;
1852}
1853
1854static int kv_enable_nb_dpm(struct amdgpu_device *adev,
1855 bool enable)
1856{
1857 struct kv_power_info *pi = kv_get_pi(adev);
1858 int ret = 0;
1859
1860 if (enable) {
1861 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1862 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable);
1863 if (ret == 0)
1864 pi->nb_dpm_enabled = true;
1865 }
1866 } else {
1867 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {
1868 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable);
1869 if (ret == 0)
1870 pi->nb_dpm_enabled = false;
1871 }
1872 }
1873
1874 return ret;
1875}
1876
1877static int kv_dpm_force_performance_level(void *handle,
1878 enum amd_dpm_forced_level level)
1879{
1880 int ret;
1881 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1882
1883 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
1884 ret = kv_force_dpm_highest(adev);
1885 if (ret)
1886 return ret;
1887 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
1888 ret = kv_force_dpm_lowest(adev);
1889 if (ret)
1890 return ret;
1891 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
1892 ret = kv_unforce_levels(adev);
1893 if (ret)
1894 return ret;
1895 }
1896
1897 adev->pm.dpm.forced_level = level;
1898
1899 return 0;
1900}
1901
1902static int kv_dpm_pre_set_power_state(void *handle)
1903{
1904 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1905 struct kv_power_info *pi = kv_get_pi(adev);
1906 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
1907 struct amdgpu_ps *new_ps = &requested_ps;
1908
1909 kv_update_requested_ps(adev, new_ps);
1910
1911 kv_apply_state_adjust_rules(adev,
1912 &pi->requested_rps,
1913 &pi->current_rps);
1914
1915 return 0;
1916}
1917
1918static int kv_dpm_set_power_state(void *handle)
1919{
1920 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1921 struct kv_power_info *pi = kv_get_pi(adev);
1922 struct amdgpu_ps *new_ps = &pi->requested_rps;
1923 struct amdgpu_ps *old_ps = &pi->current_rps;
1924 int ret;
1925
1926 if (pi->bapm_enable) {
1927 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power);
1928 if (ret) {
1929 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1930 return ret;
1931 }
1932 }
1933
1934 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
1935 if (pi->enable_dpm) {
1936 kv_set_valid_clock_range(adev, new_ps);
1937 kv_update_dfs_bypass_settings(adev, new_ps);
1938 ret = kv_calculate_ds_divider(adev);
1939 if (ret) {
1940 DRM_ERROR("kv_calculate_ds_divider failed\n");
1941 return ret;
1942 }
1943 kv_calculate_nbps_level_settings(adev);
1944 kv_calculate_dpm_settings(adev);
1945 kv_force_lowest_valid(adev);
1946 kv_enable_new_levels(adev);
1947 kv_upload_dpm_settings(adev);
1948 kv_program_nbps_index_settings(adev, new_ps);
1949 kv_unforce_levels(adev);
1950 kv_set_enabled_levels(adev);
1951 kv_force_lowest_valid(adev);
1952 kv_unforce_levels(adev);
1953
1954 ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1955 if (ret) {
1956 DRM_ERROR("kv_update_vce_dpm failed\n");
1957 return ret;
1958 }
1959 kv_update_sclk_t(adev);
1960 if (adev->asic_type == CHIP_MULLINS)
1961 kv_enable_nb_dpm(adev, true);
1962 }
1963 } else {
1964 if (pi->enable_dpm) {
1965 kv_set_valid_clock_range(adev, new_ps);
1966 kv_update_dfs_bypass_settings(adev, new_ps);
1967 ret = kv_calculate_ds_divider(adev);
1968 if (ret) {
1969 DRM_ERROR("kv_calculate_ds_divider failed\n");
1970 return ret;
1971 }
1972 kv_calculate_nbps_level_settings(adev);
1973 kv_calculate_dpm_settings(adev);
1974 kv_freeze_sclk_dpm(adev, true);
1975 kv_upload_dpm_settings(adev);
1976 kv_program_nbps_index_settings(adev, new_ps);
1977 kv_freeze_sclk_dpm(adev, false);
1978 kv_set_enabled_levels(adev);
1979 ret = kv_update_vce_dpm(adev, new_ps, old_ps);
1980 if (ret) {
1981 DRM_ERROR("kv_update_vce_dpm failed\n");
1982 return ret;
1983 }
1984 kv_update_acp_boot_level(adev);
1985 kv_update_sclk_t(adev);
1986 kv_enable_nb_dpm(adev, true);
1987 }
1988 }
1989
1990 return 0;
1991}
1992
1993static void kv_dpm_post_set_power_state(void *handle)
1994{
1995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1996 struct kv_power_info *pi = kv_get_pi(adev);
1997 struct amdgpu_ps *new_ps = &pi->requested_rps;
1998
1999 kv_update_current_ps(adev, new_ps);
2000}
2001
2002static void kv_dpm_setup_asic(struct amdgpu_device *adev)
2003{
2004 sumo_take_smu_control(adev, true);
2005 kv_init_powergate_state(adev);
2006 kv_init_sclk_t(adev);
2007}
2008
2009#if 0
2010static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2011{
2012 struct kv_power_info *pi = kv_get_pi(adev);
2013
2014 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2015 kv_force_lowest_valid(adev);
2016 kv_init_graphics_levels(adev);
2017 kv_program_bootup_state(adev);
2018 kv_upload_dpm_settings(adev);
2019 kv_force_lowest_valid(adev);
2020 kv_unforce_levels(adev);
2021 } else {
2022 kv_init_graphics_levels(adev);
2023 kv_program_bootup_state(adev);
2024 kv_freeze_sclk_dpm(adev, true);
2025 kv_upload_dpm_settings(adev);
2026 kv_freeze_sclk_dpm(adev, false);
2027 kv_set_enabled_level(adev, pi->graphics_boot_level);
2028 }
2029}
2030#endif
2031
2032static void kv_construct_max_power_limits_table(struct amdgpu_device *adev,
2033 struct amdgpu_clock_and_voltage_limits *table)
2034{
2035 struct kv_power_info *pi = kv_get_pi(adev);
2036
2037 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
2038 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
2039 table->sclk =
2040 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
2041 table->vddc =
2042 kv_convert_2bit_index_to_voltage(adev,
2043 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
2044 }
2045
2046 table->mclk = pi->sys_info.nbp_memory_clock[0];
2047}
2048
2049static void kv_patch_voltage_values(struct amdgpu_device *adev)
2050{
2051 int i;
2052 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table =
2053 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
2054 struct amdgpu_vce_clock_voltage_dependency_table *vce_table =
2055 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2056 struct amdgpu_clock_voltage_dependency_table *samu_table =
2057 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
2058 struct amdgpu_clock_voltage_dependency_table *acp_table =
2059 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
2060
2061 if (uvd_table->count) {
2062 for (i = 0; i < uvd_table->count; i++)
2063 uvd_table->entries[i].v =
2064 kv_convert_8bit_index_to_voltage(adev,
2065 uvd_table->entries[i].v);
2066 }
2067
2068 if (vce_table->count) {
2069 for (i = 0; i < vce_table->count; i++)
2070 vce_table->entries[i].v =
2071 kv_convert_8bit_index_to_voltage(adev,
2072 vce_table->entries[i].v);
2073 }
2074
2075 if (samu_table->count) {
2076 for (i = 0; i < samu_table->count; i++)
2077 samu_table->entries[i].v =
2078 kv_convert_8bit_index_to_voltage(adev,
2079 samu_table->entries[i].v);
2080 }
2081
2082 if (acp_table->count) {
2083 for (i = 0; i < acp_table->count; i++)
2084 acp_table->entries[i].v =
2085 kv_convert_8bit_index_to_voltage(adev,
2086 acp_table->entries[i].v);
2087 }
2088
2089}
2090
2091static void kv_construct_boot_state(struct amdgpu_device *adev)
2092{
2093 struct kv_power_info *pi = kv_get_pi(adev);
2094
2095 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
2096 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
2097 pi->boot_pl.ds_divider_index = 0;
2098 pi->boot_pl.ss_divider_index = 0;
2099 pi->boot_pl.allow_gnb_slow = 1;
2100 pi->boot_pl.force_nbp_state = 0;
2101 pi->boot_pl.display_wm = 0;
2102 pi->boot_pl.vce_wm = 0;
2103}
2104
2105static int kv_force_dpm_highest(struct amdgpu_device *adev)
2106{
2107 int ret;
2108 u32 enable_mask, i;
2109
2110 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2111 if (ret)
2112 return ret;
2113
2114 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
2115 if (enable_mask & (1 << i))
2116 break;
2117 }
2118
2119 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2120 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2121 else
2122 return kv_set_enabled_level(adev, i);
2123}
2124
2125static int kv_force_dpm_lowest(struct amdgpu_device *adev)
2126{
2127 int ret;
2128 u32 enable_mask, i;
2129
2130 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask);
2131 if (ret)
2132 return ret;
2133
2134 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2135 if (enable_mask & (1 << i))
2136 break;
2137 }
2138
2139 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2140 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i);
2141 else
2142 return kv_set_enabled_level(adev, i);
2143}
2144
2145static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,
2146 u32 sclk, u32 min_sclk_in_sr)
2147{
2148 struct kv_power_info *pi = kv_get_pi(adev);
2149 u32 i;
2150 u32 temp;
2151 u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK);
2152
2153 if (sclk < min)
2154 return 0;
2155
2156 if (!pi->caps_sclk_ds)
2157 return 0;
2158
2159 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
2160 temp = sclk >> i;
2161 if (temp >= min)
2162 break;
2163 }
2164
2165 return (u8)i;
2166}
2167
2168static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit)
2169{
2170 struct kv_power_info *pi = kv_get_pi(adev);
2171 struct amdgpu_clock_voltage_dependency_table *table =
2172 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2173 int i;
2174
2175 if (table && table->count) {
2176 for (i = table->count - 1; i >= 0; i--) {
2177 if (pi->high_voltage_t &&
2178 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
2179 pi->high_voltage_t)) {
2180 *limit = i;
2181 return 0;
2182 }
2183 }
2184 } else {
2185 struct sumo_sclk_voltage_mapping_table *table =
2186 &pi->sys_info.sclk_voltage_mapping_table;
2187
2188 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2189 if (pi->high_voltage_t &&
2190 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
2191 pi->high_voltage_t)) {
2192 *limit = i;
2193 return 0;
2194 }
2195 }
2196 }
2197
2198 *limit = 0;
2199 return 0;
2200}
2201
2202static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
2203 struct amdgpu_ps *new_rps,
2204 struct amdgpu_ps *old_rps)
2205{
2206 struct kv_ps *ps = kv_get_ps(new_rps);
2207 struct kv_power_info *pi = kv_get_pi(adev);
2208 u32 min_sclk = 10000; /* ??? */
2209 u32 sclk, mclk = 0;
2210 int i, limit;
2211 bool force_high;
2212 struct amdgpu_clock_voltage_dependency_table *table =
2213 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2214 u32 stable_p_state_sclk = 0;
2215 struct amdgpu_clock_and_voltage_limits *max_limits =
2216 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2217
2218 if (new_rps->vce_active) {
2219 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
2220 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
2221 } else {
2222 new_rps->evclk = 0;
2223 new_rps->ecclk = 0;
2224 }
2225
2226 mclk = max_limits->mclk;
2227 sclk = min_sclk;
2228
2229 if (pi->caps_stable_p_state) {
2230 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2231
2232 for (i = table->count - 1; i >= 0; i--) {
2233 if (stable_p_state_sclk >= table->entries[i].clk) {
2234 stable_p_state_sclk = table->entries[i].clk;
2235 break;
2236 }
2237 }
2238
2239 if (i > 0)
2240 stable_p_state_sclk = table->entries[0].clk;
2241
2242 sclk = stable_p_state_sclk;
2243 }
2244
2245 if (new_rps->vce_active) {
2246 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
2247 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
2248 }
2249
2250 ps->need_dfs_bypass = true;
2251
2252 for (i = 0; i < ps->num_levels; i++) {
2253 if (ps->levels[i].sclk < sclk)
2254 ps->levels[i].sclk = sclk;
2255 }
2256
2257 if (table && table->count) {
2258 for (i = 0; i < ps->num_levels; i++) {
2259 if (pi->high_voltage_t &&
2260 (pi->high_voltage_t <
2261 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2262 kv_get_high_voltage_limit(adev, &limit);
2263 ps->levels[i].sclk = table->entries[limit].clk;
2264 }
2265 }
2266 } else {
2267 struct sumo_sclk_voltage_mapping_table *table =
2268 &pi->sys_info.sclk_voltage_mapping_table;
2269
2270 for (i = 0; i < ps->num_levels; i++) {
2271 if (pi->high_voltage_t &&
2272 (pi->high_voltage_t <
2273 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {
2274 kv_get_high_voltage_limit(adev, &limit);
2275 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2276 }
2277 }
2278 }
2279
2280 if (pi->caps_stable_p_state) {
2281 for (i = 0; i < ps->num_levels; i++) {
2282 ps->levels[i].sclk = stable_p_state_sclk;
2283 }
2284 }
2285
2286 pi->video_start = new_rps->dclk || new_rps->vclk ||
2287 new_rps->evclk || new_rps->ecclk;
2288
2289 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2290 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2291 pi->battery_state = true;
2292 else
2293 pi->battery_state = false;
2294
2295 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2296 ps->dpm0_pg_nb_ps_lo = 0x1;
2297 ps->dpm0_pg_nb_ps_hi = 0x0;
2298 ps->dpmx_nb_ps_lo = 0x1;
2299 ps->dpmx_nb_ps_hi = 0x0;
2300 } else {
2301 ps->dpm0_pg_nb_ps_lo = 0x3;
2302 ps->dpm0_pg_nb_ps_hi = 0x0;
2303 ps->dpmx_nb_ps_lo = 0x3;
2304 ps->dpmx_nb_ps_hi = 0x0;
2305
2306 if (pi->sys_info.nb_dpm_enable) {
2307 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2308 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||
2309 pi->disable_nb_ps3_in_battery;
2310 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2311 ps->dpm0_pg_nb_ps_hi = 0x2;
2312 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2313 ps->dpmx_nb_ps_hi = 0x2;
2314 }
2315 }
2316}
2317
2318static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev,
2319 u32 index, bool enable)
2320{
2321 struct kv_power_info *pi = kv_get_pi(adev);
2322
2323 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2324}
2325
2326static int kv_calculate_ds_divider(struct amdgpu_device *adev)
2327{
2328 struct kv_power_info *pi = kv_get_pi(adev);
2329 u32 sclk_in_sr = 10000; /* ??? */
2330 u32 i;
2331
2332 if (pi->lowest_valid > pi->highest_valid)
2333 return -EINVAL;
2334
2335 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2336 pi->graphics_level[i].DeepSleepDivId =
2337 kv_get_sleep_divider_id_from_clock(adev,
2338 be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2339 sclk_in_sr);
2340 }
2341 return 0;
2342}
2343
2344static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev)
2345{
2346 struct kv_power_info *pi = kv_get_pi(adev);
2347 u32 i;
2348 bool force_high;
2349 struct amdgpu_clock_and_voltage_limits *max_limits =
2350 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2351 u32 mclk = max_limits->mclk;
2352
2353 if (pi->lowest_valid > pi->highest_valid)
2354 return -EINVAL;
2355
2356 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2357 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2358 pi->graphics_level[i].GnbSlow = 1;
2359 pi->graphics_level[i].ForceNbPs1 = 0;
2360 pi->graphics_level[i].UpH = 0;
2361 }
2362
2363 if (!pi->sys_info.nb_dpm_enable)
2364 return 0;
2365
2366 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2367 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2368
2369 if (force_high) {
2370 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2371 pi->graphics_level[i].GnbSlow = 0;
2372 } else {
2373 if (pi->battery_state)
2374 pi->graphics_level[0].ForceNbPs1 = 1;
2375
2376 pi->graphics_level[1].GnbSlow = 0;
2377 pi->graphics_level[2].GnbSlow = 0;
2378 pi->graphics_level[3].GnbSlow = 0;
2379 pi->graphics_level[4].GnbSlow = 0;
2380 }
2381 } else {
2382 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2383 pi->graphics_level[i].GnbSlow = 1;
2384 pi->graphics_level[i].ForceNbPs1 = 0;
2385 pi->graphics_level[i].UpH = 0;
2386 }
2387
2388 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2389 pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2390 pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2391 if (pi->lowest_valid != pi->highest_valid)
2392 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2393 }
2394 }
2395 return 0;
2396}
2397
2398static int kv_calculate_dpm_settings(struct amdgpu_device *adev)
2399{
2400 struct kv_power_info *pi = kv_get_pi(adev);
2401 u32 i;
2402
2403 if (pi->lowest_valid > pi->highest_valid)
2404 return -EINVAL;
2405
2406 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2407 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2408
2409 return 0;
2410}
2411
2412static void kv_init_graphics_levels(struct amdgpu_device *adev)
2413{
2414 struct kv_power_info *pi = kv_get_pi(adev);
2415 u32 i;
2416 struct amdgpu_clock_voltage_dependency_table *table =
2417 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2418
2419 if (table && table->count) {
2420 u32 vid_2bit;
2421
2422 pi->graphics_dpm_level_count = 0;
2423 for (i = 0; i < table->count; i++) {
2424 if (pi->high_voltage_t &&
2425 (pi->high_voltage_t <
2426 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
2427 break;
2428
2429 kv_set_divider_value(adev, i, table->entries[i].clk);
2430 vid_2bit = kv_convert_vid7_to_vid2(adev,
2431 &pi->sys_info.vid_mapping_table,
2432 table->entries[i].v);
2433 kv_set_vid(adev, i, vid_2bit);
2434 kv_set_at(adev, i, pi->at[i]);
2435 kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2436 pi->graphics_dpm_level_count++;
2437 }
2438 } else {
2439 struct sumo_sclk_voltage_mapping_table *table =
2440 &pi->sys_info.sclk_voltage_mapping_table;
2441
2442 pi->graphics_dpm_level_count = 0;
2443 for (i = 0; i < table->num_max_dpm_entries; i++) {
2444 if (pi->high_voltage_t &&
2445 pi->high_voltage_t <
2446 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
2447 break;
2448
2449 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
2450 kv_set_vid(adev, i, table->entries[i].vid_2bit);
2451 kv_set_at(adev, i, pi->at[i]);
2452 kv_dpm_power_level_enabled_for_throttle(adev, i, true);
2453 pi->graphics_dpm_level_count++;
2454 }
2455 }
2456
2457 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2458 kv_dpm_power_level_enable(adev, i, false);
2459}
2460
2461static void kv_enable_new_levels(struct amdgpu_device *adev)
2462{
2463 struct kv_power_info *pi = kv_get_pi(adev);
2464 u32 i;
2465
2466 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2467 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2468 kv_dpm_power_level_enable(adev, i, true);
2469 }
2470}
2471
2472static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level)
2473{
2474 u32 new_mask = (1 << level);
2475
2476 return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2477 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2478 new_mask);
2479}
2480
2481static int kv_set_enabled_levels(struct amdgpu_device *adev)
2482{
2483 struct kv_power_info *pi = kv_get_pi(adev);
2484 u32 i, new_mask = 0;
2485
2486 for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2487 new_mask |= (1 << i);
2488
2489 return amdgpu_kv_send_msg_to_smc_with_parameter(adev,
2490 PPSMC_MSG_SCLKDPM_SetEnabledMask,
2491 new_mask);
2492}
2493
2494static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
2495 struct amdgpu_ps *new_rps)
2496{
2497 struct kv_ps *new_ps = kv_get_ps(new_rps);
2498 struct kv_power_info *pi = kv_get_pi(adev);
2499 u32 nbdpmconfig1;
2500
2501 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
2502 return;
2503
2504 if (pi->sys_info.nb_dpm_enable) {
2505 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1);
2506 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK |
2507 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK |
2508 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK |
2509 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK);
2510 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) |
2511 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) |
2512 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) |
2513 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT);
2514 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1);
2515 }
2516}
2517
2518static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
2519 int min_temp, int max_temp)
2520{
2521 int low_temp = 0 * 1000;
2522 int high_temp = 255 * 1000;
2523 u32 tmp;
2524
2525 if (low_temp < min_temp)
2526 low_temp = min_temp;
2527 if (high_temp > max_temp)
2528 high_temp = max_temp;
2529 if (high_temp < low_temp) {
2530 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2531 return -EINVAL;
2532 }
2533
2534 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
2535 tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK |
2536 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
2537 tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) |
2538 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
2539 WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp);
2540
2541 adev->pm.dpm.thermal.min_temp = low_temp;
2542 adev->pm.dpm.thermal.max_temp = high_temp;
2543
2544 return 0;
2545}
2546
2547union igp_info {
2548 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2549 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2550 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2551 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2552 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2553 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2554};
2555
2556static int kv_parse_sys_info_table(struct amdgpu_device *adev)
2557{
2558 struct kv_power_info *pi = kv_get_pi(adev);
2559 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2560 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2561 union igp_info *igp_info;
2562 u8 frev, crev;
2563 u16 data_offset;
2564 int i;
2565
2566 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2567 &frev, &crev, &data_offset)) {
2568 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2569 data_offset);
2570
2571 if (crev != 8) {
2572 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2573 return -EINVAL;
2574 }
2575 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2576 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2577 pi->sys_info.bootup_nb_voltage_index =
2578 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2579 if (igp_info->info_8.ucHtcTmpLmt == 0)
2580 pi->sys_info.htc_tmp_lmt = 203;
2581 else
2582 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2583 if (igp_info->info_8.ucHtcHystLmt == 0)
2584 pi->sys_info.htc_hyst_lmt = 5;
2585 else
2586 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2587 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2588 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2589 }
2590
2591 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2592 pi->sys_info.nb_dpm_enable = true;
2593 else
2594 pi->sys_info.nb_dpm_enable = false;
2595
2596 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2597 pi->sys_info.nbp_memory_clock[i] =
2598 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2599 pi->sys_info.nbp_n_clock[i] =
2600 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2601 }
2602 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2603 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2604 pi->caps_enable_dfs_bypass = true;
2605
2606 sumo_construct_sclk_voltage_mapping_table(adev,
2607 &pi->sys_info.sclk_voltage_mapping_table,
2608 igp_info->info_8.sAvail_SCLK);
2609
2610 sumo_construct_vid_mapping_table(adev,
2611 &pi->sys_info.vid_mapping_table,
2612 igp_info->info_8.sAvail_SCLK);
2613
2614 kv_construct_max_power_limits_table(adev,
2615 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2616 }
2617 return 0;
2618}
2619
2620union power_info {
2621 struct _ATOM_POWERPLAY_INFO info;
2622 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2623 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2624 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2625 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2626 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2627};
2628
2629union pplib_clock_info {
2630 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2631 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2632 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2633 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2634};
2635
2636union pplib_power_state {
2637 struct _ATOM_PPLIB_STATE v1;
2638 struct _ATOM_PPLIB_STATE_V2 v2;
2639};
2640
2641static void kv_patch_boot_state(struct amdgpu_device *adev,
2642 struct kv_ps *ps)
2643{
2644 struct kv_power_info *pi = kv_get_pi(adev);
2645
2646 ps->num_levels = 1;
2647 ps->levels[0] = pi->boot_pl;
2648}
2649
2650static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev,
2651 struct amdgpu_ps *rps,
2652 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2653 u8 table_rev)
2654{
2655 struct kv_ps *ps = kv_get_ps(rps);
2656
2657 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2658 rps->class = le16_to_cpu(non_clock_info->usClassification);
2659 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2660
2661 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2662 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2663 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2664 } else {
2665 rps->vclk = 0;
2666 rps->dclk = 0;
2667 }
2668
2669 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2670 adev->pm.dpm.boot_ps = rps;
2671 kv_patch_boot_state(adev, ps);
2672 }
2673 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2674 adev->pm.dpm.uvd_ps = rps;
2675}
2676
2677static void kv_parse_pplib_clock_info(struct amdgpu_device *adev,
2678 struct amdgpu_ps *rps, int index,
2679 union pplib_clock_info *clock_info)
2680{
2681 struct kv_power_info *pi = kv_get_pi(adev);
2682 struct kv_ps *ps = kv_get_ps(rps);
2683 struct kv_pl *pl = &ps->levels[index];
2684 u32 sclk;
2685
2686 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2687 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2688 pl->sclk = sclk;
2689 pl->vddc_index = clock_info->sumo.vddcIndex;
2690
2691 ps->num_levels = index + 1;
2692
2693 if (pi->caps_sclk_ds) {
2694 pl->ds_divider_index = 5;
2695 pl->ss_divider_index = 5;
2696 }
2697}
2698
2699static int kv_parse_power_table(struct amdgpu_device *adev)
2700{
2701 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2702 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2703 union pplib_power_state *power_state;
2704 int i, j, k, non_clock_array_index, clock_array_index;
2705 union pplib_clock_info *clock_info;
2706 struct _StateArray *state_array;
2707 struct _ClockInfoArray *clock_info_array;
2708 struct _NonClockInfoArray *non_clock_info_array;
2709 union power_info *power_info;
2710 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2711 u16 data_offset;
2712 u8 frev, crev;
2713 u8 *power_state_offset;
2714 struct kv_ps *ps;
2715
2716 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
2717 &frev, &crev, &data_offset))
2718 return -EINVAL;
2719 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2720
2721 amdgpu_add_thermal_controller(adev);
2722
2723 state_array = (struct _StateArray *)
2724 (mode_info->atom_context->bios + data_offset +
2725 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2726 clock_info_array = (struct _ClockInfoArray *)
2727 (mode_info->atom_context->bios + data_offset +
2728 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2729 non_clock_info_array = (struct _NonClockInfoArray *)
2730 (mode_info->atom_context->bios + data_offset +
2731 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2732
2733 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
2734 sizeof(struct amdgpu_ps),
2735 GFP_KERNEL);
2736 if (!adev->pm.dpm.ps)
2737 return -ENOMEM;
2738 power_state_offset = (u8 *)state_array->states;
2739 for (i = 0; i < state_array->ucNumEntries; i++) {
2740 u8 *idx;
2741 power_state = (union pplib_power_state *)power_state_offset;
2742 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2743 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2744 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2745 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2746 if (ps == NULL) {
2747 kfree(adev->pm.dpm.ps);
2748 return -ENOMEM;
2749 }
2750 adev->pm.dpm.ps[i].ps_priv = ps;
2751 k = 0;
2752 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2753 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2754 clock_array_index = idx[j];
2755 if (clock_array_index >= clock_info_array->ucNumEntries)
2756 continue;
2757 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2758 break;
2759 clock_info = (union pplib_clock_info *)
2760 ((u8 *)&clock_info_array->clockInfo[0] +
2761 (clock_array_index * clock_info_array->ucEntrySize));
2762 kv_parse_pplib_clock_info(adev,
2763 &adev->pm.dpm.ps[i], k,
2764 clock_info);
2765 k++;
2766 }
2767 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
2768 non_clock_info,
2769 non_clock_info_array->ucEntrySize);
2770 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2771 }
2772 adev->pm.dpm.num_ps = state_array->ucNumEntries;
2773
2774 /* fill in the vce power states */
2775 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
2776 u32 sclk;
2777 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
2778 clock_info = (union pplib_clock_info *)
2779 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2780 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2781 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2782 adev->pm.dpm.vce_states[i].sclk = sclk;
2783 adev->pm.dpm.vce_states[i].mclk = 0;
2784 }
2785
2786 return 0;
2787}
2788
2789static int kv_dpm_init(struct amdgpu_device *adev)
2790{
2791 struct kv_power_info *pi;
2792 int ret, i;
2793
2794 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2795 if (pi == NULL)
2796 return -ENOMEM;
2797 adev->pm.dpm.priv = pi;
2798
2799 ret = amdgpu_get_platform_caps(adev);
2800 if (ret)
2801 return ret;
2802
2803 ret = amdgpu_parse_extended_power_table(adev);
2804 if (ret)
2805 return ret;
2806
2807 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2808 pi->at[i] = TRINITY_AT_DFLT;
2809
2810 pi->sram_end = SMC_RAM_END;
2811
2812 pi->enable_nb_dpm = true;
2813
2814 pi->caps_power_containment = true;
2815 pi->caps_cac = true;
2816 pi->enable_didt = false;
2817 if (pi->enable_didt) {
2818 pi->caps_sq_ramping = true;
2819 pi->caps_db_ramping = true;
2820 pi->caps_td_ramping = true;
2821 pi->caps_tcp_ramping = true;
2822 }
2823
2824 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
2825 pi->caps_sclk_ds = true;
2826 else
2827 pi->caps_sclk_ds = false;
2828
2829 pi->enable_auto_thermal_throttling = true;
2830 pi->disable_nb_ps3_in_battery = false;
2831 if (amdgpu_bapm == 0)
2832 pi->bapm_enable = false;
2833 else
2834 pi->bapm_enable = true;
2835 pi->voltage_drop_t = 0;
2836 pi->caps_sclk_throttle_low_notification = false;
2837 pi->caps_fps = false; /* true? */
2838 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;
2839 pi->caps_uvd_dpm = true;
2840 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;
2841 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;
2842 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;
2843 pi->caps_stable_p_state = false;
2844
2845 ret = kv_parse_sys_info_table(adev);
2846 if (ret)
2847 return ret;
2848
2849 kv_patch_voltage_values(adev);
2850 kv_construct_boot_state(adev);
2851
2852 ret = kv_parse_power_table(adev);
2853 if (ret)
2854 return ret;
2855
2856 pi->enable_dpm = true;
2857
2858 return 0;
2859}
2860
2861static void
2862kv_dpm_debugfs_print_current_performance_level(void *handle,
2863 struct seq_file *m)
2864{
2865 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2866 struct kv_power_info *pi = kv_get_pi(adev);
2867 u32 current_index =
2868 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
2869 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
2870 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
2871 u32 sclk, tmp;
2872 u16 vddc;
2873
2874 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2875 seq_printf(m, "invalid dpm profile %d\n", current_index);
2876 } else {
2877 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2878 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) &
2879 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2880 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT;
2881 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp);
2882 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
2883 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");
2884 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
2885 current_index, sclk, vddc);
2886 }
2887}
2888
2889static void
2890kv_dpm_print_power_state(void *handle, void *request_ps)
2891{
2892 int i;
2893 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
2894 struct kv_ps *ps = kv_get_ps(rps);
2895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2896
2897 amdgpu_dpm_print_class_info(rps->class, rps->class2);
2898 amdgpu_dpm_print_cap_info(rps->caps);
2899 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2900 for (i = 0; i < ps->num_levels; i++) {
2901 struct kv_pl *pl = &ps->levels[i];
2902 printk("\t\tpower level %d sclk: %u vddc: %u\n",
2903 i, pl->sclk,
2904 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index));
2905 }
2906 amdgpu_dpm_print_ps_status(adev, rps);
2907}
2908
2909static void kv_dpm_fini(struct amdgpu_device *adev)
2910{
2911 int i;
2912
2913 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
2914 kfree(adev->pm.dpm.ps[i].ps_priv);
2915 }
2916 kfree(adev->pm.dpm.ps);
2917 kfree(adev->pm.dpm.priv);
2918 amdgpu_free_extended_power_table(adev);
2919}
2920
2921static void kv_dpm_display_configuration_changed(void *handle)
2922{
2923
2924}
2925
2926static u32 kv_dpm_get_sclk(void *handle, bool low)
2927{
2928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2929 struct kv_power_info *pi = kv_get_pi(adev);
2930 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2931
2932 if (low)
2933 return requested_state->levels[0].sclk;
2934 else
2935 return requested_state->levels[requested_state->num_levels - 1].sclk;
2936}
2937
2938static u32 kv_dpm_get_mclk(void *handle, bool low)
2939{
2940 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2941 struct kv_power_info *pi = kv_get_pi(adev);
2942
2943 return pi->sys_info.bootup_uma_clk;
2944}
2945
2946/* get temperature in millidegrees */
2947static int kv_dpm_get_temp(void *handle)
2948{
2949 u32 temp;
2950 int actual_temp = 0;
2951 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2952
2953 temp = RREG32_SMC(0xC0300E0C);
2954
2955 if (temp)
2956 actual_temp = (temp / 8) - 49;
2957 else
2958 actual_temp = 0;
2959
2960 actual_temp = actual_temp * 1000;
2961
2962 return actual_temp;
2963}
2964
2965static int kv_dpm_early_init(void *handle)
2966{
2967 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2968
2969 adev->powerplay.pp_funcs = &kv_dpm_funcs;
2970 adev->powerplay.pp_handle = adev;
2971 kv_dpm_set_irq_funcs(adev);
2972
2973 return 0;
2974}
2975
2976static int kv_dpm_late_init(void *handle)
2977{
2978 /* powerdown unused blocks for now */
2979 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2980
2981 if (!adev->pm.dpm_enabled)
2982 return 0;
2983
2984 kv_dpm_powergate_acp(adev, true);
2985 kv_dpm_powergate_samu(adev, true);
2986
2987 return 0;
2988}
2989
2990static int kv_dpm_sw_init(void *handle)
2991{
2992 int ret;
2993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2994
2995 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230,
2996 &adev->pm.dpm.thermal.irq);
2997 if (ret)
2998 return ret;
2999
3000 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231,
3001 &adev->pm.dpm.thermal.irq);
3002 if (ret)
3003 return ret;
3004
3005 /* default to balanced state */
3006 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
3007 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
3008 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
3009 adev->pm.default_sclk = adev->clock.default_sclk;
3010 adev->pm.default_mclk = adev->clock.default_mclk;
3011 adev->pm.current_sclk = adev->clock.default_sclk;
3012 adev->pm.current_mclk = adev->clock.default_mclk;
3013 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
3014
3015 if (amdgpu_dpm == 0)
3016 return 0;
3017
3018 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
3019 mutex_lock(&adev->pm.mutex);
3020 ret = kv_dpm_init(adev);
3021 if (ret)
3022 goto dpm_failed;
3023 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3024 if (amdgpu_dpm == 1)
3025 amdgpu_pm_print_power_states(adev);
3026 mutex_unlock(&adev->pm.mutex);
3027 DRM_INFO("amdgpu: dpm initialized\n");
3028
3029 return 0;
3030
3031dpm_failed:
3032 kv_dpm_fini(adev);
3033 mutex_unlock(&adev->pm.mutex);
3034 DRM_ERROR("amdgpu: dpm initialization failed\n");
3035 return ret;
3036}
3037
3038static int kv_dpm_sw_fini(void *handle)
3039{
3040 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3041
3042 flush_work(&adev->pm.dpm.thermal.work);
3043
3044 mutex_lock(&adev->pm.mutex);
3045 kv_dpm_fini(adev);
3046 mutex_unlock(&adev->pm.mutex);
3047
3048 return 0;
3049}
3050
3051static int kv_dpm_hw_init(void *handle)
3052{
3053 int ret;
3054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3055
3056 if (!amdgpu_dpm)
3057 return 0;
3058
3059 mutex_lock(&adev->pm.mutex);
3060 kv_dpm_setup_asic(adev);
3061 ret = kv_dpm_enable(adev);
3062 if (ret)
3063 adev->pm.dpm_enabled = false;
3064 else
3065 adev->pm.dpm_enabled = true;
3066 mutex_unlock(&adev->pm.mutex);
3067 amdgpu_pm_compute_clocks(adev);
3068 return ret;
3069}
3070
3071static int kv_dpm_hw_fini(void *handle)
3072{
3073 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3074
3075 if (adev->pm.dpm_enabled) {
3076 mutex_lock(&adev->pm.mutex);
3077 kv_dpm_disable(adev);
3078 mutex_unlock(&adev->pm.mutex);
3079 }
3080
3081 return 0;
3082}
3083
3084static int kv_dpm_suspend(void *handle)
3085{
3086 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3087
3088 if (adev->pm.dpm_enabled) {
3089 mutex_lock(&adev->pm.mutex);
3090 /* disable dpm */
3091 kv_dpm_disable(adev);
3092 /* reset the power state */
3093 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
3094 mutex_unlock(&adev->pm.mutex);
3095 }
3096 return 0;
3097}
3098
3099static int kv_dpm_resume(void *handle)
3100{
3101 int ret;
3102 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3103
3104 if (adev->pm.dpm_enabled) {
3105 /* asic init will reset to the boot state */
3106 mutex_lock(&adev->pm.mutex);
3107 kv_dpm_setup_asic(adev);
3108 ret = kv_dpm_enable(adev);
3109 if (ret)
3110 adev->pm.dpm_enabled = false;
3111 else
3112 adev->pm.dpm_enabled = true;
3113 mutex_unlock(&adev->pm.mutex);
3114 if (adev->pm.dpm_enabled)
3115 amdgpu_pm_compute_clocks(adev);
3116 }
3117 return 0;
3118}
3119
3120static bool kv_dpm_is_idle(void *handle)
3121{
3122 return true;
3123}
3124
3125static int kv_dpm_wait_for_idle(void *handle)
3126{
3127 return 0;
3128}
3129
3130
3131static int kv_dpm_soft_reset(void *handle)
3132{
3133 return 0;
3134}
3135
3136static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev,
3137 struct amdgpu_irq_src *src,
3138 unsigned type,
3139 enum amdgpu_interrupt_state state)
3140{
3141 u32 cg_thermal_int;
3142
3143 switch (type) {
3144 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
3145 switch (state) {
3146 case AMDGPU_IRQ_STATE_DISABLE:
3147 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3148 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3149 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3150 break;
3151 case AMDGPU_IRQ_STATE_ENABLE:
3152 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3153 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
3154 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3155 break;
3156 default:
3157 break;
3158 }
3159 break;
3160
3161 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
3162 switch (state) {
3163 case AMDGPU_IRQ_STATE_DISABLE:
3164 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3165 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3166 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3167 break;
3168 case AMDGPU_IRQ_STATE_ENABLE:
3169 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL);
3170 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
3171 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int);
3172 break;
3173 default:
3174 break;
3175 }
3176 break;
3177
3178 default:
3179 break;
3180 }
3181 return 0;
3182}
3183
3184static int kv_dpm_process_interrupt(struct amdgpu_device *adev,
3185 struct amdgpu_irq_src *source,
3186 struct amdgpu_iv_entry *entry)
3187{
3188 bool queue_thermal = false;
3189
3190 if (entry == NULL)
3191 return -EINVAL;
3192
3193 switch (entry->src_id) {
3194 case 230: /* thermal low to high */
3195 DRM_DEBUG("IH: thermal low to high\n");
3196 adev->pm.dpm.thermal.high_to_low = false;
3197 queue_thermal = true;
3198 break;
3199 case 231: /* thermal high to low */
3200 DRM_DEBUG("IH: thermal high to low\n");
3201 adev->pm.dpm.thermal.high_to_low = true;
3202 queue_thermal = true;
3203 break;
3204 default:
3205 break;
3206 }
3207
3208 if (queue_thermal)
3209 schedule_work(&adev->pm.dpm.thermal.work);
3210
3211 return 0;
3212}
3213
3214static int kv_dpm_set_clockgating_state(void *handle,
3215 enum amd_clockgating_state state)
3216{
3217 return 0;
3218}
3219
3220static int kv_dpm_set_powergating_state(void *handle,
3221 enum amd_powergating_state state)
3222{
3223 return 0;
3224}
3225
3226static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
3227 const struct kv_pl *kv_cpl2)
3228{
3229 return ((kv_cpl1->sclk == kv_cpl2->sclk) &&
3230 (kv_cpl1->vddc_index == kv_cpl2->vddc_index) &&
3231 (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) &&
3232 (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
3233}
3234
3235static int kv_check_state_equal(void *handle,
3236 void *current_ps,
3237 void *request_ps,
3238 bool *equal)
3239{
3240 struct kv_ps *kv_cps;
3241 struct kv_ps *kv_rps;
3242 int i;
3243 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
3244 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
3245 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3246
3247 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
3248 return -EINVAL;
3249
3250 kv_cps = kv_get_ps(cps);
3251 kv_rps = kv_get_ps(rps);
3252
3253 if (kv_cps == NULL) {
3254 *equal = false;
3255 return 0;
3256 }
3257
3258 if (kv_cps->num_levels != kv_rps->num_levels) {
3259 *equal = false;
3260 return 0;
3261 }
3262
3263 for (i = 0; i < kv_cps->num_levels; i++) {
3264 if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
3265 &(kv_rps->levels[i]))) {
3266 *equal = false;
3267 return 0;
3268 }
3269 }
3270
3271 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
3272 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
3273 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
3274
3275 return 0;
3276}
3277
3278static int kv_dpm_read_sensor(void *handle, int idx,
3279 void *value, int *size)
3280{
3281 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3282 struct kv_power_info *pi = kv_get_pi(adev);
3283 uint32_t sclk;
3284 u32 pl_index =
3285 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
3286 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
3287 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
3288
3289 /* size must be at least 4 bytes for all sensors */
3290 if (*size < 4)
3291 return -EINVAL;
3292
3293 switch (idx) {
3294 case AMDGPU_PP_SENSOR_GFX_SCLK:
3295 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
3296 sclk = be32_to_cpu(
3297 pi->graphics_level[pl_index].SclkFrequency);
3298 *((uint32_t *)value) = sclk;
3299 *size = 4;
3300 return 0;
3301 }
3302 return -EINVAL;
3303 case AMDGPU_PP_SENSOR_GPU_TEMP:
3304 *((uint32_t *)value) = kv_dpm_get_temp(adev);
3305 *size = 4;
3306 return 0;
3307 default:
3308 return -EOPNOTSUPP;
3309 }
3310}
3311
3312static int kv_set_powergating_by_smu(void *handle,
3313 uint32_t block_type, bool gate)
3314{
3315 switch (block_type) {
3316 case AMD_IP_BLOCK_TYPE_UVD:
3317 kv_dpm_powergate_uvd(handle, gate);
3318 break;
3319 case AMD_IP_BLOCK_TYPE_VCE:
3320 kv_dpm_powergate_vce(handle, gate);
3321 break;
3322 default:
3323 break;
3324 }
3325 return 0;
3326}
3327
3328static const struct amd_ip_funcs kv_dpm_ip_funcs = {
3329 .name = "kv_dpm",
3330 .early_init = kv_dpm_early_init,
3331 .late_init = kv_dpm_late_init,
3332 .sw_init = kv_dpm_sw_init,
3333 .sw_fini = kv_dpm_sw_fini,
3334 .hw_init = kv_dpm_hw_init,
3335 .hw_fini = kv_dpm_hw_fini,
3336 .suspend = kv_dpm_suspend,
3337 .resume = kv_dpm_resume,
3338 .is_idle = kv_dpm_is_idle,
3339 .wait_for_idle = kv_dpm_wait_for_idle,
3340 .soft_reset = kv_dpm_soft_reset,
3341 .set_clockgating_state = kv_dpm_set_clockgating_state,
3342 .set_powergating_state = kv_dpm_set_powergating_state,
3343};
3344
3345const struct amdgpu_ip_block_version kv_smu_ip_block =
3346{
3347 .type = AMD_IP_BLOCK_TYPE_SMC,
3348 .major = 1,
3349 .minor = 0,
3350 .rev = 0,
3351 .funcs = &kv_dpm_ip_funcs,
3352};
3353
3354static const struct amd_pm_funcs kv_dpm_funcs = {
3355 .pre_set_power_state = &kv_dpm_pre_set_power_state,
3356 .set_power_state = &kv_dpm_set_power_state,
3357 .post_set_power_state = &kv_dpm_post_set_power_state,
3358 .display_configuration_changed = &kv_dpm_display_configuration_changed,
3359 .get_sclk = &kv_dpm_get_sclk,
3360 .get_mclk = &kv_dpm_get_mclk,
3361 .print_power_state = &kv_dpm_print_power_state,
3362 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
3363 .force_performance_level = &kv_dpm_force_performance_level,
3364 .set_powergating_by_smu = kv_set_powergating_by_smu,
3365 .enable_bapm = &kv_dpm_enable_bapm,
3366 .get_vce_clock_state = amdgpu_get_vce_clock_state,
3367 .check_state_equal = kv_check_state_equal,
3368 .read_sensor = &kv_dpm_read_sensor,
3369};
3370
3371static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
3372 .set = kv_dpm_set_interrupt_state,
3373 .process = kv_dpm_process_interrupt,
3374};
3375
3376static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev)
3377{
3378 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
3379 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs;
3380}