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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef SMU72_H
25#define SMU72_H
26
27#if !defined(SMC_MICROCODE)
28#pragma pack(push, 1)
29#endif
30
31#define SMU__NUM_SCLK_DPM_STATE 8
32#define SMU__NUM_MCLK_DPM_LEVELS 4
33#define SMU__NUM_LCLK_DPM_LEVELS 8
34#define SMU__NUM_PCIE_DPM_LEVELS 8
35
36enum SID_OPTION {
37 SID_OPTION_HI,
38 SID_OPTION_LO,
39 SID_OPTION_COUNT
40};
41
42enum Poly3rdOrderCoeff {
43 LEAKAGE_TEMPERATURE_SCALAR,
44 LEAKAGE_VOLTAGE_SCALAR,
45 DYNAMIC_VOLTAGE_SCALAR,
46 POLY_3RD_ORDER_COUNT
47};
48
49struct SMU7_Poly3rdOrder_Data {
50 int32_t a;
51 int32_t b;
52 int32_t c;
53 int32_t d;
54 uint8_t a_shift;
55 uint8_t b_shift;
56 uint8_t c_shift;
57 uint8_t x_shift;
58};
59
60typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
61
62struct Power_Calculator_Data {
63 uint16_t NoLoadVoltage;
64 uint16_t LoadVoltage;
65 uint16_t Resistance;
66 uint16_t Temperature;
67 uint16_t BaseLeakage;
68 uint16_t LkgTempScalar;
69 uint16_t LkgVoltScalar;
70 uint16_t LkgAreaScalar;
71 uint16_t LkgPower;
72 uint16_t DynVoltScalar;
73 uint32_t Cac;
74 uint32_t DynPower;
75 uint32_t TotalCurrent;
76 uint32_t TotalPower;
77};
78
79typedef struct Power_Calculator_Data PowerCalculatorData_t;
80
81struct Gc_Cac_Weight_Data {
82 uint8_t index;
83 uint32_t value;
84};
85
86typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
87
88
89typedef struct {
90 uint32_t high;
91 uint32_t low;
92} data_64_t;
93
94typedef struct {
95 data_64_t high;
96 data_64_t low;
97} data_128_t;
98
99#define SMU7_CONTEXT_ID_SMC 1
100#define SMU7_CONTEXT_ID_VBIOS 2
101
102#define SMU72_MAX_LEVELS_VDDC 16
103#define SMU72_MAX_LEVELS_VDDGFX 16
104#define SMU72_MAX_LEVELS_VDDCI 8
105#define SMU72_MAX_LEVELS_MVDD 4
106
107#define SMU_MAX_SMIO_LEVELS 4
108
109#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
110#define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
111#define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */
112#define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */
113#define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */
114#define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */
115#define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */
116#define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */
117#define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */
118
119#define DPM_NO_LIMIT 0
120#define DPM_NO_UP 1
121#define DPM_GO_DOWN 2
122#define DPM_GO_UP 3
123
124#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
125#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
126
127#define GPIO_CLAMP_MODE_VRHOT 1
128#define GPIO_CLAMP_MODE_THERM 2
129#define GPIO_CLAMP_MODE_DC 4
130
131#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
132#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
133#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
134#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
135#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
136#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
137#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
138#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
139#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
140#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
141#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
142#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
143#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
144#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
145#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
146#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
147#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
148#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
149#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
150#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
151
152/* Virtualization Defines */
153#define CG_XDMA_MASK 0x1
154#define CG_XDMA_SHIFT 0
155#define CG_UVD_MASK 0x2
156#define CG_UVD_SHIFT 1
157#define CG_VCE_MASK 0x4
158#define CG_VCE_SHIFT 2
159#define CG_SAMU_MASK 0x8
160#define CG_SAMU_SHIFT 3
161#define CG_GFX_MASK 0x10
162#define CG_GFX_SHIFT 4
163#define CG_SDMA_MASK 0x20
164#define CG_SDMA_SHIFT 5
165#define CG_HDP_MASK 0x40
166#define CG_HDP_SHIFT 6
167#define CG_MC_MASK 0x80
168#define CG_MC_SHIFT 7
169#define CG_DRM_MASK 0x100
170#define CG_DRM_SHIFT 8
171#define CG_ROM_MASK 0x200
172#define CG_ROM_SHIFT 9
173#define CG_BIF_MASK 0x400
174#define CG_BIF_SHIFT 10
175
176#define SMU72_DTE_ITERATIONS 5
177#define SMU72_DTE_SOURCES 3
178#define SMU72_DTE_SINKS 1
179#define SMU72_NUM_CPU_TES 0
180#define SMU72_NUM_GPU_TES 1
181#define SMU72_NUM_NON_TES 2
182#define SMU72_DTE_FAN_SCALAR_MIN 0x100
183#define SMU72_DTE_FAN_SCALAR_MAX 0x166
184#define SMU72_DTE_FAN_TEMP_MAX 93
185#define SMU72_DTE_FAN_TEMP_MIN 83
186
187#if defined SMU__FUSION_ONLY
188#define SMU7_DTE_ITERATIONS 5
189#define SMU7_DTE_SOURCES 5
190#define SMU7_DTE_SINKS 3
191#define SMU7_NUM_CPU_TES 2
192#define SMU7_NUM_GPU_TES 1
193#define SMU7_NUM_NON_TES 2
194#endif
195
196struct SMU7_HystController_Data {
197 uint8_t waterfall_up;
198 uint8_t waterfall_down;
199 uint8_t waterfall_limit;
200 uint8_t spare;
201 uint16_t release_cnt;
202 uint16_t release_limit;
203};
204
205typedef struct SMU7_HystController_Data SMU7_HystController_Data;
206
207struct SMU72_PIDController {
208 uint32_t Ki;
209 int32_t LFWindupUpperLim;
210 int32_t LFWindupLowerLim;
211 uint32_t StatePrecision;
212 uint32_t LfPrecision;
213 uint32_t LfOffset;
214 uint32_t MaxState;
215 uint32_t MaxLfFraction;
216 uint32_t StateShift;
217};
218
219typedef struct SMU72_PIDController SMU72_PIDController;
220
221struct SMU7_LocalDpmScoreboard {
222 uint32_t PercentageBusy;
223
224 int32_t PIDError;
225 int32_t PIDIntegral;
226 int32_t PIDOutput;
227
228 uint32_t SigmaDeltaAccum;
229 uint32_t SigmaDeltaOutput;
230 uint32_t SigmaDeltaLevel;
231
232 uint32_t UtilizationSetpoint;
233
234 uint8_t TdpClampMode;
235 uint8_t TdcClampMode;
236 uint8_t ThermClampMode;
237 uint8_t VoltageBusy;
238
239 int8_t CurrLevel;
240 int8_t TargLevel;
241 uint8_t LevelChangeInProgress;
242 uint8_t UpHyst;
243
244 uint8_t DownHyst;
245 uint8_t VoltageDownHyst;
246 uint8_t DpmEnable;
247 uint8_t DpmRunning;
248
249 uint8_t DpmForce;
250 uint8_t DpmForceLevel;
251 uint8_t DisplayWatermark;
252 uint8_t McArbIndex;
253
254 uint32_t MinimumPerfSclk;
255
256 uint8_t AcpiReq;
257 uint8_t AcpiAck;
258 uint8_t GfxClkSlow;
259 uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
260
261 uint8_t FpsFilterWeight;
262 uint8_t EnabledLevelsChange;
263 uint8_t DteClampMode;
264 uint8_t FpsClampMode;
265
266 uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
267 uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
268
269 void (*TargetStateCalculator)(uint8_t);
270 void (*SavedTargetStateCalculator)(uint8_t);
271
272 uint16_t AutoDpmInterval;
273 uint16_t AutoDpmRange;
274
275 uint8_t FpsEnabled;
276 uint8_t MaxPerfLevel;
277 uint8_t AllowLowClkInterruptToHost;
278 uint8_t FpsRunning;
279
280 uint32_t MaxAllowedFrequency;
281
282 uint32_t FilteredSclkFrequency;
283 uint32_t LastSclkFrequency;
284 uint32_t FilteredSclkFrequencyCnt;
285};
286
287typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
288
289#define SMU7_MAX_VOLTAGE_CLIENTS 12
290
291typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
292
293struct SMU_VoltageLevel {
294 uint8_t Vddc;
295 uint8_t Vddci;
296 uint8_t VddGfx;
297 uint8_t Phases;
298};
299
300typedef struct SMU_VoltageLevel SMU_VoltageLevel;
301
302struct SMU7_VoltageScoreboard {
303 SMU_VoltageLevel CurrentVoltage;
304 SMU_VoltageLevel TargetVoltage;
305 uint16_t MaxVid;
306 uint8_t HighestVidOffset;
307 uint8_t CurrentVidOffset;
308
309 uint8_t ControllerBusy;
310 uint8_t CurrentVid;
311 uint8_t CurrentVddciVid;
312 uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
313
314 SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
315 uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
316
317 uint8_t TargetIndex;
318 uint8_t Delay;
319 uint8_t ControllerEnable;
320 uint8_t ControllerRunning;
321 uint16_t CurrentStdVoltageHiSidd;
322 uint16_t CurrentStdVoltageLoSidd;
323 uint8_t OverrideVoltage;
324 uint8_t VddcUseUlvOffset;
325 uint8_t VddGfxUseUlvOffset;
326 uint8_t padding;
327
328 VoltageChangeHandler_t ChangeVddc;
329 VoltageChangeHandler_t ChangeVddGfx;
330 VoltageChangeHandler_t ChangeVddci;
331 VoltageChangeHandler_t ChangePhase;
332 VoltageChangeHandler_t ChangeMvdd;
333
334 VoltageChangeHandler_t functionLinks[6];
335
336 uint8_t *VddcFollower1;
337 uint8_t *VddcFollower2;
338 int16_t Driver_OD_RequestedVidOffset1;
339 int16_t Driver_OD_RequestedVidOffset2;
340
341};
342
343typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
344
345#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
346
347struct SMU7_PCIeLinkSpeedScoreboard {
348 uint8_t DpmEnable;
349 uint8_t DpmRunning;
350 uint8_t DpmForce;
351 uint8_t DpmForceLevel;
352
353 uint8_t CurrentLinkSpeed;
354 uint8_t EnabledLevelsChange;
355 uint16_t AutoDpmInterval;
356
357 uint16_t AutoDpmRange;
358 uint16_t AutoDpmCount;
359
360 uint8_t DpmMode;
361 uint8_t AcpiReq;
362 uint8_t AcpiAck;
363 uint8_t CurrentLinkLevel;
364
365};
366
367typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
368
369/* -------------------------------------------------------- CAC table ------------------------------------------------------ */
370#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
371#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
372#define SMU7_SCALE_I 7
373#define SMU7_SCALE_R 12
374
375struct SMU7_PowerScoreboard {
376 PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
377 PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
378
379 uint32_t TotalGpuPower;
380 uint32_t TdcCurrent;
381
382 uint16_t VddciTotalPower;
383 uint16_t sparesasfsdfd;
384 uint16_t Vddr1Power;
385 uint16_t RocPower;
386
387 uint16_t CalcMeasPowerBlend;
388 uint8_t SidOptionPower;
389 uint8_t SidOptionCurrent;
390
391 uint32_t WinTime;
392
393 uint16_t Telemetry_1_slope;
394 uint16_t Telemetry_2_slope;
395 int32_t Telemetry_1_offset;
396 int32_t Telemetry_2_offset;
397
398 uint32_t VddcCurrentTelemetry;
399 uint32_t VddGfxCurrentTelemetry;
400 uint32_t VddcPowerTelemetry;
401 uint32_t VddGfxPowerTelemetry;
402 uint32_t VddciPowerTelemetry;
403
404 uint32_t VddcPower;
405 uint32_t VddGfxPower;
406 uint32_t VddciPower;
407
408 uint32_t TelemetryCurrent[2];
409 uint32_t TelemetryVoltage[2];
410 uint32_t TelemetryPower[2];
411};
412
413typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
414
415struct SMU7_ThermalScoreboard {
416 int16_t GpuLimit;
417 int16_t GpuHyst;
418 uint16_t CurrGnbTemp;
419 uint16_t FilteredGnbTemp;
420
421 uint8_t ControllerEnable;
422 uint8_t ControllerRunning;
423 uint8_t AutoTmonCalInterval;
424 uint8_t AutoTmonCalEnable;
425
426 uint8_t ThermalDpmEnabled;
427 uint8_t SclkEnabledMask;
428 uint8_t spare[2];
429 int32_t temperature_gradient;
430
431 SMU7_HystController_Data HystControllerData;
432 int32_t WeightedSensorTemperature;
433 uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
434 uint32_t Alpha;
435};
436
437typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
438
439/* For FeatureEnables: */
440#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
441#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
442#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
443#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
444#define SMU7_UVD_DPM_CONFIG_MASK 0x10
445#define SMU7_VCE_DPM_CONFIG_MASK 0x20
446#define SMU7_ACP_DPM_CONFIG_MASK 0x40
447#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
448#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
449
450#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
451#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
452#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
453#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
454#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
455#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
456
457/* All 'soft registers' should be uint32_t. */
458struct SMU72_SoftRegisters {
459 uint32_t RefClockFrequency;
460 uint32_t PmTimerPeriod;
461 uint32_t FeatureEnables;
462
463 uint32_t PreVBlankGap;
464 uint32_t VBlankTimeout;
465 uint32_t TrainTimeGap;
466
467 uint32_t MvddSwitchTime;
468 uint32_t LongestAcpiTrainTime;
469 uint32_t AcpiDelay;
470 uint32_t G5TrainTime;
471 uint32_t DelayMpllPwron;
472 uint32_t VoltageChangeTimeout;
473
474 uint32_t HandshakeDisables;
475
476 uint8_t DisplayPhy1Config;
477 uint8_t DisplayPhy2Config;
478 uint8_t DisplayPhy3Config;
479 uint8_t DisplayPhy4Config;
480
481 uint8_t DisplayPhy5Config;
482 uint8_t DisplayPhy6Config;
483 uint8_t DisplayPhy7Config;
484 uint8_t DisplayPhy8Config;
485
486 uint32_t AverageGraphicsActivity;
487 uint32_t AverageMemoryActivity;
488 uint32_t AverageGioActivity;
489
490 uint8_t SClkDpmEnabledLevels;
491 uint8_t MClkDpmEnabledLevels;
492 uint8_t LClkDpmEnabledLevels;
493 uint8_t PCIeDpmEnabledLevels;
494
495 uint8_t UVDDpmEnabledLevels;
496 uint8_t SAMUDpmEnabledLevels;
497 uint8_t ACPDpmEnabledLevels;
498 uint8_t VCEDpmEnabledLevels;
499
500 uint32_t DRAM_LOG_ADDR_H;
501 uint32_t DRAM_LOG_ADDR_L;
502 uint32_t DRAM_LOG_PHY_ADDR_H;
503 uint32_t DRAM_LOG_PHY_ADDR_L;
504 uint32_t DRAM_LOG_BUFF_SIZE;
505 uint32_t UlvEnterCount;
506 uint32_t UlvTime;
507 uint32_t UcodeLoadStatus;
508 uint32_t Reserved[2];
509
510};
511
512typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
513
514struct SMU72_Firmware_Header {
515 uint32_t Digest[5];
516 uint32_t Version;
517 uint32_t HeaderSize;
518 uint32_t Flags;
519 uint32_t EntryPoint;
520 uint32_t CodeSize;
521 uint32_t ImageSize;
522
523 uint32_t Rtos;
524 uint32_t SoftRegisters;
525 uint32_t DpmTable;
526 uint32_t FanTable;
527 uint32_t CacConfigTable;
528 uint32_t CacStatusTable;
529 uint32_t mcRegisterTable;
530 uint32_t mcArbDramTimingTable;
531 uint32_t PmFuseTable;
532 uint32_t Globals;
533 uint32_t ClockStretcherTable;
534 uint32_t Reserved[41];
535 uint32_t Signature;
536};
537
538typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
539
540#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
541
542enum DisplayConfig {
543 PowerDown = 1,
544 DP54x4,
545 DP54x2,
546 DP54x1,
547 DP27x4,
548 DP27x2,
549 DP27x1,
550 HDMI297,
551 HDMI162,
552 LVDS,
553 DP324x4,
554 DP324x2,
555 DP324x1
556};
557
558#define MC_BLOCK_COUNT 1
559#define CPL_BLOCK_COUNT 5
560#define SE_BLOCK_COUNT 15
561#define GC_BLOCK_COUNT 24
562
563struct SMU7_Local_Cac {
564 uint8_t BlockId;
565 uint8_t SignalId;
566 uint8_t Threshold;
567 uint8_t Padding;
568};
569
570typedef struct SMU7_Local_Cac SMU7_Local_Cac;
571
572struct SMU7_Local_Cac_Table {
573 SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
574 SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
575 SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
576 SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
577};
578
579typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
580
581#if !defined(SMC_MICROCODE)
582#pragma pack(pop)
583#endif
584
585/* Description of Clock Gating bitmask for Tonga: */
586/* System Clock Gating */
587#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */
588#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */
589#define CG_SYS_BIF_MGLS_SHIFT 0
590#define CG_SYS_ROM_SHIFT 1
591#define CG_SYS_MC_MGCG_SHIFT 2
592#define CG_SYS_MC_MGLS_SHIFT 3
593#define CG_SYS_SDMA_MGCG_SHIFT 4
594#define CG_SYS_SDMA_MGLS_SHIFT 5
595#define CG_SYS_DRM_MGCG_SHIFT 6
596#define CG_SYS_HDP_MGCG_SHIFT 7
597#define CG_SYS_HDP_MGLS_SHIFT 8
598#define CG_SYS_DRM_MGLS_SHIFT 9
599
600#define CG_SYS_BIF_MGLS_MASK 0x1
601#define CG_SYS_ROM_MASK 0x2
602#define CG_SYS_MC_MGCG_MASK 0x4
603#define CG_SYS_MC_MGLS_MASK 0x8
604#define CG_SYS_SDMA_MGCG_MASK 0x10
605#define CG_SYS_SDMA_MGLS_MASK 0x20
606#define CG_SYS_DRM_MGCG_MASK 0x40
607#define CG_SYS_HDP_MGCG_MASK 0x80
608#define CG_SYS_HDP_MGLS_MASK 0x100
609#define CG_SYS_DRM_MGLS_MASK 0x200
610
611/* Graphics Clock Gating */
612#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */
613#define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */
614#define CG_GFX_CGCG_SHIFT 16
615#define CG_GFX_CGLS_SHIFT 17
616#define CG_CPF_MGCG_SHIFT 18
617#define CG_RLC_MGCG_SHIFT 19
618#define CG_GFX_OTHERS_MGCG_SHIFT 20
619
620#define CG_GFX_CGCG_MASK 0x00010000
621#define CG_GFX_CGLS_MASK 0x00020000
622#define CG_CPF_MGCG_MASK 0x00040000
623#define CG_RLC_MGCG_MASK 0x00080000
624#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
625
626/* Voltage Regulator Configuration */
627/* VR Config info is contained in dpmTable.VRConfig */
628
629#define VRCONF_VDDC_MASK 0x000000FF
630#define VRCONF_VDDC_SHIFT 0
631#define VRCONF_VDDGFX_MASK 0x0000FF00
632#define VRCONF_VDDGFX_SHIFT 8
633#define VRCONF_VDDCI_MASK 0x00FF0000
634#define VRCONF_VDDCI_SHIFT 16
635#define VRCONF_MVDD_MASK 0xFF000000
636#define VRCONF_MVDD_SHIFT 24
637
638#define VR_MERGED_WITH_VDDC 0
639#define VR_SVI2_PLANE_1 1
640#define VR_SVI2_PLANE_2 2
641#define VR_SMIO_PATTERN_1 3
642#define VR_SMIO_PATTERN_2 4
643#define VR_STATIC_VOLTAGE 5
644
645/* Clock Stretcher Configuration */
646
647#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
648#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
649
650/* The 'settings' field is subdivided in the following way: */
651#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
652#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
653#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
654#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
655#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
656#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
657
658struct SMU_ClockStretcherDataTableEntry {
659 uint8_t minVID;
660 uint8_t maxVID;
661
662 uint16_t setting;
663};
664typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
665
666struct SMU_ClockStretcherDataTable {
667 SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
668};
669typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
670
671struct SMU_CKS_LOOKUPTableEntry {
672 uint16_t minFreq;
673 uint16_t maxFreq;
674
675 uint8_t setting;
676 uint8_t padding[3];
677};
678typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
679
680struct SMU_CKS_LOOKUPTable {
681 SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
682};
683typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
684
685#endif
686
687