1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Christian König
 23 */
 24#ifndef __AMDGPU_RING_H__
 25#define __AMDGPU_RING_H__
 26
 27#include <drm/amdgpu_drm.h>
 28#include <drm/gpu_scheduler.h>
 29#include <drm/drm_print.h>
 30
 31/* max number of rings */
 32#define AMDGPU_MAX_RINGS		28
 33#define AMDGPU_MAX_HWIP_RINGS		8
 34#define AMDGPU_MAX_GFX_RINGS		2
 35#define AMDGPU_MAX_COMPUTE_RINGS	8
 36#define AMDGPU_MAX_VCE_RINGS		3
 37#define AMDGPU_MAX_UVD_ENC_RINGS	2
 38
 39#define AMDGPU_RING_PRIO_DEFAULT	1
 40#define AMDGPU_RING_PRIO_MAX		AMDGPU_GFX_PIPE_PRIO_MAX
 41
 42/* some special values for the owner field */
 43#define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)
 44#define AMDGPU_FENCE_OWNER_VM		((void *)1ul)
 45#define AMDGPU_FENCE_OWNER_KFD		((void *)2ul)
 46
 47#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
 48#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
 49#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)
 50
 51#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
 52
 53#define AMDGPU_IB_POOL_SIZE	(1024 * 1024)
 54
 55enum amdgpu_ring_type {
 56	AMDGPU_RING_TYPE_GFX		= AMDGPU_HW_IP_GFX,
 57	AMDGPU_RING_TYPE_COMPUTE	= AMDGPU_HW_IP_COMPUTE,
 58	AMDGPU_RING_TYPE_SDMA		= AMDGPU_HW_IP_DMA,
 59	AMDGPU_RING_TYPE_UVD		= AMDGPU_HW_IP_UVD,
 60	AMDGPU_RING_TYPE_VCE		= AMDGPU_HW_IP_VCE,
 61	AMDGPU_RING_TYPE_UVD_ENC	= AMDGPU_HW_IP_UVD_ENC,
 62	AMDGPU_RING_TYPE_VCN_DEC	= AMDGPU_HW_IP_VCN_DEC,
 63	AMDGPU_RING_TYPE_VCN_ENC	= AMDGPU_HW_IP_VCN_ENC,
 64	AMDGPU_RING_TYPE_VCN_JPEG	= AMDGPU_HW_IP_VCN_JPEG,
 65	AMDGPU_RING_TYPE_KIQ,
 66	AMDGPU_RING_TYPE_MES
 67};
 68
 69enum amdgpu_ib_pool_type {
 70	/* Normal submissions to the top of the pipeline. */
 71	AMDGPU_IB_POOL_DELAYED,
 72	/* Immediate submissions to the bottom of the pipeline. */
 73	AMDGPU_IB_POOL_IMMEDIATE,
 74	/* Direct submission to the ring buffer during init and reset. */
 75	AMDGPU_IB_POOL_DIRECT,
 76
 77	AMDGPU_IB_POOL_MAX
 78};
 79
 80struct amdgpu_device;
 81struct amdgpu_ring;
 82struct amdgpu_ib;
 83struct amdgpu_cs_parser;
 84struct amdgpu_job;
 85
 86struct amdgpu_sched {
 87	u32				num_scheds;
 88	struct drm_gpu_scheduler	*sched[AMDGPU_MAX_HWIP_RINGS];
 89};
 90
 91/*
 92 * Fences.
 93 */
 94struct amdgpu_fence_driver {
 95	uint64_t			gpu_addr;
 96	volatile uint32_t		*cpu_addr;
 97	/* sync_seq is protected by ring emission lock */
 98	uint32_t			sync_seq;
 99	atomic_t			last_seq;
100	bool				initialized;
101	struct amdgpu_irq_src		*irq_src;
102	unsigned			irq_type;
103	struct timer_list		fallback_timer;
104	unsigned			num_fences_mask;
105	spinlock_t			lock;
106	struct dma_fence		**fences;
107};
108
109void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
110
111int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
112				  unsigned num_hw_submission,
113				  atomic_t *sched_score);
114int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
115				   struct amdgpu_irq_src *irq_src,
116				   unsigned irq_type);
117void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
118void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
119int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
120void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
121int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
122		      unsigned flags);
123int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
124			      uint32_t timeout);
125bool amdgpu_fence_process(struct amdgpu_ring *ring);
126int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
127signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
128				      uint32_t wait_seq,
129				      signed long timeout);
130unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
131
132/*
133 * Rings.
134 */
135
136/* provided by hw blocks that expose a ring buffer for commands */
137struct amdgpu_ring_funcs {
138	enum amdgpu_ring_type	type;
139	uint32_t		align_mask;
140	u32			nop;
141	bool			support_64bit_ptrs;
142	bool			no_user_fence;
143	unsigned		vmhub;
144	unsigned		extra_dw;
145
146	/* ring read/write ptr handling */
147	u64 (*get_rptr)(struct amdgpu_ring *ring);
148	u64 (*get_wptr)(struct amdgpu_ring *ring);
149	void (*set_wptr)(struct amdgpu_ring *ring);
150	/* validating and patching of IBs */
151	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
152	int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
153	/* constants to calculate how many DW are needed for an emit */
154	unsigned emit_frame_size;
155	unsigned emit_ib_size;
156	/* command emit functions */
157	void (*emit_ib)(struct amdgpu_ring *ring,
158			struct amdgpu_job *job,
159			struct amdgpu_ib *ib,
160			uint32_t flags);
161	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
162			   uint64_t seq, unsigned flags);
163	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
164	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
165			      uint64_t pd_addr);
166	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
167	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
168				uint32_t gds_base, uint32_t gds_size,
169				uint32_t gws_base, uint32_t gws_size,
170				uint32_t oa_base, uint32_t oa_size);
171	/* testing functions */
172	int (*test_ring)(struct amdgpu_ring *ring);
173	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
174	/* insert NOP packets */
175	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
176	void (*insert_start)(struct amdgpu_ring *ring);
177	void (*insert_end)(struct amdgpu_ring *ring);
178	/* pad the indirect buffer to the necessary number of dw */
179	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
180	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
181	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
182	/* note usage for clock and power gating */
183	void (*begin_use)(struct amdgpu_ring *ring);
184	void (*end_use)(struct amdgpu_ring *ring);
185	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
186	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
187	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
188			  uint32_t reg_val_offs);
189	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
190	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
191			      uint32_t val, uint32_t mask);
192	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
193					uint32_t reg0, uint32_t reg1,
194					uint32_t ref, uint32_t mask);
195	void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
196				bool secure);
197	/* Try to soft recover the ring to make the fence signal */
198	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
199	int (*preempt_ib)(struct amdgpu_ring *ring);
200	void (*emit_mem_sync)(struct amdgpu_ring *ring);
201	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
202};
203
204struct amdgpu_ring {
205	struct amdgpu_device		*adev;
206	const struct amdgpu_ring_funcs	*funcs;
207	struct amdgpu_fence_driver	fence_drv;
208	struct drm_gpu_scheduler	sched;
209
210	struct amdgpu_bo	*ring_obj;
211	volatile uint32_t	*ring;
212	unsigned		rptr_offs;
213	u64			wptr;
214	u64			wptr_old;
215	unsigned		ring_size;
216	unsigned		max_dw;
217	int			count_dw;
218	uint64_t		gpu_addr;
219	uint64_t		ptr_mask;
220	uint32_t		buf_mask;
221	u32			idx;
222	u32			me;
223	u32			pipe;
224	u32			queue;
225	struct amdgpu_bo	*mqd_obj;
226	uint64_t                mqd_gpu_addr;
227	void                    *mqd_ptr;
228	uint64_t                eop_gpu_addr;
229	u32			doorbell_index;
230	bool			use_doorbell;
231	bool			use_pollmem;
232	unsigned		wptr_offs;
233	unsigned		fence_offs;
234	uint64_t		current_ctx;
235	char			name[16];
236	u32                     trail_seq;
237	unsigned		trail_fence_offs;
238	u64			trail_fence_gpu_addr;
239	volatile u32		*trail_fence_cpu_addr;
240	unsigned		cond_exe_offs;
241	u64			cond_exe_gpu_addr;
242	volatile u32		*cond_exe_cpu_addr;
243	unsigned		vm_inv_eng;
244	struct dma_fence	*vmid_wait;
245	bool			has_compute_vm_bug;
246	bool			no_scheduler;
247	int			hw_prio;
248
249#if defined(CONFIG_DEBUG_FS)
250	struct dentry *ent;
251#endif
252};
253
254#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
255#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
256#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
257#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
258#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
259#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
260#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
261#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
262#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
263#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
264#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
265#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
266#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
267#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
268#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
269#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
270#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
271#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
272#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
273#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
274#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
275#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
276#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
277#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
278
279int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
280void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
281void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
282void amdgpu_ring_commit(struct amdgpu_ring *ring);
283void amdgpu_ring_undo(struct amdgpu_ring *ring);
284int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
285		     unsigned int ring_size, struct amdgpu_irq_src *irq_src,
286		     unsigned int irq_type, unsigned int prio,
287		     atomic_t *sched_score);
288void amdgpu_ring_fini(struct amdgpu_ring *ring);
289void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
290						uint32_t reg0, uint32_t val0,
291						uint32_t reg1, uint32_t val1);
292bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
293			       struct dma_fence *fence);
294
295static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
296							bool cond_exec)
297{
298	*ring->cond_exe_cpu_addr = cond_exec;
299}
300
301static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
302{
303	int i = 0;
304	while (i <= ring->buf_mask)
305		ring->ring[i++] = ring->funcs->nop;
306
307}
308
309static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
310{
311	if (ring->count_dw <= 0)
312		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
313	ring->ring[ring->wptr++ & ring->buf_mask] = v;
314	ring->wptr &= ring->ptr_mask;
315	ring->count_dw--;
316}
317
318static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
319					      void *src, int count_dw)
320{
321	unsigned occupied, chunk1, chunk2;
322	void *dst;
323
324	if (unlikely(ring->count_dw < count_dw))
325		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
326
327	occupied = ring->wptr & ring->buf_mask;
328	dst = (void *)&ring->ring[occupied];
329	chunk1 = ring->buf_mask + 1 - occupied;
330	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
331	chunk2 = count_dw - chunk1;
332	chunk1 <<= 2;
333	chunk2 <<= 2;
334
335	if (chunk1)
336		memcpy(dst, src, chunk1);
337
338	if (chunk2) {
339		src += chunk1;
340		dst = (void *)ring->ring;
341		memcpy(dst, src, chunk2);
342	}
343
344	ring->wptr += count_dw;
345	ring->wptr &= ring->ptr_mask;
346	ring->count_dw -= count_dw;
347}
348
349int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
350
351int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
352			     struct amdgpu_ring *ring);
353void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
354
355#endif