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1/*
2 * Driver for the TXx9 SoC DMA Controller
3 *
4 * Copyright (C) 2009 Atsushi Nemoto
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/dma-mapping.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/scatterlist.h>
18#include "txx9dmac.h"
19
20static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
21{
22 return container_of(chan, struct txx9dmac_chan, chan);
23}
24
25static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
26{
27 return dc->ch_regs;
28}
29
30static struct txx9dmac_cregs32 __iomem *__dma_regs32(
31 const struct txx9dmac_chan *dc)
32{
33 return dc->ch_regs;
34}
35
36#define channel64_readq(dc, name) \
37 __raw_readq(&(__dma_regs(dc)->name))
38#define channel64_writeq(dc, name, val) \
39 __raw_writeq((val), &(__dma_regs(dc)->name))
40#define channel64_readl(dc, name) \
41 __raw_readl(&(__dma_regs(dc)->name))
42#define channel64_writel(dc, name, val) \
43 __raw_writel((val), &(__dma_regs(dc)->name))
44
45#define channel32_readl(dc, name) \
46 __raw_readl(&(__dma_regs32(dc)->name))
47#define channel32_writel(dc, name, val) \
48 __raw_writel((val), &(__dma_regs32(dc)->name))
49
50#define channel_readq(dc, name) channel64_readq(dc, name)
51#define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
52#define channel_readl(dc, name) \
53 (is_dmac64(dc) ? \
54 channel64_readl(dc, name) : channel32_readl(dc, name))
55#define channel_writel(dc, name, val) \
56 (is_dmac64(dc) ? \
57 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
58
59static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
60{
61 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
62 return channel64_readq(dc, CHAR);
63 else
64 return channel64_readl(dc, CHAR);
65}
66
67static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
68{
69 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
70 channel64_writeq(dc, CHAR, val);
71 else
72 channel64_writel(dc, CHAR, val);
73}
74
75static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
76{
77#if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
78 channel64_writel(dc, CHAR, 0);
79 channel64_writel(dc, __pad_CHAR, 0);
80#else
81 channel64_writeq(dc, CHAR, 0);
82#endif
83}
84
85static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
86{
87 if (is_dmac64(dc))
88 return channel64_read_CHAR(dc);
89 else
90 return channel32_readl(dc, CHAR);
91}
92
93static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
94{
95 if (is_dmac64(dc))
96 channel64_write_CHAR(dc, val);
97 else
98 channel32_writel(dc, CHAR, val);
99}
100
101static struct txx9dmac_regs __iomem *__txx9dmac_regs(
102 const struct txx9dmac_dev *ddev)
103{
104 return ddev->regs;
105}
106
107static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
108 const struct txx9dmac_dev *ddev)
109{
110 return ddev->regs;
111}
112
113#define dma64_readl(ddev, name) \
114 __raw_readl(&(__txx9dmac_regs(ddev)->name))
115#define dma64_writel(ddev, name, val) \
116 __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
117
118#define dma32_readl(ddev, name) \
119 __raw_readl(&(__txx9dmac_regs32(ddev)->name))
120#define dma32_writel(ddev, name, val) \
121 __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
122
123#define dma_readl(ddev, name) \
124 (__is_dmac64(ddev) ? \
125 dma64_readl(ddev, name) : dma32_readl(ddev, name))
126#define dma_writel(ddev, name, val) \
127 (__is_dmac64(ddev) ? \
128 dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
129
130static struct device *chan2dev(struct dma_chan *chan)
131{
132 return &chan->dev->device;
133}
134static struct device *chan2parent(struct dma_chan *chan)
135{
136 return chan->dev->device.parent;
137}
138
139static struct txx9dmac_desc *
140txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
141{
142 return container_of(txd, struct txx9dmac_desc, txd);
143}
144
145static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
146 const struct txx9dmac_desc *desc)
147{
148 return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
149}
150
151static void desc_write_CHAR(const struct txx9dmac_chan *dc,
152 struct txx9dmac_desc *desc, dma_addr_t val)
153{
154 if (is_dmac64(dc))
155 desc->hwdesc.CHAR = val;
156 else
157 desc->hwdesc32.CHAR = val;
158}
159
160#define TXX9_DMA_MAX_COUNT 0x04000000
161
162#define TXX9_DMA_INITIAL_DESC_COUNT 64
163
164static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
165{
166 return list_entry(dc->active_list.next,
167 struct txx9dmac_desc, desc_node);
168}
169
170static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
171{
172 return list_entry(dc->active_list.prev,
173 struct txx9dmac_desc, desc_node);
174}
175
176static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
177{
178 return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
179}
180
181static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
182{
183 if (!list_empty(&desc->tx_list))
184 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
185 return desc;
186}
187
188static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
189
190static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
191 gfp_t flags)
192{
193 struct txx9dmac_dev *ddev = dc->ddev;
194 struct txx9dmac_desc *desc;
195
196 desc = kzalloc(sizeof(*desc), flags);
197 if (!desc)
198 return NULL;
199 INIT_LIST_HEAD(&desc->tx_list);
200 dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
201 desc->txd.tx_submit = txx9dmac_tx_submit;
202 /* txd.flags will be overwritten in prep funcs */
203 desc->txd.flags = DMA_CTRL_ACK;
204 desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
205 ddev->descsize, DMA_TO_DEVICE);
206 return desc;
207}
208
209static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
210{
211 struct txx9dmac_desc *desc, *_desc;
212 struct txx9dmac_desc *ret = NULL;
213 unsigned int i = 0;
214
215 spin_lock_bh(&dc->lock);
216 list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
217 if (async_tx_test_ack(&desc->txd)) {
218 list_del(&desc->desc_node);
219 ret = desc;
220 break;
221 }
222 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
223 i++;
224 }
225 spin_unlock_bh(&dc->lock);
226
227 dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
228 i);
229 if (!ret) {
230 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
231 if (ret) {
232 spin_lock_bh(&dc->lock);
233 dc->descs_allocated++;
234 spin_unlock_bh(&dc->lock);
235 } else
236 dev_err(chan2dev(&dc->chan),
237 "not enough descriptors available\n");
238 }
239 return ret;
240}
241
242static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
243 struct txx9dmac_desc *desc)
244{
245 struct txx9dmac_dev *ddev = dc->ddev;
246 struct txx9dmac_desc *child;
247
248 list_for_each_entry(child, &desc->tx_list, desc_node)
249 dma_sync_single_for_cpu(chan2parent(&dc->chan),
250 child->txd.phys, ddev->descsize,
251 DMA_TO_DEVICE);
252 dma_sync_single_for_cpu(chan2parent(&dc->chan),
253 desc->txd.phys, ddev->descsize,
254 DMA_TO_DEVICE);
255}
256
257/*
258 * Move a descriptor, including any children, to the free list.
259 * `desc' must not be on any lists.
260 */
261static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
262 struct txx9dmac_desc *desc)
263{
264 if (desc) {
265 struct txx9dmac_desc *child;
266
267 txx9dmac_sync_desc_for_cpu(dc, desc);
268
269 spin_lock_bh(&dc->lock);
270 list_for_each_entry(child, &desc->tx_list, desc_node)
271 dev_vdbg(chan2dev(&dc->chan),
272 "moving child desc %p to freelist\n",
273 child);
274 list_splice_init(&desc->tx_list, &dc->free_list);
275 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
276 desc);
277 list_add(&desc->desc_node, &dc->free_list);
278 spin_unlock_bh(&dc->lock);
279 }
280}
281
282/* Called with dc->lock held and bh disabled */
283static dma_cookie_t
284txx9dmac_assign_cookie(struct txx9dmac_chan *dc, struct txx9dmac_desc *desc)
285{
286 dma_cookie_t cookie = dc->chan.cookie;
287
288 if (++cookie < 0)
289 cookie = 1;
290
291 dc->chan.cookie = cookie;
292 desc->txd.cookie = cookie;
293
294 return cookie;
295}
296
297/*----------------------------------------------------------------------*/
298
299static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
300{
301 if (is_dmac64(dc))
302 dev_err(chan2dev(&dc->chan),
303 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
304 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
305 (u64)channel64_read_CHAR(dc),
306 channel64_readq(dc, SAR),
307 channel64_readq(dc, DAR),
308 channel64_readl(dc, CNTR),
309 channel64_readl(dc, SAIR),
310 channel64_readl(dc, DAIR),
311 channel64_readl(dc, CCR),
312 channel64_readl(dc, CSR));
313 else
314 dev_err(chan2dev(&dc->chan),
315 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
316 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
317 channel32_readl(dc, CHAR),
318 channel32_readl(dc, SAR),
319 channel32_readl(dc, DAR),
320 channel32_readl(dc, CNTR),
321 channel32_readl(dc, SAIR),
322 channel32_readl(dc, DAIR),
323 channel32_readl(dc, CCR),
324 channel32_readl(dc, CSR));
325}
326
327static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
328{
329 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
330 if (is_dmac64(dc)) {
331 channel64_clear_CHAR(dc);
332 channel_writeq(dc, SAR, 0);
333 channel_writeq(dc, DAR, 0);
334 } else {
335 channel_writel(dc, CHAR, 0);
336 channel_writel(dc, SAR, 0);
337 channel_writel(dc, DAR, 0);
338 }
339 channel_writel(dc, CNTR, 0);
340 channel_writel(dc, SAIR, 0);
341 channel_writel(dc, DAIR, 0);
342 channel_writel(dc, CCR, 0);
343 mmiowb();
344}
345
346/* Called with dc->lock held and bh disabled */
347static void txx9dmac_dostart(struct txx9dmac_chan *dc,
348 struct txx9dmac_desc *first)
349{
350 struct txx9dmac_slave *ds = dc->chan.private;
351 u32 sai, dai;
352
353 dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
354 first->txd.cookie, first);
355 /* ASSERT: channel is idle */
356 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
357 dev_err(chan2dev(&dc->chan),
358 "BUG: Attempted to start non-idle channel\n");
359 txx9dmac_dump_regs(dc);
360 /* The tasklet will hopefully advance the queue... */
361 return;
362 }
363
364 if (is_dmac64(dc)) {
365 channel64_writel(dc, CNTR, 0);
366 channel64_writel(dc, CSR, 0xffffffff);
367 if (ds) {
368 if (ds->tx_reg) {
369 sai = ds->reg_width;
370 dai = 0;
371 } else {
372 sai = 0;
373 dai = ds->reg_width;
374 }
375 } else {
376 sai = 8;
377 dai = 8;
378 }
379 channel64_writel(dc, SAIR, sai);
380 channel64_writel(dc, DAIR, dai);
381 /* All 64-bit DMAC supports SMPCHN */
382 channel64_writel(dc, CCR, dc->ccr);
383 /* Writing a non zero value to CHAR will assert XFACT */
384 channel64_write_CHAR(dc, first->txd.phys);
385 } else {
386 channel32_writel(dc, CNTR, 0);
387 channel32_writel(dc, CSR, 0xffffffff);
388 if (ds) {
389 if (ds->tx_reg) {
390 sai = ds->reg_width;
391 dai = 0;
392 } else {
393 sai = 0;
394 dai = ds->reg_width;
395 }
396 } else {
397 sai = 4;
398 dai = 4;
399 }
400 channel32_writel(dc, SAIR, sai);
401 channel32_writel(dc, DAIR, dai);
402 if (txx9_dma_have_SMPCHN()) {
403 channel32_writel(dc, CCR, dc->ccr);
404 /* Writing a non zero value to CHAR will assert XFACT */
405 channel32_writel(dc, CHAR, first->txd.phys);
406 } else {
407 channel32_writel(dc, CHAR, first->txd.phys);
408 channel32_writel(dc, CCR, dc->ccr);
409 }
410 }
411}
412
413/*----------------------------------------------------------------------*/
414
415static void
416txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
417 struct txx9dmac_desc *desc)
418{
419 dma_async_tx_callback callback;
420 void *param;
421 struct dma_async_tx_descriptor *txd = &desc->txd;
422 struct txx9dmac_slave *ds = dc->chan.private;
423
424 dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
425 txd->cookie, desc);
426
427 dc->completed = txd->cookie;
428 callback = txd->callback;
429 param = txd->callback_param;
430
431 txx9dmac_sync_desc_for_cpu(dc, desc);
432 list_splice_init(&desc->tx_list, &dc->free_list);
433 list_move(&desc->desc_node, &dc->free_list);
434
435 if (!ds) {
436 dma_addr_t dmaaddr;
437 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
438 dmaaddr = is_dmac64(dc) ?
439 desc->hwdesc.DAR : desc->hwdesc32.DAR;
440 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
441 dma_unmap_single(chan2parent(&dc->chan),
442 dmaaddr, desc->len, DMA_FROM_DEVICE);
443 else
444 dma_unmap_page(chan2parent(&dc->chan),
445 dmaaddr, desc->len, DMA_FROM_DEVICE);
446 }
447 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
448 dmaaddr = is_dmac64(dc) ?
449 desc->hwdesc.SAR : desc->hwdesc32.SAR;
450 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
451 dma_unmap_single(chan2parent(&dc->chan),
452 dmaaddr, desc->len, DMA_TO_DEVICE);
453 else
454 dma_unmap_page(chan2parent(&dc->chan),
455 dmaaddr, desc->len, DMA_TO_DEVICE);
456 }
457 }
458
459 /*
460 * The API requires that no submissions are done from a
461 * callback, so we don't need to drop the lock here
462 */
463 if (callback)
464 callback(param);
465 dma_run_dependencies(txd);
466}
467
468static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
469{
470 struct txx9dmac_dev *ddev = dc->ddev;
471 struct txx9dmac_desc *desc;
472 struct txx9dmac_desc *prev = NULL;
473
474 BUG_ON(!list_empty(list));
475 do {
476 desc = txx9dmac_first_queued(dc);
477 if (prev) {
478 desc_write_CHAR(dc, prev, desc->txd.phys);
479 dma_sync_single_for_device(chan2parent(&dc->chan),
480 prev->txd.phys, ddev->descsize,
481 DMA_TO_DEVICE);
482 }
483 prev = txx9dmac_last_child(desc);
484 list_move_tail(&desc->desc_node, list);
485 /* Make chain-completion interrupt happen */
486 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
487 !txx9dmac_chan_INTENT(dc))
488 break;
489 } while (!list_empty(&dc->queue));
490}
491
492static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
493{
494 struct txx9dmac_desc *desc, *_desc;
495 LIST_HEAD(list);
496
497 /*
498 * Submit queued descriptors ASAP, i.e. before we go through
499 * the completed ones.
500 */
501 list_splice_init(&dc->active_list, &list);
502 if (!list_empty(&dc->queue)) {
503 txx9dmac_dequeue(dc, &dc->active_list);
504 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
505 }
506
507 list_for_each_entry_safe(desc, _desc, &list, desc_node)
508 txx9dmac_descriptor_complete(dc, desc);
509}
510
511static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
512 struct txx9dmac_hwdesc *desc)
513{
514 if (is_dmac64(dc)) {
515#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
516 dev_crit(chan2dev(&dc->chan),
517 " desc: ch%#llx s%#llx d%#llx c%#x\n",
518 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
519#else
520 dev_crit(chan2dev(&dc->chan),
521 " desc: ch%#llx s%#llx d%#llx c%#x"
522 " si%#x di%#x cc%#x cs%#x\n",
523 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
524 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
525#endif
526 } else {
527 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
528#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
529 dev_crit(chan2dev(&dc->chan),
530 " desc: ch%#x s%#x d%#x c%#x\n",
531 d->CHAR, d->SAR, d->DAR, d->CNTR);
532#else
533 dev_crit(chan2dev(&dc->chan),
534 " desc: ch%#x s%#x d%#x c%#x"
535 " si%#x di%#x cc%#x cs%#x\n",
536 d->CHAR, d->SAR, d->DAR, d->CNTR,
537 d->SAIR, d->DAIR, d->CCR, d->CSR);
538#endif
539 }
540}
541
542static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
543{
544 struct txx9dmac_desc *bad_desc;
545 struct txx9dmac_desc *child;
546 u32 errors;
547
548 /*
549 * The descriptor currently at the head of the active list is
550 * borked. Since we don't have any way to report errors, we'll
551 * just have to scream loudly and try to carry on.
552 */
553 dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
554 txx9dmac_dump_regs(dc);
555
556 bad_desc = txx9dmac_first_active(dc);
557 list_del_init(&bad_desc->desc_node);
558
559 /* Clear all error flags and try to restart the controller */
560 errors = csr & (TXX9_DMA_CSR_ABCHC |
561 TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
562 TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
563 channel_writel(dc, CSR, errors);
564
565 if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
566 txx9dmac_dequeue(dc, &dc->active_list);
567 if (!list_empty(&dc->active_list))
568 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
569
570 dev_crit(chan2dev(&dc->chan),
571 "Bad descriptor submitted for DMA! (cookie: %d)\n",
572 bad_desc->txd.cookie);
573 txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
574 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
575 txx9dmac_dump_desc(dc, &child->hwdesc);
576 /* Pretend the descriptor completed successfully */
577 txx9dmac_descriptor_complete(dc, bad_desc);
578}
579
580static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
581{
582 dma_addr_t chain;
583 struct txx9dmac_desc *desc, *_desc;
584 struct txx9dmac_desc *child;
585 u32 csr;
586
587 if (is_dmac64(dc)) {
588 chain = channel64_read_CHAR(dc);
589 csr = channel64_readl(dc, CSR);
590 channel64_writel(dc, CSR, csr);
591 } else {
592 chain = channel32_readl(dc, CHAR);
593 csr = channel32_readl(dc, CSR);
594 channel32_writel(dc, CSR, csr);
595 }
596 /* For dynamic chain, we should look at XFACT instead of NCHNC */
597 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
598 /* Everything we've submitted is done */
599 txx9dmac_complete_all(dc);
600 return;
601 }
602 if (!(csr & TXX9_DMA_CSR_CHNEN))
603 chain = 0; /* last descriptor of this chain */
604
605 dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
606 (u64)chain);
607
608 list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
609 if (desc_read_CHAR(dc, desc) == chain) {
610 /* This one is currently in progress */
611 if (csr & TXX9_DMA_CSR_ABCHC)
612 goto scan_done;
613 return;
614 }
615
616 list_for_each_entry(child, &desc->tx_list, desc_node)
617 if (desc_read_CHAR(dc, child) == chain) {
618 /* Currently in progress */
619 if (csr & TXX9_DMA_CSR_ABCHC)
620 goto scan_done;
621 return;
622 }
623
624 /*
625 * No descriptors so far seem to be in progress, i.e.
626 * this one must be done.
627 */
628 txx9dmac_descriptor_complete(dc, desc);
629 }
630scan_done:
631 if (csr & TXX9_DMA_CSR_ABCHC) {
632 txx9dmac_handle_error(dc, csr);
633 return;
634 }
635
636 dev_err(chan2dev(&dc->chan),
637 "BUG: All descriptors done, but channel not idle!\n");
638
639 /* Try to continue after resetting the channel... */
640 txx9dmac_reset_chan(dc);
641
642 if (!list_empty(&dc->queue)) {
643 txx9dmac_dequeue(dc, &dc->active_list);
644 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
645 }
646}
647
648static void txx9dmac_chan_tasklet(unsigned long data)
649{
650 int irq;
651 u32 csr;
652 struct txx9dmac_chan *dc;
653
654 dc = (struct txx9dmac_chan *)data;
655 csr = channel_readl(dc, CSR);
656 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
657
658 spin_lock(&dc->lock);
659 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
660 TXX9_DMA_CSR_NTRNFC))
661 txx9dmac_scan_descriptors(dc);
662 spin_unlock(&dc->lock);
663 irq = dc->irq;
664
665 enable_irq(irq);
666}
667
668static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
669{
670 struct txx9dmac_chan *dc = dev_id;
671
672 dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
673 channel_readl(dc, CSR));
674
675 tasklet_schedule(&dc->tasklet);
676 /*
677 * Just disable the interrupts. We'll turn them back on in the
678 * softirq handler.
679 */
680 disable_irq_nosync(irq);
681
682 return IRQ_HANDLED;
683}
684
685static void txx9dmac_tasklet(unsigned long data)
686{
687 int irq;
688 u32 csr;
689 struct txx9dmac_chan *dc;
690
691 struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
692 u32 mcr;
693 int i;
694
695 mcr = dma_readl(ddev, MCR);
696 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
697 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
698 if ((mcr >> (24 + i)) & 0x11) {
699 dc = ddev->chan[i];
700 csr = channel_readl(dc, CSR);
701 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
702 csr);
703 spin_lock(&dc->lock);
704 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
705 TXX9_DMA_CSR_NTRNFC))
706 txx9dmac_scan_descriptors(dc);
707 spin_unlock(&dc->lock);
708 }
709 }
710 irq = ddev->irq;
711
712 enable_irq(irq);
713}
714
715static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
716{
717 struct txx9dmac_dev *ddev = dev_id;
718
719 dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
720 dma_readl(ddev, MCR));
721
722 tasklet_schedule(&ddev->tasklet);
723 /*
724 * Just disable the interrupts. We'll turn them back on in the
725 * softirq handler.
726 */
727 disable_irq_nosync(irq);
728
729 return IRQ_HANDLED;
730}
731
732/*----------------------------------------------------------------------*/
733
734static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
735{
736 struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
737 struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
738 dma_cookie_t cookie;
739
740 spin_lock_bh(&dc->lock);
741 cookie = txx9dmac_assign_cookie(dc, desc);
742
743 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
744 desc->txd.cookie, desc);
745
746 list_add_tail(&desc->desc_node, &dc->queue);
747 spin_unlock_bh(&dc->lock);
748
749 return cookie;
750}
751
752static struct dma_async_tx_descriptor *
753txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
754 size_t len, unsigned long flags)
755{
756 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
757 struct txx9dmac_dev *ddev = dc->ddev;
758 struct txx9dmac_desc *desc;
759 struct txx9dmac_desc *first;
760 struct txx9dmac_desc *prev;
761 size_t xfer_count;
762 size_t offset;
763
764 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
765 (u64)dest, (u64)src, len, flags);
766
767 if (unlikely(!len)) {
768 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
769 return NULL;
770 }
771
772 prev = first = NULL;
773
774 for (offset = 0; offset < len; offset += xfer_count) {
775 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
776 /*
777 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
778 * ERT-TX49H4-016 (slightly conservative)
779 */
780 if (__is_dmac64(ddev)) {
781 if (xfer_count > 0x100 &&
782 (xfer_count & 0xff) >= 0xfa &&
783 (xfer_count & 0xff) <= 0xff)
784 xfer_count -= 0x20;
785 } else {
786 if (xfer_count > 0x80 &&
787 (xfer_count & 0x7f) >= 0x7e &&
788 (xfer_count & 0x7f) <= 0x7f)
789 xfer_count -= 0x20;
790 }
791
792 desc = txx9dmac_desc_get(dc);
793 if (!desc) {
794 txx9dmac_desc_put(dc, first);
795 return NULL;
796 }
797
798 if (__is_dmac64(ddev)) {
799 desc->hwdesc.SAR = src + offset;
800 desc->hwdesc.DAR = dest + offset;
801 desc->hwdesc.CNTR = xfer_count;
802 txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
803 dc->ccr | TXX9_DMA_CCR_XFACT);
804 } else {
805 desc->hwdesc32.SAR = src + offset;
806 desc->hwdesc32.DAR = dest + offset;
807 desc->hwdesc32.CNTR = xfer_count;
808 txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
809 dc->ccr | TXX9_DMA_CCR_XFACT);
810 }
811
812 /*
813 * The descriptors on tx_list are not reachable from
814 * the dc->queue list or dc->active_list after a
815 * submit. If we put all descriptors on active_list,
816 * calling of callback on the completion will be more
817 * complex.
818 */
819 if (!first) {
820 first = desc;
821 } else {
822 desc_write_CHAR(dc, prev, desc->txd.phys);
823 dma_sync_single_for_device(chan2parent(&dc->chan),
824 prev->txd.phys, ddev->descsize,
825 DMA_TO_DEVICE);
826 list_add_tail(&desc->desc_node, &first->tx_list);
827 }
828 prev = desc;
829 }
830
831 /* Trigger interrupt after last block */
832 if (flags & DMA_PREP_INTERRUPT)
833 txx9dmac_desc_set_INTENT(ddev, prev);
834
835 desc_write_CHAR(dc, prev, 0);
836 dma_sync_single_for_device(chan2parent(&dc->chan),
837 prev->txd.phys, ddev->descsize,
838 DMA_TO_DEVICE);
839
840 first->txd.flags = flags;
841 first->len = len;
842
843 return &first->txd;
844}
845
846static struct dma_async_tx_descriptor *
847txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
848 unsigned int sg_len, enum dma_data_direction direction,
849 unsigned long flags)
850{
851 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
852 struct txx9dmac_dev *ddev = dc->ddev;
853 struct txx9dmac_slave *ds = chan->private;
854 struct txx9dmac_desc *prev;
855 struct txx9dmac_desc *first;
856 unsigned int i;
857 struct scatterlist *sg;
858
859 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
860
861 BUG_ON(!ds || !ds->reg_width);
862 if (ds->tx_reg)
863 BUG_ON(direction != DMA_TO_DEVICE);
864 else
865 BUG_ON(direction != DMA_FROM_DEVICE);
866 if (unlikely(!sg_len))
867 return NULL;
868
869 prev = first = NULL;
870
871 for_each_sg(sgl, sg, sg_len, i) {
872 struct txx9dmac_desc *desc;
873 dma_addr_t mem;
874 u32 sai, dai;
875
876 desc = txx9dmac_desc_get(dc);
877 if (!desc) {
878 txx9dmac_desc_put(dc, first);
879 return NULL;
880 }
881
882 mem = sg_dma_address(sg);
883
884 if (__is_dmac64(ddev)) {
885 if (direction == DMA_TO_DEVICE) {
886 desc->hwdesc.SAR = mem;
887 desc->hwdesc.DAR = ds->tx_reg;
888 } else {
889 desc->hwdesc.SAR = ds->rx_reg;
890 desc->hwdesc.DAR = mem;
891 }
892 desc->hwdesc.CNTR = sg_dma_len(sg);
893 } else {
894 if (direction == DMA_TO_DEVICE) {
895 desc->hwdesc32.SAR = mem;
896 desc->hwdesc32.DAR = ds->tx_reg;
897 } else {
898 desc->hwdesc32.SAR = ds->rx_reg;
899 desc->hwdesc32.DAR = mem;
900 }
901 desc->hwdesc32.CNTR = sg_dma_len(sg);
902 }
903 if (direction == DMA_TO_DEVICE) {
904 sai = ds->reg_width;
905 dai = 0;
906 } else {
907 sai = 0;
908 dai = ds->reg_width;
909 }
910 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
911 dc->ccr | TXX9_DMA_CCR_XFACT);
912
913 if (!first) {
914 first = desc;
915 } else {
916 desc_write_CHAR(dc, prev, desc->txd.phys);
917 dma_sync_single_for_device(chan2parent(&dc->chan),
918 prev->txd.phys,
919 ddev->descsize,
920 DMA_TO_DEVICE);
921 list_add_tail(&desc->desc_node, &first->tx_list);
922 }
923 prev = desc;
924 }
925
926 /* Trigger interrupt after last block */
927 if (flags & DMA_PREP_INTERRUPT)
928 txx9dmac_desc_set_INTENT(ddev, prev);
929
930 desc_write_CHAR(dc, prev, 0);
931 dma_sync_single_for_device(chan2parent(&dc->chan),
932 prev->txd.phys, ddev->descsize,
933 DMA_TO_DEVICE);
934
935 first->txd.flags = flags;
936 first->len = 0;
937
938 return &first->txd;
939}
940
941static int txx9dmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
942 unsigned long arg)
943{
944 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
945 struct txx9dmac_desc *desc, *_desc;
946 LIST_HEAD(list);
947
948 /* Only supports DMA_TERMINATE_ALL */
949 if (cmd != DMA_TERMINATE_ALL)
950 return -EINVAL;
951
952 dev_vdbg(chan2dev(chan), "terminate_all\n");
953 spin_lock_bh(&dc->lock);
954
955 txx9dmac_reset_chan(dc);
956
957 /* active_list entries will end up before queued entries */
958 list_splice_init(&dc->queue, &list);
959 list_splice_init(&dc->active_list, &list);
960
961 spin_unlock_bh(&dc->lock);
962
963 /* Flush all pending and queued descriptors */
964 list_for_each_entry_safe(desc, _desc, &list, desc_node)
965 txx9dmac_descriptor_complete(dc, desc);
966
967 return 0;
968}
969
970static enum dma_status
971txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
972 struct dma_tx_state *txstate)
973{
974 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
975 dma_cookie_t last_used;
976 dma_cookie_t last_complete;
977 int ret;
978
979 last_complete = dc->completed;
980 last_used = chan->cookie;
981
982 ret = dma_async_is_complete(cookie, last_complete, last_used);
983 if (ret != DMA_SUCCESS) {
984 spin_lock_bh(&dc->lock);
985 txx9dmac_scan_descriptors(dc);
986 spin_unlock_bh(&dc->lock);
987
988 last_complete = dc->completed;
989 last_used = chan->cookie;
990
991 ret = dma_async_is_complete(cookie, last_complete, last_used);
992 }
993
994 dma_set_tx_state(txstate, last_complete, last_used, 0);
995
996 return ret;
997}
998
999static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
1000 struct txx9dmac_desc *prev)
1001{
1002 struct txx9dmac_dev *ddev = dc->ddev;
1003 struct txx9dmac_desc *desc;
1004 LIST_HEAD(list);
1005
1006 prev = txx9dmac_last_child(prev);
1007 txx9dmac_dequeue(dc, &list);
1008 desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
1009 desc_write_CHAR(dc, prev, desc->txd.phys);
1010 dma_sync_single_for_device(chan2parent(&dc->chan),
1011 prev->txd.phys, ddev->descsize,
1012 DMA_TO_DEVICE);
1013 mmiowb();
1014 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
1015 channel_read_CHAR(dc) == prev->txd.phys)
1016 /* Restart chain DMA */
1017 channel_write_CHAR(dc, desc->txd.phys);
1018 list_splice_tail(&list, &dc->active_list);
1019}
1020
1021static void txx9dmac_issue_pending(struct dma_chan *chan)
1022{
1023 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1024
1025 spin_lock_bh(&dc->lock);
1026
1027 if (!list_empty(&dc->active_list))
1028 txx9dmac_scan_descriptors(dc);
1029 if (!list_empty(&dc->queue)) {
1030 if (list_empty(&dc->active_list)) {
1031 txx9dmac_dequeue(dc, &dc->active_list);
1032 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
1033 } else if (txx9_dma_have_SMPCHN()) {
1034 struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
1035
1036 if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
1037 txx9dmac_chan_INTENT(dc))
1038 txx9dmac_chain_dynamic(dc, prev);
1039 }
1040 }
1041
1042 spin_unlock_bh(&dc->lock);
1043}
1044
1045static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
1046{
1047 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1048 struct txx9dmac_slave *ds = chan->private;
1049 struct txx9dmac_desc *desc;
1050 int i;
1051
1052 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1053
1054 /* ASSERT: channel is idle */
1055 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
1056 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1057 return -EIO;
1058 }
1059
1060 dc->completed = chan->cookie = 1;
1061
1062 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1063 txx9dmac_chan_set_SMPCHN(dc);
1064 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1065 dc->ccr |= TXX9_DMA_CCR_INTENC;
1066 if (chan->device->device_prep_dma_memcpy) {
1067 if (ds)
1068 return -EINVAL;
1069 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1070 } else {
1071 if (!ds ||
1072 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1073 return -EINVAL;
1074 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1075 TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1076 txx9dmac_chan_set_INTENT(dc);
1077 }
1078
1079 spin_lock_bh(&dc->lock);
1080 i = dc->descs_allocated;
1081 while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1082 spin_unlock_bh(&dc->lock);
1083
1084 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1085 if (!desc) {
1086 dev_info(chan2dev(chan),
1087 "only allocated %d descriptors\n", i);
1088 spin_lock_bh(&dc->lock);
1089 break;
1090 }
1091 txx9dmac_desc_put(dc, desc);
1092
1093 spin_lock_bh(&dc->lock);
1094 i = ++dc->descs_allocated;
1095 }
1096 spin_unlock_bh(&dc->lock);
1097
1098 dev_dbg(chan2dev(chan),
1099 "alloc_chan_resources allocated %d descriptors\n", i);
1100
1101 return i;
1102}
1103
1104static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1105{
1106 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1107 struct txx9dmac_dev *ddev = dc->ddev;
1108 struct txx9dmac_desc *desc, *_desc;
1109 LIST_HEAD(list);
1110
1111 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1112 dc->descs_allocated);
1113
1114 /* ASSERT: channel is idle */
1115 BUG_ON(!list_empty(&dc->active_list));
1116 BUG_ON(!list_empty(&dc->queue));
1117 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1118
1119 spin_lock_bh(&dc->lock);
1120 list_splice_init(&dc->free_list, &list);
1121 dc->descs_allocated = 0;
1122 spin_unlock_bh(&dc->lock);
1123
1124 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1125 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1126 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1127 ddev->descsize, DMA_TO_DEVICE);
1128 kfree(desc);
1129 }
1130
1131 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1132}
1133
1134/*----------------------------------------------------------------------*/
1135
1136static void txx9dmac_off(struct txx9dmac_dev *ddev)
1137{
1138 dma_writel(ddev, MCR, 0);
1139 mmiowb();
1140}
1141
1142static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1143{
1144 struct txx9dmac_chan_platform_data *cpdata = pdev->dev.platform_data;
1145 struct platform_device *dmac_dev = cpdata->dmac_dev;
1146 struct txx9dmac_platform_data *pdata = dmac_dev->dev.platform_data;
1147 struct txx9dmac_chan *dc;
1148 int err;
1149 int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1150 int irq;
1151
1152 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1153 if (!dc)
1154 return -ENOMEM;
1155
1156 dc->dma.dev = &pdev->dev;
1157 dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1158 dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1159 dc->dma.device_control = txx9dmac_control;
1160 dc->dma.device_tx_status = txx9dmac_tx_status;
1161 dc->dma.device_issue_pending = txx9dmac_issue_pending;
1162 if (pdata && pdata->memcpy_chan == ch) {
1163 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1164 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1165 } else {
1166 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1167 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1168 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1169 }
1170
1171 INIT_LIST_HEAD(&dc->dma.channels);
1172 dc->ddev = platform_get_drvdata(dmac_dev);
1173 if (dc->ddev->irq < 0) {
1174 irq = platform_get_irq(pdev, 0);
1175 if (irq < 0)
1176 return irq;
1177 tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
1178 (unsigned long)dc);
1179 dc->irq = irq;
1180 err = devm_request_irq(&pdev->dev, dc->irq,
1181 txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1182 if (err)
1183 return err;
1184 } else
1185 dc->irq = -1;
1186 dc->ddev->chan[ch] = dc;
1187 dc->chan.device = &dc->dma;
1188 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1189 dc->chan.cookie = dc->completed = 1;
1190
1191 if (is_dmac64(dc))
1192 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1193 else
1194 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1195 spin_lock_init(&dc->lock);
1196
1197 INIT_LIST_HEAD(&dc->active_list);
1198 INIT_LIST_HEAD(&dc->queue);
1199 INIT_LIST_HEAD(&dc->free_list);
1200
1201 txx9dmac_reset_chan(dc);
1202
1203 platform_set_drvdata(pdev, dc);
1204
1205 err = dma_async_device_register(&dc->dma);
1206 if (err)
1207 return err;
1208 dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1209 dc->dma.dev_id,
1210 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1211 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1212
1213 return 0;
1214}
1215
1216static int __exit txx9dmac_chan_remove(struct platform_device *pdev)
1217{
1218 struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1219
1220 dma_async_device_unregister(&dc->dma);
1221 if (dc->irq >= 0)
1222 tasklet_kill(&dc->tasklet);
1223 dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1224 return 0;
1225}
1226
1227static int __init txx9dmac_probe(struct platform_device *pdev)
1228{
1229 struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
1230 struct resource *io;
1231 struct txx9dmac_dev *ddev;
1232 u32 mcr;
1233 int err;
1234
1235 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1236 if (!io)
1237 return -EINVAL;
1238
1239 ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1240 if (!ddev)
1241 return -ENOMEM;
1242
1243 if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1244 dev_name(&pdev->dev)))
1245 return -EBUSY;
1246
1247 ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1248 if (!ddev->regs)
1249 return -ENOMEM;
1250 ddev->have_64bit_regs = pdata->have_64bit_regs;
1251 if (__is_dmac64(ddev))
1252 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1253 else
1254 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1255
1256 /* force dma off, just in case */
1257 txx9dmac_off(ddev);
1258
1259 ddev->irq = platform_get_irq(pdev, 0);
1260 if (ddev->irq >= 0) {
1261 tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
1262 (unsigned long)ddev);
1263 err = devm_request_irq(&pdev->dev, ddev->irq,
1264 txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1265 if (err)
1266 return err;
1267 }
1268
1269 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1270 if (pdata && pdata->memcpy_chan >= 0)
1271 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1272 dma_writel(ddev, MCR, mcr);
1273
1274 platform_set_drvdata(pdev, ddev);
1275 return 0;
1276}
1277
1278static int __exit txx9dmac_remove(struct platform_device *pdev)
1279{
1280 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1281
1282 txx9dmac_off(ddev);
1283 if (ddev->irq >= 0)
1284 tasklet_kill(&ddev->tasklet);
1285 return 0;
1286}
1287
1288static void txx9dmac_shutdown(struct platform_device *pdev)
1289{
1290 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1291
1292 txx9dmac_off(ddev);
1293}
1294
1295static int txx9dmac_suspend_noirq(struct device *dev)
1296{
1297 struct platform_device *pdev = to_platform_device(dev);
1298 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1299
1300 txx9dmac_off(ddev);
1301 return 0;
1302}
1303
1304static int txx9dmac_resume_noirq(struct device *dev)
1305{
1306 struct platform_device *pdev = to_platform_device(dev);
1307 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1308 struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
1309 u32 mcr;
1310
1311 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1312 if (pdata && pdata->memcpy_chan >= 0)
1313 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1314 dma_writel(ddev, MCR, mcr);
1315 return 0;
1316
1317}
1318
1319static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1320 .suspend_noirq = txx9dmac_suspend_noirq,
1321 .resume_noirq = txx9dmac_resume_noirq,
1322};
1323
1324static struct platform_driver txx9dmac_chan_driver = {
1325 .remove = __exit_p(txx9dmac_chan_remove),
1326 .driver = {
1327 .name = "txx9dmac-chan",
1328 },
1329};
1330
1331static struct platform_driver txx9dmac_driver = {
1332 .remove = __exit_p(txx9dmac_remove),
1333 .shutdown = txx9dmac_shutdown,
1334 .driver = {
1335 .name = "txx9dmac",
1336 .pm = &txx9dmac_dev_pm_ops,
1337 },
1338};
1339
1340static int __init txx9dmac_init(void)
1341{
1342 int rc;
1343
1344 rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1345 if (!rc) {
1346 rc = platform_driver_probe(&txx9dmac_chan_driver,
1347 txx9dmac_chan_probe);
1348 if (rc)
1349 platform_driver_unregister(&txx9dmac_driver);
1350 }
1351 return rc;
1352}
1353module_init(txx9dmac_init);
1354
1355static void __exit txx9dmac_exit(void)
1356{
1357 platform_driver_unregister(&txx9dmac_chan_driver);
1358 platform_driver_unregister(&txx9dmac_driver);
1359}
1360module_exit(txx9dmac_exit);
1361
1362MODULE_LICENSE("GPL");
1363MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1364MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1365MODULE_ALIAS("platform:txx9dmac");
1366MODULE_ALIAS("platform:txx9dmac-chan");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for the TXx9 SoC DMA Controller
4 *
5 * Copyright (C) 2009 Atsushi Nemoto
6 */
7#include <linux/dma-mapping.h>
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14#include <linux/scatterlist.h>
15
16#include "dmaengine.h"
17#include "txx9dmac.h"
18
19static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
20{
21 return container_of(chan, struct txx9dmac_chan, chan);
22}
23
24static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
25{
26 return dc->ch_regs;
27}
28
29static struct txx9dmac_cregs32 __iomem *__dma_regs32(
30 const struct txx9dmac_chan *dc)
31{
32 return dc->ch_regs;
33}
34
35#define channel64_readq(dc, name) \
36 __raw_readq(&(__dma_regs(dc)->name))
37#define channel64_writeq(dc, name, val) \
38 __raw_writeq((val), &(__dma_regs(dc)->name))
39#define channel64_readl(dc, name) \
40 __raw_readl(&(__dma_regs(dc)->name))
41#define channel64_writel(dc, name, val) \
42 __raw_writel((val), &(__dma_regs(dc)->name))
43
44#define channel32_readl(dc, name) \
45 __raw_readl(&(__dma_regs32(dc)->name))
46#define channel32_writel(dc, name, val) \
47 __raw_writel((val), &(__dma_regs32(dc)->name))
48
49#define channel_readq(dc, name) channel64_readq(dc, name)
50#define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
51#define channel_readl(dc, name) \
52 (is_dmac64(dc) ? \
53 channel64_readl(dc, name) : channel32_readl(dc, name))
54#define channel_writel(dc, name, val) \
55 (is_dmac64(dc) ? \
56 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
57
58static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
59{
60 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
61 return channel64_readq(dc, CHAR);
62 else
63 return channel64_readl(dc, CHAR);
64}
65
66static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
67{
68 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
69 channel64_writeq(dc, CHAR, val);
70 else
71 channel64_writel(dc, CHAR, val);
72}
73
74static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
75{
76#if defined(CONFIG_32BIT) && !defined(CONFIG_PHYS_ADDR_T_64BIT)
77 channel64_writel(dc, CHAR, 0);
78 channel64_writel(dc, __pad_CHAR, 0);
79#else
80 channel64_writeq(dc, CHAR, 0);
81#endif
82}
83
84static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
85{
86 if (is_dmac64(dc))
87 return channel64_read_CHAR(dc);
88 else
89 return channel32_readl(dc, CHAR);
90}
91
92static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
93{
94 if (is_dmac64(dc))
95 channel64_write_CHAR(dc, val);
96 else
97 channel32_writel(dc, CHAR, val);
98}
99
100static struct txx9dmac_regs __iomem *__txx9dmac_regs(
101 const struct txx9dmac_dev *ddev)
102{
103 return ddev->regs;
104}
105
106static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
107 const struct txx9dmac_dev *ddev)
108{
109 return ddev->regs;
110}
111
112#define dma64_readl(ddev, name) \
113 __raw_readl(&(__txx9dmac_regs(ddev)->name))
114#define dma64_writel(ddev, name, val) \
115 __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
116
117#define dma32_readl(ddev, name) \
118 __raw_readl(&(__txx9dmac_regs32(ddev)->name))
119#define dma32_writel(ddev, name, val) \
120 __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
121
122#define dma_readl(ddev, name) \
123 (__is_dmac64(ddev) ? \
124 dma64_readl(ddev, name) : dma32_readl(ddev, name))
125#define dma_writel(ddev, name, val) \
126 (__is_dmac64(ddev) ? \
127 dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
128
129static struct device *chan2dev(struct dma_chan *chan)
130{
131 return &chan->dev->device;
132}
133static struct device *chan2parent(struct dma_chan *chan)
134{
135 return chan->dev->device.parent;
136}
137
138static struct txx9dmac_desc *
139txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
140{
141 return container_of(txd, struct txx9dmac_desc, txd);
142}
143
144static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
145 const struct txx9dmac_desc *desc)
146{
147 return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
148}
149
150static void desc_write_CHAR(const struct txx9dmac_chan *dc,
151 struct txx9dmac_desc *desc, dma_addr_t val)
152{
153 if (is_dmac64(dc))
154 desc->hwdesc.CHAR = val;
155 else
156 desc->hwdesc32.CHAR = val;
157}
158
159#define TXX9_DMA_MAX_COUNT 0x04000000
160
161#define TXX9_DMA_INITIAL_DESC_COUNT 64
162
163static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
164{
165 return list_entry(dc->active_list.next,
166 struct txx9dmac_desc, desc_node);
167}
168
169static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
170{
171 return list_entry(dc->active_list.prev,
172 struct txx9dmac_desc, desc_node);
173}
174
175static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
176{
177 return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
178}
179
180static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
181{
182 if (!list_empty(&desc->tx_list))
183 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
184 return desc;
185}
186
187static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
188
189static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
190 gfp_t flags)
191{
192 struct txx9dmac_dev *ddev = dc->ddev;
193 struct txx9dmac_desc *desc;
194
195 desc = kzalloc(sizeof(*desc), flags);
196 if (!desc)
197 return NULL;
198 INIT_LIST_HEAD(&desc->tx_list);
199 dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
200 desc->txd.tx_submit = txx9dmac_tx_submit;
201 /* txd.flags will be overwritten in prep funcs */
202 desc->txd.flags = DMA_CTRL_ACK;
203 desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
204 ddev->descsize, DMA_TO_DEVICE);
205 return desc;
206}
207
208static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
209{
210 struct txx9dmac_desc *desc, *_desc;
211 struct txx9dmac_desc *ret = NULL;
212 unsigned int i = 0;
213
214 spin_lock_bh(&dc->lock);
215 list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
216 if (async_tx_test_ack(&desc->txd)) {
217 list_del(&desc->desc_node);
218 ret = desc;
219 break;
220 }
221 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
222 i++;
223 }
224 spin_unlock_bh(&dc->lock);
225
226 dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
227 i);
228 if (!ret) {
229 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
230 if (ret) {
231 spin_lock_bh(&dc->lock);
232 dc->descs_allocated++;
233 spin_unlock_bh(&dc->lock);
234 } else
235 dev_err(chan2dev(&dc->chan),
236 "not enough descriptors available\n");
237 }
238 return ret;
239}
240
241static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
242 struct txx9dmac_desc *desc)
243{
244 struct txx9dmac_dev *ddev = dc->ddev;
245 struct txx9dmac_desc *child;
246
247 list_for_each_entry(child, &desc->tx_list, desc_node)
248 dma_sync_single_for_cpu(chan2parent(&dc->chan),
249 child->txd.phys, ddev->descsize,
250 DMA_TO_DEVICE);
251 dma_sync_single_for_cpu(chan2parent(&dc->chan),
252 desc->txd.phys, ddev->descsize,
253 DMA_TO_DEVICE);
254}
255
256/*
257 * Move a descriptor, including any children, to the free list.
258 * `desc' must not be on any lists.
259 */
260static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
261 struct txx9dmac_desc *desc)
262{
263 if (desc) {
264 struct txx9dmac_desc *child;
265
266 txx9dmac_sync_desc_for_cpu(dc, desc);
267
268 spin_lock_bh(&dc->lock);
269 list_for_each_entry(child, &desc->tx_list, desc_node)
270 dev_vdbg(chan2dev(&dc->chan),
271 "moving child desc %p to freelist\n",
272 child);
273 list_splice_init(&desc->tx_list, &dc->free_list);
274 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
275 desc);
276 list_add(&desc->desc_node, &dc->free_list);
277 spin_unlock_bh(&dc->lock);
278 }
279}
280
281/*----------------------------------------------------------------------*/
282
283static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
284{
285 if (is_dmac64(dc))
286 dev_err(chan2dev(&dc->chan),
287 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
288 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
289 (u64)channel64_read_CHAR(dc),
290 channel64_readq(dc, SAR),
291 channel64_readq(dc, DAR),
292 channel64_readl(dc, CNTR),
293 channel64_readl(dc, SAIR),
294 channel64_readl(dc, DAIR),
295 channel64_readl(dc, CCR),
296 channel64_readl(dc, CSR));
297 else
298 dev_err(chan2dev(&dc->chan),
299 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
300 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
301 channel32_readl(dc, CHAR),
302 channel32_readl(dc, SAR),
303 channel32_readl(dc, DAR),
304 channel32_readl(dc, CNTR),
305 channel32_readl(dc, SAIR),
306 channel32_readl(dc, DAIR),
307 channel32_readl(dc, CCR),
308 channel32_readl(dc, CSR));
309}
310
311static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
312{
313 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
314 if (is_dmac64(dc)) {
315 channel64_clear_CHAR(dc);
316 channel_writeq(dc, SAR, 0);
317 channel_writeq(dc, DAR, 0);
318 } else {
319 channel_writel(dc, CHAR, 0);
320 channel_writel(dc, SAR, 0);
321 channel_writel(dc, DAR, 0);
322 }
323 channel_writel(dc, CNTR, 0);
324 channel_writel(dc, SAIR, 0);
325 channel_writel(dc, DAIR, 0);
326 channel_writel(dc, CCR, 0);
327}
328
329/* Called with dc->lock held and bh disabled */
330static void txx9dmac_dostart(struct txx9dmac_chan *dc,
331 struct txx9dmac_desc *first)
332{
333 struct txx9dmac_slave *ds = dc->chan.private;
334 u32 sai, dai;
335
336 dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
337 first->txd.cookie, first);
338 /* ASSERT: channel is idle */
339 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
340 dev_err(chan2dev(&dc->chan),
341 "BUG: Attempted to start non-idle channel\n");
342 txx9dmac_dump_regs(dc);
343 /* The tasklet will hopefully advance the queue... */
344 return;
345 }
346
347 if (is_dmac64(dc)) {
348 channel64_writel(dc, CNTR, 0);
349 channel64_writel(dc, CSR, 0xffffffff);
350 if (ds) {
351 if (ds->tx_reg) {
352 sai = ds->reg_width;
353 dai = 0;
354 } else {
355 sai = 0;
356 dai = ds->reg_width;
357 }
358 } else {
359 sai = 8;
360 dai = 8;
361 }
362 channel64_writel(dc, SAIR, sai);
363 channel64_writel(dc, DAIR, dai);
364 /* All 64-bit DMAC supports SMPCHN */
365 channel64_writel(dc, CCR, dc->ccr);
366 /* Writing a non zero value to CHAR will assert XFACT */
367 channel64_write_CHAR(dc, first->txd.phys);
368 } else {
369 channel32_writel(dc, CNTR, 0);
370 channel32_writel(dc, CSR, 0xffffffff);
371 if (ds) {
372 if (ds->tx_reg) {
373 sai = ds->reg_width;
374 dai = 0;
375 } else {
376 sai = 0;
377 dai = ds->reg_width;
378 }
379 } else {
380 sai = 4;
381 dai = 4;
382 }
383 channel32_writel(dc, SAIR, sai);
384 channel32_writel(dc, DAIR, dai);
385 if (txx9_dma_have_SMPCHN()) {
386 channel32_writel(dc, CCR, dc->ccr);
387 /* Writing a non zero value to CHAR will assert XFACT */
388 channel32_writel(dc, CHAR, first->txd.phys);
389 } else {
390 channel32_writel(dc, CHAR, first->txd.phys);
391 channel32_writel(dc, CCR, dc->ccr);
392 }
393 }
394}
395
396/*----------------------------------------------------------------------*/
397
398static void
399txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
400 struct txx9dmac_desc *desc)
401{
402 struct dmaengine_desc_callback cb;
403 struct dma_async_tx_descriptor *txd = &desc->txd;
404
405 dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
406 txd->cookie, desc);
407
408 dma_cookie_complete(txd);
409 dmaengine_desc_get_callback(txd, &cb);
410
411 txx9dmac_sync_desc_for_cpu(dc, desc);
412 list_splice_init(&desc->tx_list, &dc->free_list);
413 list_move(&desc->desc_node, &dc->free_list);
414
415 dma_descriptor_unmap(txd);
416 /*
417 * The API requires that no submissions are done from a
418 * callback, so we don't need to drop the lock here
419 */
420 dmaengine_desc_callback_invoke(&cb, NULL);
421 dma_run_dependencies(txd);
422}
423
424static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
425{
426 struct txx9dmac_dev *ddev = dc->ddev;
427 struct txx9dmac_desc *desc;
428 struct txx9dmac_desc *prev = NULL;
429
430 BUG_ON(!list_empty(list));
431 do {
432 desc = txx9dmac_first_queued(dc);
433 if (prev) {
434 desc_write_CHAR(dc, prev, desc->txd.phys);
435 dma_sync_single_for_device(chan2parent(&dc->chan),
436 prev->txd.phys, ddev->descsize,
437 DMA_TO_DEVICE);
438 }
439 prev = txx9dmac_last_child(desc);
440 list_move_tail(&desc->desc_node, list);
441 /* Make chain-completion interrupt happen */
442 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
443 !txx9dmac_chan_INTENT(dc))
444 break;
445 } while (!list_empty(&dc->queue));
446}
447
448static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
449{
450 struct txx9dmac_desc *desc, *_desc;
451 LIST_HEAD(list);
452
453 /*
454 * Submit queued descriptors ASAP, i.e. before we go through
455 * the completed ones.
456 */
457 list_splice_init(&dc->active_list, &list);
458 if (!list_empty(&dc->queue)) {
459 txx9dmac_dequeue(dc, &dc->active_list);
460 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
461 }
462
463 list_for_each_entry_safe(desc, _desc, &list, desc_node)
464 txx9dmac_descriptor_complete(dc, desc);
465}
466
467static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
468 struct txx9dmac_hwdesc *desc)
469{
470 if (is_dmac64(dc)) {
471#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
472 dev_crit(chan2dev(&dc->chan),
473 " desc: ch%#llx s%#llx d%#llx c%#x\n",
474 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
475#else
476 dev_crit(chan2dev(&dc->chan),
477 " desc: ch%#llx s%#llx d%#llx c%#x"
478 " si%#x di%#x cc%#x cs%#x\n",
479 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
480 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
481#endif
482 } else {
483 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
484#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
485 dev_crit(chan2dev(&dc->chan),
486 " desc: ch%#x s%#x d%#x c%#x\n",
487 d->CHAR, d->SAR, d->DAR, d->CNTR);
488#else
489 dev_crit(chan2dev(&dc->chan),
490 " desc: ch%#x s%#x d%#x c%#x"
491 " si%#x di%#x cc%#x cs%#x\n",
492 d->CHAR, d->SAR, d->DAR, d->CNTR,
493 d->SAIR, d->DAIR, d->CCR, d->CSR);
494#endif
495 }
496}
497
498static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
499{
500 struct txx9dmac_desc *bad_desc;
501 struct txx9dmac_desc *child;
502 u32 errors;
503
504 /*
505 * The descriptor currently at the head of the active list is
506 * borked. Since we don't have any way to report errors, we'll
507 * just have to scream loudly and try to carry on.
508 */
509 dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
510 txx9dmac_dump_regs(dc);
511
512 bad_desc = txx9dmac_first_active(dc);
513 list_del_init(&bad_desc->desc_node);
514
515 /* Clear all error flags and try to restart the controller */
516 errors = csr & (TXX9_DMA_CSR_ABCHC |
517 TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
518 TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
519 channel_writel(dc, CSR, errors);
520
521 if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
522 txx9dmac_dequeue(dc, &dc->active_list);
523 if (!list_empty(&dc->active_list))
524 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
525
526 dev_crit(chan2dev(&dc->chan),
527 "Bad descriptor submitted for DMA! (cookie: %d)\n",
528 bad_desc->txd.cookie);
529 txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
530 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
531 txx9dmac_dump_desc(dc, &child->hwdesc);
532 /* Pretend the descriptor completed successfully */
533 txx9dmac_descriptor_complete(dc, bad_desc);
534}
535
536static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
537{
538 dma_addr_t chain;
539 struct txx9dmac_desc *desc, *_desc;
540 struct txx9dmac_desc *child;
541 u32 csr;
542
543 if (is_dmac64(dc)) {
544 chain = channel64_read_CHAR(dc);
545 csr = channel64_readl(dc, CSR);
546 channel64_writel(dc, CSR, csr);
547 } else {
548 chain = channel32_readl(dc, CHAR);
549 csr = channel32_readl(dc, CSR);
550 channel32_writel(dc, CSR, csr);
551 }
552 /* For dynamic chain, we should look at XFACT instead of NCHNC */
553 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
554 /* Everything we've submitted is done */
555 txx9dmac_complete_all(dc);
556 return;
557 }
558 if (!(csr & TXX9_DMA_CSR_CHNEN))
559 chain = 0; /* last descriptor of this chain */
560
561 dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
562 (u64)chain);
563
564 list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
565 if (desc_read_CHAR(dc, desc) == chain) {
566 /* This one is currently in progress */
567 if (csr & TXX9_DMA_CSR_ABCHC)
568 goto scan_done;
569 return;
570 }
571
572 list_for_each_entry(child, &desc->tx_list, desc_node)
573 if (desc_read_CHAR(dc, child) == chain) {
574 /* Currently in progress */
575 if (csr & TXX9_DMA_CSR_ABCHC)
576 goto scan_done;
577 return;
578 }
579
580 /*
581 * No descriptors so far seem to be in progress, i.e.
582 * this one must be done.
583 */
584 txx9dmac_descriptor_complete(dc, desc);
585 }
586scan_done:
587 if (csr & TXX9_DMA_CSR_ABCHC) {
588 txx9dmac_handle_error(dc, csr);
589 return;
590 }
591
592 dev_err(chan2dev(&dc->chan),
593 "BUG: All descriptors done, but channel not idle!\n");
594
595 /* Try to continue after resetting the channel... */
596 txx9dmac_reset_chan(dc);
597
598 if (!list_empty(&dc->queue)) {
599 txx9dmac_dequeue(dc, &dc->active_list);
600 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
601 }
602}
603
604static void txx9dmac_chan_tasklet(struct tasklet_struct *t)
605{
606 int irq;
607 u32 csr;
608 struct txx9dmac_chan *dc;
609
610 dc = from_tasklet(dc, t, tasklet);
611 csr = channel_readl(dc, CSR);
612 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
613
614 spin_lock(&dc->lock);
615 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
616 TXX9_DMA_CSR_NTRNFC))
617 txx9dmac_scan_descriptors(dc);
618 spin_unlock(&dc->lock);
619 irq = dc->irq;
620
621 enable_irq(irq);
622}
623
624static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
625{
626 struct txx9dmac_chan *dc = dev_id;
627
628 dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
629 channel_readl(dc, CSR));
630
631 tasklet_schedule(&dc->tasklet);
632 /*
633 * Just disable the interrupts. We'll turn them back on in the
634 * softirq handler.
635 */
636 disable_irq_nosync(irq);
637
638 return IRQ_HANDLED;
639}
640
641static void txx9dmac_tasklet(struct tasklet_struct *t)
642{
643 int irq;
644 u32 csr;
645 struct txx9dmac_chan *dc;
646
647 struct txx9dmac_dev *ddev = from_tasklet(ddev, t, tasklet);
648 u32 mcr;
649 int i;
650
651 mcr = dma_readl(ddev, MCR);
652 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
653 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
654 if ((mcr >> (24 + i)) & 0x11) {
655 dc = ddev->chan[i];
656 csr = channel_readl(dc, CSR);
657 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
658 csr);
659 spin_lock(&dc->lock);
660 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
661 TXX9_DMA_CSR_NTRNFC))
662 txx9dmac_scan_descriptors(dc);
663 spin_unlock(&dc->lock);
664 }
665 }
666 irq = ddev->irq;
667
668 enable_irq(irq);
669}
670
671static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
672{
673 struct txx9dmac_dev *ddev = dev_id;
674
675 dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
676 dma_readl(ddev, MCR));
677
678 tasklet_schedule(&ddev->tasklet);
679 /*
680 * Just disable the interrupts. We'll turn them back on in the
681 * softirq handler.
682 */
683 disable_irq_nosync(irq);
684
685 return IRQ_HANDLED;
686}
687
688/*----------------------------------------------------------------------*/
689
690static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
691{
692 struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
693 struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
694 dma_cookie_t cookie;
695
696 spin_lock_bh(&dc->lock);
697 cookie = dma_cookie_assign(tx);
698
699 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
700 desc->txd.cookie, desc);
701
702 list_add_tail(&desc->desc_node, &dc->queue);
703 spin_unlock_bh(&dc->lock);
704
705 return cookie;
706}
707
708static struct dma_async_tx_descriptor *
709txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
710 size_t len, unsigned long flags)
711{
712 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
713 struct txx9dmac_dev *ddev = dc->ddev;
714 struct txx9dmac_desc *desc;
715 struct txx9dmac_desc *first;
716 struct txx9dmac_desc *prev;
717 size_t xfer_count;
718 size_t offset;
719
720 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
721 (u64)dest, (u64)src, len, flags);
722
723 if (unlikely(!len)) {
724 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
725 return NULL;
726 }
727
728 prev = first = NULL;
729
730 for (offset = 0; offset < len; offset += xfer_count) {
731 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
732 /*
733 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
734 * ERT-TX49H4-016 (slightly conservative)
735 */
736 if (__is_dmac64(ddev)) {
737 if (xfer_count > 0x100 &&
738 (xfer_count & 0xff) >= 0xfa &&
739 (xfer_count & 0xff) <= 0xff)
740 xfer_count -= 0x20;
741 } else {
742 if (xfer_count > 0x80 &&
743 (xfer_count & 0x7f) >= 0x7e &&
744 (xfer_count & 0x7f) <= 0x7f)
745 xfer_count -= 0x20;
746 }
747
748 desc = txx9dmac_desc_get(dc);
749 if (!desc) {
750 txx9dmac_desc_put(dc, first);
751 return NULL;
752 }
753
754 if (__is_dmac64(ddev)) {
755 desc->hwdesc.SAR = src + offset;
756 desc->hwdesc.DAR = dest + offset;
757 desc->hwdesc.CNTR = xfer_count;
758 txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
759 dc->ccr | TXX9_DMA_CCR_XFACT);
760 } else {
761 desc->hwdesc32.SAR = src + offset;
762 desc->hwdesc32.DAR = dest + offset;
763 desc->hwdesc32.CNTR = xfer_count;
764 txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
765 dc->ccr | TXX9_DMA_CCR_XFACT);
766 }
767
768 /*
769 * The descriptors on tx_list are not reachable from
770 * the dc->queue list or dc->active_list after a
771 * submit. If we put all descriptors on active_list,
772 * calling of callback on the completion will be more
773 * complex.
774 */
775 if (!first) {
776 first = desc;
777 } else {
778 desc_write_CHAR(dc, prev, desc->txd.phys);
779 dma_sync_single_for_device(chan2parent(&dc->chan),
780 prev->txd.phys, ddev->descsize,
781 DMA_TO_DEVICE);
782 list_add_tail(&desc->desc_node, &first->tx_list);
783 }
784 prev = desc;
785 }
786
787 /* Trigger interrupt after last block */
788 if (flags & DMA_PREP_INTERRUPT)
789 txx9dmac_desc_set_INTENT(ddev, prev);
790
791 desc_write_CHAR(dc, prev, 0);
792 dma_sync_single_for_device(chan2parent(&dc->chan),
793 prev->txd.phys, ddev->descsize,
794 DMA_TO_DEVICE);
795
796 first->txd.flags = flags;
797 first->len = len;
798
799 return &first->txd;
800}
801
802static struct dma_async_tx_descriptor *
803txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
804 unsigned int sg_len, enum dma_transfer_direction direction,
805 unsigned long flags, void *context)
806{
807 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
808 struct txx9dmac_dev *ddev = dc->ddev;
809 struct txx9dmac_slave *ds = chan->private;
810 struct txx9dmac_desc *prev;
811 struct txx9dmac_desc *first;
812 unsigned int i;
813 struct scatterlist *sg;
814
815 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
816
817 BUG_ON(!ds || !ds->reg_width);
818 if (ds->tx_reg)
819 BUG_ON(direction != DMA_MEM_TO_DEV);
820 else
821 BUG_ON(direction != DMA_DEV_TO_MEM);
822 if (unlikely(!sg_len))
823 return NULL;
824
825 prev = first = NULL;
826
827 for_each_sg(sgl, sg, sg_len, i) {
828 struct txx9dmac_desc *desc;
829 dma_addr_t mem;
830 u32 sai, dai;
831
832 desc = txx9dmac_desc_get(dc);
833 if (!desc) {
834 txx9dmac_desc_put(dc, first);
835 return NULL;
836 }
837
838 mem = sg_dma_address(sg);
839
840 if (__is_dmac64(ddev)) {
841 if (direction == DMA_MEM_TO_DEV) {
842 desc->hwdesc.SAR = mem;
843 desc->hwdesc.DAR = ds->tx_reg;
844 } else {
845 desc->hwdesc.SAR = ds->rx_reg;
846 desc->hwdesc.DAR = mem;
847 }
848 desc->hwdesc.CNTR = sg_dma_len(sg);
849 } else {
850 if (direction == DMA_MEM_TO_DEV) {
851 desc->hwdesc32.SAR = mem;
852 desc->hwdesc32.DAR = ds->tx_reg;
853 } else {
854 desc->hwdesc32.SAR = ds->rx_reg;
855 desc->hwdesc32.DAR = mem;
856 }
857 desc->hwdesc32.CNTR = sg_dma_len(sg);
858 }
859 if (direction == DMA_MEM_TO_DEV) {
860 sai = ds->reg_width;
861 dai = 0;
862 } else {
863 sai = 0;
864 dai = ds->reg_width;
865 }
866 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
867 dc->ccr | TXX9_DMA_CCR_XFACT);
868
869 if (!first) {
870 first = desc;
871 } else {
872 desc_write_CHAR(dc, prev, desc->txd.phys);
873 dma_sync_single_for_device(chan2parent(&dc->chan),
874 prev->txd.phys,
875 ddev->descsize,
876 DMA_TO_DEVICE);
877 list_add_tail(&desc->desc_node, &first->tx_list);
878 }
879 prev = desc;
880 }
881
882 /* Trigger interrupt after last block */
883 if (flags & DMA_PREP_INTERRUPT)
884 txx9dmac_desc_set_INTENT(ddev, prev);
885
886 desc_write_CHAR(dc, prev, 0);
887 dma_sync_single_for_device(chan2parent(&dc->chan),
888 prev->txd.phys, ddev->descsize,
889 DMA_TO_DEVICE);
890
891 first->txd.flags = flags;
892 first->len = 0;
893
894 return &first->txd;
895}
896
897static int txx9dmac_terminate_all(struct dma_chan *chan)
898{
899 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
900 struct txx9dmac_desc *desc, *_desc;
901 LIST_HEAD(list);
902
903 dev_vdbg(chan2dev(chan), "terminate_all\n");
904 spin_lock_bh(&dc->lock);
905
906 txx9dmac_reset_chan(dc);
907
908 /* active_list entries will end up before queued entries */
909 list_splice_init(&dc->queue, &list);
910 list_splice_init(&dc->active_list, &list);
911
912 spin_unlock_bh(&dc->lock);
913
914 /* Flush all pending and queued descriptors */
915 list_for_each_entry_safe(desc, _desc, &list, desc_node)
916 txx9dmac_descriptor_complete(dc, desc);
917
918 return 0;
919}
920
921static enum dma_status
922txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
923 struct dma_tx_state *txstate)
924{
925 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
926 enum dma_status ret;
927
928 ret = dma_cookie_status(chan, cookie, txstate);
929 if (ret == DMA_COMPLETE)
930 return DMA_COMPLETE;
931
932 spin_lock_bh(&dc->lock);
933 txx9dmac_scan_descriptors(dc);
934 spin_unlock_bh(&dc->lock);
935
936 return dma_cookie_status(chan, cookie, txstate);
937}
938
939static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
940 struct txx9dmac_desc *prev)
941{
942 struct txx9dmac_dev *ddev = dc->ddev;
943 struct txx9dmac_desc *desc;
944 LIST_HEAD(list);
945
946 prev = txx9dmac_last_child(prev);
947 txx9dmac_dequeue(dc, &list);
948 desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
949 desc_write_CHAR(dc, prev, desc->txd.phys);
950 dma_sync_single_for_device(chan2parent(&dc->chan),
951 prev->txd.phys, ddev->descsize,
952 DMA_TO_DEVICE);
953 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
954 channel_read_CHAR(dc) == prev->txd.phys)
955 /* Restart chain DMA */
956 channel_write_CHAR(dc, desc->txd.phys);
957 list_splice_tail(&list, &dc->active_list);
958}
959
960static void txx9dmac_issue_pending(struct dma_chan *chan)
961{
962 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
963
964 spin_lock_bh(&dc->lock);
965
966 if (!list_empty(&dc->active_list))
967 txx9dmac_scan_descriptors(dc);
968 if (!list_empty(&dc->queue)) {
969 if (list_empty(&dc->active_list)) {
970 txx9dmac_dequeue(dc, &dc->active_list);
971 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
972 } else if (txx9_dma_have_SMPCHN()) {
973 struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
974
975 if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
976 txx9dmac_chan_INTENT(dc))
977 txx9dmac_chain_dynamic(dc, prev);
978 }
979 }
980
981 spin_unlock_bh(&dc->lock);
982}
983
984static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
985{
986 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
987 struct txx9dmac_slave *ds = chan->private;
988 struct txx9dmac_desc *desc;
989 int i;
990
991 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
992
993 /* ASSERT: channel is idle */
994 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
995 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
996 return -EIO;
997 }
998
999 dma_cookie_init(chan);
1000
1001 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1002 txx9dmac_chan_set_SMPCHN(dc);
1003 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1004 dc->ccr |= TXX9_DMA_CCR_INTENC;
1005 if (chan->device->device_prep_dma_memcpy) {
1006 if (ds)
1007 return -EINVAL;
1008 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1009 } else {
1010 if (!ds ||
1011 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1012 return -EINVAL;
1013 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1014 TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1015 txx9dmac_chan_set_INTENT(dc);
1016 }
1017
1018 spin_lock_bh(&dc->lock);
1019 i = dc->descs_allocated;
1020 while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1021 spin_unlock_bh(&dc->lock);
1022
1023 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1024 if (!desc) {
1025 dev_info(chan2dev(chan),
1026 "only allocated %d descriptors\n", i);
1027 spin_lock_bh(&dc->lock);
1028 break;
1029 }
1030 txx9dmac_desc_put(dc, desc);
1031
1032 spin_lock_bh(&dc->lock);
1033 i = ++dc->descs_allocated;
1034 }
1035 spin_unlock_bh(&dc->lock);
1036
1037 dev_dbg(chan2dev(chan),
1038 "alloc_chan_resources allocated %d descriptors\n", i);
1039
1040 return i;
1041}
1042
1043static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1044{
1045 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1046 struct txx9dmac_dev *ddev = dc->ddev;
1047 struct txx9dmac_desc *desc, *_desc;
1048 LIST_HEAD(list);
1049
1050 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1051 dc->descs_allocated);
1052
1053 /* ASSERT: channel is idle */
1054 BUG_ON(!list_empty(&dc->active_list));
1055 BUG_ON(!list_empty(&dc->queue));
1056 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1057
1058 spin_lock_bh(&dc->lock);
1059 list_splice_init(&dc->free_list, &list);
1060 dc->descs_allocated = 0;
1061 spin_unlock_bh(&dc->lock);
1062
1063 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1064 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1065 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1066 ddev->descsize, DMA_TO_DEVICE);
1067 kfree(desc);
1068 }
1069
1070 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1071}
1072
1073/*----------------------------------------------------------------------*/
1074
1075static void txx9dmac_off(struct txx9dmac_dev *ddev)
1076{
1077 dma_writel(ddev, MCR, 0);
1078}
1079
1080static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1081{
1082 struct txx9dmac_chan_platform_data *cpdata =
1083 dev_get_platdata(&pdev->dev);
1084 struct platform_device *dmac_dev = cpdata->dmac_dev;
1085 struct txx9dmac_platform_data *pdata = dev_get_platdata(&dmac_dev->dev);
1086 struct txx9dmac_chan *dc;
1087 int err;
1088 int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1089 int irq;
1090
1091 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1092 if (!dc)
1093 return -ENOMEM;
1094
1095 dc->dma.dev = &pdev->dev;
1096 dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1097 dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1098 dc->dma.device_terminate_all = txx9dmac_terminate_all;
1099 dc->dma.device_tx_status = txx9dmac_tx_status;
1100 dc->dma.device_issue_pending = txx9dmac_issue_pending;
1101 if (pdata && pdata->memcpy_chan == ch) {
1102 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1103 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1104 } else {
1105 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1106 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1107 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1108 }
1109
1110 INIT_LIST_HEAD(&dc->dma.channels);
1111 dc->ddev = platform_get_drvdata(dmac_dev);
1112 if (dc->ddev->irq < 0) {
1113 irq = platform_get_irq(pdev, 0);
1114 if (irq < 0)
1115 return irq;
1116 tasklet_setup(&dc->tasklet, txx9dmac_chan_tasklet);
1117 dc->irq = irq;
1118 err = devm_request_irq(&pdev->dev, dc->irq,
1119 txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1120 if (err)
1121 return err;
1122 } else
1123 dc->irq = -1;
1124 dc->ddev->chan[ch] = dc;
1125 dc->chan.device = &dc->dma;
1126 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1127 dma_cookie_init(&dc->chan);
1128
1129 if (is_dmac64(dc))
1130 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1131 else
1132 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1133 spin_lock_init(&dc->lock);
1134
1135 INIT_LIST_HEAD(&dc->active_list);
1136 INIT_LIST_HEAD(&dc->queue);
1137 INIT_LIST_HEAD(&dc->free_list);
1138
1139 txx9dmac_reset_chan(dc);
1140
1141 platform_set_drvdata(pdev, dc);
1142
1143 err = dma_async_device_register(&dc->dma);
1144 if (err)
1145 return err;
1146 dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1147 dc->dma.dev_id,
1148 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1149 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1150
1151 return 0;
1152}
1153
1154static int txx9dmac_chan_remove(struct platform_device *pdev)
1155{
1156 struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1157
1158
1159 dma_async_device_unregister(&dc->dma);
1160 if (dc->irq >= 0) {
1161 devm_free_irq(&pdev->dev, dc->irq, dc);
1162 tasklet_kill(&dc->tasklet);
1163 }
1164 dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1165 return 0;
1166}
1167
1168static int __init txx9dmac_probe(struct platform_device *pdev)
1169{
1170 struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1171 struct resource *io;
1172 struct txx9dmac_dev *ddev;
1173 u32 mcr;
1174 int err;
1175
1176 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1177 if (!io)
1178 return -EINVAL;
1179
1180 ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1181 if (!ddev)
1182 return -ENOMEM;
1183
1184 if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1185 dev_name(&pdev->dev)))
1186 return -EBUSY;
1187
1188 ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1189 if (!ddev->regs)
1190 return -ENOMEM;
1191 ddev->have_64bit_regs = pdata->have_64bit_regs;
1192 if (__is_dmac64(ddev))
1193 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1194 else
1195 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1196
1197 /* force dma off, just in case */
1198 txx9dmac_off(ddev);
1199
1200 ddev->irq = platform_get_irq(pdev, 0);
1201 if (ddev->irq >= 0) {
1202 tasklet_setup(&ddev->tasklet, txx9dmac_tasklet);
1203 err = devm_request_irq(&pdev->dev, ddev->irq,
1204 txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1205 if (err)
1206 return err;
1207 }
1208
1209 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1210 if (pdata && pdata->memcpy_chan >= 0)
1211 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1212 dma_writel(ddev, MCR, mcr);
1213
1214 platform_set_drvdata(pdev, ddev);
1215 return 0;
1216}
1217
1218static int txx9dmac_remove(struct platform_device *pdev)
1219{
1220 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1221
1222 txx9dmac_off(ddev);
1223 if (ddev->irq >= 0) {
1224 devm_free_irq(&pdev->dev, ddev->irq, ddev);
1225 tasklet_kill(&ddev->tasklet);
1226 }
1227 return 0;
1228}
1229
1230static void txx9dmac_shutdown(struct platform_device *pdev)
1231{
1232 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1233
1234 txx9dmac_off(ddev);
1235}
1236
1237static int txx9dmac_suspend_noirq(struct device *dev)
1238{
1239 struct txx9dmac_dev *ddev = dev_get_drvdata(dev);
1240
1241 txx9dmac_off(ddev);
1242 return 0;
1243}
1244
1245static int txx9dmac_resume_noirq(struct device *dev)
1246{
1247 struct txx9dmac_dev *ddev = dev_get_drvdata(dev);
1248 struct txx9dmac_platform_data *pdata = dev_get_platdata(dev);
1249 u32 mcr;
1250
1251 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1252 if (pdata && pdata->memcpy_chan >= 0)
1253 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1254 dma_writel(ddev, MCR, mcr);
1255 return 0;
1256
1257}
1258
1259static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1260 .suspend_noirq = txx9dmac_suspend_noirq,
1261 .resume_noirq = txx9dmac_resume_noirq,
1262};
1263
1264static struct platform_driver txx9dmac_chan_driver = {
1265 .remove = txx9dmac_chan_remove,
1266 .driver = {
1267 .name = "txx9dmac-chan",
1268 },
1269};
1270
1271static struct platform_driver txx9dmac_driver = {
1272 .remove = txx9dmac_remove,
1273 .shutdown = txx9dmac_shutdown,
1274 .driver = {
1275 .name = "txx9dmac",
1276 .pm = &txx9dmac_dev_pm_ops,
1277 },
1278};
1279
1280static int __init txx9dmac_init(void)
1281{
1282 int rc;
1283
1284 rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1285 if (!rc) {
1286 rc = platform_driver_probe(&txx9dmac_chan_driver,
1287 txx9dmac_chan_probe);
1288 if (rc)
1289 platform_driver_unregister(&txx9dmac_driver);
1290 }
1291 return rc;
1292}
1293module_init(txx9dmac_init);
1294
1295static void __exit txx9dmac_exit(void)
1296{
1297 platform_driver_unregister(&txx9dmac_chan_driver);
1298 platform_driver_unregister(&txx9dmac_driver);
1299}
1300module_exit(txx9dmac_exit);
1301
1302MODULE_LICENSE("GPL");
1303MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1304MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1305MODULE_ALIAS("platform:txx9dmac");
1306MODULE_ALIAS("platform:txx9dmac-chan");