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1/*
2 * nicstar.c
3 *
4 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
5 *
6 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
7 * It was taken from the frle-0.22 device driver.
8 * As the file doesn't have a copyright notice, in the file
9 * nicstarmac.copyright I put the copyright notice from the
10 * frle-0.22 device driver.
11 * Some code is based on the nicstar driver by M. Welsh.
12 *
13 * Author: Rui Prior (rprior@inescn.pt)
14 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
15 *
16 *
17 * (C) INESC 1999
18 */
19
20/*
21 * IMPORTANT INFORMATION
22 *
23 * There are currently three types of spinlocks:
24 *
25 * 1 - Per card interrupt spinlock (to protect structures and such)
26 * 2 - Per SCQ scq spinlock
27 * 3 - Per card resource spinlock (to access registers, etc.)
28 *
29 * These must NEVER be grabbed in reverse order.
30 *
31 */
32
33/* Header files */
34
35#include <linux/module.h>
36#include <linux/kernel.h>
37#include <linux/skbuff.h>
38#include <linux/atmdev.h>
39#include <linux/atm.h>
40#include <linux/pci.h>
41#include <linux/dma-mapping.h>
42#include <linux/types.h>
43#include <linux/string.h>
44#include <linux/delay.h>
45#include <linux/init.h>
46#include <linux/sched.h>
47#include <linux/timer.h>
48#include <linux/interrupt.h>
49#include <linux/bitops.h>
50#include <linux/slab.h>
51#include <linux/idr.h>
52#include <asm/io.h>
53#include <asm/uaccess.h>
54#include <linux/atomic.h>
55#include "nicstar.h"
56#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
57#include "suni.h"
58#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
59#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
60#include "idt77105.h"
61#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
62
63/* Additional code */
64
65#include "nicstarmac.c"
66
67/* Configurable parameters */
68
69#undef PHY_LOOPBACK
70#undef TX_DEBUG
71#undef RX_DEBUG
72#undef GENERAL_DEBUG
73#undef EXTRA_DEBUG
74
75#undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know
76 you're going to use only raw ATM */
77
78/* Do not touch these */
79
80#ifdef TX_DEBUG
81#define TXPRINTK(args...) printk(args)
82#else
83#define TXPRINTK(args...)
84#endif /* TX_DEBUG */
85
86#ifdef RX_DEBUG
87#define RXPRINTK(args...) printk(args)
88#else
89#define RXPRINTK(args...)
90#endif /* RX_DEBUG */
91
92#ifdef GENERAL_DEBUG
93#define PRINTK(args...) printk(args)
94#else
95#define PRINTK(args...)
96#endif /* GENERAL_DEBUG */
97
98#ifdef EXTRA_DEBUG
99#define XPRINTK(args...) printk(args)
100#else
101#define XPRINTK(args...)
102#endif /* EXTRA_DEBUG */
103
104/* Macros */
105
106#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
107
108#define NS_DELAY mdelay(1)
109
110#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
111
112#ifndef ATM_SKB
113#define ATM_SKB(s) (&(s)->atm)
114#endif
115
116#define scq_virt_to_bus(scq, p) \
117 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
118
119/* Function declarations */
120
121static u32 ns_read_sram(ns_dev * card, u32 sram_address);
122static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
123 int count);
124static int __devinit ns_init_card(int i, struct pci_dev *pcidev);
125static void __devinit ns_init_card_error(ns_dev * card, int error);
126static scq_info *get_scq(ns_dev *card, int size, u32 scd);
127static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
128static void push_rxbufs(ns_dev *, struct sk_buff *);
129static irqreturn_t ns_irq_handler(int irq, void *dev_id);
130static int ns_open(struct atm_vcc *vcc);
131static void ns_close(struct atm_vcc *vcc);
132static void fill_tst(ns_dev * card, int n, vc_map * vc);
133static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
134static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
135 struct sk_buff *skb);
136static void process_tsq(ns_dev * card);
137static void drain_scq(ns_dev * card, scq_info * scq, int pos);
138static void process_rsq(ns_dev * card);
139static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
140#ifdef NS_USE_DESTRUCTORS
141static void ns_sb_destructor(struct sk_buff *sb);
142static void ns_lb_destructor(struct sk_buff *lb);
143static void ns_hb_destructor(struct sk_buff *hb);
144#endif /* NS_USE_DESTRUCTORS */
145static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
146static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
147static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
148static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
149static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
150static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
151static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
152#ifdef EXTRA_DEBUG
153static void which_list(ns_dev * card, struct sk_buff *skb);
154#endif
155static void ns_poll(unsigned long arg);
156static int ns_parse_mac(char *mac, unsigned char *esi);
157static void ns_phy_put(struct atm_dev *dev, unsigned char value,
158 unsigned long addr);
159static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
160
161/* Global variables */
162
163static struct ns_dev *cards[NS_MAX_CARDS];
164static unsigned num_cards;
165static struct atmdev_ops atm_ops = {
166 .open = ns_open,
167 .close = ns_close,
168 .ioctl = ns_ioctl,
169 .send = ns_send,
170 .phy_put = ns_phy_put,
171 .phy_get = ns_phy_get,
172 .proc_read = ns_proc_read,
173 .owner = THIS_MODULE,
174};
175
176static struct timer_list ns_timer;
177static char *mac[NS_MAX_CARDS];
178module_param_array(mac, charp, NULL, 0);
179MODULE_LICENSE("GPL");
180
181/* Functions */
182
183static int __devinit nicstar_init_one(struct pci_dev *pcidev,
184 const struct pci_device_id *ent)
185{
186 static int index = -1;
187 unsigned int error;
188
189 index++;
190 cards[index] = NULL;
191
192 error = ns_init_card(index, pcidev);
193 if (error) {
194 cards[index--] = NULL; /* don't increment index */
195 goto err_out;
196 }
197
198 return 0;
199err_out:
200 return -ENODEV;
201}
202
203static void __devexit nicstar_remove_one(struct pci_dev *pcidev)
204{
205 int i, j;
206 ns_dev *card = pci_get_drvdata(pcidev);
207 struct sk_buff *hb;
208 struct sk_buff *iovb;
209 struct sk_buff *lb;
210 struct sk_buff *sb;
211
212 i = card->index;
213
214 if (cards[i] == NULL)
215 return;
216
217 if (card->atmdev->phy && card->atmdev->phy->stop)
218 card->atmdev->phy->stop(card->atmdev);
219
220 /* Stop everything */
221 writel(0x00000000, card->membase + CFG);
222
223 /* De-register device */
224 atm_dev_deregister(card->atmdev);
225
226 /* Disable PCI device */
227 pci_disable_device(pcidev);
228
229 /* Free up resources */
230 j = 0;
231 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
232 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
233 dev_kfree_skb_any(hb);
234 j++;
235 }
236 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
237 j = 0;
238 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
239 card->iovpool.count);
240 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
241 dev_kfree_skb_any(iovb);
242 j++;
243 }
244 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
245 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
246 dev_kfree_skb_any(lb);
247 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
248 dev_kfree_skb_any(sb);
249 free_scq(card, card->scq0, NULL);
250 for (j = 0; j < NS_FRSCD_NUM; j++) {
251 if (card->scd2vc[j] != NULL)
252 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
253 }
254 idr_remove_all(&card->idr);
255 idr_destroy(&card->idr);
256 pci_free_consistent(card->pcidev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
257 card->rsq.org, card->rsq.dma);
258 pci_free_consistent(card->pcidev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
259 card->tsq.org, card->tsq.dma);
260 free_irq(card->pcidev->irq, card);
261 iounmap(card->membase);
262 kfree(card);
263}
264
265static struct pci_device_id nicstar_pci_tbl[] __devinitdata = {
266 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
267 {0,} /* terminate list */
268};
269
270MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
271
272static struct pci_driver nicstar_driver = {
273 .name = "nicstar",
274 .id_table = nicstar_pci_tbl,
275 .probe = nicstar_init_one,
276 .remove = __devexit_p(nicstar_remove_one),
277};
278
279static int __init nicstar_init(void)
280{
281 unsigned error = 0; /* Initialized to remove compile warning */
282
283 XPRINTK("nicstar: nicstar_init() called.\n");
284
285 error = pci_register_driver(&nicstar_driver);
286
287 TXPRINTK("nicstar: TX debug enabled.\n");
288 RXPRINTK("nicstar: RX debug enabled.\n");
289 PRINTK("nicstar: General debug enabled.\n");
290#ifdef PHY_LOOPBACK
291 printk("nicstar: using PHY loopback.\n");
292#endif /* PHY_LOOPBACK */
293 XPRINTK("nicstar: nicstar_init() returned.\n");
294
295 if (!error) {
296 init_timer(&ns_timer);
297 ns_timer.expires = jiffies + NS_POLL_PERIOD;
298 ns_timer.data = 0UL;
299 ns_timer.function = ns_poll;
300 add_timer(&ns_timer);
301 }
302
303 return error;
304}
305
306static void __exit nicstar_cleanup(void)
307{
308 XPRINTK("nicstar: nicstar_cleanup() called.\n");
309
310 del_timer(&ns_timer);
311
312 pci_unregister_driver(&nicstar_driver);
313
314 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
315}
316
317static u32 ns_read_sram(ns_dev * card, u32 sram_address)
318{
319 unsigned long flags;
320 u32 data;
321 sram_address <<= 2;
322 sram_address &= 0x0007FFFC; /* address must be dword aligned */
323 sram_address |= 0x50000000; /* SRAM read command */
324 spin_lock_irqsave(&card->res_lock, flags);
325 while (CMD_BUSY(card)) ;
326 writel(sram_address, card->membase + CMD);
327 while (CMD_BUSY(card)) ;
328 data = readl(card->membase + DR0);
329 spin_unlock_irqrestore(&card->res_lock, flags);
330 return data;
331}
332
333static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
334 int count)
335{
336 unsigned long flags;
337 int i, c;
338 count--; /* count range now is 0..3 instead of 1..4 */
339 c = count;
340 c <<= 2; /* to use increments of 4 */
341 spin_lock_irqsave(&card->res_lock, flags);
342 while (CMD_BUSY(card)) ;
343 for (i = 0; i <= c; i += 4)
344 writel(*(value++), card->membase + i);
345 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
346 so card->membase + DR0 == card->membase */
347 sram_address <<= 2;
348 sram_address &= 0x0007FFFC;
349 sram_address |= (0x40000000 | count);
350 writel(sram_address, card->membase + CMD);
351 spin_unlock_irqrestore(&card->res_lock, flags);
352}
353
354static int __devinit ns_init_card(int i, struct pci_dev *pcidev)
355{
356 int j;
357 struct ns_dev *card = NULL;
358 unsigned char pci_latency;
359 unsigned error;
360 u32 data;
361 u32 u32d[4];
362 u32 ns_cfg_rctsize;
363 int bcount;
364 unsigned long membase;
365
366 error = 0;
367
368 if (pci_enable_device(pcidev)) {
369 printk("nicstar%d: can't enable PCI device\n", i);
370 error = 2;
371 ns_init_card_error(card, error);
372 return error;
373 }
374 if ((pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0) ||
375 (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0)) {
376 printk(KERN_WARNING
377 "nicstar%d: No suitable DMA available.\n", i);
378 error = 2;
379 ns_init_card_error(card, error);
380 return error;
381 }
382
383 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) {
384 printk
385 ("nicstar%d: can't allocate memory for device structure.\n",
386 i);
387 error = 2;
388 ns_init_card_error(card, error);
389 return error;
390 }
391 cards[i] = card;
392 spin_lock_init(&card->int_lock);
393 spin_lock_init(&card->res_lock);
394
395 pci_set_drvdata(pcidev, card);
396
397 card->index = i;
398 card->atmdev = NULL;
399 card->pcidev = pcidev;
400 membase = pci_resource_start(pcidev, 1);
401 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
402 if (!card->membase) {
403 printk("nicstar%d: can't ioremap() membase.\n", i);
404 error = 3;
405 ns_init_card_error(card, error);
406 return error;
407 }
408 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
409
410 pci_set_master(pcidev);
411
412 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
413 printk("nicstar%d: can't read PCI latency timer.\n", i);
414 error = 6;
415 ns_init_card_error(card, error);
416 return error;
417 }
418#ifdef NS_PCI_LATENCY
419 if (pci_latency < NS_PCI_LATENCY) {
420 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
421 NS_PCI_LATENCY);
422 for (j = 1; j < 4; j++) {
423 if (pci_write_config_byte
424 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
425 break;
426 }
427 if (j == 4) {
428 printk
429 ("nicstar%d: can't set PCI latency timer to %d.\n",
430 i, NS_PCI_LATENCY);
431 error = 7;
432 ns_init_card_error(card, error);
433 return error;
434 }
435 }
436#endif /* NS_PCI_LATENCY */
437
438 /* Clear timer overflow */
439 data = readl(card->membase + STAT);
440 if (data & NS_STAT_TMROF)
441 writel(NS_STAT_TMROF, card->membase + STAT);
442
443 /* Software reset */
444 writel(NS_CFG_SWRST, card->membase + CFG);
445 NS_DELAY;
446 writel(0x00000000, card->membase + CFG);
447
448 /* PHY reset */
449 writel(0x00000008, card->membase + GP);
450 NS_DELAY;
451 writel(0x00000001, card->membase + GP);
452 NS_DELAY;
453 while (CMD_BUSY(card)) ;
454 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
455 NS_DELAY;
456
457 /* Detect PHY type */
458 while (CMD_BUSY(card)) ;
459 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
460 while (CMD_BUSY(card)) ;
461 data = readl(card->membase + DR0);
462 switch (data) {
463 case 0x00000009:
464 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
465 card->max_pcr = ATM_25_PCR;
466 while (CMD_BUSY(card)) ;
467 writel(0x00000008, card->membase + DR0);
468 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
469 /* Clear an eventual pending interrupt */
470 writel(NS_STAT_SFBQF, card->membase + STAT);
471#ifdef PHY_LOOPBACK
472 while (CMD_BUSY(card)) ;
473 writel(0x00000022, card->membase + DR0);
474 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
475#endif /* PHY_LOOPBACK */
476 break;
477 case 0x00000030:
478 case 0x00000031:
479 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
480 card->max_pcr = ATM_OC3_PCR;
481#ifdef PHY_LOOPBACK
482 while (CMD_BUSY(card)) ;
483 writel(0x00000002, card->membase + DR0);
484 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
485#endif /* PHY_LOOPBACK */
486 break;
487 default:
488 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
489 error = 8;
490 ns_init_card_error(card, error);
491 return error;
492 }
493 writel(0x00000000, card->membase + GP);
494
495 /* Determine SRAM size */
496 data = 0x76543210;
497 ns_write_sram(card, 0x1C003, &data, 1);
498 data = 0x89ABCDEF;
499 ns_write_sram(card, 0x14003, &data, 1);
500 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
501 ns_read_sram(card, 0x1C003) == 0x76543210)
502 card->sram_size = 128;
503 else
504 card->sram_size = 32;
505 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
506
507 card->rct_size = NS_MAX_RCTSIZE;
508
509#if (NS_MAX_RCTSIZE == 4096)
510 if (card->sram_size == 128)
511 printk
512 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
513 i);
514#elif (NS_MAX_RCTSIZE == 16384)
515 if (card->sram_size == 32) {
516 printk
517 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
518 i);
519 card->rct_size = 4096;
520 }
521#else
522#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
523#endif
524
525 card->vpibits = NS_VPIBITS;
526 if (card->rct_size == 4096)
527 card->vcibits = 12 - NS_VPIBITS;
528 else /* card->rct_size == 16384 */
529 card->vcibits = 14 - NS_VPIBITS;
530
531 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
532 if (mac[i] == NULL)
533 nicstar_init_eprom(card->membase);
534
535 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
536 writel(0x00000000, card->membase + VPM);
537
538 /* Initialize TSQ */
539 card->tsq.org = pci_alloc_consistent(card->pcidev,
540 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
541 &card->tsq.dma);
542 if (card->tsq.org == NULL) {
543 printk("nicstar%d: can't allocate TSQ.\n", i);
544 error = 10;
545 ns_init_card_error(card, error);
546 return error;
547 }
548 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
549 card->tsq.next = card->tsq.base;
550 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
551 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
552 ns_tsi_init(card->tsq.base + j);
553 writel(0x00000000, card->membase + TSQH);
554 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
555 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
556
557 /* Initialize RSQ */
558 card->rsq.org = pci_alloc_consistent(card->pcidev,
559 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
560 &card->rsq.dma);
561 if (card->rsq.org == NULL) {
562 printk("nicstar%d: can't allocate RSQ.\n", i);
563 error = 11;
564 ns_init_card_error(card, error);
565 return error;
566 }
567 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
568 card->rsq.next = card->rsq.base;
569 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
570 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
571 ns_rsqe_init(card->rsq.base + j);
572 writel(0x00000000, card->membase + RSQH);
573 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
574 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
575
576 /* Initialize SCQ0, the only VBR SCQ used */
577 card->scq1 = NULL;
578 card->scq2 = NULL;
579 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
580 if (card->scq0 == NULL) {
581 printk("nicstar%d: can't get SCQ0.\n", i);
582 error = 12;
583 ns_init_card_error(card, error);
584 return error;
585 }
586 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
587 u32d[1] = (u32) 0x00000000;
588 u32d[2] = (u32) 0xffffffff;
589 u32d[3] = (u32) 0x00000000;
590 ns_write_sram(card, NS_VRSCD0, u32d, 4);
591 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
592 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
593 card->scq0->scd = NS_VRSCD0;
594 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
595
596 /* Initialize TSTs */
597 card->tst_addr = NS_TST0;
598 card->tst_free_entries = NS_TST_NUM_ENTRIES;
599 data = NS_TST_OPCODE_VARIABLE;
600 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
601 ns_write_sram(card, NS_TST0 + j, &data, 1);
602 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
603 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
604 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
605 ns_write_sram(card, NS_TST1 + j, &data, 1);
606 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
607 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
608 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
609 card->tste2vc[j] = NULL;
610 writel(NS_TST0 << 2, card->membase + TSTB);
611
612 /* Initialize RCT. AAL type is set on opening the VC. */
613#ifdef RCQ_SUPPORT
614 u32d[0] = NS_RCTE_RAWCELLINTEN;
615#else
616 u32d[0] = 0x00000000;
617#endif /* RCQ_SUPPORT */
618 u32d[1] = 0x00000000;
619 u32d[2] = 0x00000000;
620 u32d[3] = 0xFFFFFFFF;
621 for (j = 0; j < card->rct_size; j++)
622 ns_write_sram(card, j * 4, u32d, 4);
623
624 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map));
625
626 for (j = 0; j < NS_FRSCD_NUM; j++)
627 card->scd2vc[j] = NULL;
628
629 /* Initialize buffer levels */
630 card->sbnr.min = MIN_SB;
631 card->sbnr.init = NUM_SB;
632 card->sbnr.max = MAX_SB;
633 card->lbnr.min = MIN_LB;
634 card->lbnr.init = NUM_LB;
635 card->lbnr.max = MAX_LB;
636 card->iovnr.min = MIN_IOVB;
637 card->iovnr.init = NUM_IOVB;
638 card->iovnr.max = MAX_IOVB;
639 card->hbnr.min = MIN_HB;
640 card->hbnr.init = NUM_HB;
641 card->hbnr.max = MAX_HB;
642
643 card->sm_handle = 0x00000000;
644 card->sm_addr = 0x00000000;
645 card->lg_handle = 0x00000000;
646 card->lg_addr = 0x00000000;
647
648 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
649
650 idr_init(&card->idr);
651
652 /* Pre-allocate some huge buffers */
653 skb_queue_head_init(&card->hbpool.queue);
654 card->hbpool.count = 0;
655 for (j = 0; j < NUM_HB; j++) {
656 struct sk_buff *hb;
657 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
658 if (hb == NULL) {
659 printk
660 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
661 i, j, NUM_HB);
662 error = 13;
663 ns_init_card_error(card, error);
664 return error;
665 }
666 NS_PRV_BUFTYPE(hb) = BUF_NONE;
667 skb_queue_tail(&card->hbpool.queue, hb);
668 card->hbpool.count++;
669 }
670
671 /* Allocate large buffers */
672 skb_queue_head_init(&card->lbpool.queue);
673 card->lbpool.count = 0; /* Not used */
674 for (j = 0; j < NUM_LB; j++) {
675 struct sk_buff *lb;
676 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
677 if (lb == NULL) {
678 printk
679 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
680 i, j, NUM_LB);
681 error = 14;
682 ns_init_card_error(card, error);
683 return error;
684 }
685 NS_PRV_BUFTYPE(lb) = BUF_LG;
686 skb_queue_tail(&card->lbpool.queue, lb);
687 skb_reserve(lb, NS_SMBUFSIZE);
688 push_rxbufs(card, lb);
689 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
690 if (j == 1) {
691 card->rcbuf = lb;
692 card->rawcell = (struct ns_rcqe *) lb->data;
693 card->rawch = NS_PRV_DMA(lb);
694 }
695 }
696 /* Test for strange behaviour which leads to crashes */
697 if ((bcount =
698 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
699 printk
700 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
701 i, j, bcount);
702 error = 14;
703 ns_init_card_error(card, error);
704 return error;
705 }
706
707 /* Allocate small buffers */
708 skb_queue_head_init(&card->sbpool.queue);
709 card->sbpool.count = 0; /* Not used */
710 for (j = 0; j < NUM_SB; j++) {
711 struct sk_buff *sb;
712 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
713 if (sb == NULL) {
714 printk
715 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
716 i, j, NUM_SB);
717 error = 15;
718 ns_init_card_error(card, error);
719 return error;
720 }
721 NS_PRV_BUFTYPE(sb) = BUF_SM;
722 skb_queue_tail(&card->sbpool.queue, sb);
723 skb_reserve(sb, NS_AAL0_HEADER);
724 push_rxbufs(card, sb);
725 }
726 /* Test for strange behaviour which leads to crashes */
727 if ((bcount =
728 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
729 printk
730 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
731 i, j, bcount);
732 error = 15;
733 ns_init_card_error(card, error);
734 return error;
735 }
736
737 /* Allocate iovec buffers */
738 skb_queue_head_init(&card->iovpool.queue);
739 card->iovpool.count = 0;
740 for (j = 0; j < NUM_IOVB; j++) {
741 struct sk_buff *iovb;
742 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
743 if (iovb == NULL) {
744 printk
745 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
746 i, j, NUM_IOVB);
747 error = 16;
748 ns_init_card_error(card, error);
749 return error;
750 }
751 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
752 skb_queue_tail(&card->iovpool.queue, iovb);
753 card->iovpool.count++;
754 }
755
756 /* Configure NICStAR */
757 if (card->rct_size == 4096)
758 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
759 else /* (card->rct_size == 16384) */
760 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
761
762 card->efbie = 1;
763
764 card->intcnt = 0;
765 if (request_irq
766 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
767 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
768 error = 9;
769 ns_init_card_error(card, error);
770 return error;
771 }
772
773 /* Register device */
774 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
775 -1, NULL);
776 if (card->atmdev == NULL) {
777 printk("nicstar%d: can't register device.\n", i);
778 error = 17;
779 ns_init_card_error(card, error);
780 return error;
781 }
782
783 if (ns_parse_mac(mac[i], card->atmdev->esi)) {
784 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
785 card->atmdev->esi, 6);
786 if (memcmp(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00", 6) ==
787 0) {
788 nicstar_read_eprom(card->membase,
789 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
790 card->atmdev->esi, 6);
791 }
792 }
793
794 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
795
796 card->atmdev->dev_data = card;
797 card->atmdev->ci_range.vpi_bits = card->vpibits;
798 card->atmdev->ci_range.vci_bits = card->vcibits;
799 card->atmdev->link_rate = card->max_pcr;
800 card->atmdev->phy = NULL;
801
802#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
803 if (card->max_pcr == ATM_OC3_PCR)
804 suni_init(card->atmdev);
805#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
806
807#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
808 if (card->max_pcr == ATM_25_PCR)
809 idt77105_init(card->atmdev);
810#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
811
812 if (card->atmdev->phy && card->atmdev->phy->start)
813 card->atmdev->phy->start(card->atmdev);
814
815 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
816 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
817 NS_CFG_PHYIE, card->membase + CFG);
818
819 num_cards++;
820
821 return error;
822}
823
824static void __devinit ns_init_card_error(ns_dev * card, int error)
825{
826 if (error >= 17) {
827 writel(0x00000000, card->membase + CFG);
828 }
829 if (error >= 16) {
830 struct sk_buff *iovb;
831 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
832 dev_kfree_skb_any(iovb);
833 }
834 if (error >= 15) {
835 struct sk_buff *sb;
836 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
837 dev_kfree_skb_any(sb);
838 free_scq(card, card->scq0, NULL);
839 }
840 if (error >= 14) {
841 struct sk_buff *lb;
842 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
843 dev_kfree_skb_any(lb);
844 }
845 if (error >= 13) {
846 struct sk_buff *hb;
847 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
848 dev_kfree_skb_any(hb);
849 }
850 if (error >= 12) {
851 kfree(card->rsq.org);
852 }
853 if (error >= 11) {
854 kfree(card->tsq.org);
855 }
856 if (error >= 10) {
857 free_irq(card->pcidev->irq, card);
858 }
859 if (error >= 4) {
860 iounmap(card->membase);
861 }
862 if (error >= 3) {
863 pci_disable_device(card->pcidev);
864 kfree(card);
865 }
866}
867
868static scq_info *get_scq(ns_dev *card, int size, u32 scd)
869{
870 scq_info *scq;
871 int i;
872
873 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
874 return NULL;
875
876 scq = kmalloc(sizeof(scq_info), GFP_KERNEL);
877 if (!scq)
878 return NULL;
879 scq->org = pci_alloc_consistent(card->pcidev, 2 * size, &scq->dma);
880 if (!scq->org) {
881 kfree(scq);
882 return NULL;
883 }
884 scq->skb = kmalloc(sizeof(struct sk_buff *) *
885 (size / NS_SCQE_SIZE), GFP_KERNEL);
886 if (!scq->skb) {
887 kfree(scq->org);
888 kfree(scq);
889 return NULL;
890 }
891 scq->num_entries = size / NS_SCQE_SIZE;
892 scq->base = PTR_ALIGN(scq->org, size);
893 scq->next = scq->base;
894 scq->last = scq->base + (scq->num_entries - 1);
895 scq->tail = scq->last;
896 scq->scd = scd;
897 scq->num_entries = size / NS_SCQE_SIZE;
898 scq->tbd_count = 0;
899 init_waitqueue_head(&scq->scqfull_waitq);
900 scq->full = 0;
901 spin_lock_init(&scq->lock);
902
903 for (i = 0; i < scq->num_entries; i++)
904 scq->skb[i] = NULL;
905
906 return scq;
907}
908
909/* For variable rate SCQ vcc must be NULL */
910static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
911{
912 int i;
913
914 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
915 for (i = 0; i < scq->num_entries; i++) {
916 if (scq->skb[i] != NULL) {
917 vcc = ATM_SKB(scq->skb[i])->vcc;
918 if (vcc->pop != NULL)
919 vcc->pop(vcc, scq->skb[i]);
920 else
921 dev_kfree_skb_any(scq->skb[i]);
922 }
923 } else { /* vcc must be != NULL */
924
925 if (vcc == NULL) {
926 printk
927 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
928 for (i = 0; i < scq->num_entries; i++)
929 dev_kfree_skb_any(scq->skb[i]);
930 } else
931 for (i = 0; i < scq->num_entries; i++) {
932 if (scq->skb[i] != NULL) {
933 if (vcc->pop != NULL)
934 vcc->pop(vcc, scq->skb[i]);
935 else
936 dev_kfree_skb_any(scq->skb[i]);
937 }
938 }
939 }
940 kfree(scq->skb);
941 pci_free_consistent(card->pcidev,
942 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
943 VBR_SCQSIZE : CBR_SCQSIZE),
944 scq->org, scq->dma);
945 kfree(scq);
946}
947
948/* The handles passed must be pointers to the sk_buff containing the small
949 or large buffer(s) cast to u32. */
950static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
951{
952 struct sk_buff *handle1, *handle2;
953 u32 id1 = 0, id2 = 0;
954 u32 addr1, addr2;
955 u32 stat;
956 unsigned long flags;
957 int err;
958
959 /* *BARF* */
960 handle2 = NULL;
961 addr2 = 0;
962 handle1 = skb;
963 addr1 = pci_map_single(card->pcidev,
964 skb->data,
965 (NS_PRV_BUFTYPE(skb) == BUF_SM
966 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
967 PCI_DMA_TODEVICE);
968 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
969
970#ifdef GENERAL_DEBUG
971 if (!addr1)
972 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
973 card->index);
974#endif /* GENERAL_DEBUG */
975
976 stat = readl(card->membase + STAT);
977 card->sbfqc = ns_stat_sfbqc_get(stat);
978 card->lbfqc = ns_stat_lfbqc_get(stat);
979 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
980 if (!addr2) {
981 if (card->sm_addr) {
982 addr2 = card->sm_addr;
983 handle2 = card->sm_handle;
984 card->sm_addr = 0x00000000;
985 card->sm_handle = 0x00000000;
986 } else { /* (!sm_addr) */
987
988 card->sm_addr = addr1;
989 card->sm_handle = handle1;
990 }
991 }
992 } else { /* buf_type == BUF_LG */
993
994 if (!addr2) {
995 if (card->lg_addr) {
996 addr2 = card->lg_addr;
997 handle2 = card->lg_handle;
998 card->lg_addr = 0x00000000;
999 card->lg_handle = 0x00000000;
1000 } else { /* (!lg_addr) */
1001
1002 card->lg_addr = addr1;
1003 card->lg_handle = handle1;
1004 }
1005 }
1006 }
1007
1008 if (addr2) {
1009 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
1010 if (card->sbfqc >= card->sbnr.max) {
1011 skb_unlink(handle1, &card->sbpool.queue);
1012 dev_kfree_skb_any(handle1);
1013 skb_unlink(handle2, &card->sbpool.queue);
1014 dev_kfree_skb_any(handle2);
1015 return;
1016 } else
1017 card->sbfqc += 2;
1018 } else { /* (buf_type == BUF_LG) */
1019
1020 if (card->lbfqc >= card->lbnr.max) {
1021 skb_unlink(handle1, &card->lbpool.queue);
1022 dev_kfree_skb_any(handle1);
1023 skb_unlink(handle2, &card->lbpool.queue);
1024 dev_kfree_skb_any(handle2);
1025 return;
1026 } else
1027 card->lbfqc += 2;
1028 }
1029
1030 do {
1031 if (!idr_pre_get(&card->idr, GFP_ATOMIC)) {
1032 printk(KERN_ERR
1033 "nicstar%d: no free memory for idr\n",
1034 card->index);
1035 goto out;
1036 }
1037
1038 if (!id1)
1039 err = idr_get_new_above(&card->idr, handle1, 0, &id1);
1040
1041 if (!id2 && err == 0)
1042 err = idr_get_new_above(&card->idr, handle2, 0, &id2);
1043
1044 } while (err == -EAGAIN);
1045
1046 if (err)
1047 goto out;
1048
1049 spin_lock_irqsave(&card->res_lock, flags);
1050 while (CMD_BUSY(card)) ;
1051 writel(addr2, card->membase + DR3);
1052 writel(id2, card->membase + DR2);
1053 writel(addr1, card->membase + DR1);
1054 writel(id1, card->membase + DR0);
1055 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1056 card->membase + CMD);
1057 spin_unlock_irqrestore(&card->res_lock, flags);
1058
1059 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1060 card->index,
1061 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1062 addr1, addr2);
1063 }
1064
1065 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1066 card->lbfqc >= card->lbnr.min) {
1067 card->efbie = 1;
1068 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1069 card->membase + CFG);
1070 }
1071
1072out:
1073 return;
1074}
1075
1076static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1077{
1078 u32 stat_r;
1079 ns_dev *card;
1080 struct atm_dev *dev;
1081 unsigned long flags;
1082
1083 card = (ns_dev *) dev_id;
1084 dev = card->atmdev;
1085 card->intcnt++;
1086
1087 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1088
1089 spin_lock_irqsave(&card->int_lock, flags);
1090
1091 stat_r = readl(card->membase + STAT);
1092
1093 /* Transmit Status Indicator has been written to T. S. Queue */
1094 if (stat_r & NS_STAT_TSIF) {
1095 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1096 process_tsq(card);
1097 writel(NS_STAT_TSIF, card->membase + STAT);
1098 }
1099
1100 /* Incomplete CS-PDU has been transmitted */
1101 if (stat_r & NS_STAT_TXICP) {
1102 writel(NS_STAT_TXICP, card->membase + STAT);
1103 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1104 card->index);
1105 }
1106
1107 /* Transmit Status Queue 7/8 full */
1108 if (stat_r & NS_STAT_TSQF) {
1109 writel(NS_STAT_TSQF, card->membase + STAT);
1110 PRINTK("nicstar%d: TSQ full.\n", card->index);
1111 process_tsq(card);
1112 }
1113
1114 /* Timer overflow */
1115 if (stat_r & NS_STAT_TMROF) {
1116 writel(NS_STAT_TMROF, card->membase + STAT);
1117 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1118 }
1119
1120 /* PHY device interrupt signal active */
1121 if (stat_r & NS_STAT_PHYI) {
1122 writel(NS_STAT_PHYI, card->membase + STAT);
1123 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1124 if (dev->phy && dev->phy->interrupt) {
1125 dev->phy->interrupt(dev);
1126 }
1127 }
1128
1129 /* Small Buffer Queue is full */
1130 if (stat_r & NS_STAT_SFBQF) {
1131 writel(NS_STAT_SFBQF, card->membase + STAT);
1132 printk("nicstar%d: Small free buffer queue is full.\n",
1133 card->index);
1134 }
1135
1136 /* Large Buffer Queue is full */
1137 if (stat_r & NS_STAT_LFBQF) {
1138 writel(NS_STAT_LFBQF, card->membase + STAT);
1139 printk("nicstar%d: Large free buffer queue is full.\n",
1140 card->index);
1141 }
1142
1143 /* Receive Status Queue is full */
1144 if (stat_r & NS_STAT_RSQF) {
1145 writel(NS_STAT_RSQF, card->membase + STAT);
1146 printk("nicstar%d: RSQ full.\n", card->index);
1147 process_rsq(card);
1148 }
1149
1150 /* Complete CS-PDU received */
1151 if (stat_r & NS_STAT_EOPDU) {
1152 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1153 process_rsq(card);
1154 writel(NS_STAT_EOPDU, card->membase + STAT);
1155 }
1156
1157 /* Raw cell received */
1158 if (stat_r & NS_STAT_RAWCF) {
1159 writel(NS_STAT_RAWCF, card->membase + STAT);
1160#ifndef RCQ_SUPPORT
1161 printk("nicstar%d: Raw cell received and no support yet...\n",
1162 card->index);
1163#endif /* RCQ_SUPPORT */
1164 /* NOTE: the following procedure may keep a raw cell pending until the
1165 next interrupt. As this preliminary support is only meant to
1166 avoid buffer leakage, this is not an issue. */
1167 while (readl(card->membase + RAWCT) != card->rawch) {
1168
1169 if (ns_rcqe_islast(card->rawcell)) {
1170 struct sk_buff *oldbuf;
1171
1172 oldbuf = card->rcbuf;
1173 card->rcbuf = idr_find(&card->idr,
1174 ns_rcqe_nextbufhandle(card->rawcell));
1175 card->rawch = NS_PRV_DMA(card->rcbuf);
1176 card->rawcell = (struct ns_rcqe *)
1177 card->rcbuf->data;
1178 recycle_rx_buf(card, oldbuf);
1179 } else {
1180 card->rawch += NS_RCQE_SIZE;
1181 card->rawcell++;
1182 }
1183 }
1184 }
1185
1186 /* Small buffer queue is empty */
1187 if (stat_r & NS_STAT_SFBQE) {
1188 int i;
1189 struct sk_buff *sb;
1190
1191 writel(NS_STAT_SFBQE, card->membase + STAT);
1192 printk("nicstar%d: Small free buffer queue empty.\n",
1193 card->index);
1194 for (i = 0; i < card->sbnr.min; i++) {
1195 sb = dev_alloc_skb(NS_SMSKBSIZE);
1196 if (sb == NULL) {
1197 writel(readl(card->membase + CFG) &
1198 ~NS_CFG_EFBIE, card->membase + CFG);
1199 card->efbie = 0;
1200 break;
1201 }
1202 NS_PRV_BUFTYPE(sb) = BUF_SM;
1203 skb_queue_tail(&card->sbpool.queue, sb);
1204 skb_reserve(sb, NS_AAL0_HEADER);
1205 push_rxbufs(card, sb);
1206 }
1207 card->sbfqc = i;
1208 process_rsq(card);
1209 }
1210
1211 /* Large buffer queue empty */
1212 if (stat_r & NS_STAT_LFBQE) {
1213 int i;
1214 struct sk_buff *lb;
1215
1216 writel(NS_STAT_LFBQE, card->membase + STAT);
1217 printk("nicstar%d: Large free buffer queue empty.\n",
1218 card->index);
1219 for (i = 0; i < card->lbnr.min; i++) {
1220 lb = dev_alloc_skb(NS_LGSKBSIZE);
1221 if (lb == NULL) {
1222 writel(readl(card->membase + CFG) &
1223 ~NS_CFG_EFBIE, card->membase + CFG);
1224 card->efbie = 0;
1225 break;
1226 }
1227 NS_PRV_BUFTYPE(lb) = BUF_LG;
1228 skb_queue_tail(&card->lbpool.queue, lb);
1229 skb_reserve(lb, NS_SMBUFSIZE);
1230 push_rxbufs(card, lb);
1231 }
1232 card->lbfqc = i;
1233 process_rsq(card);
1234 }
1235
1236 /* Receive Status Queue is 7/8 full */
1237 if (stat_r & NS_STAT_RSQAF) {
1238 writel(NS_STAT_RSQAF, card->membase + STAT);
1239 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1240 process_rsq(card);
1241 }
1242
1243 spin_unlock_irqrestore(&card->int_lock, flags);
1244 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1245 return IRQ_HANDLED;
1246}
1247
1248static int ns_open(struct atm_vcc *vcc)
1249{
1250 ns_dev *card;
1251 vc_map *vc;
1252 unsigned long tmpl, modl;
1253 int tcr, tcra; /* target cell rate, and absolute value */
1254 int n = 0; /* Number of entries in the TST. Initialized to remove
1255 the compiler warning. */
1256 u32 u32d[4];
1257 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1258 warning. How I wish compilers were clever enough to
1259 tell which variables can truly be used
1260 uninitialized... */
1261 int inuse; /* tx or rx vc already in use by another vcc */
1262 short vpi = vcc->vpi;
1263 int vci = vcc->vci;
1264
1265 card = (ns_dev *) vcc->dev->dev_data;
1266 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1267 vci);
1268 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1269 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1270 return -EINVAL;
1271 }
1272
1273 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1274 vcc->dev_data = vc;
1275
1276 inuse = 0;
1277 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1278 inuse = 1;
1279 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1280 inuse += 2;
1281 if (inuse) {
1282 printk("nicstar%d: %s vci already in use.\n", card->index,
1283 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1284 return -EINVAL;
1285 }
1286
1287 set_bit(ATM_VF_ADDR, &vcc->flags);
1288
1289 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1290 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1291 needed to do that. */
1292 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1293 scq_info *scq;
1294
1295 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1296 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1297 /* Check requested cell rate and availability of SCD */
1298 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1299 && vcc->qos.txtp.min_pcr == 0) {
1300 PRINTK
1301 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1302 card->index);
1303 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1304 clear_bit(ATM_VF_ADDR, &vcc->flags);
1305 return -EINVAL;
1306 }
1307
1308 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1309 tcra = tcr >= 0 ? tcr : -tcr;
1310
1311 PRINTK("nicstar%d: target cell rate = %d.\n",
1312 card->index, vcc->qos.txtp.max_pcr);
1313
1314 tmpl =
1315 (unsigned long)tcra *(unsigned long)
1316 NS_TST_NUM_ENTRIES;
1317 modl = tmpl % card->max_pcr;
1318
1319 n = (int)(tmpl / card->max_pcr);
1320 if (tcr > 0) {
1321 if (modl > 0)
1322 n++;
1323 } else if (tcr == 0) {
1324 if ((n =
1325 (card->tst_free_entries -
1326 NS_TST_RESERVED)) <= 0) {
1327 PRINTK
1328 ("nicstar%d: no CBR bandwidth free.\n",
1329 card->index);
1330 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1331 clear_bit(ATM_VF_ADDR, &vcc->flags);
1332 return -EINVAL;
1333 }
1334 }
1335
1336 if (n == 0) {
1337 printk
1338 ("nicstar%d: selected bandwidth < granularity.\n",
1339 card->index);
1340 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1341 clear_bit(ATM_VF_ADDR, &vcc->flags);
1342 return -EINVAL;
1343 }
1344
1345 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1346 PRINTK
1347 ("nicstar%d: not enough free CBR bandwidth.\n",
1348 card->index);
1349 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1350 clear_bit(ATM_VF_ADDR, &vcc->flags);
1351 return -EINVAL;
1352 } else
1353 card->tst_free_entries -= n;
1354
1355 XPRINTK("nicstar%d: writing %d tst entries.\n",
1356 card->index, n);
1357 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1358 if (card->scd2vc[frscdi] == NULL) {
1359 card->scd2vc[frscdi] = vc;
1360 break;
1361 }
1362 }
1363 if (frscdi == NS_FRSCD_NUM) {
1364 PRINTK
1365 ("nicstar%d: no SCD available for CBR channel.\n",
1366 card->index);
1367 card->tst_free_entries += n;
1368 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1369 clear_bit(ATM_VF_ADDR, &vcc->flags);
1370 return -EBUSY;
1371 }
1372
1373 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1374
1375 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1376 if (scq == NULL) {
1377 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1378 card->index);
1379 card->scd2vc[frscdi] = NULL;
1380 card->tst_free_entries += n;
1381 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1382 clear_bit(ATM_VF_ADDR, &vcc->flags);
1383 return -ENOMEM;
1384 }
1385 vc->scq = scq;
1386 u32d[0] = scq_virt_to_bus(scq, scq->base);
1387 u32d[1] = (u32) 0x00000000;
1388 u32d[2] = (u32) 0xffffffff;
1389 u32d[3] = (u32) 0x00000000;
1390 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1391
1392 fill_tst(card, n, vc);
1393 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1394 vc->cbr_scd = 0x00000000;
1395 vc->scq = card->scq0;
1396 }
1397
1398 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1399 vc->tx = 1;
1400 vc->tx_vcc = vcc;
1401 vc->tbd_count = 0;
1402 }
1403 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1404 u32 status;
1405
1406 vc->rx = 1;
1407 vc->rx_vcc = vcc;
1408 vc->rx_iov = NULL;
1409
1410 /* Open the connection in hardware */
1411 if (vcc->qos.aal == ATM_AAL5)
1412 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1413 else /* vcc->qos.aal == ATM_AAL0 */
1414 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1415#ifdef RCQ_SUPPORT
1416 status |= NS_RCTE_RAWCELLINTEN;
1417#endif /* RCQ_SUPPORT */
1418 ns_write_sram(card,
1419 NS_RCT +
1420 (vpi << card->vcibits | vci) *
1421 NS_RCT_ENTRY_SIZE, &status, 1);
1422 }
1423
1424 }
1425
1426 set_bit(ATM_VF_READY, &vcc->flags);
1427 return 0;
1428}
1429
1430static void ns_close(struct atm_vcc *vcc)
1431{
1432 vc_map *vc;
1433 ns_dev *card;
1434 u32 data;
1435 int i;
1436
1437 vc = vcc->dev_data;
1438 card = vcc->dev->dev_data;
1439 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1440 (int)vcc->vpi, vcc->vci);
1441
1442 clear_bit(ATM_VF_READY, &vcc->flags);
1443
1444 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1445 u32 addr;
1446 unsigned long flags;
1447
1448 addr =
1449 NS_RCT +
1450 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1451 spin_lock_irqsave(&card->res_lock, flags);
1452 while (CMD_BUSY(card)) ;
1453 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1454 card->membase + CMD);
1455 spin_unlock_irqrestore(&card->res_lock, flags);
1456
1457 vc->rx = 0;
1458 if (vc->rx_iov != NULL) {
1459 struct sk_buff *iovb;
1460 u32 stat;
1461
1462 stat = readl(card->membase + STAT);
1463 card->sbfqc = ns_stat_sfbqc_get(stat);
1464 card->lbfqc = ns_stat_lfbqc_get(stat);
1465
1466 PRINTK
1467 ("nicstar%d: closing a VC with pending rx buffers.\n",
1468 card->index);
1469 iovb = vc->rx_iov;
1470 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1471 NS_PRV_IOVCNT(iovb));
1472 NS_PRV_IOVCNT(iovb) = 0;
1473 spin_lock_irqsave(&card->int_lock, flags);
1474 recycle_iov_buf(card, iovb);
1475 spin_unlock_irqrestore(&card->int_lock, flags);
1476 vc->rx_iov = NULL;
1477 }
1478 }
1479
1480 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1481 vc->tx = 0;
1482 }
1483
1484 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1485 unsigned long flags;
1486 ns_scqe *scqep;
1487 scq_info *scq;
1488
1489 scq = vc->scq;
1490
1491 for (;;) {
1492 spin_lock_irqsave(&scq->lock, flags);
1493 scqep = scq->next;
1494 if (scqep == scq->base)
1495 scqep = scq->last;
1496 else
1497 scqep--;
1498 if (scqep == scq->tail) {
1499 spin_unlock_irqrestore(&scq->lock, flags);
1500 break;
1501 }
1502 /* If the last entry is not a TSR, place one in the SCQ in order to
1503 be able to completely drain it and then close. */
1504 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1505 ns_scqe tsr;
1506 u32 scdi, scqi;
1507 u32 data;
1508 int index;
1509
1510 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1511 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1512 scqi = scq->next - scq->base;
1513 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1514 tsr.word_3 = 0x00000000;
1515 tsr.word_4 = 0x00000000;
1516 *scq->next = tsr;
1517 index = (int)scqi;
1518 scq->skb[index] = NULL;
1519 if (scq->next == scq->last)
1520 scq->next = scq->base;
1521 else
1522 scq->next++;
1523 data = scq_virt_to_bus(scq, scq->next);
1524 ns_write_sram(card, scq->scd, &data, 1);
1525 }
1526 spin_unlock_irqrestore(&scq->lock, flags);
1527 schedule();
1528 }
1529
1530 /* Free all TST entries */
1531 data = NS_TST_OPCODE_VARIABLE;
1532 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1533 if (card->tste2vc[i] == vc) {
1534 ns_write_sram(card, card->tst_addr + i, &data,
1535 1);
1536 card->tste2vc[i] = NULL;
1537 card->tst_free_entries++;
1538 }
1539 }
1540
1541 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1542 free_scq(card, vc->scq, vcc);
1543 }
1544
1545 /* remove all references to vcc before deleting it */
1546 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1547 unsigned long flags;
1548 scq_info *scq = card->scq0;
1549
1550 spin_lock_irqsave(&scq->lock, flags);
1551
1552 for (i = 0; i < scq->num_entries; i++) {
1553 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1554 ATM_SKB(scq->skb[i])->vcc = NULL;
1555 atm_return(vcc, scq->skb[i]->truesize);
1556 PRINTK
1557 ("nicstar: deleted pending vcc mapping\n");
1558 }
1559 }
1560
1561 spin_unlock_irqrestore(&scq->lock, flags);
1562 }
1563
1564 vcc->dev_data = NULL;
1565 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1566 clear_bit(ATM_VF_ADDR, &vcc->flags);
1567
1568#ifdef RX_DEBUG
1569 {
1570 u32 stat, cfg;
1571 stat = readl(card->membase + STAT);
1572 cfg = readl(card->membase + CFG);
1573 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1574 printk
1575 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1576 card->tsq.base, card->tsq.next,
1577 card->tsq.last, readl(card->membase + TSQT));
1578 printk
1579 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1580 card->rsq.base, card->rsq.next,
1581 card->rsq.last, readl(card->membase + RSQT));
1582 printk("Empty free buffer queue interrupt %s \n",
1583 card->efbie ? "enabled" : "disabled");
1584 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1585 ns_stat_sfbqc_get(stat), card->sbpool.count,
1586 ns_stat_lfbqc_get(stat), card->lbpool.count);
1587 printk("hbpool.count = %d iovpool.count = %d \n",
1588 card->hbpool.count, card->iovpool.count);
1589 }
1590#endif /* RX_DEBUG */
1591}
1592
1593static void fill_tst(ns_dev * card, int n, vc_map * vc)
1594{
1595 u32 new_tst;
1596 unsigned long cl;
1597 int e, r;
1598 u32 data;
1599
1600 /* It would be very complicated to keep the two TSTs synchronized while
1601 assuring that writes are only made to the inactive TST. So, for now I
1602 will use only one TST. If problems occur, I will change this again */
1603
1604 new_tst = card->tst_addr;
1605
1606 /* Fill procedure */
1607
1608 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1609 if (card->tste2vc[e] == NULL)
1610 break;
1611 }
1612 if (e == NS_TST_NUM_ENTRIES) {
1613 printk("nicstar%d: No free TST entries found. \n", card->index);
1614 return;
1615 }
1616
1617 r = n;
1618 cl = NS_TST_NUM_ENTRIES;
1619 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1620
1621 while (r > 0) {
1622 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1623 card->tste2vc[e] = vc;
1624 ns_write_sram(card, new_tst + e, &data, 1);
1625 cl -= NS_TST_NUM_ENTRIES;
1626 r--;
1627 }
1628
1629 if (++e == NS_TST_NUM_ENTRIES) {
1630 e = 0;
1631 }
1632 cl += n;
1633 }
1634
1635 /* End of fill procedure */
1636
1637 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1638 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1639 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1640 card->tst_addr = new_tst;
1641}
1642
1643static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1644{
1645 ns_dev *card;
1646 vc_map *vc;
1647 scq_info *scq;
1648 unsigned long buflen;
1649 ns_scqe scqe;
1650 u32 flags; /* TBD flags, not CPU flags */
1651
1652 card = vcc->dev->dev_data;
1653 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1654 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1655 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1656 card->index);
1657 atomic_inc(&vcc->stats->tx_err);
1658 dev_kfree_skb_any(skb);
1659 return -EINVAL;
1660 }
1661
1662 if (!vc->tx) {
1663 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1664 card->index);
1665 atomic_inc(&vcc->stats->tx_err);
1666 dev_kfree_skb_any(skb);
1667 return -EINVAL;
1668 }
1669
1670 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1671 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1672 card->index);
1673 atomic_inc(&vcc->stats->tx_err);
1674 dev_kfree_skb_any(skb);
1675 return -EINVAL;
1676 }
1677
1678 if (skb_shinfo(skb)->nr_frags != 0) {
1679 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1680 atomic_inc(&vcc->stats->tx_err);
1681 dev_kfree_skb_any(skb);
1682 return -EINVAL;
1683 }
1684
1685 ATM_SKB(skb)->vcc = vcc;
1686
1687 NS_PRV_DMA(skb) = pci_map_single(card->pcidev, skb->data,
1688 skb->len, PCI_DMA_TODEVICE);
1689
1690 if (vcc->qos.aal == ATM_AAL5) {
1691 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1692 flags = NS_TBD_AAL5;
1693 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1694 scqe.word_3 = cpu_to_le32(skb->len);
1695 scqe.word_4 =
1696 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1697 ATM_SKB(skb)->
1698 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1699 flags |= NS_TBD_EOPDU;
1700 } else { /* (vcc->qos.aal == ATM_AAL0) */
1701
1702 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1703 flags = NS_TBD_AAL0;
1704 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1705 scqe.word_3 = cpu_to_le32(0x00000000);
1706 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1707 flags |= NS_TBD_EOPDU;
1708 scqe.word_4 =
1709 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1710 /* Force the VPI/VCI to be the same as in VCC struct */
1711 scqe.word_4 |=
1712 cpu_to_le32((((u32) vcc->
1713 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1714 vci) <<
1715 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1716 }
1717
1718 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1719 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1720 scq = ((vc_map *) vcc->dev_data)->scq;
1721 } else {
1722 scqe.word_1 =
1723 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1724 scq = card->scq0;
1725 }
1726
1727 if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
1728 atomic_inc(&vcc->stats->tx_err);
1729 dev_kfree_skb_any(skb);
1730 return -EIO;
1731 }
1732 atomic_inc(&vcc->stats->tx);
1733
1734 return 0;
1735}
1736
1737static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1738 struct sk_buff *skb)
1739{
1740 unsigned long flags;
1741 ns_scqe tsr;
1742 u32 scdi, scqi;
1743 int scq_is_vbr;
1744 u32 data;
1745 int index;
1746
1747 spin_lock_irqsave(&scq->lock, flags);
1748 while (scq->tail == scq->next) {
1749 if (in_interrupt()) {
1750 spin_unlock_irqrestore(&scq->lock, flags);
1751 printk("nicstar%d: Error pushing TBD.\n", card->index);
1752 return 1;
1753 }
1754
1755 scq->full = 1;
1756 spin_unlock_irqrestore(&scq->lock, flags);
1757 interruptible_sleep_on_timeout(&scq->scqfull_waitq,
1758 SCQFULL_TIMEOUT);
1759 spin_lock_irqsave(&scq->lock, flags);
1760
1761 if (scq->full) {
1762 spin_unlock_irqrestore(&scq->lock, flags);
1763 printk("nicstar%d: Timeout pushing TBD.\n",
1764 card->index);
1765 return 1;
1766 }
1767 }
1768 *scq->next = *tbd;
1769 index = (int)(scq->next - scq->base);
1770 scq->skb[index] = skb;
1771 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1772 card->index, skb, index);
1773 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1774 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1775 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1776 scq->next);
1777 if (scq->next == scq->last)
1778 scq->next = scq->base;
1779 else
1780 scq->next++;
1781
1782 vc->tbd_count++;
1783 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1784 scq->tbd_count++;
1785 scq_is_vbr = 1;
1786 } else
1787 scq_is_vbr = 0;
1788
1789 if (vc->tbd_count >= MAX_TBD_PER_VC
1790 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1791 int has_run = 0;
1792
1793 while (scq->tail == scq->next) {
1794 if (in_interrupt()) {
1795 data = scq_virt_to_bus(scq, scq->next);
1796 ns_write_sram(card, scq->scd, &data, 1);
1797 spin_unlock_irqrestore(&scq->lock, flags);
1798 printk("nicstar%d: Error pushing TSR.\n",
1799 card->index);
1800 return 0;
1801 }
1802
1803 scq->full = 1;
1804 if (has_run++)
1805 break;
1806 spin_unlock_irqrestore(&scq->lock, flags);
1807 interruptible_sleep_on_timeout(&scq->scqfull_waitq,
1808 SCQFULL_TIMEOUT);
1809 spin_lock_irqsave(&scq->lock, flags);
1810 }
1811
1812 if (!scq->full) {
1813 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1814 if (scq_is_vbr)
1815 scdi = NS_TSR_SCDISVBR;
1816 else
1817 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1818 scqi = scq->next - scq->base;
1819 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1820 tsr.word_3 = 0x00000000;
1821 tsr.word_4 = 0x00000000;
1822
1823 *scq->next = tsr;
1824 index = (int)scqi;
1825 scq->skb[index] = NULL;
1826 XPRINTK
1827 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1828 card->index, le32_to_cpu(tsr.word_1),
1829 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1830 le32_to_cpu(tsr.word_4), scq->next);
1831 if (scq->next == scq->last)
1832 scq->next = scq->base;
1833 else
1834 scq->next++;
1835 vc->tbd_count = 0;
1836 scq->tbd_count = 0;
1837 } else
1838 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1839 card->index);
1840 }
1841 data = scq_virt_to_bus(scq, scq->next);
1842 ns_write_sram(card, scq->scd, &data, 1);
1843
1844 spin_unlock_irqrestore(&scq->lock, flags);
1845
1846 return 0;
1847}
1848
1849static void process_tsq(ns_dev * card)
1850{
1851 u32 scdi;
1852 scq_info *scq;
1853 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1854 int serviced_entries; /* flag indicating at least on entry was serviced */
1855
1856 serviced_entries = 0;
1857
1858 if (card->tsq.next == card->tsq.last)
1859 one_ahead = card->tsq.base;
1860 else
1861 one_ahead = card->tsq.next + 1;
1862
1863 if (one_ahead == card->tsq.last)
1864 two_ahead = card->tsq.base;
1865 else
1866 two_ahead = one_ahead + 1;
1867
1868 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1869 !ns_tsi_isempty(two_ahead))
1870 /* At most two empty, as stated in the 77201 errata */
1871 {
1872 serviced_entries = 1;
1873
1874 /* Skip the one or two possible empty entries */
1875 while (ns_tsi_isempty(card->tsq.next)) {
1876 if (card->tsq.next == card->tsq.last)
1877 card->tsq.next = card->tsq.base;
1878 else
1879 card->tsq.next++;
1880 }
1881
1882 if (!ns_tsi_tmrof(card->tsq.next)) {
1883 scdi = ns_tsi_getscdindex(card->tsq.next);
1884 if (scdi == NS_TSI_SCDISVBR)
1885 scq = card->scq0;
1886 else {
1887 if (card->scd2vc[scdi] == NULL) {
1888 printk
1889 ("nicstar%d: could not find VC from SCD index.\n",
1890 card->index);
1891 ns_tsi_init(card->tsq.next);
1892 return;
1893 }
1894 scq = card->scd2vc[scdi]->scq;
1895 }
1896 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1897 scq->full = 0;
1898 wake_up_interruptible(&(scq->scqfull_waitq));
1899 }
1900
1901 ns_tsi_init(card->tsq.next);
1902 previous = card->tsq.next;
1903 if (card->tsq.next == card->tsq.last)
1904 card->tsq.next = card->tsq.base;
1905 else
1906 card->tsq.next++;
1907
1908 if (card->tsq.next == card->tsq.last)
1909 one_ahead = card->tsq.base;
1910 else
1911 one_ahead = card->tsq.next + 1;
1912
1913 if (one_ahead == card->tsq.last)
1914 two_ahead = card->tsq.base;
1915 else
1916 two_ahead = one_ahead + 1;
1917 }
1918
1919 if (serviced_entries)
1920 writel(PTR_DIFF(previous, card->tsq.base),
1921 card->membase + TSQH);
1922}
1923
1924static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1925{
1926 struct atm_vcc *vcc;
1927 struct sk_buff *skb;
1928 int i;
1929 unsigned long flags;
1930
1931 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1932 card->index, scq, pos);
1933 if (pos >= scq->num_entries) {
1934 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1935 return;
1936 }
1937
1938 spin_lock_irqsave(&scq->lock, flags);
1939 i = (int)(scq->tail - scq->base);
1940 if (++i == scq->num_entries)
1941 i = 0;
1942 while (i != pos) {
1943 skb = scq->skb[i];
1944 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1945 card->index, skb, i);
1946 if (skb != NULL) {
1947 pci_unmap_single(card->pcidev,
1948 NS_PRV_DMA(skb),
1949 skb->len,
1950 PCI_DMA_TODEVICE);
1951 vcc = ATM_SKB(skb)->vcc;
1952 if (vcc && vcc->pop != NULL) {
1953 vcc->pop(vcc, skb);
1954 } else {
1955 dev_kfree_skb_irq(skb);
1956 }
1957 scq->skb[i] = NULL;
1958 }
1959 if (++i == scq->num_entries)
1960 i = 0;
1961 }
1962 scq->tail = scq->base + pos;
1963 spin_unlock_irqrestore(&scq->lock, flags);
1964}
1965
1966static void process_rsq(ns_dev * card)
1967{
1968 ns_rsqe *previous;
1969
1970 if (!ns_rsqe_valid(card->rsq.next))
1971 return;
1972 do {
1973 dequeue_rx(card, card->rsq.next);
1974 ns_rsqe_init(card->rsq.next);
1975 previous = card->rsq.next;
1976 if (card->rsq.next == card->rsq.last)
1977 card->rsq.next = card->rsq.base;
1978 else
1979 card->rsq.next++;
1980 } while (ns_rsqe_valid(card->rsq.next));
1981 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1982}
1983
1984static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1985{
1986 u32 vpi, vci;
1987 vc_map *vc;
1988 struct sk_buff *iovb;
1989 struct iovec *iov;
1990 struct atm_vcc *vcc;
1991 struct sk_buff *skb;
1992 unsigned short aal5_len;
1993 int len;
1994 u32 stat;
1995 u32 id;
1996
1997 stat = readl(card->membase + STAT);
1998 card->sbfqc = ns_stat_sfbqc_get(stat);
1999 card->lbfqc = ns_stat_lfbqc_get(stat);
2000
2001 id = le32_to_cpu(rsqe->buffer_handle);
2002 skb = idr_find(&card->idr, id);
2003 if (!skb) {
2004 RXPRINTK(KERN_ERR
2005 "nicstar%d: idr_find() failed!\n", card->index);
2006 return;
2007 }
2008 idr_remove(&card->idr, id);
2009 pci_dma_sync_single_for_cpu(card->pcidev,
2010 NS_PRV_DMA(skb),
2011 (NS_PRV_BUFTYPE(skb) == BUF_SM
2012 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2013 PCI_DMA_FROMDEVICE);
2014 pci_unmap_single(card->pcidev,
2015 NS_PRV_DMA(skb),
2016 (NS_PRV_BUFTYPE(skb) == BUF_SM
2017 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2018 PCI_DMA_FROMDEVICE);
2019 vpi = ns_rsqe_vpi(rsqe);
2020 vci = ns_rsqe_vci(rsqe);
2021 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2022 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2023 card->index, vpi, vci);
2024 recycle_rx_buf(card, skb);
2025 return;
2026 }
2027
2028 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2029 if (!vc->rx) {
2030 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2031 card->index, vpi, vci);
2032 recycle_rx_buf(card, skb);
2033 return;
2034 }
2035
2036 vcc = vc->rx_vcc;
2037
2038 if (vcc->qos.aal == ATM_AAL0) {
2039 struct sk_buff *sb;
2040 unsigned char *cell;
2041 int i;
2042
2043 cell = skb->data;
2044 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2045 if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) {
2046 printk
2047 ("nicstar%d: Can't allocate buffers for aal0.\n",
2048 card->index);
2049 atomic_add(i, &vcc->stats->rx_drop);
2050 break;
2051 }
2052 if (!atm_charge(vcc, sb->truesize)) {
2053 RXPRINTK
2054 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2055 card->index);
2056 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2057 dev_kfree_skb_any(sb);
2058 break;
2059 }
2060 /* Rebuild the header */
2061 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2062 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2063 if (i == 1 && ns_rsqe_eopdu(rsqe))
2064 *((u32 *) sb->data) |= 0x00000002;
2065 skb_put(sb, NS_AAL0_HEADER);
2066 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2067 skb_put(sb, ATM_CELL_PAYLOAD);
2068 ATM_SKB(sb)->vcc = vcc;
2069 __net_timestamp(sb);
2070 vcc->push(vcc, sb);
2071 atomic_inc(&vcc->stats->rx);
2072 cell += ATM_CELL_PAYLOAD;
2073 }
2074
2075 recycle_rx_buf(card, skb);
2076 return;
2077 }
2078
2079 /* To reach this point, the AAL layer can only be AAL5 */
2080
2081 if ((iovb = vc->rx_iov) == NULL) {
2082 iovb = skb_dequeue(&(card->iovpool.queue));
2083 if (iovb == NULL) { /* No buffers in the queue */
2084 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2085 if (iovb == NULL) {
2086 printk("nicstar%d: Out of iovec buffers.\n",
2087 card->index);
2088 atomic_inc(&vcc->stats->rx_drop);
2089 recycle_rx_buf(card, skb);
2090 return;
2091 }
2092 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2093 } else if (--card->iovpool.count < card->iovnr.min) {
2094 struct sk_buff *new_iovb;
2095 if ((new_iovb =
2096 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2097 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2098 skb_queue_tail(&card->iovpool.queue, new_iovb);
2099 card->iovpool.count++;
2100 }
2101 }
2102 vc->rx_iov = iovb;
2103 NS_PRV_IOVCNT(iovb) = 0;
2104 iovb->len = 0;
2105 iovb->data = iovb->head;
2106 skb_reset_tail_pointer(iovb);
2107 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2108 buffer is stored as iovec base, NOT a pointer to the
2109 small or large buffer itself. */
2110 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2111 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2112 atomic_inc(&vcc->stats->rx_err);
2113 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2114 NS_MAX_IOVECS);
2115 NS_PRV_IOVCNT(iovb) = 0;
2116 iovb->len = 0;
2117 iovb->data = iovb->head;
2118 skb_reset_tail_pointer(iovb);
2119 }
2120 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2121 iov->iov_base = (void *)skb;
2122 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2123 iovb->len += iov->iov_len;
2124
2125#ifdef EXTRA_DEBUG
2126 if (NS_PRV_IOVCNT(iovb) == 1) {
2127 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2128 printk
2129 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2130 card->index);
2131 which_list(card, skb);
2132 atomic_inc(&vcc->stats->rx_err);
2133 recycle_rx_buf(card, skb);
2134 vc->rx_iov = NULL;
2135 recycle_iov_buf(card, iovb);
2136 return;
2137 }
2138 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2139
2140 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2141 printk
2142 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2143 card->index);
2144 which_list(card, skb);
2145 atomic_inc(&vcc->stats->rx_err);
2146 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2147 NS_PRV_IOVCNT(iovb));
2148 vc->rx_iov = NULL;
2149 recycle_iov_buf(card, iovb);
2150 return;
2151 }
2152 }
2153#endif /* EXTRA_DEBUG */
2154
2155 if (ns_rsqe_eopdu(rsqe)) {
2156 /* This works correctly regardless of the endianness of the host */
2157 unsigned char *L1L2 = (unsigned char *)
2158 (skb->data + iov->iov_len - 6);
2159 aal5_len = L1L2[0] << 8 | L1L2[1];
2160 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2161 if (ns_rsqe_crcerr(rsqe) ||
2162 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2163 printk("nicstar%d: AAL5 CRC error", card->index);
2164 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2165 printk(" - PDU size mismatch.\n");
2166 else
2167 printk(".\n");
2168 atomic_inc(&vcc->stats->rx_err);
2169 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2170 NS_PRV_IOVCNT(iovb));
2171 vc->rx_iov = NULL;
2172 recycle_iov_buf(card, iovb);
2173 return;
2174 }
2175
2176 /* By this point we (hopefully) have a complete SDU without errors. */
2177
2178 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2179 /* skb points to a small buffer */
2180 if (!atm_charge(vcc, skb->truesize)) {
2181 push_rxbufs(card, skb);
2182 atomic_inc(&vcc->stats->rx_drop);
2183 } else {
2184 skb_put(skb, len);
2185 dequeue_sm_buf(card, skb);
2186#ifdef NS_USE_DESTRUCTORS
2187 skb->destructor = ns_sb_destructor;
2188#endif /* NS_USE_DESTRUCTORS */
2189 ATM_SKB(skb)->vcc = vcc;
2190 __net_timestamp(skb);
2191 vcc->push(vcc, skb);
2192 atomic_inc(&vcc->stats->rx);
2193 }
2194 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2195 struct sk_buff *sb;
2196
2197 sb = (struct sk_buff *)(iov - 1)->iov_base;
2198 /* skb points to a large buffer */
2199
2200 if (len <= NS_SMBUFSIZE) {
2201 if (!atm_charge(vcc, sb->truesize)) {
2202 push_rxbufs(card, sb);
2203 atomic_inc(&vcc->stats->rx_drop);
2204 } else {
2205 skb_put(sb, len);
2206 dequeue_sm_buf(card, sb);
2207#ifdef NS_USE_DESTRUCTORS
2208 sb->destructor = ns_sb_destructor;
2209#endif /* NS_USE_DESTRUCTORS */
2210 ATM_SKB(sb)->vcc = vcc;
2211 __net_timestamp(sb);
2212 vcc->push(vcc, sb);
2213 atomic_inc(&vcc->stats->rx);
2214 }
2215
2216 push_rxbufs(card, skb);
2217
2218 } else { /* len > NS_SMBUFSIZE, the usual case */
2219
2220 if (!atm_charge(vcc, skb->truesize)) {
2221 push_rxbufs(card, skb);
2222 atomic_inc(&vcc->stats->rx_drop);
2223 } else {
2224 dequeue_lg_buf(card, skb);
2225#ifdef NS_USE_DESTRUCTORS
2226 skb->destructor = ns_lb_destructor;
2227#endif /* NS_USE_DESTRUCTORS */
2228 skb_push(skb, NS_SMBUFSIZE);
2229 skb_copy_from_linear_data(sb, skb->data,
2230 NS_SMBUFSIZE);
2231 skb_put(skb, len - NS_SMBUFSIZE);
2232 ATM_SKB(skb)->vcc = vcc;
2233 __net_timestamp(skb);
2234 vcc->push(vcc, skb);
2235 atomic_inc(&vcc->stats->rx);
2236 }
2237
2238 push_rxbufs(card, sb);
2239
2240 }
2241
2242 } else { /* Must push a huge buffer */
2243
2244 struct sk_buff *hb, *sb, *lb;
2245 int remaining, tocopy;
2246 int j;
2247
2248 hb = skb_dequeue(&(card->hbpool.queue));
2249 if (hb == NULL) { /* No buffers in the queue */
2250
2251 hb = dev_alloc_skb(NS_HBUFSIZE);
2252 if (hb == NULL) {
2253 printk
2254 ("nicstar%d: Out of huge buffers.\n",
2255 card->index);
2256 atomic_inc(&vcc->stats->rx_drop);
2257 recycle_iovec_rx_bufs(card,
2258 (struct iovec *)
2259 iovb->data,
2260 NS_PRV_IOVCNT(iovb));
2261 vc->rx_iov = NULL;
2262 recycle_iov_buf(card, iovb);
2263 return;
2264 } else if (card->hbpool.count < card->hbnr.min) {
2265 struct sk_buff *new_hb;
2266 if ((new_hb =
2267 dev_alloc_skb(NS_HBUFSIZE)) !=
2268 NULL) {
2269 skb_queue_tail(&card->hbpool.
2270 queue, new_hb);
2271 card->hbpool.count++;
2272 }
2273 }
2274 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2275 } else if (--card->hbpool.count < card->hbnr.min) {
2276 struct sk_buff *new_hb;
2277 if ((new_hb =
2278 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2279 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2280 skb_queue_tail(&card->hbpool.queue,
2281 new_hb);
2282 card->hbpool.count++;
2283 }
2284 if (card->hbpool.count < card->hbnr.min) {
2285 if ((new_hb =
2286 dev_alloc_skb(NS_HBUFSIZE)) !=
2287 NULL) {
2288 NS_PRV_BUFTYPE(new_hb) =
2289 BUF_NONE;
2290 skb_queue_tail(&card->hbpool.
2291 queue, new_hb);
2292 card->hbpool.count++;
2293 }
2294 }
2295 }
2296
2297 iov = (struct iovec *)iovb->data;
2298
2299 if (!atm_charge(vcc, hb->truesize)) {
2300 recycle_iovec_rx_bufs(card, iov,
2301 NS_PRV_IOVCNT(iovb));
2302 if (card->hbpool.count < card->hbnr.max) {
2303 skb_queue_tail(&card->hbpool.queue, hb);
2304 card->hbpool.count++;
2305 } else
2306 dev_kfree_skb_any(hb);
2307 atomic_inc(&vcc->stats->rx_drop);
2308 } else {
2309 /* Copy the small buffer to the huge buffer */
2310 sb = (struct sk_buff *)iov->iov_base;
2311 skb_copy_from_linear_data(sb, hb->data,
2312 iov->iov_len);
2313 skb_put(hb, iov->iov_len);
2314 remaining = len - iov->iov_len;
2315 iov++;
2316 /* Free the small buffer */
2317 push_rxbufs(card, sb);
2318
2319 /* Copy all large buffers to the huge buffer and free them */
2320 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2321 lb = (struct sk_buff *)iov->iov_base;
2322 tocopy =
2323 min_t(int, remaining, iov->iov_len);
2324 skb_copy_from_linear_data(lb,
2325 skb_tail_pointer
2326 (hb), tocopy);
2327 skb_put(hb, tocopy);
2328 iov++;
2329 remaining -= tocopy;
2330 push_rxbufs(card, lb);
2331 }
2332#ifdef EXTRA_DEBUG
2333 if (remaining != 0 || hb->len != len)
2334 printk
2335 ("nicstar%d: Huge buffer len mismatch.\n",
2336 card->index);
2337#endif /* EXTRA_DEBUG */
2338 ATM_SKB(hb)->vcc = vcc;
2339#ifdef NS_USE_DESTRUCTORS
2340 hb->destructor = ns_hb_destructor;
2341#endif /* NS_USE_DESTRUCTORS */
2342 __net_timestamp(hb);
2343 vcc->push(vcc, hb);
2344 atomic_inc(&vcc->stats->rx);
2345 }
2346 }
2347
2348 vc->rx_iov = NULL;
2349 recycle_iov_buf(card, iovb);
2350 }
2351
2352}
2353
2354#ifdef NS_USE_DESTRUCTORS
2355
2356static void ns_sb_destructor(struct sk_buff *sb)
2357{
2358 ns_dev *card;
2359 u32 stat;
2360
2361 card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data;
2362 stat = readl(card->membase + STAT);
2363 card->sbfqc = ns_stat_sfbqc_get(stat);
2364 card->lbfqc = ns_stat_lfbqc_get(stat);
2365
2366 do {
2367 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2368 if (sb == NULL)
2369 break;
2370 NS_PRV_BUFTYPE(sb) = BUF_SM;
2371 skb_queue_tail(&card->sbpool.queue, sb);
2372 skb_reserve(sb, NS_AAL0_HEADER);
2373 push_rxbufs(card, sb);
2374 } while (card->sbfqc < card->sbnr.min);
2375}
2376
2377static void ns_lb_destructor(struct sk_buff *lb)
2378{
2379 ns_dev *card;
2380 u32 stat;
2381
2382 card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data;
2383 stat = readl(card->membase + STAT);
2384 card->sbfqc = ns_stat_sfbqc_get(stat);
2385 card->lbfqc = ns_stat_lfbqc_get(stat);
2386
2387 do {
2388 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2389 if (lb == NULL)
2390 break;
2391 NS_PRV_BUFTYPE(lb) = BUF_LG;
2392 skb_queue_tail(&card->lbpool.queue, lb);
2393 skb_reserve(lb, NS_SMBUFSIZE);
2394 push_rxbufs(card, lb);
2395 } while (card->lbfqc < card->lbnr.min);
2396}
2397
2398static void ns_hb_destructor(struct sk_buff *hb)
2399{
2400 ns_dev *card;
2401
2402 card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data;
2403
2404 while (card->hbpool.count < card->hbnr.init) {
2405 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2406 if (hb == NULL)
2407 break;
2408 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2409 skb_queue_tail(&card->hbpool.queue, hb);
2410 card->hbpool.count++;
2411 }
2412}
2413
2414#endif /* NS_USE_DESTRUCTORS */
2415
2416static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2417{
2418 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2419 printk("nicstar%d: What kind of rx buffer is this?\n",
2420 card->index);
2421 dev_kfree_skb_any(skb);
2422 } else
2423 push_rxbufs(card, skb);
2424}
2425
2426static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2427{
2428 while (count-- > 0)
2429 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2430}
2431
2432static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2433{
2434 if (card->iovpool.count < card->iovnr.max) {
2435 skb_queue_tail(&card->iovpool.queue, iovb);
2436 card->iovpool.count++;
2437 } else
2438 dev_kfree_skb_any(iovb);
2439}
2440
2441static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2442{
2443 skb_unlink(sb, &card->sbpool.queue);
2444#ifdef NS_USE_DESTRUCTORS
2445 if (card->sbfqc < card->sbnr.min)
2446#else
2447 if (card->sbfqc < card->sbnr.init) {
2448 struct sk_buff *new_sb;
2449 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2450 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2451 skb_queue_tail(&card->sbpool.queue, new_sb);
2452 skb_reserve(new_sb, NS_AAL0_HEADER);
2453 push_rxbufs(card, new_sb);
2454 }
2455 }
2456 if (card->sbfqc < card->sbnr.init)
2457#endif /* NS_USE_DESTRUCTORS */
2458 {
2459 struct sk_buff *new_sb;
2460 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2461 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2462 skb_queue_tail(&card->sbpool.queue, new_sb);
2463 skb_reserve(new_sb, NS_AAL0_HEADER);
2464 push_rxbufs(card, new_sb);
2465 }
2466 }
2467}
2468
2469static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2470{
2471 skb_unlink(lb, &card->lbpool.queue);
2472#ifdef NS_USE_DESTRUCTORS
2473 if (card->lbfqc < card->lbnr.min)
2474#else
2475 if (card->lbfqc < card->lbnr.init) {
2476 struct sk_buff *new_lb;
2477 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2478 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2479 skb_queue_tail(&card->lbpool.queue, new_lb);
2480 skb_reserve(new_lb, NS_SMBUFSIZE);
2481 push_rxbufs(card, new_lb);
2482 }
2483 }
2484 if (card->lbfqc < card->lbnr.init)
2485#endif /* NS_USE_DESTRUCTORS */
2486 {
2487 struct sk_buff *new_lb;
2488 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2489 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2490 skb_queue_tail(&card->lbpool.queue, new_lb);
2491 skb_reserve(new_lb, NS_SMBUFSIZE);
2492 push_rxbufs(card, new_lb);
2493 }
2494 }
2495}
2496
2497static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2498{
2499 u32 stat;
2500 ns_dev *card;
2501 int left;
2502
2503 left = (int)*pos;
2504 card = (ns_dev *) dev->dev_data;
2505 stat = readl(card->membase + STAT);
2506 if (!left--)
2507 return sprintf(page, "Pool count min init max \n");
2508 if (!left--)
2509 return sprintf(page, "Small %5d %5d %5d %5d \n",
2510 ns_stat_sfbqc_get(stat), card->sbnr.min,
2511 card->sbnr.init, card->sbnr.max);
2512 if (!left--)
2513 return sprintf(page, "Large %5d %5d %5d %5d \n",
2514 ns_stat_lfbqc_get(stat), card->lbnr.min,
2515 card->lbnr.init, card->lbnr.max);
2516 if (!left--)
2517 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2518 card->hbpool.count, card->hbnr.min,
2519 card->hbnr.init, card->hbnr.max);
2520 if (!left--)
2521 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2522 card->iovpool.count, card->iovnr.min,
2523 card->iovnr.init, card->iovnr.max);
2524 if (!left--) {
2525 int retval;
2526 retval =
2527 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2528 card->intcnt = 0;
2529 return retval;
2530 }
2531#if 0
2532 /* Dump 25.6 Mbps PHY registers */
2533 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2534 here just in case it's needed for debugging. */
2535 if (card->max_pcr == ATM_25_PCR && !left--) {
2536 u32 phy_regs[4];
2537 u32 i;
2538
2539 for (i = 0; i < 4; i++) {
2540 while (CMD_BUSY(card)) ;
2541 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2542 card->membase + CMD);
2543 while (CMD_BUSY(card)) ;
2544 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2545 }
2546
2547 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2548 phy_regs[0], phy_regs[1], phy_regs[2],
2549 phy_regs[3]);
2550 }
2551#endif /* 0 - Dump 25.6 Mbps PHY registers */
2552#if 0
2553 /* Dump TST */
2554 if (left-- < NS_TST_NUM_ENTRIES) {
2555 if (card->tste2vc[left + 1] == NULL)
2556 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2557 else
2558 return sprintf(page, "%5d - %d %d \n", left + 1,
2559 card->tste2vc[left + 1]->tx_vcc->vpi,
2560 card->tste2vc[left + 1]->tx_vcc->vci);
2561 }
2562#endif /* 0 */
2563 return 0;
2564}
2565
2566static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2567{
2568 ns_dev *card;
2569 pool_levels pl;
2570 long btype;
2571 unsigned long flags;
2572
2573 card = dev->dev_data;
2574 switch (cmd) {
2575 case NS_GETPSTAT:
2576 if (get_user
2577 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2578 return -EFAULT;
2579 switch (pl.buftype) {
2580 case NS_BUFTYPE_SMALL:
2581 pl.count =
2582 ns_stat_sfbqc_get(readl(card->membase + STAT));
2583 pl.level.min = card->sbnr.min;
2584 pl.level.init = card->sbnr.init;
2585 pl.level.max = card->sbnr.max;
2586 break;
2587
2588 case NS_BUFTYPE_LARGE:
2589 pl.count =
2590 ns_stat_lfbqc_get(readl(card->membase + STAT));
2591 pl.level.min = card->lbnr.min;
2592 pl.level.init = card->lbnr.init;
2593 pl.level.max = card->lbnr.max;
2594 break;
2595
2596 case NS_BUFTYPE_HUGE:
2597 pl.count = card->hbpool.count;
2598 pl.level.min = card->hbnr.min;
2599 pl.level.init = card->hbnr.init;
2600 pl.level.max = card->hbnr.max;
2601 break;
2602
2603 case NS_BUFTYPE_IOVEC:
2604 pl.count = card->iovpool.count;
2605 pl.level.min = card->iovnr.min;
2606 pl.level.init = card->iovnr.init;
2607 pl.level.max = card->iovnr.max;
2608 break;
2609
2610 default:
2611 return -ENOIOCTLCMD;
2612
2613 }
2614 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2615 return (sizeof(pl));
2616 else
2617 return -EFAULT;
2618
2619 case NS_SETBUFLEV:
2620 if (!capable(CAP_NET_ADMIN))
2621 return -EPERM;
2622 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2623 return -EFAULT;
2624 if (pl.level.min >= pl.level.init
2625 || pl.level.init >= pl.level.max)
2626 return -EINVAL;
2627 if (pl.level.min == 0)
2628 return -EINVAL;
2629 switch (pl.buftype) {
2630 case NS_BUFTYPE_SMALL:
2631 if (pl.level.max > TOP_SB)
2632 return -EINVAL;
2633 card->sbnr.min = pl.level.min;
2634 card->sbnr.init = pl.level.init;
2635 card->sbnr.max = pl.level.max;
2636 break;
2637
2638 case NS_BUFTYPE_LARGE:
2639 if (pl.level.max > TOP_LB)
2640 return -EINVAL;
2641 card->lbnr.min = pl.level.min;
2642 card->lbnr.init = pl.level.init;
2643 card->lbnr.max = pl.level.max;
2644 break;
2645
2646 case NS_BUFTYPE_HUGE:
2647 if (pl.level.max > TOP_HB)
2648 return -EINVAL;
2649 card->hbnr.min = pl.level.min;
2650 card->hbnr.init = pl.level.init;
2651 card->hbnr.max = pl.level.max;
2652 break;
2653
2654 case NS_BUFTYPE_IOVEC:
2655 if (pl.level.max > TOP_IOVB)
2656 return -EINVAL;
2657 card->iovnr.min = pl.level.min;
2658 card->iovnr.init = pl.level.init;
2659 card->iovnr.max = pl.level.max;
2660 break;
2661
2662 default:
2663 return -EINVAL;
2664
2665 }
2666 return 0;
2667
2668 case NS_ADJBUFLEV:
2669 if (!capable(CAP_NET_ADMIN))
2670 return -EPERM;
2671 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2672 switch (btype) {
2673 case NS_BUFTYPE_SMALL:
2674 while (card->sbfqc < card->sbnr.init) {
2675 struct sk_buff *sb;
2676
2677 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2678 if (sb == NULL)
2679 return -ENOMEM;
2680 NS_PRV_BUFTYPE(sb) = BUF_SM;
2681 skb_queue_tail(&card->sbpool.queue, sb);
2682 skb_reserve(sb, NS_AAL0_HEADER);
2683 push_rxbufs(card, sb);
2684 }
2685 break;
2686
2687 case NS_BUFTYPE_LARGE:
2688 while (card->lbfqc < card->lbnr.init) {
2689 struct sk_buff *lb;
2690
2691 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2692 if (lb == NULL)
2693 return -ENOMEM;
2694 NS_PRV_BUFTYPE(lb) = BUF_LG;
2695 skb_queue_tail(&card->lbpool.queue, lb);
2696 skb_reserve(lb, NS_SMBUFSIZE);
2697 push_rxbufs(card, lb);
2698 }
2699 break;
2700
2701 case NS_BUFTYPE_HUGE:
2702 while (card->hbpool.count > card->hbnr.init) {
2703 struct sk_buff *hb;
2704
2705 spin_lock_irqsave(&card->int_lock, flags);
2706 hb = skb_dequeue(&card->hbpool.queue);
2707 card->hbpool.count--;
2708 spin_unlock_irqrestore(&card->int_lock, flags);
2709 if (hb == NULL)
2710 printk
2711 ("nicstar%d: huge buffer count inconsistent.\n",
2712 card->index);
2713 else
2714 dev_kfree_skb_any(hb);
2715
2716 }
2717 while (card->hbpool.count < card->hbnr.init) {
2718 struct sk_buff *hb;
2719
2720 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2721 if (hb == NULL)
2722 return -ENOMEM;
2723 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2724 spin_lock_irqsave(&card->int_lock, flags);
2725 skb_queue_tail(&card->hbpool.queue, hb);
2726 card->hbpool.count++;
2727 spin_unlock_irqrestore(&card->int_lock, flags);
2728 }
2729 break;
2730
2731 case NS_BUFTYPE_IOVEC:
2732 while (card->iovpool.count > card->iovnr.init) {
2733 struct sk_buff *iovb;
2734
2735 spin_lock_irqsave(&card->int_lock, flags);
2736 iovb = skb_dequeue(&card->iovpool.queue);
2737 card->iovpool.count--;
2738 spin_unlock_irqrestore(&card->int_lock, flags);
2739 if (iovb == NULL)
2740 printk
2741 ("nicstar%d: iovec buffer count inconsistent.\n",
2742 card->index);
2743 else
2744 dev_kfree_skb_any(iovb);
2745
2746 }
2747 while (card->iovpool.count < card->iovnr.init) {
2748 struct sk_buff *iovb;
2749
2750 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2751 if (iovb == NULL)
2752 return -ENOMEM;
2753 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2754 spin_lock_irqsave(&card->int_lock, flags);
2755 skb_queue_tail(&card->iovpool.queue, iovb);
2756 card->iovpool.count++;
2757 spin_unlock_irqrestore(&card->int_lock, flags);
2758 }
2759 break;
2760
2761 default:
2762 return -EINVAL;
2763
2764 }
2765 return 0;
2766
2767 default:
2768 if (dev->phy && dev->phy->ioctl) {
2769 return dev->phy->ioctl(dev, cmd, arg);
2770 } else {
2771 printk("nicstar%d: %s == NULL \n", card->index,
2772 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2773 return -ENOIOCTLCMD;
2774 }
2775 }
2776}
2777
2778#ifdef EXTRA_DEBUG
2779static void which_list(ns_dev * card, struct sk_buff *skb)
2780{
2781 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2782}
2783#endif /* EXTRA_DEBUG */
2784
2785static void ns_poll(unsigned long arg)
2786{
2787 int i;
2788 ns_dev *card;
2789 unsigned long flags;
2790 u32 stat_r, stat_w;
2791
2792 PRINTK("nicstar: Entering ns_poll().\n");
2793 for (i = 0; i < num_cards; i++) {
2794 card = cards[i];
2795 if (spin_is_locked(&card->int_lock)) {
2796 /* Probably it isn't worth spinning */
2797 continue;
2798 }
2799 spin_lock_irqsave(&card->int_lock, flags);
2800
2801 stat_w = 0;
2802 stat_r = readl(card->membase + STAT);
2803 if (stat_r & NS_STAT_TSIF)
2804 stat_w |= NS_STAT_TSIF;
2805 if (stat_r & NS_STAT_EOPDU)
2806 stat_w |= NS_STAT_EOPDU;
2807
2808 process_tsq(card);
2809 process_rsq(card);
2810
2811 writel(stat_w, card->membase + STAT);
2812 spin_unlock_irqrestore(&card->int_lock, flags);
2813 }
2814 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2815 PRINTK("nicstar: Leaving ns_poll().\n");
2816}
2817
2818static int ns_parse_mac(char *mac, unsigned char *esi)
2819{
2820 int i, j;
2821 short byte1, byte0;
2822
2823 if (mac == NULL || esi == NULL)
2824 return -1;
2825 j = 0;
2826 for (i = 0; i < 6; i++) {
2827 if ((byte1 = hex_to_bin(mac[j++])) < 0)
2828 return -1;
2829 if ((byte0 = hex_to_bin(mac[j++])) < 0)
2830 return -1;
2831 esi[i] = (unsigned char)(byte1 * 16 + byte0);
2832 if (i < 5) {
2833 if (mac[j++] != ':')
2834 return -1;
2835 }
2836 }
2837 return 0;
2838}
2839
2840
2841static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2842 unsigned long addr)
2843{
2844 ns_dev *card;
2845 unsigned long flags;
2846
2847 card = dev->dev_data;
2848 spin_lock_irqsave(&card->res_lock, flags);
2849 while (CMD_BUSY(card)) ;
2850 writel((u32) value, card->membase + DR0);
2851 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2852 card->membase + CMD);
2853 spin_unlock_irqrestore(&card->res_lock, flags);
2854}
2855
2856static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2857{
2858 ns_dev *card;
2859 unsigned long flags;
2860 u32 data;
2861
2862 card = dev->dev_data;
2863 spin_lock_irqsave(&card->res_lock, flags);
2864 while (CMD_BUSY(card)) ;
2865 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2866 card->membase + CMD);
2867 while (CMD_BUSY(card)) ;
2868 data = readl(card->membase + DR0) & 0x000000FF;
2869 spin_unlock_irqrestore(&card->res_lock, flags);
2870 return (unsigned char)data;
2871}
2872
2873module_init(nicstar_init);
2874module_exit(nicstar_cleanup);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 */
20
21/*
22 * IMPORTANT INFORMATION
23 *
24 * There are currently three types of spinlocks:
25 *
26 * 1 - Per card interrupt spinlock (to protect structures and such)
27 * 2 - Per SCQ scq spinlock
28 * 3 - Per card resource spinlock (to access registers, etc.)
29 *
30 * These must NEVER be grabbed in reverse order.
31 *
32 */
33
34/* Header files */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/skbuff.h>
39#include <linux/atmdev.h>
40#include <linux/atm.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/types.h>
44#include <linux/string.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/timer.h>
49#include <linux/interrupt.h>
50#include <linux/bitops.h>
51#include <linux/slab.h>
52#include <linux/idr.h>
53#include <asm/io.h>
54#include <linux/uaccess.h>
55#include <linux/atomic.h>
56#include <linux/etherdevice.h>
57#include "nicstar.h"
58#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59#include "suni.h"
60#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62#include "idt77105.h"
63#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65/* Additional code */
66
67#include "nicstarmac.c"
68
69/* Configurable parameters */
70
71#undef PHY_LOOPBACK
72#undef TX_DEBUG
73#undef RX_DEBUG
74#undef GENERAL_DEBUG
75#undef EXTRA_DEBUG
76
77/* Do not touch these */
78
79#ifdef TX_DEBUG
80#define TXPRINTK(args...) printk(args)
81#else
82#define TXPRINTK(args...)
83#endif /* TX_DEBUG */
84
85#ifdef RX_DEBUG
86#define RXPRINTK(args...) printk(args)
87#else
88#define RXPRINTK(args...)
89#endif /* RX_DEBUG */
90
91#ifdef GENERAL_DEBUG
92#define PRINTK(args...) printk(args)
93#else
94#define PRINTK(args...) do {} while (0)
95#endif /* GENERAL_DEBUG */
96
97#ifdef EXTRA_DEBUG
98#define XPRINTK(args...) printk(args)
99#else
100#define XPRINTK(args...)
101#endif /* EXTRA_DEBUG */
102
103/* Macros */
104
105#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107#define NS_DELAY mdelay(1)
108
109#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111#ifndef ATM_SKB
112#define ATM_SKB(s) (&(s)->atm)
113#endif
114
115#define scq_virt_to_bus(scq, p) \
116 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118/* Function declarations */
119
120static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122 int count);
123static int ns_init_card(int i, struct pci_dev *pcidev);
124static void ns_init_card_error(ns_dev * card, int error);
125static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127static void push_rxbufs(ns_dev *, struct sk_buff *);
128static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129static int ns_open(struct atm_vcc *vcc);
130static void ns_close(struct atm_vcc *vcc);
131static void fill_tst(ns_dev * card, int n, vc_map * vc);
132static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb);
134static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
135 struct sk_buff *skb, bool may_sleep);
136static void process_tsq(ns_dev * card);
137static void drain_scq(ns_dev * card, scq_info * scq, int pos);
138static void process_rsq(ns_dev * card);
139static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
140static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
141static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
142static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
143static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
144static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
145static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
146static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
147#ifdef EXTRA_DEBUG
148static void which_list(ns_dev * card, struct sk_buff *skb);
149#endif
150static void ns_poll(struct timer_list *unused);
151static void ns_phy_put(struct atm_dev *dev, unsigned char value,
152 unsigned long addr);
153static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
154
155/* Global variables */
156
157static struct ns_dev *cards[NS_MAX_CARDS];
158static unsigned num_cards;
159static const struct atmdev_ops atm_ops = {
160 .open = ns_open,
161 .close = ns_close,
162 .ioctl = ns_ioctl,
163 .send = ns_send,
164 .send_bh = ns_send_bh,
165 .phy_put = ns_phy_put,
166 .phy_get = ns_phy_get,
167 .proc_read = ns_proc_read,
168 .owner = THIS_MODULE,
169};
170
171static struct timer_list ns_timer;
172static char *mac[NS_MAX_CARDS];
173module_param_array(mac, charp, NULL, 0);
174MODULE_LICENSE("GPL");
175
176/* Functions */
177
178static int nicstar_init_one(struct pci_dev *pcidev,
179 const struct pci_device_id *ent)
180{
181 static int index = -1;
182 unsigned int error;
183
184 index++;
185 cards[index] = NULL;
186
187 error = ns_init_card(index, pcidev);
188 if (error) {
189 cards[index--] = NULL; /* don't increment index */
190 goto err_out;
191 }
192
193 return 0;
194err_out:
195 return -ENODEV;
196}
197
198static void nicstar_remove_one(struct pci_dev *pcidev)
199{
200 int i, j;
201 ns_dev *card = pci_get_drvdata(pcidev);
202 struct sk_buff *hb;
203 struct sk_buff *iovb;
204 struct sk_buff *lb;
205 struct sk_buff *sb;
206
207 i = card->index;
208
209 if (cards[i] == NULL)
210 return;
211
212 if (card->atmdev->phy && card->atmdev->phy->stop)
213 card->atmdev->phy->stop(card->atmdev);
214
215 /* Stop everything */
216 writel(0x00000000, card->membase + CFG);
217
218 /* De-register device */
219 atm_dev_deregister(card->atmdev);
220
221 /* Disable PCI device */
222 pci_disable_device(pcidev);
223
224 /* Free up resources */
225 j = 0;
226 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
227 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
228 dev_kfree_skb_any(hb);
229 j++;
230 }
231 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
232 j = 0;
233 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
234 card->iovpool.count);
235 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
236 dev_kfree_skb_any(iovb);
237 j++;
238 }
239 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
240 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
241 dev_kfree_skb_any(lb);
242 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
243 dev_kfree_skb_any(sb);
244 free_scq(card, card->scq0, NULL);
245 for (j = 0; j < NS_FRSCD_NUM; j++) {
246 if (card->scd2vc[j] != NULL)
247 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
248 }
249 idr_destroy(&card->idr);
250 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
251 card->rsq.org, card->rsq.dma);
252 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
253 card->tsq.org, card->tsq.dma);
254 free_irq(card->pcidev->irq, card);
255 iounmap(card->membase);
256 kfree(card);
257}
258
259static const struct pci_device_id nicstar_pci_tbl[] = {
260 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
261 {0,} /* terminate list */
262};
263
264MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
265
266static struct pci_driver nicstar_driver = {
267 .name = "nicstar",
268 .id_table = nicstar_pci_tbl,
269 .probe = nicstar_init_one,
270 .remove = nicstar_remove_one,
271};
272
273static int __init nicstar_init(void)
274{
275 unsigned error = 0; /* Initialized to remove compile warning */
276
277 XPRINTK("nicstar: nicstar_init() called.\n");
278
279 error = pci_register_driver(&nicstar_driver);
280
281 TXPRINTK("nicstar: TX debug enabled.\n");
282 RXPRINTK("nicstar: RX debug enabled.\n");
283 PRINTK("nicstar: General debug enabled.\n");
284#ifdef PHY_LOOPBACK
285 printk("nicstar: using PHY loopback.\n");
286#endif /* PHY_LOOPBACK */
287 XPRINTK("nicstar: nicstar_init() returned.\n");
288
289 if (!error) {
290 timer_setup(&ns_timer, ns_poll, 0);
291 ns_timer.expires = jiffies + NS_POLL_PERIOD;
292 add_timer(&ns_timer);
293 }
294
295 return error;
296}
297
298static void __exit nicstar_cleanup(void)
299{
300 XPRINTK("nicstar: nicstar_cleanup() called.\n");
301
302 del_timer_sync(&ns_timer);
303
304 pci_unregister_driver(&nicstar_driver);
305
306 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
307}
308
309static u32 ns_read_sram(ns_dev * card, u32 sram_address)
310{
311 unsigned long flags;
312 u32 data;
313 sram_address <<= 2;
314 sram_address &= 0x0007FFFC; /* address must be dword aligned */
315 sram_address |= 0x50000000; /* SRAM read command */
316 spin_lock_irqsave(&card->res_lock, flags);
317 while (CMD_BUSY(card)) ;
318 writel(sram_address, card->membase + CMD);
319 while (CMD_BUSY(card)) ;
320 data = readl(card->membase + DR0);
321 spin_unlock_irqrestore(&card->res_lock, flags);
322 return data;
323}
324
325static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
326 int count)
327{
328 unsigned long flags;
329 int i, c;
330 count--; /* count range now is 0..3 instead of 1..4 */
331 c = count;
332 c <<= 2; /* to use increments of 4 */
333 spin_lock_irqsave(&card->res_lock, flags);
334 while (CMD_BUSY(card)) ;
335 for (i = 0; i <= c; i += 4)
336 writel(*(value++), card->membase + i);
337 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
338 so card->membase + DR0 == card->membase */
339 sram_address <<= 2;
340 sram_address &= 0x0007FFFC;
341 sram_address |= (0x40000000 | count);
342 writel(sram_address, card->membase + CMD);
343 spin_unlock_irqrestore(&card->res_lock, flags);
344}
345
346static int ns_init_card(int i, struct pci_dev *pcidev)
347{
348 int j;
349 struct ns_dev *card = NULL;
350 unsigned char pci_latency;
351 unsigned error;
352 u32 data;
353 u32 u32d[4];
354 u32 ns_cfg_rctsize;
355 int bcount;
356 unsigned long membase;
357
358 error = 0;
359
360 if (pci_enable_device(pcidev)) {
361 printk("nicstar%d: can't enable PCI device\n", i);
362 error = 2;
363 ns_init_card_error(card, error);
364 return error;
365 }
366 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
367 printk(KERN_WARNING
368 "nicstar%d: No suitable DMA available.\n", i);
369 error = 2;
370 ns_init_card_error(card, error);
371 return error;
372 }
373
374 card = kmalloc(sizeof(*card), GFP_KERNEL);
375 if (!card) {
376 printk
377 ("nicstar%d: can't allocate memory for device structure.\n",
378 i);
379 error = 2;
380 ns_init_card_error(card, error);
381 return error;
382 }
383 cards[i] = card;
384 spin_lock_init(&card->int_lock);
385 spin_lock_init(&card->res_lock);
386
387 pci_set_drvdata(pcidev, card);
388
389 card->index = i;
390 card->atmdev = NULL;
391 card->pcidev = pcidev;
392 membase = pci_resource_start(pcidev, 1);
393 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
394 if (!card->membase) {
395 printk("nicstar%d: can't ioremap() membase.\n", i);
396 error = 3;
397 ns_init_card_error(card, error);
398 return error;
399 }
400 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
401
402 pci_set_master(pcidev);
403
404 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
405 printk("nicstar%d: can't read PCI latency timer.\n", i);
406 error = 6;
407 ns_init_card_error(card, error);
408 return error;
409 }
410#ifdef NS_PCI_LATENCY
411 if (pci_latency < NS_PCI_LATENCY) {
412 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
413 NS_PCI_LATENCY);
414 for (j = 1; j < 4; j++) {
415 if (pci_write_config_byte
416 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
417 break;
418 }
419 if (j == 4) {
420 printk
421 ("nicstar%d: can't set PCI latency timer to %d.\n",
422 i, NS_PCI_LATENCY);
423 error = 7;
424 ns_init_card_error(card, error);
425 return error;
426 }
427 }
428#endif /* NS_PCI_LATENCY */
429
430 /* Clear timer overflow */
431 data = readl(card->membase + STAT);
432 if (data & NS_STAT_TMROF)
433 writel(NS_STAT_TMROF, card->membase + STAT);
434
435 /* Software reset */
436 writel(NS_CFG_SWRST, card->membase + CFG);
437 NS_DELAY;
438 writel(0x00000000, card->membase + CFG);
439
440 /* PHY reset */
441 writel(0x00000008, card->membase + GP);
442 NS_DELAY;
443 writel(0x00000001, card->membase + GP);
444 NS_DELAY;
445 while (CMD_BUSY(card)) ;
446 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
447 NS_DELAY;
448
449 /* Detect PHY type */
450 while (CMD_BUSY(card)) ;
451 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
452 while (CMD_BUSY(card)) ;
453 data = readl(card->membase + DR0);
454 switch (data) {
455 case 0x00000009:
456 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
457 card->max_pcr = ATM_25_PCR;
458 while (CMD_BUSY(card)) ;
459 writel(0x00000008, card->membase + DR0);
460 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
461 /* Clear an eventual pending interrupt */
462 writel(NS_STAT_SFBQF, card->membase + STAT);
463#ifdef PHY_LOOPBACK
464 while (CMD_BUSY(card)) ;
465 writel(0x00000022, card->membase + DR0);
466 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
467#endif /* PHY_LOOPBACK */
468 break;
469 case 0x00000030:
470 case 0x00000031:
471 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
472 card->max_pcr = ATM_OC3_PCR;
473#ifdef PHY_LOOPBACK
474 while (CMD_BUSY(card)) ;
475 writel(0x00000002, card->membase + DR0);
476 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
477#endif /* PHY_LOOPBACK */
478 break;
479 default:
480 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
481 error = 8;
482 ns_init_card_error(card, error);
483 return error;
484 }
485 writel(0x00000000, card->membase + GP);
486
487 /* Determine SRAM size */
488 data = 0x76543210;
489 ns_write_sram(card, 0x1C003, &data, 1);
490 data = 0x89ABCDEF;
491 ns_write_sram(card, 0x14003, &data, 1);
492 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
493 ns_read_sram(card, 0x1C003) == 0x76543210)
494 card->sram_size = 128;
495 else
496 card->sram_size = 32;
497 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
498
499 card->rct_size = NS_MAX_RCTSIZE;
500
501#if (NS_MAX_RCTSIZE == 4096)
502 if (card->sram_size == 128)
503 printk
504 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
505 i);
506#elif (NS_MAX_RCTSIZE == 16384)
507 if (card->sram_size == 32) {
508 printk
509 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
510 i);
511 card->rct_size = 4096;
512 }
513#else
514#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
515#endif
516
517 card->vpibits = NS_VPIBITS;
518 if (card->rct_size == 4096)
519 card->vcibits = 12 - NS_VPIBITS;
520 else /* card->rct_size == 16384 */
521 card->vcibits = 14 - NS_VPIBITS;
522
523 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
524 if (mac[i] == NULL)
525 nicstar_init_eprom(card->membase);
526
527 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
528 writel(0x00000000, card->membase + VPM);
529
530 card->intcnt = 0;
531 if (request_irq
532 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
533 pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
534 error = 9;
535 ns_init_card_error(card, error);
536 return error;
537 }
538
539 /* Initialize TSQ */
540 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
541 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
542 &card->tsq.dma, GFP_KERNEL);
543 if (card->tsq.org == NULL) {
544 printk("nicstar%d: can't allocate TSQ.\n", i);
545 error = 10;
546 ns_init_card_error(card, error);
547 return error;
548 }
549 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
550 card->tsq.next = card->tsq.base;
551 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
552 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
553 ns_tsi_init(card->tsq.base + j);
554 writel(0x00000000, card->membase + TSQH);
555 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
556 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
557
558 /* Initialize RSQ */
559 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
560 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
561 &card->rsq.dma, GFP_KERNEL);
562 if (card->rsq.org == NULL) {
563 printk("nicstar%d: can't allocate RSQ.\n", i);
564 error = 11;
565 ns_init_card_error(card, error);
566 return error;
567 }
568 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
569 card->rsq.next = card->rsq.base;
570 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
571 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
572 ns_rsqe_init(card->rsq.base + j);
573 writel(0x00000000, card->membase + RSQH);
574 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
575 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
576
577 /* Initialize SCQ0, the only VBR SCQ used */
578 card->scq1 = NULL;
579 card->scq2 = NULL;
580 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
581 if (card->scq0 == NULL) {
582 printk("nicstar%d: can't get SCQ0.\n", i);
583 error = 12;
584 ns_init_card_error(card, error);
585 return error;
586 }
587 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
588 u32d[1] = (u32) 0x00000000;
589 u32d[2] = (u32) 0xffffffff;
590 u32d[3] = (u32) 0x00000000;
591 ns_write_sram(card, NS_VRSCD0, u32d, 4);
592 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
593 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
594 card->scq0->scd = NS_VRSCD0;
595 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
596
597 /* Initialize TSTs */
598 card->tst_addr = NS_TST0;
599 card->tst_free_entries = NS_TST_NUM_ENTRIES;
600 data = NS_TST_OPCODE_VARIABLE;
601 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
602 ns_write_sram(card, NS_TST0 + j, &data, 1);
603 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
604 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
605 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
606 ns_write_sram(card, NS_TST1 + j, &data, 1);
607 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
608 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
609 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
610 card->tste2vc[j] = NULL;
611 writel(NS_TST0 << 2, card->membase + TSTB);
612
613 /* Initialize RCT. AAL type is set on opening the VC. */
614#ifdef RCQ_SUPPORT
615 u32d[0] = NS_RCTE_RAWCELLINTEN;
616#else
617 u32d[0] = 0x00000000;
618#endif /* RCQ_SUPPORT */
619 u32d[1] = 0x00000000;
620 u32d[2] = 0x00000000;
621 u32d[3] = 0xFFFFFFFF;
622 for (j = 0; j < card->rct_size; j++)
623 ns_write_sram(card, j * 4, u32d, 4);
624
625 memset(card->vcmap, 0, sizeof(card->vcmap));
626
627 for (j = 0; j < NS_FRSCD_NUM; j++)
628 card->scd2vc[j] = NULL;
629
630 /* Initialize buffer levels */
631 card->sbnr.min = MIN_SB;
632 card->sbnr.init = NUM_SB;
633 card->sbnr.max = MAX_SB;
634 card->lbnr.min = MIN_LB;
635 card->lbnr.init = NUM_LB;
636 card->lbnr.max = MAX_LB;
637 card->iovnr.min = MIN_IOVB;
638 card->iovnr.init = NUM_IOVB;
639 card->iovnr.max = MAX_IOVB;
640 card->hbnr.min = MIN_HB;
641 card->hbnr.init = NUM_HB;
642 card->hbnr.max = MAX_HB;
643
644 card->sm_handle = NULL;
645 card->sm_addr = 0x00000000;
646 card->lg_handle = NULL;
647 card->lg_addr = 0x00000000;
648
649 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
650
651 idr_init(&card->idr);
652
653 /* Pre-allocate some huge buffers */
654 skb_queue_head_init(&card->hbpool.queue);
655 card->hbpool.count = 0;
656 for (j = 0; j < NUM_HB; j++) {
657 struct sk_buff *hb;
658 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
659 if (hb == NULL) {
660 printk
661 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
662 i, j, NUM_HB);
663 error = 13;
664 ns_init_card_error(card, error);
665 return error;
666 }
667 NS_PRV_BUFTYPE(hb) = BUF_NONE;
668 skb_queue_tail(&card->hbpool.queue, hb);
669 card->hbpool.count++;
670 }
671
672 /* Allocate large buffers */
673 skb_queue_head_init(&card->lbpool.queue);
674 card->lbpool.count = 0; /* Not used */
675 for (j = 0; j < NUM_LB; j++) {
676 struct sk_buff *lb;
677 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
678 if (lb == NULL) {
679 printk
680 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
681 i, j, NUM_LB);
682 error = 14;
683 ns_init_card_error(card, error);
684 return error;
685 }
686 NS_PRV_BUFTYPE(lb) = BUF_LG;
687 skb_queue_tail(&card->lbpool.queue, lb);
688 skb_reserve(lb, NS_SMBUFSIZE);
689 push_rxbufs(card, lb);
690 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
691 if (j == 1) {
692 card->rcbuf = lb;
693 card->rawcell = (struct ns_rcqe *) lb->data;
694 card->rawch = NS_PRV_DMA(lb);
695 }
696 }
697 /* Test for strange behaviour which leads to crashes */
698 if ((bcount =
699 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
700 printk
701 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
702 i, j, bcount);
703 error = 14;
704 ns_init_card_error(card, error);
705 return error;
706 }
707
708 /* Allocate small buffers */
709 skb_queue_head_init(&card->sbpool.queue);
710 card->sbpool.count = 0; /* Not used */
711 for (j = 0; j < NUM_SB; j++) {
712 struct sk_buff *sb;
713 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
714 if (sb == NULL) {
715 printk
716 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
717 i, j, NUM_SB);
718 error = 15;
719 ns_init_card_error(card, error);
720 return error;
721 }
722 NS_PRV_BUFTYPE(sb) = BUF_SM;
723 skb_queue_tail(&card->sbpool.queue, sb);
724 skb_reserve(sb, NS_AAL0_HEADER);
725 push_rxbufs(card, sb);
726 }
727 /* Test for strange behaviour which leads to crashes */
728 if ((bcount =
729 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
730 printk
731 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
732 i, j, bcount);
733 error = 15;
734 ns_init_card_error(card, error);
735 return error;
736 }
737
738 /* Allocate iovec buffers */
739 skb_queue_head_init(&card->iovpool.queue);
740 card->iovpool.count = 0;
741 for (j = 0; j < NUM_IOVB; j++) {
742 struct sk_buff *iovb;
743 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
744 if (iovb == NULL) {
745 printk
746 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
747 i, j, NUM_IOVB);
748 error = 16;
749 ns_init_card_error(card, error);
750 return error;
751 }
752 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
753 skb_queue_tail(&card->iovpool.queue, iovb);
754 card->iovpool.count++;
755 }
756
757 /* Configure NICStAR */
758 if (card->rct_size == 4096)
759 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
760 else /* (card->rct_size == 16384) */
761 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
762
763 card->efbie = 1;
764
765 /* Register device */
766 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
767 -1, NULL);
768 if (card->atmdev == NULL) {
769 printk("nicstar%d: can't register device.\n", i);
770 error = 17;
771 ns_init_card_error(card, error);
772 return error;
773 }
774
775 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
776 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
777 card->atmdev->esi, 6);
778 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
779 nicstar_read_eprom(card->membase,
780 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
781 card->atmdev->esi, 6);
782 }
783 }
784
785 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
786
787 card->atmdev->dev_data = card;
788 card->atmdev->ci_range.vpi_bits = card->vpibits;
789 card->atmdev->ci_range.vci_bits = card->vcibits;
790 card->atmdev->link_rate = card->max_pcr;
791 card->atmdev->phy = NULL;
792
793#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
794 if (card->max_pcr == ATM_OC3_PCR)
795 suni_init(card->atmdev);
796#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
797
798#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
799 if (card->max_pcr == ATM_25_PCR)
800 idt77105_init(card->atmdev);
801#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
802
803 if (card->atmdev->phy && card->atmdev->phy->start)
804 card->atmdev->phy->start(card->atmdev);
805
806 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
807 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
808 NS_CFG_PHYIE, card->membase + CFG);
809
810 num_cards++;
811
812 return error;
813}
814
815static void ns_init_card_error(ns_dev *card, int error)
816{
817 if (error >= 17) {
818 writel(0x00000000, card->membase + CFG);
819 }
820 if (error >= 16) {
821 struct sk_buff *iovb;
822 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
823 dev_kfree_skb_any(iovb);
824 }
825 if (error >= 15) {
826 struct sk_buff *sb;
827 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
828 dev_kfree_skb_any(sb);
829 free_scq(card, card->scq0, NULL);
830 }
831 if (error >= 14) {
832 struct sk_buff *lb;
833 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
834 dev_kfree_skb_any(lb);
835 }
836 if (error >= 13) {
837 struct sk_buff *hb;
838 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
839 dev_kfree_skb_any(hb);
840 }
841 if (error >= 12) {
842 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
843 card->rsq.org, card->rsq.dma);
844 }
845 if (error >= 11) {
846 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
847 card->tsq.org, card->tsq.dma);
848 }
849 if (error >= 10) {
850 free_irq(card->pcidev->irq, card);
851 }
852 if (error >= 4) {
853 iounmap(card->membase);
854 }
855 if (error >= 3) {
856 pci_disable_device(card->pcidev);
857 kfree(card);
858 }
859}
860
861static scq_info *get_scq(ns_dev *card, int size, u32 scd)
862{
863 scq_info *scq;
864 int i;
865
866 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
867 return NULL;
868
869 scq = kmalloc(sizeof(*scq), GFP_KERNEL);
870 if (!scq)
871 return NULL;
872 scq->org = dma_alloc_coherent(&card->pcidev->dev,
873 2 * size, &scq->dma, GFP_KERNEL);
874 if (!scq->org) {
875 kfree(scq);
876 return NULL;
877 }
878 scq->skb = kmalloc_array(size / NS_SCQE_SIZE,
879 sizeof(*scq->skb),
880 GFP_KERNEL);
881 if (!scq->skb) {
882 dma_free_coherent(&card->pcidev->dev,
883 2 * size, scq->org, scq->dma);
884 kfree(scq);
885 return NULL;
886 }
887 scq->num_entries = size / NS_SCQE_SIZE;
888 scq->base = PTR_ALIGN(scq->org, size);
889 scq->next = scq->base;
890 scq->last = scq->base + (scq->num_entries - 1);
891 scq->tail = scq->last;
892 scq->scd = scd;
893 scq->num_entries = size / NS_SCQE_SIZE;
894 scq->tbd_count = 0;
895 init_waitqueue_head(&scq->scqfull_waitq);
896 scq->full = 0;
897 spin_lock_init(&scq->lock);
898
899 for (i = 0; i < scq->num_entries; i++)
900 scq->skb[i] = NULL;
901
902 return scq;
903}
904
905/* For variable rate SCQ vcc must be NULL */
906static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
907{
908 int i;
909
910 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
911 for (i = 0; i < scq->num_entries; i++) {
912 if (scq->skb[i] != NULL) {
913 vcc = ATM_SKB(scq->skb[i])->vcc;
914 if (vcc->pop != NULL)
915 vcc->pop(vcc, scq->skb[i]);
916 else
917 dev_kfree_skb_any(scq->skb[i]);
918 }
919 } else { /* vcc must be != NULL */
920
921 if (vcc == NULL) {
922 printk
923 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
924 for (i = 0; i < scq->num_entries; i++)
925 dev_kfree_skb_any(scq->skb[i]);
926 } else
927 for (i = 0; i < scq->num_entries; i++) {
928 if (scq->skb[i] != NULL) {
929 if (vcc->pop != NULL)
930 vcc->pop(vcc, scq->skb[i]);
931 else
932 dev_kfree_skb_any(scq->skb[i]);
933 }
934 }
935 }
936 kfree(scq->skb);
937 dma_free_coherent(&card->pcidev->dev,
938 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
939 VBR_SCQSIZE : CBR_SCQSIZE),
940 scq->org, scq->dma);
941 kfree(scq);
942}
943
944/* The handles passed must be pointers to the sk_buff containing the small
945 or large buffer(s) cast to u32. */
946static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
947{
948 struct sk_buff *handle1, *handle2;
949 int id1, id2;
950 u32 addr1, addr2;
951 u32 stat;
952 unsigned long flags;
953
954 /* *BARF* */
955 handle2 = NULL;
956 addr2 = 0;
957 handle1 = skb;
958 addr1 = dma_map_single(&card->pcidev->dev,
959 skb->data,
960 (NS_PRV_BUFTYPE(skb) == BUF_SM
961 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
962 DMA_TO_DEVICE);
963 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
964
965#ifdef GENERAL_DEBUG
966 if (!addr1)
967 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
968 card->index);
969#endif /* GENERAL_DEBUG */
970
971 stat = readl(card->membase + STAT);
972 card->sbfqc = ns_stat_sfbqc_get(stat);
973 card->lbfqc = ns_stat_lfbqc_get(stat);
974 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
975 if (!addr2) {
976 if (card->sm_addr) {
977 addr2 = card->sm_addr;
978 handle2 = card->sm_handle;
979 card->sm_addr = 0x00000000;
980 card->sm_handle = NULL;
981 } else { /* (!sm_addr) */
982
983 card->sm_addr = addr1;
984 card->sm_handle = handle1;
985 }
986 }
987 } else { /* buf_type == BUF_LG */
988
989 if (!addr2) {
990 if (card->lg_addr) {
991 addr2 = card->lg_addr;
992 handle2 = card->lg_handle;
993 card->lg_addr = 0x00000000;
994 card->lg_handle = NULL;
995 } else { /* (!lg_addr) */
996
997 card->lg_addr = addr1;
998 card->lg_handle = handle1;
999 }
1000 }
1001 }
1002
1003 if (addr2) {
1004 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
1005 if (card->sbfqc >= card->sbnr.max) {
1006 skb_unlink(handle1, &card->sbpool.queue);
1007 dev_kfree_skb_any(handle1);
1008 skb_unlink(handle2, &card->sbpool.queue);
1009 dev_kfree_skb_any(handle2);
1010 return;
1011 } else
1012 card->sbfqc += 2;
1013 } else { /* (buf_type == BUF_LG) */
1014
1015 if (card->lbfqc >= card->lbnr.max) {
1016 skb_unlink(handle1, &card->lbpool.queue);
1017 dev_kfree_skb_any(handle1);
1018 skb_unlink(handle2, &card->lbpool.queue);
1019 dev_kfree_skb_any(handle2);
1020 return;
1021 } else
1022 card->lbfqc += 2;
1023 }
1024
1025 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1026 if (id1 < 0)
1027 goto out;
1028
1029 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1030 if (id2 < 0)
1031 goto out;
1032
1033 spin_lock_irqsave(&card->res_lock, flags);
1034 while (CMD_BUSY(card)) ;
1035 writel(addr2, card->membase + DR3);
1036 writel(id2, card->membase + DR2);
1037 writel(addr1, card->membase + DR1);
1038 writel(id1, card->membase + DR0);
1039 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1040 card->membase + CMD);
1041 spin_unlock_irqrestore(&card->res_lock, flags);
1042
1043 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1044 card->index,
1045 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1046 addr1, addr2);
1047 }
1048
1049 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1050 card->lbfqc >= card->lbnr.min) {
1051 card->efbie = 1;
1052 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1053 card->membase + CFG);
1054 }
1055
1056out:
1057 return;
1058}
1059
1060static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1061{
1062 u32 stat_r;
1063 ns_dev *card;
1064 struct atm_dev *dev;
1065 unsigned long flags;
1066
1067 card = (ns_dev *) dev_id;
1068 dev = card->atmdev;
1069 card->intcnt++;
1070
1071 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1072
1073 spin_lock_irqsave(&card->int_lock, flags);
1074
1075 stat_r = readl(card->membase + STAT);
1076
1077 /* Transmit Status Indicator has been written to T. S. Queue */
1078 if (stat_r & NS_STAT_TSIF) {
1079 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1080 process_tsq(card);
1081 writel(NS_STAT_TSIF, card->membase + STAT);
1082 }
1083
1084 /* Incomplete CS-PDU has been transmitted */
1085 if (stat_r & NS_STAT_TXICP) {
1086 writel(NS_STAT_TXICP, card->membase + STAT);
1087 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1088 card->index);
1089 }
1090
1091 /* Transmit Status Queue 7/8 full */
1092 if (stat_r & NS_STAT_TSQF) {
1093 writel(NS_STAT_TSQF, card->membase + STAT);
1094 PRINTK("nicstar%d: TSQ full.\n", card->index);
1095 process_tsq(card);
1096 }
1097
1098 /* Timer overflow */
1099 if (stat_r & NS_STAT_TMROF) {
1100 writel(NS_STAT_TMROF, card->membase + STAT);
1101 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1102 }
1103
1104 /* PHY device interrupt signal active */
1105 if (stat_r & NS_STAT_PHYI) {
1106 writel(NS_STAT_PHYI, card->membase + STAT);
1107 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1108 if (dev->phy && dev->phy->interrupt) {
1109 dev->phy->interrupt(dev);
1110 }
1111 }
1112
1113 /* Small Buffer Queue is full */
1114 if (stat_r & NS_STAT_SFBQF) {
1115 writel(NS_STAT_SFBQF, card->membase + STAT);
1116 printk("nicstar%d: Small free buffer queue is full.\n",
1117 card->index);
1118 }
1119
1120 /* Large Buffer Queue is full */
1121 if (stat_r & NS_STAT_LFBQF) {
1122 writel(NS_STAT_LFBQF, card->membase + STAT);
1123 printk("nicstar%d: Large free buffer queue is full.\n",
1124 card->index);
1125 }
1126
1127 /* Receive Status Queue is full */
1128 if (stat_r & NS_STAT_RSQF) {
1129 writel(NS_STAT_RSQF, card->membase + STAT);
1130 printk("nicstar%d: RSQ full.\n", card->index);
1131 process_rsq(card);
1132 }
1133
1134 /* Complete CS-PDU received */
1135 if (stat_r & NS_STAT_EOPDU) {
1136 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1137 process_rsq(card);
1138 writel(NS_STAT_EOPDU, card->membase + STAT);
1139 }
1140
1141 /* Raw cell received */
1142 if (stat_r & NS_STAT_RAWCF) {
1143 writel(NS_STAT_RAWCF, card->membase + STAT);
1144#ifndef RCQ_SUPPORT
1145 printk("nicstar%d: Raw cell received and no support yet...\n",
1146 card->index);
1147#endif /* RCQ_SUPPORT */
1148 /* NOTE: the following procedure may keep a raw cell pending until the
1149 next interrupt. As this preliminary support is only meant to
1150 avoid buffer leakage, this is not an issue. */
1151 while (readl(card->membase + RAWCT) != card->rawch) {
1152
1153 if (ns_rcqe_islast(card->rawcell)) {
1154 struct sk_buff *oldbuf;
1155
1156 oldbuf = card->rcbuf;
1157 card->rcbuf = idr_find(&card->idr,
1158 ns_rcqe_nextbufhandle(card->rawcell));
1159 card->rawch = NS_PRV_DMA(card->rcbuf);
1160 card->rawcell = (struct ns_rcqe *)
1161 card->rcbuf->data;
1162 recycle_rx_buf(card, oldbuf);
1163 } else {
1164 card->rawch += NS_RCQE_SIZE;
1165 card->rawcell++;
1166 }
1167 }
1168 }
1169
1170 /* Small buffer queue is empty */
1171 if (stat_r & NS_STAT_SFBQE) {
1172 int i;
1173 struct sk_buff *sb;
1174
1175 writel(NS_STAT_SFBQE, card->membase + STAT);
1176 printk("nicstar%d: Small free buffer queue empty.\n",
1177 card->index);
1178 for (i = 0; i < card->sbnr.min; i++) {
1179 sb = dev_alloc_skb(NS_SMSKBSIZE);
1180 if (sb == NULL) {
1181 writel(readl(card->membase + CFG) &
1182 ~NS_CFG_EFBIE, card->membase + CFG);
1183 card->efbie = 0;
1184 break;
1185 }
1186 NS_PRV_BUFTYPE(sb) = BUF_SM;
1187 skb_queue_tail(&card->sbpool.queue, sb);
1188 skb_reserve(sb, NS_AAL0_HEADER);
1189 push_rxbufs(card, sb);
1190 }
1191 card->sbfqc = i;
1192 process_rsq(card);
1193 }
1194
1195 /* Large buffer queue empty */
1196 if (stat_r & NS_STAT_LFBQE) {
1197 int i;
1198 struct sk_buff *lb;
1199
1200 writel(NS_STAT_LFBQE, card->membase + STAT);
1201 printk("nicstar%d: Large free buffer queue empty.\n",
1202 card->index);
1203 for (i = 0; i < card->lbnr.min; i++) {
1204 lb = dev_alloc_skb(NS_LGSKBSIZE);
1205 if (lb == NULL) {
1206 writel(readl(card->membase + CFG) &
1207 ~NS_CFG_EFBIE, card->membase + CFG);
1208 card->efbie = 0;
1209 break;
1210 }
1211 NS_PRV_BUFTYPE(lb) = BUF_LG;
1212 skb_queue_tail(&card->lbpool.queue, lb);
1213 skb_reserve(lb, NS_SMBUFSIZE);
1214 push_rxbufs(card, lb);
1215 }
1216 card->lbfqc = i;
1217 process_rsq(card);
1218 }
1219
1220 /* Receive Status Queue is 7/8 full */
1221 if (stat_r & NS_STAT_RSQAF) {
1222 writel(NS_STAT_RSQAF, card->membase + STAT);
1223 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1224 process_rsq(card);
1225 }
1226
1227 spin_unlock_irqrestore(&card->int_lock, flags);
1228 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1229 return IRQ_HANDLED;
1230}
1231
1232static int ns_open(struct atm_vcc *vcc)
1233{
1234 ns_dev *card;
1235 vc_map *vc;
1236 unsigned long tmpl, modl;
1237 int tcr, tcra; /* target cell rate, and absolute value */
1238 int n = 0; /* Number of entries in the TST. Initialized to remove
1239 the compiler warning. */
1240 u32 u32d[4];
1241 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1242 warning. How I wish compilers were clever enough to
1243 tell which variables can truly be used
1244 uninitialized... */
1245 int inuse; /* tx or rx vc already in use by another vcc */
1246 short vpi = vcc->vpi;
1247 int vci = vcc->vci;
1248
1249 card = (ns_dev *) vcc->dev->dev_data;
1250 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1251 vci);
1252 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1253 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1254 return -EINVAL;
1255 }
1256
1257 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1258 vcc->dev_data = vc;
1259
1260 inuse = 0;
1261 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1262 inuse = 1;
1263 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1264 inuse += 2;
1265 if (inuse) {
1266 printk("nicstar%d: %s vci already in use.\n", card->index,
1267 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1268 return -EINVAL;
1269 }
1270
1271 set_bit(ATM_VF_ADDR, &vcc->flags);
1272
1273 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1274 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1275 needed to do that. */
1276 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1277 scq_info *scq;
1278
1279 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1280 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1281 /* Check requested cell rate and availability of SCD */
1282 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1283 && vcc->qos.txtp.min_pcr == 0) {
1284 PRINTK
1285 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1286 card->index);
1287 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1288 clear_bit(ATM_VF_ADDR, &vcc->flags);
1289 return -EINVAL;
1290 }
1291
1292 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1293 tcra = tcr >= 0 ? tcr : -tcr;
1294
1295 PRINTK("nicstar%d: target cell rate = %d.\n",
1296 card->index, vcc->qos.txtp.max_pcr);
1297
1298 tmpl =
1299 (unsigned long)tcra *(unsigned long)
1300 NS_TST_NUM_ENTRIES;
1301 modl = tmpl % card->max_pcr;
1302
1303 n = (int)(tmpl / card->max_pcr);
1304 if (tcr > 0) {
1305 if (modl > 0)
1306 n++;
1307 } else if (tcr == 0) {
1308 if ((n =
1309 (card->tst_free_entries -
1310 NS_TST_RESERVED)) <= 0) {
1311 PRINTK
1312 ("nicstar%d: no CBR bandwidth free.\n",
1313 card->index);
1314 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1315 clear_bit(ATM_VF_ADDR, &vcc->flags);
1316 return -EINVAL;
1317 }
1318 }
1319
1320 if (n == 0) {
1321 printk
1322 ("nicstar%d: selected bandwidth < granularity.\n",
1323 card->index);
1324 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1325 clear_bit(ATM_VF_ADDR, &vcc->flags);
1326 return -EINVAL;
1327 }
1328
1329 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1330 PRINTK
1331 ("nicstar%d: not enough free CBR bandwidth.\n",
1332 card->index);
1333 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1334 clear_bit(ATM_VF_ADDR, &vcc->flags);
1335 return -EINVAL;
1336 } else
1337 card->tst_free_entries -= n;
1338
1339 XPRINTK("nicstar%d: writing %d tst entries.\n",
1340 card->index, n);
1341 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1342 if (card->scd2vc[frscdi] == NULL) {
1343 card->scd2vc[frscdi] = vc;
1344 break;
1345 }
1346 }
1347 if (frscdi == NS_FRSCD_NUM) {
1348 PRINTK
1349 ("nicstar%d: no SCD available for CBR channel.\n",
1350 card->index);
1351 card->tst_free_entries += n;
1352 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1353 clear_bit(ATM_VF_ADDR, &vcc->flags);
1354 return -EBUSY;
1355 }
1356
1357 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1358
1359 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1360 if (scq == NULL) {
1361 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1362 card->index);
1363 card->scd2vc[frscdi] = NULL;
1364 card->tst_free_entries += n;
1365 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1366 clear_bit(ATM_VF_ADDR, &vcc->flags);
1367 return -ENOMEM;
1368 }
1369 vc->scq = scq;
1370 u32d[0] = scq_virt_to_bus(scq, scq->base);
1371 u32d[1] = (u32) 0x00000000;
1372 u32d[2] = (u32) 0xffffffff;
1373 u32d[3] = (u32) 0x00000000;
1374 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1375
1376 fill_tst(card, n, vc);
1377 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1378 vc->cbr_scd = 0x00000000;
1379 vc->scq = card->scq0;
1380 }
1381
1382 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1383 vc->tx = 1;
1384 vc->tx_vcc = vcc;
1385 vc->tbd_count = 0;
1386 }
1387 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1388 u32 status;
1389
1390 vc->rx = 1;
1391 vc->rx_vcc = vcc;
1392 vc->rx_iov = NULL;
1393
1394 /* Open the connection in hardware */
1395 if (vcc->qos.aal == ATM_AAL5)
1396 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1397 else /* vcc->qos.aal == ATM_AAL0 */
1398 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1399#ifdef RCQ_SUPPORT
1400 status |= NS_RCTE_RAWCELLINTEN;
1401#endif /* RCQ_SUPPORT */
1402 ns_write_sram(card,
1403 NS_RCT +
1404 (vpi << card->vcibits | vci) *
1405 NS_RCT_ENTRY_SIZE, &status, 1);
1406 }
1407
1408 }
1409
1410 set_bit(ATM_VF_READY, &vcc->flags);
1411 return 0;
1412}
1413
1414static void ns_close(struct atm_vcc *vcc)
1415{
1416 vc_map *vc;
1417 ns_dev *card;
1418 u32 data;
1419 int i;
1420
1421 vc = vcc->dev_data;
1422 card = vcc->dev->dev_data;
1423 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1424 (int)vcc->vpi, vcc->vci);
1425
1426 clear_bit(ATM_VF_READY, &vcc->flags);
1427
1428 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1429 u32 addr;
1430 unsigned long flags;
1431
1432 addr =
1433 NS_RCT +
1434 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1435 spin_lock_irqsave(&card->res_lock, flags);
1436 while (CMD_BUSY(card)) ;
1437 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1438 card->membase + CMD);
1439 spin_unlock_irqrestore(&card->res_lock, flags);
1440
1441 vc->rx = 0;
1442 if (vc->rx_iov != NULL) {
1443 struct sk_buff *iovb;
1444 u32 stat;
1445
1446 stat = readl(card->membase + STAT);
1447 card->sbfqc = ns_stat_sfbqc_get(stat);
1448 card->lbfqc = ns_stat_lfbqc_get(stat);
1449
1450 PRINTK
1451 ("nicstar%d: closing a VC with pending rx buffers.\n",
1452 card->index);
1453 iovb = vc->rx_iov;
1454 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1455 NS_PRV_IOVCNT(iovb));
1456 NS_PRV_IOVCNT(iovb) = 0;
1457 spin_lock_irqsave(&card->int_lock, flags);
1458 recycle_iov_buf(card, iovb);
1459 spin_unlock_irqrestore(&card->int_lock, flags);
1460 vc->rx_iov = NULL;
1461 }
1462 }
1463
1464 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1465 vc->tx = 0;
1466 }
1467
1468 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1469 unsigned long flags;
1470 ns_scqe *scqep;
1471 scq_info *scq;
1472
1473 scq = vc->scq;
1474
1475 for (;;) {
1476 spin_lock_irqsave(&scq->lock, flags);
1477 scqep = scq->next;
1478 if (scqep == scq->base)
1479 scqep = scq->last;
1480 else
1481 scqep--;
1482 if (scqep == scq->tail) {
1483 spin_unlock_irqrestore(&scq->lock, flags);
1484 break;
1485 }
1486 /* If the last entry is not a TSR, place one in the SCQ in order to
1487 be able to completely drain it and then close. */
1488 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1489 ns_scqe tsr;
1490 u32 scdi, scqi;
1491 u32 data;
1492 int index;
1493
1494 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1495 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1496 scqi = scq->next - scq->base;
1497 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1498 tsr.word_3 = 0x00000000;
1499 tsr.word_4 = 0x00000000;
1500 *scq->next = tsr;
1501 index = (int)scqi;
1502 scq->skb[index] = NULL;
1503 if (scq->next == scq->last)
1504 scq->next = scq->base;
1505 else
1506 scq->next++;
1507 data = scq_virt_to_bus(scq, scq->next);
1508 ns_write_sram(card, scq->scd, &data, 1);
1509 }
1510 spin_unlock_irqrestore(&scq->lock, flags);
1511 schedule();
1512 }
1513
1514 /* Free all TST entries */
1515 data = NS_TST_OPCODE_VARIABLE;
1516 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1517 if (card->tste2vc[i] == vc) {
1518 ns_write_sram(card, card->tst_addr + i, &data,
1519 1);
1520 card->tste2vc[i] = NULL;
1521 card->tst_free_entries++;
1522 }
1523 }
1524
1525 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1526 free_scq(card, vc->scq, vcc);
1527 }
1528
1529 /* remove all references to vcc before deleting it */
1530 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1531 unsigned long flags;
1532 scq_info *scq = card->scq0;
1533
1534 spin_lock_irqsave(&scq->lock, flags);
1535
1536 for (i = 0; i < scq->num_entries; i++) {
1537 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1538 ATM_SKB(scq->skb[i])->vcc = NULL;
1539 atm_return(vcc, scq->skb[i]->truesize);
1540 PRINTK
1541 ("nicstar: deleted pending vcc mapping\n");
1542 }
1543 }
1544
1545 spin_unlock_irqrestore(&scq->lock, flags);
1546 }
1547
1548 vcc->dev_data = NULL;
1549 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1550 clear_bit(ATM_VF_ADDR, &vcc->flags);
1551
1552#ifdef RX_DEBUG
1553 {
1554 u32 stat, cfg;
1555 stat = readl(card->membase + STAT);
1556 cfg = readl(card->membase + CFG);
1557 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1558 printk
1559 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1560 card->tsq.base, card->tsq.next,
1561 card->tsq.last, readl(card->membase + TSQT));
1562 printk
1563 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1564 card->rsq.base, card->rsq.next,
1565 card->rsq.last, readl(card->membase + RSQT));
1566 printk("Empty free buffer queue interrupt %s \n",
1567 card->efbie ? "enabled" : "disabled");
1568 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1569 ns_stat_sfbqc_get(stat), card->sbpool.count,
1570 ns_stat_lfbqc_get(stat), card->lbpool.count);
1571 printk("hbpool.count = %d iovpool.count = %d \n",
1572 card->hbpool.count, card->iovpool.count);
1573 }
1574#endif /* RX_DEBUG */
1575}
1576
1577static void fill_tst(ns_dev * card, int n, vc_map * vc)
1578{
1579 u32 new_tst;
1580 unsigned long cl;
1581 int e, r;
1582 u32 data;
1583
1584 /* It would be very complicated to keep the two TSTs synchronized while
1585 assuring that writes are only made to the inactive TST. So, for now I
1586 will use only one TST. If problems occur, I will change this again */
1587
1588 new_tst = card->tst_addr;
1589
1590 /* Fill procedure */
1591
1592 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1593 if (card->tste2vc[e] == NULL)
1594 break;
1595 }
1596 if (e == NS_TST_NUM_ENTRIES) {
1597 printk("nicstar%d: No free TST entries found. \n", card->index);
1598 return;
1599 }
1600
1601 r = n;
1602 cl = NS_TST_NUM_ENTRIES;
1603 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1604
1605 while (r > 0) {
1606 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1607 card->tste2vc[e] = vc;
1608 ns_write_sram(card, new_tst + e, &data, 1);
1609 cl -= NS_TST_NUM_ENTRIES;
1610 r--;
1611 }
1612
1613 if (++e == NS_TST_NUM_ENTRIES) {
1614 e = 0;
1615 }
1616 cl += n;
1617 }
1618
1619 /* End of fill procedure */
1620
1621 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1622 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1623 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1624 card->tst_addr = new_tst;
1625}
1626
1627static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep)
1628{
1629 ns_dev *card;
1630 vc_map *vc;
1631 scq_info *scq;
1632 unsigned long buflen;
1633 ns_scqe scqe;
1634 u32 flags; /* TBD flags, not CPU flags */
1635
1636 card = vcc->dev->dev_data;
1637 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1638 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1639 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1640 card->index);
1641 atomic_inc(&vcc->stats->tx_err);
1642 dev_kfree_skb_any(skb);
1643 return -EINVAL;
1644 }
1645
1646 if (!vc->tx) {
1647 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1648 card->index);
1649 atomic_inc(&vcc->stats->tx_err);
1650 dev_kfree_skb_any(skb);
1651 return -EINVAL;
1652 }
1653
1654 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1655 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1656 card->index);
1657 atomic_inc(&vcc->stats->tx_err);
1658 dev_kfree_skb_any(skb);
1659 return -EINVAL;
1660 }
1661
1662 if (skb_shinfo(skb)->nr_frags != 0) {
1663 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1664 atomic_inc(&vcc->stats->tx_err);
1665 dev_kfree_skb_any(skb);
1666 return -EINVAL;
1667 }
1668
1669 ATM_SKB(skb)->vcc = vcc;
1670
1671 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1672 skb->len, DMA_TO_DEVICE);
1673
1674 if (vcc->qos.aal == ATM_AAL5) {
1675 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1676 flags = NS_TBD_AAL5;
1677 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1678 scqe.word_3 = cpu_to_le32(skb->len);
1679 scqe.word_4 =
1680 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1681 ATM_SKB(skb)->
1682 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1683 flags |= NS_TBD_EOPDU;
1684 } else { /* (vcc->qos.aal == ATM_AAL0) */
1685
1686 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1687 flags = NS_TBD_AAL0;
1688 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1689 scqe.word_3 = cpu_to_le32(0x00000000);
1690 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1691 flags |= NS_TBD_EOPDU;
1692 scqe.word_4 =
1693 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1694 /* Force the VPI/VCI to be the same as in VCC struct */
1695 scqe.word_4 |=
1696 cpu_to_le32((((u32) vcc->
1697 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1698 vci) <<
1699 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1700 }
1701
1702 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1703 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1704 scq = ((vc_map *) vcc->dev_data)->scq;
1705 } else {
1706 scqe.word_1 =
1707 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1708 scq = card->scq0;
1709 }
1710
1711 if (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) {
1712 atomic_inc(&vcc->stats->tx_err);
1713 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1714 DMA_TO_DEVICE);
1715 dev_kfree_skb_any(skb);
1716 return -EIO;
1717 }
1718 atomic_inc(&vcc->stats->tx);
1719
1720 return 0;
1721}
1722
1723static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1724{
1725 return _ns_send(vcc, skb, true);
1726}
1727
1728static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb)
1729{
1730 return _ns_send(vcc, skb, false);
1731}
1732
1733static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1734 struct sk_buff *skb, bool may_sleep)
1735{
1736 unsigned long flags;
1737 ns_scqe tsr;
1738 u32 scdi, scqi;
1739 int scq_is_vbr;
1740 u32 data;
1741 int index;
1742
1743 spin_lock_irqsave(&scq->lock, flags);
1744 while (scq->tail == scq->next) {
1745 if (!may_sleep) {
1746 spin_unlock_irqrestore(&scq->lock, flags);
1747 printk("nicstar%d: Error pushing TBD.\n", card->index);
1748 return 1;
1749 }
1750
1751 scq->full = 1;
1752 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1753 scq->tail != scq->next,
1754 scq->lock,
1755 SCQFULL_TIMEOUT);
1756
1757 if (scq->full) {
1758 spin_unlock_irqrestore(&scq->lock, flags);
1759 printk("nicstar%d: Timeout pushing TBD.\n",
1760 card->index);
1761 return 1;
1762 }
1763 }
1764 *scq->next = *tbd;
1765 index = (int)(scq->next - scq->base);
1766 scq->skb[index] = skb;
1767 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1768 card->index, skb, index);
1769 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1770 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1771 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1772 scq->next);
1773 if (scq->next == scq->last)
1774 scq->next = scq->base;
1775 else
1776 scq->next++;
1777
1778 vc->tbd_count++;
1779 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1780 scq->tbd_count++;
1781 scq_is_vbr = 1;
1782 } else
1783 scq_is_vbr = 0;
1784
1785 if (vc->tbd_count >= MAX_TBD_PER_VC
1786 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1787 int has_run = 0;
1788
1789 while (scq->tail == scq->next) {
1790 if (!may_sleep) {
1791 data = scq_virt_to_bus(scq, scq->next);
1792 ns_write_sram(card, scq->scd, &data, 1);
1793 spin_unlock_irqrestore(&scq->lock, flags);
1794 printk("nicstar%d: Error pushing TSR.\n",
1795 card->index);
1796 return 0;
1797 }
1798
1799 scq->full = 1;
1800 if (has_run++)
1801 break;
1802 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1803 scq->tail != scq->next,
1804 scq->lock,
1805 SCQFULL_TIMEOUT);
1806 }
1807
1808 if (!scq->full) {
1809 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1810 if (scq_is_vbr)
1811 scdi = NS_TSR_SCDISVBR;
1812 else
1813 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1814 scqi = scq->next - scq->base;
1815 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1816 tsr.word_3 = 0x00000000;
1817 tsr.word_4 = 0x00000000;
1818
1819 *scq->next = tsr;
1820 index = (int)scqi;
1821 scq->skb[index] = NULL;
1822 XPRINTK
1823 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1824 card->index, le32_to_cpu(tsr.word_1),
1825 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1826 le32_to_cpu(tsr.word_4), scq->next);
1827 if (scq->next == scq->last)
1828 scq->next = scq->base;
1829 else
1830 scq->next++;
1831 vc->tbd_count = 0;
1832 scq->tbd_count = 0;
1833 } else
1834 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1835 card->index);
1836 }
1837 data = scq_virt_to_bus(scq, scq->next);
1838 ns_write_sram(card, scq->scd, &data, 1);
1839
1840 spin_unlock_irqrestore(&scq->lock, flags);
1841
1842 return 0;
1843}
1844
1845static void process_tsq(ns_dev * card)
1846{
1847 u32 scdi;
1848 scq_info *scq;
1849 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1850 int serviced_entries; /* flag indicating at least on entry was serviced */
1851
1852 serviced_entries = 0;
1853
1854 if (card->tsq.next == card->tsq.last)
1855 one_ahead = card->tsq.base;
1856 else
1857 one_ahead = card->tsq.next + 1;
1858
1859 if (one_ahead == card->tsq.last)
1860 two_ahead = card->tsq.base;
1861 else
1862 two_ahead = one_ahead + 1;
1863
1864 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1865 !ns_tsi_isempty(two_ahead))
1866 /* At most two empty, as stated in the 77201 errata */
1867 {
1868 serviced_entries = 1;
1869
1870 /* Skip the one or two possible empty entries */
1871 while (ns_tsi_isempty(card->tsq.next)) {
1872 if (card->tsq.next == card->tsq.last)
1873 card->tsq.next = card->tsq.base;
1874 else
1875 card->tsq.next++;
1876 }
1877
1878 if (!ns_tsi_tmrof(card->tsq.next)) {
1879 scdi = ns_tsi_getscdindex(card->tsq.next);
1880 if (scdi == NS_TSI_SCDISVBR)
1881 scq = card->scq0;
1882 else {
1883 if (card->scd2vc[scdi] == NULL) {
1884 printk
1885 ("nicstar%d: could not find VC from SCD index.\n",
1886 card->index);
1887 ns_tsi_init(card->tsq.next);
1888 return;
1889 }
1890 scq = card->scd2vc[scdi]->scq;
1891 }
1892 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1893 scq->full = 0;
1894 wake_up_interruptible(&(scq->scqfull_waitq));
1895 }
1896
1897 ns_tsi_init(card->tsq.next);
1898 previous = card->tsq.next;
1899 if (card->tsq.next == card->tsq.last)
1900 card->tsq.next = card->tsq.base;
1901 else
1902 card->tsq.next++;
1903
1904 if (card->tsq.next == card->tsq.last)
1905 one_ahead = card->tsq.base;
1906 else
1907 one_ahead = card->tsq.next + 1;
1908
1909 if (one_ahead == card->tsq.last)
1910 two_ahead = card->tsq.base;
1911 else
1912 two_ahead = one_ahead + 1;
1913 }
1914
1915 if (serviced_entries)
1916 writel(PTR_DIFF(previous, card->tsq.base),
1917 card->membase + TSQH);
1918}
1919
1920static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1921{
1922 struct atm_vcc *vcc;
1923 struct sk_buff *skb;
1924 int i;
1925 unsigned long flags;
1926
1927 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1928 card->index, scq, pos);
1929 if (pos >= scq->num_entries) {
1930 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1931 return;
1932 }
1933
1934 spin_lock_irqsave(&scq->lock, flags);
1935 i = (int)(scq->tail - scq->base);
1936 if (++i == scq->num_entries)
1937 i = 0;
1938 while (i != pos) {
1939 skb = scq->skb[i];
1940 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1941 card->index, skb, i);
1942 if (skb != NULL) {
1943 dma_unmap_single(&card->pcidev->dev,
1944 NS_PRV_DMA(skb),
1945 skb->len,
1946 DMA_TO_DEVICE);
1947 vcc = ATM_SKB(skb)->vcc;
1948 if (vcc && vcc->pop != NULL) {
1949 vcc->pop(vcc, skb);
1950 } else {
1951 dev_kfree_skb_irq(skb);
1952 }
1953 scq->skb[i] = NULL;
1954 }
1955 if (++i == scq->num_entries)
1956 i = 0;
1957 }
1958 scq->tail = scq->base + pos;
1959 spin_unlock_irqrestore(&scq->lock, flags);
1960}
1961
1962static void process_rsq(ns_dev * card)
1963{
1964 ns_rsqe *previous;
1965
1966 if (!ns_rsqe_valid(card->rsq.next))
1967 return;
1968 do {
1969 dequeue_rx(card, card->rsq.next);
1970 ns_rsqe_init(card->rsq.next);
1971 previous = card->rsq.next;
1972 if (card->rsq.next == card->rsq.last)
1973 card->rsq.next = card->rsq.base;
1974 else
1975 card->rsq.next++;
1976 } while (ns_rsqe_valid(card->rsq.next));
1977 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1978}
1979
1980static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1981{
1982 u32 vpi, vci;
1983 vc_map *vc;
1984 struct sk_buff *iovb;
1985 struct iovec *iov;
1986 struct atm_vcc *vcc;
1987 struct sk_buff *skb;
1988 unsigned short aal5_len;
1989 int len;
1990 u32 stat;
1991 u32 id;
1992
1993 stat = readl(card->membase + STAT);
1994 card->sbfqc = ns_stat_sfbqc_get(stat);
1995 card->lbfqc = ns_stat_lfbqc_get(stat);
1996
1997 id = le32_to_cpu(rsqe->buffer_handle);
1998 skb = idr_remove(&card->idr, id);
1999 if (!skb) {
2000 RXPRINTK(KERN_ERR
2001 "nicstar%d: skb not found!\n", card->index);
2002 return;
2003 }
2004 dma_sync_single_for_cpu(&card->pcidev->dev,
2005 NS_PRV_DMA(skb),
2006 (NS_PRV_BUFTYPE(skb) == BUF_SM
2007 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2008 DMA_FROM_DEVICE);
2009 dma_unmap_single(&card->pcidev->dev,
2010 NS_PRV_DMA(skb),
2011 (NS_PRV_BUFTYPE(skb) == BUF_SM
2012 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2013 DMA_FROM_DEVICE);
2014 vpi = ns_rsqe_vpi(rsqe);
2015 vci = ns_rsqe_vci(rsqe);
2016 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2017 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2018 card->index, vpi, vci);
2019 recycle_rx_buf(card, skb);
2020 return;
2021 }
2022
2023 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2024 if (!vc->rx) {
2025 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2026 card->index, vpi, vci);
2027 recycle_rx_buf(card, skb);
2028 return;
2029 }
2030
2031 vcc = vc->rx_vcc;
2032
2033 if (vcc->qos.aal == ATM_AAL0) {
2034 struct sk_buff *sb;
2035 unsigned char *cell;
2036 int i;
2037
2038 cell = skb->data;
2039 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2040 sb = dev_alloc_skb(NS_SMSKBSIZE);
2041 if (!sb) {
2042 printk
2043 ("nicstar%d: Can't allocate buffers for aal0.\n",
2044 card->index);
2045 atomic_add(i, &vcc->stats->rx_drop);
2046 break;
2047 }
2048 if (!atm_charge(vcc, sb->truesize)) {
2049 RXPRINTK
2050 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2051 card->index);
2052 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2053 dev_kfree_skb_any(sb);
2054 break;
2055 }
2056 /* Rebuild the header */
2057 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2058 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2059 if (i == 1 && ns_rsqe_eopdu(rsqe))
2060 *((u32 *) sb->data) |= 0x00000002;
2061 skb_put(sb, NS_AAL0_HEADER);
2062 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2063 skb_put(sb, ATM_CELL_PAYLOAD);
2064 ATM_SKB(sb)->vcc = vcc;
2065 __net_timestamp(sb);
2066 vcc->push(vcc, sb);
2067 atomic_inc(&vcc->stats->rx);
2068 cell += ATM_CELL_PAYLOAD;
2069 }
2070
2071 recycle_rx_buf(card, skb);
2072 return;
2073 }
2074
2075 /* To reach this point, the AAL layer can only be AAL5 */
2076
2077 if ((iovb = vc->rx_iov) == NULL) {
2078 iovb = skb_dequeue(&(card->iovpool.queue));
2079 if (iovb == NULL) { /* No buffers in the queue */
2080 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2081 if (iovb == NULL) {
2082 printk("nicstar%d: Out of iovec buffers.\n",
2083 card->index);
2084 atomic_inc(&vcc->stats->rx_drop);
2085 recycle_rx_buf(card, skb);
2086 return;
2087 }
2088 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2089 } else if (--card->iovpool.count < card->iovnr.min) {
2090 struct sk_buff *new_iovb;
2091 if ((new_iovb =
2092 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2093 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2094 skb_queue_tail(&card->iovpool.queue, new_iovb);
2095 card->iovpool.count++;
2096 }
2097 }
2098 vc->rx_iov = iovb;
2099 NS_PRV_IOVCNT(iovb) = 0;
2100 iovb->len = 0;
2101 iovb->data = iovb->head;
2102 skb_reset_tail_pointer(iovb);
2103 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2104 buffer is stored as iovec base, NOT a pointer to the
2105 small or large buffer itself. */
2106 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2107 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2108 atomic_inc(&vcc->stats->rx_err);
2109 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2110 NS_MAX_IOVECS);
2111 NS_PRV_IOVCNT(iovb) = 0;
2112 iovb->len = 0;
2113 iovb->data = iovb->head;
2114 skb_reset_tail_pointer(iovb);
2115 }
2116 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2117 iov->iov_base = (void *)skb;
2118 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2119 iovb->len += iov->iov_len;
2120
2121#ifdef EXTRA_DEBUG
2122 if (NS_PRV_IOVCNT(iovb) == 1) {
2123 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2124 printk
2125 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2126 card->index);
2127 which_list(card, skb);
2128 atomic_inc(&vcc->stats->rx_err);
2129 recycle_rx_buf(card, skb);
2130 vc->rx_iov = NULL;
2131 recycle_iov_buf(card, iovb);
2132 return;
2133 }
2134 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2135
2136 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2137 printk
2138 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2139 card->index);
2140 which_list(card, skb);
2141 atomic_inc(&vcc->stats->rx_err);
2142 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2143 NS_PRV_IOVCNT(iovb));
2144 vc->rx_iov = NULL;
2145 recycle_iov_buf(card, iovb);
2146 return;
2147 }
2148 }
2149#endif /* EXTRA_DEBUG */
2150
2151 if (ns_rsqe_eopdu(rsqe)) {
2152 /* This works correctly regardless of the endianness of the host */
2153 unsigned char *L1L2 = (unsigned char *)
2154 (skb->data + iov->iov_len - 6);
2155 aal5_len = L1L2[0] << 8 | L1L2[1];
2156 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2157 if (ns_rsqe_crcerr(rsqe) ||
2158 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2159 printk("nicstar%d: AAL5 CRC error", card->index);
2160 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2161 printk(" - PDU size mismatch.\n");
2162 else
2163 printk(".\n");
2164 atomic_inc(&vcc->stats->rx_err);
2165 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2166 NS_PRV_IOVCNT(iovb));
2167 vc->rx_iov = NULL;
2168 recycle_iov_buf(card, iovb);
2169 return;
2170 }
2171
2172 /* By this point we (hopefully) have a complete SDU without errors. */
2173
2174 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2175 /* skb points to a small buffer */
2176 if (!atm_charge(vcc, skb->truesize)) {
2177 push_rxbufs(card, skb);
2178 atomic_inc(&vcc->stats->rx_drop);
2179 } else {
2180 skb_put(skb, len);
2181 dequeue_sm_buf(card, skb);
2182 ATM_SKB(skb)->vcc = vcc;
2183 __net_timestamp(skb);
2184 vcc->push(vcc, skb);
2185 atomic_inc(&vcc->stats->rx);
2186 }
2187 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2188 struct sk_buff *sb;
2189
2190 sb = (struct sk_buff *)(iov - 1)->iov_base;
2191 /* skb points to a large buffer */
2192
2193 if (len <= NS_SMBUFSIZE) {
2194 if (!atm_charge(vcc, sb->truesize)) {
2195 push_rxbufs(card, sb);
2196 atomic_inc(&vcc->stats->rx_drop);
2197 } else {
2198 skb_put(sb, len);
2199 dequeue_sm_buf(card, sb);
2200 ATM_SKB(sb)->vcc = vcc;
2201 __net_timestamp(sb);
2202 vcc->push(vcc, sb);
2203 atomic_inc(&vcc->stats->rx);
2204 }
2205
2206 push_rxbufs(card, skb);
2207
2208 } else { /* len > NS_SMBUFSIZE, the usual case */
2209
2210 if (!atm_charge(vcc, skb->truesize)) {
2211 push_rxbufs(card, skb);
2212 atomic_inc(&vcc->stats->rx_drop);
2213 } else {
2214 dequeue_lg_buf(card, skb);
2215 skb_push(skb, NS_SMBUFSIZE);
2216 skb_copy_from_linear_data(sb, skb->data,
2217 NS_SMBUFSIZE);
2218 skb_put(skb, len - NS_SMBUFSIZE);
2219 ATM_SKB(skb)->vcc = vcc;
2220 __net_timestamp(skb);
2221 vcc->push(vcc, skb);
2222 atomic_inc(&vcc->stats->rx);
2223 }
2224
2225 push_rxbufs(card, sb);
2226
2227 }
2228
2229 } else { /* Must push a huge buffer */
2230
2231 struct sk_buff *hb, *sb, *lb;
2232 int remaining, tocopy;
2233 int j;
2234
2235 hb = skb_dequeue(&(card->hbpool.queue));
2236 if (hb == NULL) { /* No buffers in the queue */
2237
2238 hb = dev_alloc_skb(NS_HBUFSIZE);
2239 if (hb == NULL) {
2240 printk
2241 ("nicstar%d: Out of huge buffers.\n",
2242 card->index);
2243 atomic_inc(&vcc->stats->rx_drop);
2244 recycle_iovec_rx_bufs(card,
2245 (struct iovec *)
2246 iovb->data,
2247 NS_PRV_IOVCNT(iovb));
2248 vc->rx_iov = NULL;
2249 recycle_iov_buf(card, iovb);
2250 return;
2251 } else if (card->hbpool.count < card->hbnr.min) {
2252 struct sk_buff *new_hb;
2253 if ((new_hb =
2254 dev_alloc_skb(NS_HBUFSIZE)) !=
2255 NULL) {
2256 skb_queue_tail(&card->hbpool.
2257 queue, new_hb);
2258 card->hbpool.count++;
2259 }
2260 }
2261 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2262 } else if (--card->hbpool.count < card->hbnr.min) {
2263 struct sk_buff *new_hb;
2264 if ((new_hb =
2265 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2266 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2267 skb_queue_tail(&card->hbpool.queue,
2268 new_hb);
2269 card->hbpool.count++;
2270 }
2271 if (card->hbpool.count < card->hbnr.min) {
2272 if ((new_hb =
2273 dev_alloc_skb(NS_HBUFSIZE)) !=
2274 NULL) {
2275 NS_PRV_BUFTYPE(new_hb) =
2276 BUF_NONE;
2277 skb_queue_tail(&card->hbpool.
2278 queue, new_hb);
2279 card->hbpool.count++;
2280 }
2281 }
2282 }
2283
2284 iov = (struct iovec *)iovb->data;
2285
2286 if (!atm_charge(vcc, hb->truesize)) {
2287 recycle_iovec_rx_bufs(card, iov,
2288 NS_PRV_IOVCNT(iovb));
2289 if (card->hbpool.count < card->hbnr.max) {
2290 skb_queue_tail(&card->hbpool.queue, hb);
2291 card->hbpool.count++;
2292 } else
2293 dev_kfree_skb_any(hb);
2294 atomic_inc(&vcc->stats->rx_drop);
2295 } else {
2296 /* Copy the small buffer to the huge buffer */
2297 sb = (struct sk_buff *)iov->iov_base;
2298 skb_copy_from_linear_data(sb, hb->data,
2299 iov->iov_len);
2300 skb_put(hb, iov->iov_len);
2301 remaining = len - iov->iov_len;
2302 iov++;
2303 /* Free the small buffer */
2304 push_rxbufs(card, sb);
2305
2306 /* Copy all large buffers to the huge buffer and free them */
2307 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2308 lb = (struct sk_buff *)iov->iov_base;
2309 tocopy =
2310 min_t(int, remaining, iov->iov_len);
2311 skb_copy_from_linear_data(lb,
2312 skb_tail_pointer
2313 (hb), tocopy);
2314 skb_put(hb, tocopy);
2315 iov++;
2316 remaining -= tocopy;
2317 push_rxbufs(card, lb);
2318 }
2319#ifdef EXTRA_DEBUG
2320 if (remaining != 0 || hb->len != len)
2321 printk
2322 ("nicstar%d: Huge buffer len mismatch.\n",
2323 card->index);
2324#endif /* EXTRA_DEBUG */
2325 ATM_SKB(hb)->vcc = vcc;
2326 __net_timestamp(hb);
2327 vcc->push(vcc, hb);
2328 atomic_inc(&vcc->stats->rx);
2329 }
2330 }
2331
2332 vc->rx_iov = NULL;
2333 recycle_iov_buf(card, iovb);
2334 }
2335
2336}
2337
2338static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2339{
2340 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2341 printk("nicstar%d: What kind of rx buffer is this?\n",
2342 card->index);
2343 dev_kfree_skb_any(skb);
2344 } else
2345 push_rxbufs(card, skb);
2346}
2347
2348static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2349{
2350 while (count-- > 0)
2351 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2352}
2353
2354static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2355{
2356 if (card->iovpool.count < card->iovnr.max) {
2357 skb_queue_tail(&card->iovpool.queue, iovb);
2358 card->iovpool.count++;
2359 } else
2360 dev_kfree_skb_any(iovb);
2361}
2362
2363static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2364{
2365 skb_unlink(sb, &card->sbpool.queue);
2366 if (card->sbfqc < card->sbnr.init) {
2367 struct sk_buff *new_sb;
2368 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2369 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2370 skb_queue_tail(&card->sbpool.queue, new_sb);
2371 skb_reserve(new_sb, NS_AAL0_HEADER);
2372 push_rxbufs(card, new_sb);
2373 }
2374 }
2375 if (card->sbfqc < card->sbnr.init)
2376 {
2377 struct sk_buff *new_sb;
2378 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2379 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2380 skb_queue_tail(&card->sbpool.queue, new_sb);
2381 skb_reserve(new_sb, NS_AAL0_HEADER);
2382 push_rxbufs(card, new_sb);
2383 }
2384 }
2385}
2386
2387static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2388{
2389 skb_unlink(lb, &card->lbpool.queue);
2390 if (card->lbfqc < card->lbnr.init) {
2391 struct sk_buff *new_lb;
2392 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2393 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2394 skb_queue_tail(&card->lbpool.queue, new_lb);
2395 skb_reserve(new_lb, NS_SMBUFSIZE);
2396 push_rxbufs(card, new_lb);
2397 }
2398 }
2399 if (card->lbfqc < card->lbnr.init)
2400 {
2401 struct sk_buff *new_lb;
2402 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2403 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2404 skb_queue_tail(&card->lbpool.queue, new_lb);
2405 skb_reserve(new_lb, NS_SMBUFSIZE);
2406 push_rxbufs(card, new_lb);
2407 }
2408 }
2409}
2410
2411static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2412{
2413 u32 stat;
2414 ns_dev *card;
2415 int left;
2416
2417 left = (int)*pos;
2418 card = (ns_dev *) dev->dev_data;
2419 stat = readl(card->membase + STAT);
2420 if (!left--)
2421 return sprintf(page, "Pool count min init max \n");
2422 if (!left--)
2423 return sprintf(page, "Small %5d %5d %5d %5d \n",
2424 ns_stat_sfbqc_get(stat), card->sbnr.min,
2425 card->sbnr.init, card->sbnr.max);
2426 if (!left--)
2427 return sprintf(page, "Large %5d %5d %5d %5d \n",
2428 ns_stat_lfbqc_get(stat), card->lbnr.min,
2429 card->lbnr.init, card->lbnr.max);
2430 if (!left--)
2431 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2432 card->hbpool.count, card->hbnr.min,
2433 card->hbnr.init, card->hbnr.max);
2434 if (!left--)
2435 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2436 card->iovpool.count, card->iovnr.min,
2437 card->iovnr.init, card->iovnr.max);
2438 if (!left--) {
2439 int retval;
2440 retval =
2441 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2442 card->intcnt = 0;
2443 return retval;
2444 }
2445#if 0
2446 /* Dump 25.6 Mbps PHY registers */
2447 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2448 here just in case it's needed for debugging. */
2449 if (card->max_pcr == ATM_25_PCR && !left--) {
2450 u32 phy_regs[4];
2451 u32 i;
2452
2453 for (i = 0; i < 4; i++) {
2454 while (CMD_BUSY(card)) ;
2455 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2456 card->membase + CMD);
2457 while (CMD_BUSY(card)) ;
2458 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2459 }
2460
2461 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2462 phy_regs[0], phy_regs[1], phy_regs[2],
2463 phy_regs[3]);
2464 }
2465#endif /* 0 - Dump 25.6 Mbps PHY registers */
2466#if 0
2467 /* Dump TST */
2468 if (left-- < NS_TST_NUM_ENTRIES) {
2469 if (card->tste2vc[left + 1] == NULL)
2470 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2471 else
2472 return sprintf(page, "%5d - %d %d \n", left + 1,
2473 card->tste2vc[left + 1]->tx_vcc->vpi,
2474 card->tste2vc[left + 1]->tx_vcc->vci);
2475 }
2476#endif /* 0 */
2477 return 0;
2478}
2479
2480static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2481{
2482 ns_dev *card;
2483 pool_levels pl;
2484 long btype;
2485 unsigned long flags;
2486
2487 card = dev->dev_data;
2488 switch (cmd) {
2489 case NS_GETPSTAT:
2490 if (get_user
2491 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2492 return -EFAULT;
2493 switch (pl.buftype) {
2494 case NS_BUFTYPE_SMALL:
2495 pl.count =
2496 ns_stat_sfbqc_get(readl(card->membase + STAT));
2497 pl.level.min = card->sbnr.min;
2498 pl.level.init = card->sbnr.init;
2499 pl.level.max = card->sbnr.max;
2500 break;
2501
2502 case NS_BUFTYPE_LARGE:
2503 pl.count =
2504 ns_stat_lfbqc_get(readl(card->membase + STAT));
2505 pl.level.min = card->lbnr.min;
2506 pl.level.init = card->lbnr.init;
2507 pl.level.max = card->lbnr.max;
2508 break;
2509
2510 case NS_BUFTYPE_HUGE:
2511 pl.count = card->hbpool.count;
2512 pl.level.min = card->hbnr.min;
2513 pl.level.init = card->hbnr.init;
2514 pl.level.max = card->hbnr.max;
2515 break;
2516
2517 case NS_BUFTYPE_IOVEC:
2518 pl.count = card->iovpool.count;
2519 pl.level.min = card->iovnr.min;
2520 pl.level.init = card->iovnr.init;
2521 pl.level.max = card->iovnr.max;
2522 break;
2523
2524 default:
2525 return -ENOIOCTLCMD;
2526
2527 }
2528 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2529 return (sizeof(pl));
2530 else
2531 return -EFAULT;
2532
2533 case NS_SETBUFLEV:
2534 if (!capable(CAP_NET_ADMIN))
2535 return -EPERM;
2536 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2537 return -EFAULT;
2538 if (pl.level.min >= pl.level.init
2539 || pl.level.init >= pl.level.max)
2540 return -EINVAL;
2541 if (pl.level.min == 0)
2542 return -EINVAL;
2543 switch (pl.buftype) {
2544 case NS_BUFTYPE_SMALL:
2545 if (pl.level.max > TOP_SB)
2546 return -EINVAL;
2547 card->sbnr.min = pl.level.min;
2548 card->sbnr.init = pl.level.init;
2549 card->sbnr.max = pl.level.max;
2550 break;
2551
2552 case NS_BUFTYPE_LARGE:
2553 if (pl.level.max > TOP_LB)
2554 return -EINVAL;
2555 card->lbnr.min = pl.level.min;
2556 card->lbnr.init = pl.level.init;
2557 card->lbnr.max = pl.level.max;
2558 break;
2559
2560 case NS_BUFTYPE_HUGE:
2561 if (pl.level.max > TOP_HB)
2562 return -EINVAL;
2563 card->hbnr.min = pl.level.min;
2564 card->hbnr.init = pl.level.init;
2565 card->hbnr.max = pl.level.max;
2566 break;
2567
2568 case NS_BUFTYPE_IOVEC:
2569 if (pl.level.max > TOP_IOVB)
2570 return -EINVAL;
2571 card->iovnr.min = pl.level.min;
2572 card->iovnr.init = pl.level.init;
2573 card->iovnr.max = pl.level.max;
2574 break;
2575
2576 default:
2577 return -EINVAL;
2578
2579 }
2580 return 0;
2581
2582 case NS_ADJBUFLEV:
2583 if (!capable(CAP_NET_ADMIN))
2584 return -EPERM;
2585 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2586 switch (btype) {
2587 case NS_BUFTYPE_SMALL:
2588 while (card->sbfqc < card->sbnr.init) {
2589 struct sk_buff *sb;
2590
2591 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2592 if (sb == NULL)
2593 return -ENOMEM;
2594 NS_PRV_BUFTYPE(sb) = BUF_SM;
2595 skb_queue_tail(&card->sbpool.queue, sb);
2596 skb_reserve(sb, NS_AAL0_HEADER);
2597 push_rxbufs(card, sb);
2598 }
2599 break;
2600
2601 case NS_BUFTYPE_LARGE:
2602 while (card->lbfqc < card->lbnr.init) {
2603 struct sk_buff *lb;
2604
2605 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2606 if (lb == NULL)
2607 return -ENOMEM;
2608 NS_PRV_BUFTYPE(lb) = BUF_LG;
2609 skb_queue_tail(&card->lbpool.queue, lb);
2610 skb_reserve(lb, NS_SMBUFSIZE);
2611 push_rxbufs(card, lb);
2612 }
2613 break;
2614
2615 case NS_BUFTYPE_HUGE:
2616 while (card->hbpool.count > card->hbnr.init) {
2617 struct sk_buff *hb;
2618
2619 spin_lock_irqsave(&card->int_lock, flags);
2620 hb = skb_dequeue(&card->hbpool.queue);
2621 card->hbpool.count--;
2622 spin_unlock_irqrestore(&card->int_lock, flags);
2623 if (hb == NULL)
2624 printk
2625 ("nicstar%d: huge buffer count inconsistent.\n",
2626 card->index);
2627 else
2628 dev_kfree_skb_any(hb);
2629
2630 }
2631 while (card->hbpool.count < card->hbnr.init) {
2632 struct sk_buff *hb;
2633
2634 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2635 if (hb == NULL)
2636 return -ENOMEM;
2637 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2638 spin_lock_irqsave(&card->int_lock, flags);
2639 skb_queue_tail(&card->hbpool.queue, hb);
2640 card->hbpool.count++;
2641 spin_unlock_irqrestore(&card->int_lock, flags);
2642 }
2643 break;
2644
2645 case NS_BUFTYPE_IOVEC:
2646 while (card->iovpool.count > card->iovnr.init) {
2647 struct sk_buff *iovb;
2648
2649 spin_lock_irqsave(&card->int_lock, flags);
2650 iovb = skb_dequeue(&card->iovpool.queue);
2651 card->iovpool.count--;
2652 spin_unlock_irqrestore(&card->int_lock, flags);
2653 if (iovb == NULL)
2654 printk
2655 ("nicstar%d: iovec buffer count inconsistent.\n",
2656 card->index);
2657 else
2658 dev_kfree_skb_any(iovb);
2659
2660 }
2661 while (card->iovpool.count < card->iovnr.init) {
2662 struct sk_buff *iovb;
2663
2664 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2665 if (iovb == NULL)
2666 return -ENOMEM;
2667 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2668 spin_lock_irqsave(&card->int_lock, flags);
2669 skb_queue_tail(&card->iovpool.queue, iovb);
2670 card->iovpool.count++;
2671 spin_unlock_irqrestore(&card->int_lock, flags);
2672 }
2673 break;
2674
2675 default:
2676 return -EINVAL;
2677
2678 }
2679 return 0;
2680
2681 default:
2682 if (dev->phy && dev->phy->ioctl) {
2683 return dev->phy->ioctl(dev, cmd, arg);
2684 } else {
2685 printk("nicstar%d: %s == NULL \n", card->index,
2686 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2687 return -ENOIOCTLCMD;
2688 }
2689 }
2690}
2691
2692#ifdef EXTRA_DEBUG
2693static void which_list(ns_dev * card, struct sk_buff *skb)
2694{
2695 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2696}
2697#endif /* EXTRA_DEBUG */
2698
2699static void ns_poll(struct timer_list *unused)
2700{
2701 int i;
2702 ns_dev *card;
2703 unsigned long flags;
2704 u32 stat_r, stat_w;
2705
2706 PRINTK("nicstar: Entering ns_poll().\n");
2707 for (i = 0; i < num_cards; i++) {
2708 card = cards[i];
2709 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2710 /* Probably it isn't worth spinning */
2711 continue;
2712 }
2713
2714 stat_w = 0;
2715 stat_r = readl(card->membase + STAT);
2716 if (stat_r & NS_STAT_TSIF)
2717 stat_w |= NS_STAT_TSIF;
2718 if (stat_r & NS_STAT_EOPDU)
2719 stat_w |= NS_STAT_EOPDU;
2720
2721 process_tsq(card);
2722 process_rsq(card);
2723
2724 writel(stat_w, card->membase + STAT);
2725 spin_unlock_irqrestore(&card->int_lock, flags);
2726 }
2727 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2728 PRINTK("nicstar: Leaving ns_poll().\n");
2729}
2730
2731static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2732 unsigned long addr)
2733{
2734 ns_dev *card;
2735 unsigned long flags;
2736
2737 card = dev->dev_data;
2738 spin_lock_irqsave(&card->res_lock, flags);
2739 while (CMD_BUSY(card)) ;
2740 writel((u32) value, card->membase + DR0);
2741 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2742 card->membase + CMD);
2743 spin_unlock_irqrestore(&card->res_lock, flags);
2744}
2745
2746static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2747{
2748 ns_dev *card;
2749 unsigned long flags;
2750 u32 data;
2751
2752 card = dev->dev_data;
2753 spin_lock_irqsave(&card->res_lock, flags);
2754 while (CMD_BUSY(card)) ;
2755 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2756 card->membase + CMD);
2757 while (CMD_BUSY(card)) ;
2758 data = readl(card->membase + DR0) & 0x000000FF;
2759 spin_unlock_irqrestore(&card->res_lock, flags);
2760 return (unsigned char)data;
2761}
2762
2763module_init(nicstar_init);
2764module_exit(nicstar_cleanup);