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1#include <linux/errno.h>
2#include <linux/kernel.h>
3#include <linux/mm.h>
4#include <linux/smp.h>
5#include <linux/prctl.h>
6#include <linux/slab.h>
7#include <linux/sched.h>
8#include <linux/module.h>
9#include <linux/pm.h>
10#include <linux/clockchips.h>
11#include <linux/random.h>
12#include <linux/user-return-notifier.h>
13#include <linux/dmi.h>
14#include <linux/utsname.h>
15#include <trace/events/power.h>
16#include <linux/hw_breakpoint.h>
17#include <asm/cpu.h>
18#include <asm/system.h>
19#include <asm/apic.h>
20#include <asm/syscalls.h>
21#include <asm/idle.h>
22#include <asm/uaccess.h>
23#include <asm/i387.h>
24#include <asm/debugreg.h>
25
26struct kmem_cache *task_xstate_cachep;
27EXPORT_SYMBOL_GPL(task_xstate_cachep);
28
29int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
30{
31 int ret;
32
33 *dst = *src;
34 if (fpu_allocated(&src->thread.fpu)) {
35 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
36 ret = fpu_alloc(&dst->thread.fpu);
37 if (ret)
38 return ret;
39 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
40 }
41 return 0;
42}
43
44void free_thread_xstate(struct task_struct *tsk)
45{
46 fpu_free(&tsk->thread.fpu);
47}
48
49void free_thread_info(struct thread_info *ti)
50{
51 free_thread_xstate(ti->task);
52 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
53}
54
55void arch_task_cache_init(void)
56{
57 task_xstate_cachep =
58 kmem_cache_create("task_xstate", xstate_size,
59 __alignof__(union thread_xstate),
60 SLAB_PANIC | SLAB_NOTRACK, NULL);
61}
62
63/*
64 * Free current thread data structures etc..
65 */
66void exit_thread(void)
67{
68 struct task_struct *me = current;
69 struct thread_struct *t = &me->thread;
70 unsigned long *bp = t->io_bitmap_ptr;
71
72 if (bp) {
73 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
74
75 t->io_bitmap_ptr = NULL;
76 clear_thread_flag(TIF_IO_BITMAP);
77 /*
78 * Careful, clear this in the TSS too:
79 */
80 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
81 t->io_bitmap_max = 0;
82 put_cpu();
83 kfree(bp);
84 }
85}
86
87void show_regs(struct pt_regs *regs)
88{
89 show_registers(regs);
90 show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0);
91}
92
93void show_regs_common(void)
94{
95 const char *vendor, *product, *board;
96
97 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
98 if (!vendor)
99 vendor = "";
100 product = dmi_get_system_info(DMI_PRODUCT_NAME);
101 if (!product)
102 product = "";
103
104 /* Board Name is optional */
105 board = dmi_get_system_info(DMI_BOARD_NAME);
106
107 printk(KERN_CONT "\n");
108 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
109 current->pid, current->comm, print_tainted(),
110 init_utsname()->release,
111 (int)strcspn(init_utsname()->version, " "),
112 init_utsname()->version);
113 printk(KERN_CONT " %s %s", vendor, product);
114 if (board)
115 printk(KERN_CONT "/%s", board);
116 printk(KERN_CONT "\n");
117}
118
119void flush_thread(void)
120{
121 struct task_struct *tsk = current;
122
123 flush_ptrace_hw_breakpoint(tsk);
124 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
125 /*
126 * Forget coprocessor state..
127 */
128 tsk->fpu_counter = 0;
129 clear_fpu(tsk);
130 clear_used_math();
131}
132
133static void hard_disable_TSC(void)
134{
135 write_cr4(read_cr4() | X86_CR4_TSD);
136}
137
138void disable_TSC(void)
139{
140 preempt_disable();
141 if (!test_and_set_thread_flag(TIF_NOTSC))
142 /*
143 * Must flip the CPU state synchronously with
144 * TIF_NOTSC in the current running context.
145 */
146 hard_disable_TSC();
147 preempt_enable();
148}
149
150static void hard_enable_TSC(void)
151{
152 write_cr4(read_cr4() & ~X86_CR4_TSD);
153}
154
155static void enable_TSC(void)
156{
157 preempt_disable();
158 if (test_and_clear_thread_flag(TIF_NOTSC))
159 /*
160 * Must flip the CPU state synchronously with
161 * TIF_NOTSC in the current running context.
162 */
163 hard_enable_TSC();
164 preempt_enable();
165}
166
167int get_tsc_mode(unsigned long adr)
168{
169 unsigned int val;
170
171 if (test_thread_flag(TIF_NOTSC))
172 val = PR_TSC_SIGSEGV;
173 else
174 val = PR_TSC_ENABLE;
175
176 return put_user(val, (unsigned int __user *)adr);
177}
178
179int set_tsc_mode(unsigned int val)
180{
181 if (val == PR_TSC_SIGSEGV)
182 disable_TSC();
183 else if (val == PR_TSC_ENABLE)
184 enable_TSC();
185 else
186 return -EINVAL;
187
188 return 0;
189}
190
191void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
192 struct tss_struct *tss)
193{
194 struct thread_struct *prev, *next;
195
196 prev = &prev_p->thread;
197 next = &next_p->thread;
198
199 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
200 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
201 unsigned long debugctl = get_debugctlmsr();
202
203 debugctl &= ~DEBUGCTLMSR_BTF;
204 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
205 debugctl |= DEBUGCTLMSR_BTF;
206
207 update_debugctlmsr(debugctl);
208 }
209
210 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
211 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
212 /* prev and next are different */
213 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
214 hard_disable_TSC();
215 else
216 hard_enable_TSC();
217 }
218
219 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
220 /*
221 * Copy the relevant range of the IO bitmap.
222 * Normally this is 128 bytes or less:
223 */
224 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
225 max(prev->io_bitmap_max, next->io_bitmap_max));
226 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
227 /*
228 * Clear any possible leftover bits:
229 */
230 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
231 }
232 propagate_user_return_notify(prev_p, next_p);
233}
234
235int sys_fork(struct pt_regs *regs)
236{
237 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
238}
239
240/*
241 * This is trivial, and on the face of it looks like it
242 * could equally well be done in user mode.
243 *
244 * Not so, for quite unobvious reasons - register pressure.
245 * In user mode vfork() cannot have a stack frame, and if
246 * done by calling the "clone()" system call directly, you
247 * do not have enough call-clobbered registers to hold all
248 * the information you need.
249 */
250int sys_vfork(struct pt_regs *regs)
251{
252 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
253 NULL, NULL);
254}
255
256long
257sys_clone(unsigned long clone_flags, unsigned long newsp,
258 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
259{
260 if (!newsp)
261 newsp = regs->sp;
262 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
263}
264
265/*
266 * This gets run with %si containing the
267 * function to call, and %di containing
268 * the "args".
269 */
270extern void kernel_thread_helper(void);
271
272/*
273 * Create a kernel thread
274 */
275int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
276{
277 struct pt_regs regs;
278
279 memset(®s, 0, sizeof(regs));
280
281 regs.si = (unsigned long) fn;
282 regs.di = (unsigned long) arg;
283
284#ifdef CONFIG_X86_32
285 regs.ds = __USER_DS;
286 regs.es = __USER_DS;
287 regs.fs = __KERNEL_PERCPU;
288 regs.gs = __KERNEL_STACK_CANARY;
289#else
290 regs.ss = __KERNEL_DS;
291#endif
292
293 regs.orig_ax = -1;
294 regs.ip = (unsigned long) kernel_thread_helper;
295 regs.cs = __KERNEL_CS | get_kernel_rpl();
296 regs.flags = X86_EFLAGS_IF | 0x2;
297
298 /* Ok, create the new process.. */
299 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
300}
301EXPORT_SYMBOL(kernel_thread);
302
303/*
304 * sys_execve() executes a new program.
305 */
306long sys_execve(const char __user *name,
307 const char __user *const __user *argv,
308 const char __user *const __user *envp, struct pt_regs *regs)
309{
310 long error;
311 char *filename;
312
313 filename = getname(name);
314 error = PTR_ERR(filename);
315 if (IS_ERR(filename))
316 return error;
317 error = do_execve(filename, argv, envp, regs);
318
319#ifdef CONFIG_X86_32
320 if (error == 0) {
321 /* Make sure we don't return using sysenter.. */
322 set_thread_flag(TIF_IRET);
323 }
324#endif
325
326 putname(filename);
327 return error;
328}
329
330/*
331 * Idle related variables and functions
332 */
333unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
334EXPORT_SYMBOL(boot_option_idle_override);
335
336/*
337 * Powermanagement idle function, if any..
338 */
339void (*pm_idle)(void);
340#ifdef CONFIG_APM_MODULE
341EXPORT_SYMBOL(pm_idle);
342#endif
343
344#ifdef CONFIG_X86_32
345/*
346 * This halt magic was a workaround for ancient floppy DMA
347 * wreckage. It should be safe to remove.
348 */
349static int hlt_counter;
350void disable_hlt(void)
351{
352 hlt_counter++;
353}
354EXPORT_SYMBOL(disable_hlt);
355
356void enable_hlt(void)
357{
358 hlt_counter--;
359}
360EXPORT_SYMBOL(enable_hlt);
361
362static inline int hlt_use_halt(void)
363{
364 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
365}
366#else
367static inline int hlt_use_halt(void)
368{
369 return 1;
370}
371#endif
372
373/*
374 * We use this if we don't have any better
375 * idle routine..
376 */
377void default_idle(void)
378{
379 if (hlt_use_halt()) {
380 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
381 trace_cpu_idle(1, smp_processor_id());
382 current_thread_info()->status &= ~TS_POLLING;
383 /*
384 * TS_POLLING-cleared state must be visible before we
385 * test NEED_RESCHED:
386 */
387 smp_mb();
388
389 if (!need_resched())
390 safe_halt(); /* enables interrupts racelessly */
391 else
392 local_irq_enable();
393 current_thread_info()->status |= TS_POLLING;
394 trace_power_end(smp_processor_id());
395 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
396 } else {
397 local_irq_enable();
398 /* loop is done by the caller */
399 cpu_relax();
400 }
401}
402#ifdef CONFIG_APM_MODULE
403EXPORT_SYMBOL(default_idle);
404#endif
405
406void stop_this_cpu(void *dummy)
407{
408 local_irq_disable();
409 /*
410 * Remove this CPU:
411 */
412 set_cpu_online(smp_processor_id(), false);
413 disable_local_APIC();
414
415 for (;;) {
416 if (hlt_works(smp_processor_id()))
417 halt();
418 }
419}
420
421static void do_nothing(void *unused)
422{
423}
424
425/*
426 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
427 * pm_idle and update to new pm_idle value. Required while changing pm_idle
428 * handler on SMP systems.
429 *
430 * Caller must have changed pm_idle to the new value before the call. Old
431 * pm_idle value will not be used by any CPU after the return of this function.
432 */
433void cpu_idle_wait(void)
434{
435 smp_mb();
436 /* kick all the CPUs so that they exit out of pm_idle */
437 smp_call_function(do_nothing, NULL, 1);
438}
439EXPORT_SYMBOL_GPL(cpu_idle_wait);
440
441/* Default MONITOR/MWAIT with no hints, used for default C1 state */
442static void mwait_idle(void)
443{
444 if (!need_resched()) {
445 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
446 trace_cpu_idle(1, smp_processor_id());
447 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
448 clflush((void *)¤t_thread_info()->flags);
449
450 __monitor((void *)¤t_thread_info()->flags, 0, 0);
451 smp_mb();
452 if (!need_resched())
453 __sti_mwait(0, 0);
454 else
455 local_irq_enable();
456 trace_power_end(smp_processor_id());
457 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
458 } else
459 local_irq_enable();
460}
461
462/*
463 * On SMP it's slightly faster (but much more power-consuming!)
464 * to poll the ->work.need_resched flag instead of waiting for the
465 * cross-CPU IPI to arrive. Use this option with caution.
466 */
467static void poll_idle(void)
468{
469 trace_power_start(POWER_CSTATE, 0, smp_processor_id());
470 trace_cpu_idle(0, smp_processor_id());
471 local_irq_enable();
472 while (!need_resched())
473 cpu_relax();
474 trace_power_end(smp_processor_id());
475 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
476}
477
478/*
479 * mwait selection logic:
480 *
481 * It depends on the CPU. For AMD CPUs that support MWAIT this is
482 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
483 * then depend on a clock divisor and current Pstate of the core. If
484 * all cores of a processor are in halt state (C1) the processor can
485 * enter the C1E (C1 enhanced) state. If mwait is used this will never
486 * happen.
487 *
488 * idle=mwait overrides this decision and forces the usage of mwait.
489 */
490
491#define MWAIT_INFO 0x05
492#define MWAIT_ECX_EXTENDED_INFO 0x01
493#define MWAIT_EDX_C1 0xf0
494
495int mwait_usable(const struct cpuinfo_x86 *c)
496{
497 u32 eax, ebx, ecx, edx;
498
499 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
500 return 1;
501
502 if (c->cpuid_level < MWAIT_INFO)
503 return 0;
504
505 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
506 /* Check, whether EDX has extended info about MWAIT */
507 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
508 return 1;
509
510 /*
511 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
512 * C1 supports MWAIT
513 */
514 return (edx & MWAIT_EDX_C1);
515}
516
517bool amd_e400_c1e_detected;
518EXPORT_SYMBOL(amd_e400_c1e_detected);
519
520static cpumask_var_t amd_e400_c1e_mask;
521
522void amd_e400_remove_cpu(int cpu)
523{
524 if (amd_e400_c1e_mask != NULL)
525 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
526}
527
528/*
529 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
530 * pending message MSR. If we detect C1E, then we handle it the same
531 * way as C3 power states (local apic timer and TSC stop)
532 */
533static void amd_e400_idle(void)
534{
535 if (need_resched())
536 return;
537
538 if (!amd_e400_c1e_detected) {
539 u32 lo, hi;
540
541 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
542
543 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
544 amd_e400_c1e_detected = true;
545 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
546 mark_tsc_unstable("TSC halt in AMD C1E");
547 printk(KERN_INFO "System has AMD C1E enabled\n");
548 }
549 }
550
551 if (amd_e400_c1e_detected) {
552 int cpu = smp_processor_id();
553
554 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
555 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
556 /*
557 * Force broadcast so ACPI can not interfere.
558 */
559 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
560 &cpu);
561 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
562 cpu);
563 }
564 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
565
566 default_idle();
567
568 /*
569 * The switch back from broadcast mode needs to be
570 * called with interrupts disabled.
571 */
572 local_irq_disable();
573 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
574 local_irq_enable();
575 } else
576 default_idle();
577}
578
579void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
580{
581#ifdef CONFIG_SMP
582 if (pm_idle == poll_idle && smp_num_siblings > 1) {
583 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
584 " performance may degrade.\n");
585 }
586#endif
587 if (pm_idle)
588 return;
589
590 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
591 /*
592 * One CPU supports mwait => All CPUs supports mwait
593 */
594 printk(KERN_INFO "using mwait in idle threads.\n");
595 pm_idle = mwait_idle;
596 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
597 /* E400: APIC timer interrupt does not wake up CPU from C1e */
598 printk(KERN_INFO "using AMD E400 aware idle routine\n");
599 pm_idle = amd_e400_idle;
600 } else
601 pm_idle = default_idle;
602}
603
604void __init init_amd_e400_c1e_mask(void)
605{
606 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
607 if (pm_idle == amd_e400_idle)
608 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
609}
610
611static int __init idle_setup(char *str)
612{
613 if (!str)
614 return -EINVAL;
615
616 if (!strcmp(str, "poll")) {
617 printk("using polling idle threads.\n");
618 pm_idle = poll_idle;
619 boot_option_idle_override = IDLE_POLL;
620 } else if (!strcmp(str, "mwait")) {
621 boot_option_idle_override = IDLE_FORCE_MWAIT;
622 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
623 } else if (!strcmp(str, "halt")) {
624 /*
625 * When the boot option of idle=halt is added, halt is
626 * forced to be used for CPU idle. In such case CPU C2/C3
627 * won't be used again.
628 * To continue to load the CPU idle driver, don't touch
629 * the boot_option_idle_override.
630 */
631 pm_idle = default_idle;
632 boot_option_idle_override = IDLE_HALT;
633 } else if (!strcmp(str, "nomwait")) {
634 /*
635 * If the boot option of "idle=nomwait" is added,
636 * it means that mwait will be disabled for CPU C2/C3
637 * states. In such case it won't touch the variable
638 * of boot_option_idle_override.
639 */
640 boot_option_idle_override = IDLE_NOMWAIT;
641 } else
642 return -1;
643
644 return 0;
645}
646early_param("idle", idle_setup);
647
648unsigned long arch_align_stack(unsigned long sp)
649{
650 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
651 sp -= get_random_int() % 8192;
652 return sp & ~0xf;
653}
654
655unsigned long arch_randomize_brk(struct mm_struct *mm)
656{
657 unsigned long range_end = mm->brk + 0x02000000;
658 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
659}
660
1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <linux/acpi.h>
26#include <linux/elf-randomize.h>
27#include <trace/events/power.h>
28#include <linux/hw_breakpoint.h>
29#include <asm/cpu.h>
30#include <asm/apic.h>
31#include <linux/uaccess.h>
32#include <asm/mwait.h>
33#include <asm/fpu/internal.h>
34#include <asm/debugreg.h>
35#include <asm/nmi.h>
36#include <asm/tlbflush.h>
37#include <asm/mce.h>
38#include <asm/vm86.h>
39#include <asm/switch_to.h>
40#include <asm/desc.h>
41#include <asm/prctl.h>
42#include <asm/spec-ctrl.h>
43#include <asm/io_bitmap.h>
44#include <asm/proto.h>
45#include <asm/frame.h>
46
47#include "process.h"
48
49/*
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
55 */
56__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
57 .x86_tss = {
58 /*
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
62 * Poison it.
63 */
64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
65
66#ifdef CONFIG_X86_32
67 .sp1 = TOP_OF_INIT_STACK,
68
69 .ss0 = __KERNEL_DS,
70 .ss1 = __KERNEL_CS,
71#endif
72 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
73 },
74};
75EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
76
77DEFINE_PER_CPU(bool, __tss_limit_invalid);
78EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
79
80/*
81 * this gets called so that we can store lazy state into memory and copy the
82 * current task into the new thread.
83 */
84int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
85{
86 memcpy(dst, src, arch_task_struct_size);
87#ifdef CONFIG_VM86
88 dst->thread.vm86 = NULL;
89#endif
90 return fpu_clone(dst);
91}
92
93/*
94 * Free thread data structures etc..
95 */
96void exit_thread(struct task_struct *tsk)
97{
98 struct thread_struct *t = &tsk->thread;
99 struct fpu *fpu = &t->fpu;
100
101 if (test_thread_flag(TIF_IO_BITMAP))
102 io_bitmap_exit(tsk);
103
104 free_vm86(t);
105
106 fpu__drop(fpu);
107}
108
109static int set_new_tls(struct task_struct *p, unsigned long tls)
110{
111 struct user_desc __user *utls = (struct user_desc __user *)tls;
112
113 if (in_ia32_syscall())
114 return do_set_thread_area(p, -1, utls, 0);
115 else
116 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
117}
118
119int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
120 struct task_struct *p, unsigned long tls)
121{
122 struct inactive_task_frame *frame;
123 struct fork_frame *fork_frame;
124 struct pt_regs *childregs;
125 int ret = 0;
126
127 childregs = task_pt_regs(p);
128 fork_frame = container_of(childregs, struct fork_frame, regs);
129 frame = &fork_frame->frame;
130
131 frame->bp = encode_frame_pointer(childregs);
132 frame->ret_addr = (unsigned long) ret_from_fork;
133 p->thread.sp = (unsigned long) fork_frame;
134 p->thread.io_bitmap = NULL;
135 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
136
137#ifdef CONFIG_X86_64
138 current_save_fsgs();
139 p->thread.fsindex = current->thread.fsindex;
140 p->thread.fsbase = current->thread.fsbase;
141 p->thread.gsindex = current->thread.gsindex;
142 p->thread.gsbase = current->thread.gsbase;
143
144 savesegment(es, p->thread.es);
145 savesegment(ds, p->thread.ds);
146#else
147 p->thread.sp0 = (unsigned long) (childregs + 1);
148 /*
149 * Clear all status flags including IF and set fixed bit. 64bit
150 * does not have this initialization as the frame does not contain
151 * flags. The flags consistency (especially vs. AC) is there
152 * ensured via objtool, which lacks 32bit support.
153 */
154 frame->flags = X86_EFLAGS_FIXED;
155#endif
156
157 /* Kernel thread ? */
158 if (unlikely(p->flags & PF_KTHREAD)) {
159 p->thread.pkru = pkru_get_init_value();
160 memset(childregs, 0, sizeof(struct pt_regs));
161 kthread_frame_init(frame, sp, arg);
162 return 0;
163 }
164
165 /*
166 * Clone current's PKRU value from hardware. tsk->thread.pkru
167 * is only valid when scheduled out.
168 */
169 p->thread.pkru = read_pkru();
170
171 frame->bx = 0;
172 *childregs = *current_pt_regs();
173 childregs->ax = 0;
174 if (sp)
175 childregs->sp = sp;
176
177#ifdef CONFIG_X86_32
178 task_user_gs(p) = get_user_gs(current_pt_regs());
179#endif
180
181 if (unlikely(p->flags & PF_IO_WORKER)) {
182 /*
183 * An IO thread is a user space thread, but it doesn't
184 * return to ret_after_fork().
185 *
186 * In order to indicate that to tools like gdb,
187 * we reset the stack and instruction pointers.
188 *
189 * It does the same kernel frame setup to return to a kernel
190 * function that a kernel thread does.
191 */
192 childregs->sp = 0;
193 childregs->ip = 0;
194 kthread_frame_init(frame, sp, arg);
195 return 0;
196 }
197
198 /* Set a new TLS for the child thread? */
199 if (clone_flags & CLONE_SETTLS)
200 ret = set_new_tls(p, tls);
201
202 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
203 io_bitmap_share(p);
204
205 return ret;
206}
207
208static void pkru_flush_thread(void)
209{
210 /*
211 * If PKRU is enabled the default PKRU value has to be loaded into
212 * the hardware right here (similar to context switch).
213 */
214 pkru_write_default();
215}
216
217void flush_thread(void)
218{
219 struct task_struct *tsk = current;
220
221 flush_ptrace_hw_breakpoint(tsk);
222 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
223
224 fpu_flush_thread();
225 pkru_flush_thread();
226}
227
228void disable_TSC(void)
229{
230 preempt_disable();
231 if (!test_and_set_thread_flag(TIF_NOTSC))
232 /*
233 * Must flip the CPU state synchronously with
234 * TIF_NOTSC in the current running context.
235 */
236 cr4_set_bits(X86_CR4_TSD);
237 preempt_enable();
238}
239
240static void enable_TSC(void)
241{
242 preempt_disable();
243 if (test_and_clear_thread_flag(TIF_NOTSC))
244 /*
245 * Must flip the CPU state synchronously with
246 * TIF_NOTSC in the current running context.
247 */
248 cr4_clear_bits(X86_CR4_TSD);
249 preempt_enable();
250}
251
252int get_tsc_mode(unsigned long adr)
253{
254 unsigned int val;
255
256 if (test_thread_flag(TIF_NOTSC))
257 val = PR_TSC_SIGSEGV;
258 else
259 val = PR_TSC_ENABLE;
260
261 return put_user(val, (unsigned int __user *)adr);
262}
263
264int set_tsc_mode(unsigned int val)
265{
266 if (val == PR_TSC_SIGSEGV)
267 disable_TSC();
268 else if (val == PR_TSC_ENABLE)
269 enable_TSC();
270 else
271 return -EINVAL;
272
273 return 0;
274}
275
276DEFINE_PER_CPU(u64, msr_misc_features_shadow);
277
278static void set_cpuid_faulting(bool on)
279{
280 u64 msrval;
281
282 msrval = this_cpu_read(msr_misc_features_shadow);
283 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
284 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
285 this_cpu_write(msr_misc_features_shadow, msrval);
286 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
287}
288
289static void disable_cpuid(void)
290{
291 preempt_disable();
292 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
293 /*
294 * Must flip the CPU state synchronously with
295 * TIF_NOCPUID in the current running context.
296 */
297 set_cpuid_faulting(true);
298 }
299 preempt_enable();
300}
301
302static void enable_cpuid(void)
303{
304 preempt_disable();
305 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
306 /*
307 * Must flip the CPU state synchronously with
308 * TIF_NOCPUID in the current running context.
309 */
310 set_cpuid_faulting(false);
311 }
312 preempt_enable();
313}
314
315static int get_cpuid_mode(void)
316{
317 return !test_thread_flag(TIF_NOCPUID);
318}
319
320static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
321{
322 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
323 return -ENODEV;
324
325 if (cpuid_enabled)
326 enable_cpuid();
327 else
328 disable_cpuid();
329
330 return 0;
331}
332
333/*
334 * Called immediately after a successful exec.
335 */
336void arch_setup_new_exec(void)
337{
338 /* If cpuid was previously disabled for this task, re-enable it. */
339 if (test_thread_flag(TIF_NOCPUID))
340 enable_cpuid();
341
342 /*
343 * Don't inherit TIF_SSBD across exec boundary when
344 * PR_SPEC_DISABLE_NOEXEC is used.
345 */
346 if (test_thread_flag(TIF_SSBD) &&
347 task_spec_ssb_noexec(current)) {
348 clear_thread_flag(TIF_SSBD);
349 task_clear_spec_ssb_disable(current);
350 task_clear_spec_ssb_noexec(current);
351 speculation_ctrl_update(task_thread_info(current)->flags);
352 }
353}
354
355#ifdef CONFIG_X86_IOPL_IOPERM
356static inline void switch_to_bitmap(unsigned long tifp)
357{
358 /*
359 * Invalidate I/O bitmap if the previous task used it. This prevents
360 * any possible leakage of an active I/O bitmap.
361 *
362 * If the next task has an I/O bitmap it will handle it on exit to
363 * user mode.
364 */
365 if (tifp & _TIF_IO_BITMAP)
366 tss_invalidate_io_bitmap();
367}
368
369static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
370{
371 /*
372 * Copy at least the byte range of the incoming tasks bitmap which
373 * covers the permitted I/O ports.
374 *
375 * If the previous task which used an I/O bitmap had more bits
376 * permitted, then the copy needs to cover those as well so they
377 * get turned off.
378 */
379 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
380 max(tss->io_bitmap.prev_max, iobm->max));
381
382 /*
383 * Store the new max and the sequence number of this bitmap
384 * and a pointer to the bitmap itself.
385 */
386 tss->io_bitmap.prev_max = iobm->max;
387 tss->io_bitmap.prev_sequence = iobm->sequence;
388}
389
390/**
391 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
392 */
393void native_tss_update_io_bitmap(void)
394{
395 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
396 struct thread_struct *t = ¤t->thread;
397 u16 *base = &tss->x86_tss.io_bitmap_base;
398
399 if (!test_thread_flag(TIF_IO_BITMAP)) {
400 native_tss_invalidate_io_bitmap();
401 return;
402 }
403
404 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
405 *base = IO_BITMAP_OFFSET_VALID_ALL;
406 } else {
407 struct io_bitmap *iobm = t->io_bitmap;
408
409 /*
410 * Only copy bitmap data when the sequence number differs. The
411 * update time is accounted to the incoming task.
412 */
413 if (tss->io_bitmap.prev_sequence != iobm->sequence)
414 tss_copy_io_bitmap(tss, iobm);
415
416 /* Enable the bitmap */
417 *base = IO_BITMAP_OFFSET_VALID_MAP;
418 }
419
420 /*
421 * Make sure that the TSS limit is covering the IO bitmap. It might have
422 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
423 * access from user space to trigger a #GP because tbe bitmap is outside
424 * the TSS limit.
425 */
426 refresh_tss_limit();
427}
428#else /* CONFIG_X86_IOPL_IOPERM */
429static inline void switch_to_bitmap(unsigned long tifp) { }
430#endif
431
432#ifdef CONFIG_SMP
433
434struct ssb_state {
435 struct ssb_state *shared_state;
436 raw_spinlock_t lock;
437 unsigned int disable_state;
438 unsigned long local_state;
439};
440
441#define LSTATE_SSB 0
442
443static DEFINE_PER_CPU(struct ssb_state, ssb_state);
444
445void speculative_store_bypass_ht_init(void)
446{
447 struct ssb_state *st = this_cpu_ptr(&ssb_state);
448 unsigned int this_cpu = smp_processor_id();
449 unsigned int cpu;
450
451 st->local_state = 0;
452
453 /*
454 * Shared state setup happens once on the first bringup
455 * of the CPU. It's not destroyed on CPU hotunplug.
456 */
457 if (st->shared_state)
458 return;
459
460 raw_spin_lock_init(&st->lock);
461
462 /*
463 * Go over HT siblings and check whether one of them has set up the
464 * shared state pointer already.
465 */
466 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
467 if (cpu == this_cpu)
468 continue;
469
470 if (!per_cpu(ssb_state, cpu).shared_state)
471 continue;
472
473 /* Link it to the state of the sibling: */
474 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
475 return;
476 }
477
478 /*
479 * First HT sibling to come up on the core. Link shared state of
480 * the first HT sibling to itself. The siblings on the same core
481 * which come up later will see the shared state pointer and link
482 * themselves to the state of this CPU.
483 */
484 st->shared_state = st;
485}
486
487/*
488 * Logic is: First HT sibling enables SSBD for both siblings in the core
489 * and last sibling to disable it, disables it for the whole core. This how
490 * MSR_SPEC_CTRL works in "hardware":
491 *
492 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
493 */
494static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
495{
496 struct ssb_state *st = this_cpu_ptr(&ssb_state);
497 u64 msr = x86_amd_ls_cfg_base;
498
499 if (!static_cpu_has(X86_FEATURE_ZEN)) {
500 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
501 wrmsrl(MSR_AMD64_LS_CFG, msr);
502 return;
503 }
504
505 if (tifn & _TIF_SSBD) {
506 /*
507 * Since this can race with prctl(), block reentry on the
508 * same CPU.
509 */
510 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
511 return;
512
513 msr |= x86_amd_ls_cfg_ssbd_mask;
514
515 raw_spin_lock(&st->shared_state->lock);
516 /* First sibling enables SSBD: */
517 if (!st->shared_state->disable_state)
518 wrmsrl(MSR_AMD64_LS_CFG, msr);
519 st->shared_state->disable_state++;
520 raw_spin_unlock(&st->shared_state->lock);
521 } else {
522 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
523 return;
524
525 raw_spin_lock(&st->shared_state->lock);
526 st->shared_state->disable_state--;
527 if (!st->shared_state->disable_state)
528 wrmsrl(MSR_AMD64_LS_CFG, msr);
529 raw_spin_unlock(&st->shared_state->lock);
530 }
531}
532#else
533static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
534{
535 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
536
537 wrmsrl(MSR_AMD64_LS_CFG, msr);
538}
539#endif
540
541static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
542{
543 /*
544 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
545 * so ssbd_tif_to_spec_ctrl() just works.
546 */
547 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
548}
549
550/*
551 * Update the MSRs managing speculation control, during context switch.
552 *
553 * tifp: Previous task's thread flags
554 * tifn: Next task's thread flags
555 */
556static __always_inline void __speculation_ctrl_update(unsigned long tifp,
557 unsigned long tifn)
558{
559 unsigned long tif_diff = tifp ^ tifn;
560 u64 msr = x86_spec_ctrl_base;
561 bool updmsr = false;
562
563 lockdep_assert_irqs_disabled();
564
565 /* Handle change of TIF_SSBD depending on the mitigation method. */
566 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
567 if (tif_diff & _TIF_SSBD)
568 amd_set_ssb_virt_state(tifn);
569 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
570 if (tif_diff & _TIF_SSBD)
571 amd_set_core_ssb_state(tifn);
572 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
573 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
574 updmsr |= !!(tif_diff & _TIF_SSBD);
575 msr |= ssbd_tif_to_spec_ctrl(tifn);
576 }
577
578 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
579 if (IS_ENABLED(CONFIG_SMP) &&
580 static_branch_unlikely(&switch_to_cond_stibp)) {
581 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
582 msr |= stibp_tif_to_spec_ctrl(tifn);
583 }
584
585 if (updmsr)
586 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
587}
588
589static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
590{
591 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
592 if (task_spec_ssb_disable(tsk))
593 set_tsk_thread_flag(tsk, TIF_SSBD);
594 else
595 clear_tsk_thread_flag(tsk, TIF_SSBD);
596
597 if (task_spec_ib_disable(tsk))
598 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
599 else
600 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
601 }
602 /* Return the updated threadinfo flags*/
603 return task_thread_info(tsk)->flags;
604}
605
606void speculation_ctrl_update(unsigned long tif)
607{
608 unsigned long flags;
609
610 /* Forced update. Make sure all relevant TIF flags are different */
611 local_irq_save(flags);
612 __speculation_ctrl_update(~tif, tif);
613 local_irq_restore(flags);
614}
615
616/* Called from seccomp/prctl update */
617void speculation_ctrl_update_current(void)
618{
619 preempt_disable();
620 speculation_ctrl_update(speculation_ctrl_update_tif(current));
621 preempt_enable();
622}
623
624static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
625{
626 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
627
628 newval = cr4 ^ mask;
629 if (newval != cr4) {
630 this_cpu_write(cpu_tlbstate.cr4, newval);
631 __write_cr4(newval);
632 }
633}
634
635void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
636{
637 unsigned long tifp, tifn;
638
639 tifn = READ_ONCE(task_thread_info(next_p)->flags);
640 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
641
642 switch_to_bitmap(tifp);
643
644 propagate_user_return_notify(prev_p, next_p);
645
646 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
647 arch_has_block_step()) {
648 unsigned long debugctl, msk;
649
650 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
651 debugctl &= ~DEBUGCTLMSR_BTF;
652 msk = tifn & _TIF_BLOCKSTEP;
653 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
654 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
655 }
656
657 if ((tifp ^ tifn) & _TIF_NOTSC)
658 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
659
660 if ((tifp ^ tifn) & _TIF_NOCPUID)
661 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
662
663 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
664 __speculation_ctrl_update(tifp, tifn);
665 } else {
666 speculation_ctrl_update_tif(prev_p);
667 tifn = speculation_ctrl_update_tif(next_p);
668
669 /* Enforce MSR update to ensure consistent state */
670 __speculation_ctrl_update(~tifn, tifn);
671 }
672
673 if ((tifp ^ tifn) & _TIF_SLD)
674 switch_to_sld(tifn);
675}
676
677/*
678 * Idle related variables and functions
679 */
680unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
681EXPORT_SYMBOL(boot_option_idle_override);
682
683static void (*x86_idle)(void);
684
685#ifndef CONFIG_SMP
686static inline void play_dead(void)
687{
688 BUG();
689}
690#endif
691
692void arch_cpu_idle_enter(void)
693{
694 tsc_verify_tsc_adjust(false);
695 local_touch_nmi();
696}
697
698void arch_cpu_idle_dead(void)
699{
700 play_dead();
701}
702
703/*
704 * Called from the generic idle code.
705 */
706void arch_cpu_idle(void)
707{
708 x86_idle();
709}
710
711/*
712 * We use this if we don't have any better idle routine..
713 */
714void __cpuidle default_idle(void)
715{
716 raw_safe_halt();
717}
718#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
719EXPORT_SYMBOL(default_idle);
720#endif
721
722#ifdef CONFIG_XEN
723bool xen_set_default_idle(void)
724{
725 bool ret = !!x86_idle;
726
727 x86_idle = default_idle;
728
729 return ret;
730}
731#endif
732
733void stop_this_cpu(void *dummy)
734{
735 local_irq_disable();
736 /*
737 * Remove this CPU:
738 */
739 set_cpu_online(smp_processor_id(), false);
740 disable_local_APIC();
741 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
742
743 /*
744 * Use wbinvd on processors that support SME. This provides support
745 * for performing a successful kexec when going from SME inactive
746 * to SME active (or vice-versa). The cache must be cleared so that
747 * if there are entries with the same physical address, both with and
748 * without the encryption bit, they don't race each other when flushed
749 * and potentially end up with the wrong entry being committed to
750 * memory.
751 */
752 if (boot_cpu_has(X86_FEATURE_SME))
753 native_wbinvd();
754 for (;;) {
755 /*
756 * Use native_halt() so that memory contents don't change
757 * (stack usage and variables) after possibly issuing the
758 * native_wbinvd() above.
759 */
760 native_halt();
761 }
762}
763
764/*
765 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
766 * states (local apic timer and TSC stop).
767 *
768 * XXX this function is completely buggered vs RCU and tracing.
769 */
770static void amd_e400_idle(void)
771{
772 /*
773 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
774 * gets set after static_cpu_has() places have been converted via
775 * alternatives.
776 */
777 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
778 default_idle();
779 return;
780 }
781
782 tick_broadcast_enter();
783
784 default_idle();
785
786 /*
787 * The switch back from broadcast mode needs to be called with
788 * interrupts disabled.
789 */
790 raw_local_irq_disable();
791 tick_broadcast_exit();
792 raw_local_irq_enable();
793}
794
795/*
796 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
797 * We can't rely on cpuidle installing MWAIT, because it will not load
798 * on systems that support only C1 -- so the boot default must be MWAIT.
799 *
800 * Some AMD machines are the opposite, they depend on using HALT.
801 *
802 * So for default C1, which is used during boot until cpuidle loads,
803 * use MWAIT-C1 on Intel HW that has it, else use HALT.
804 */
805static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
806{
807 if (c->x86_vendor != X86_VENDOR_INTEL)
808 return 0;
809
810 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
811 return 0;
812
813 return 1;
814}
815
816/*
817 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
818 * with interrupts enabled and no flags, which is backwards compatible with the
819 * original MWAIT implementation.
820 */
821static __cpuidle void mwait_idle(void)
822{
823 if (!current_set_polling_and_test()) {
824 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
825 mb(); /* quirk */
826 clflush((void *)¤t_thread_info()->flags);
827 mb(); /* quirk */
828 }
829
830 __monitor((void *)¤t_thread_info()->flags, 0, 0);
831 if (!need_resched())
832 __sti_mwait(0, 0);
833 else
834 raw_local_irq_enable();
835 } else {
836 raw_local_irq_enable();
837 }
838 __current_clr_polling();
839}
840
841void select_idle_routine(const struct cpuinfo_x86 *c)
842{
843#ifdef CONFIG_SMP
844 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
845 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
846#endif
847 if (x86_idle || boot_option_idle_override == IDLE_POLL)
848 return;
849
850 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
851 pr_info("using AMD E400 aware idle routine\n");
852 x86_idle = amd_e400_idle;
853 } else if (prefer_mwait_c1_over_halt(c)) {
854 pr_info("using mwait in idle threads\n");
855 x86_idle = mwait_idle;
856 } else
857 x86_idle = default_idle;
858}
859
860void amd_e400_c1e_apic_setup(void)
861{
862 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
863 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
864 local_irq_disable();
865 tick_broadcast_force();
866 local_irq_enable();
867 }
868}
869
870void __init arch_post_acpi_subsys_init(void)
871{
872 u32 lo, hi;
873
874 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
875 return;
876
877 /*
878 * AMD E400 detection needs to happen after ACPI has been enabled. If
879 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
880 * MSR_K8_INT_PENDING_MSG.
881 */
882 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
883 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
884 return;
885
886 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
887
888 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
889 mark_tsc_unstable("TSC halt in AMD C1E");
890 pr_info("System has AMD C1E enabled\n");
891}
892
893static int __init idle_setup(char *str)
894{
895 if (!str)
896 return -EINVAL;
897
898 if (!strcmp(str, "poll")) {
899 pr_info("using polling idle threads\n");
900 boot_option_idle_override = IDLE_POLL;
901 cpu_idle_poll_ctrl(true);
902 } else if (!strcmp(str, "halt")) {
903 /*
904 * When the boot option of idle=halt is added, halt is
905 * forced to be used for CPU idle. In such case CPU C2/C3
906 * won't be used again.
907 * To continue to load the CPU idle driver, don't touch
908 * the boot_option_idle_override.
909 */
910 x86_idle = default_idle;
911 boot_option_idle_override = IDLE_HALT;
912 } else if (!strcmp(str, "nomwait")) {
913 /*
914 * If the boot option of "idle=nomwait" is added,
915 * it means that mwait will be disabled for CPU C2/C3
916 * states. In such case it won't touch the variable
917 * of boot_option_idle_override.
918 */
919 boot_option_idle_override = IDLE_NOMWAIT;
920 } else
921 return -1;
922
923 return 0;
924}
925early_param("idle", idle_setup);
926
927unsigned long arch_align_stack(unsigned long sp)
928{
929 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
930 sp -= get_random_int() % 8192;
931 return sp & ~0xf;
932}
933
934unsigned long arch_randomize_brk(struct mm_struct *mm)
935{
936 return randomize_page(mm->brk, 0x02000000);
937}
938
939/*
940 * Called from fs/proc with a reference on @p to find the function
941 * which called into schedule(). This needs to be done carefully
942 * because the task might wake up and we might look at a stack
943 * changing under us.
944 */
945unsigned long get_wchan(struct task_struct *p)
946{
947 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
948 int count = 0;
949
950 if (p == current || task_is_running(p))
951 return 0;
952
953 if (!try_get_task_stack(p))
954 return 0;
955
956 start = (unsigned long)task_stack_page(p);
957 if (!start)
958 goto out;
959
960 /*
961 * Layout of the stack page:
962 *
963 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
964 * PADDING
965 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
966 * stack
967 * ----------- bottom = start
968 *
969 * The tasks stack pointer points at the location where the
970 * framepointer is stored. The data on the stack is:
971 * ... IP FP ... IP FP
972 *
973 * We need to read FP and IP, so we need to adjust the upper
974 * bound by another unsigned long.
975 */
976 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
977 top -= 2 * sizeof(unsigned long);
978 bottom = start;
979
980 sp = READ_ONCE(p->thread.sp);
981 if (sp < bottom || sp > top)
982 goto out;
983
984 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
985 do {
986 if (fp < bottom || fp > top)
987 goto out;
988 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
989 if (!in_sched_functions(ip)) {
990 ret = ip;
991 goto out;
992 }
993 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
994 } while (count++ < 16 && !task_is_running(p));
995
996out:
997 put_task_stack(p);
998 return ret;
999}
1000
1001long do_arch_prctl_common(struct task_struct *task, int option,
1002 unsigned long cpuid_enabled)
1003{
1004 switch (option) {
1005 case ARCH_GET_CPUID:
1006 return get_cpuid_mode();
1007 case ARCH_SET_CPUID:
1008 return set_cpuid_mode(task, cpuid_enabled);
1009 }
1010
1011 return -EINVAL;
1012}