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1/*
2 * traps.h: Format of entries for the Sparc trap table.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7#ifndef _SPARC_TRAPS_H
8#define _SPARC_TRAPS_H
9
10#define NUM_SPARC_TRAPS 255
11
12#ifndef __ASSEMBLY__
13#ifdef __KERNEL__
14/* This is for V8 compliant Sparc CPUS */
15struct tt_entry {
16 unsigned long inst_one;
17 unsigned long inst_two;
18 unsigned long inst_three;
19 unsigned long inst_four;
20};
21
22/* We set this to _start in system setup. */
23extern struct tt_entry *sparc_ttable;
24
25#endif /* (__KERNEL__) */
26#endif /* !(__ASSEMBLY__) */
27
28/* For patching the trap table at boot time, we need to know how to
29 * form various common Sparc instructions. Thus these macros...
30 */
31
32#define SPARC_MOV_CONST_L3(const) (0xa6102000 | (const&0xfff))
33
34/* The following assumes that the branch lies before the place we
35 * are branching to. This is the case for a trap vector...
36 * You have been warned.
37 */
38#define SPARC_BRANCH(dest_addr, inst_addr) \
39 (0x10800000 | (((dest_addr-inst_addr)>>2)&0x3fffff))
40
41#define SPARC_RD_PSR_L0 (0xa1480000)
42#define SPARC_RD_WIM_L3 (0xa7500000)
43#define SPARC_NOP (0x01000000)
44
45/* Various interesting trap levels. */
46/* First, hardware traps. */
47#define SP_TRAP_TFLT 0x1 /* Text fault */
48#define SP_TRAP_II 0x2 /* Illegal Instruction */
49#define SP_TRAP_PI 0x3 /* Privileged Instruction */
50#define SP_TRAP_FPD 0x4 /* Floating Point Disabled */
51#define SP_TRAP_WOVF 0x5 /* Window Overflow */
52#define SP_TRAP_WUNF 0x6 /* Window Underflow */
53#define SP_TRAP_MNA 0x7 /* Memory Address Unaligned */
54#define SP_TRAP_FPE 0x8 /* Floating Point Exception */
55#define SP_TRAP_DFLT 0x9 /* Data Fault */
56#define SP_TRAP_TOF 0xa /* Tag Overflow */
57#define SP_TRAP_WDOG 0xb /* Watchpoint Detected */
58#define SP_TRAP_IRQ1 0x11 /* IRQ level 1 */
59#define SP_TRAP_IRQ2 0x12 /* IRQ level 2 */
60#define SP_TRAP_IRQ3 0x13 /* IRQ level 3 */
61#define SP_TRAP_IRQ4 0x14 /* IRQ level 4 */
62#define SP_TRAP_IRQ5 0x15 /* IRQ level 5 */
63#define SP_TRAP_IRQ6 0x16 /* IRQ level 6 */
64#define SP_TRAP_IRQ7 0x17 /* IRQ level 7 */
65#define SP_TRAP_IRQ8 0x18 /* IRQ level 8 */
66#define SP_TRAP_IRQ9 0x19 /* IRQ level 9 */
67#define SP_TRAP_IRQ10 0x1a /* IRQ level 10 */
68#define SP_TRAP_IRQ11 0x1b /* IRQ level 11 */
69#define SP_TRAP_IRQ12 0x1c /* IRQ level 12 */
70#define SP_TRAP_IRQ13 0x1d /* IRQ level 13 */
71#define SP_TRAP_IRQ14 0x1e /* IRQ level 14 */
72#define SP_TRAP_IRQ15 0x1f /* IRQ level 15 Non-maskable */
73#define SP_TRAP_RACC 0x20 /* Register Access Error ??? */
74#define SP_TRAP_IACC 0x21 /* Instruction Access Error */
75#define SP_TRAP_CPDIS 0x24 /* Co-Processor Disabled */
76#define SP_TRAP_BADFL 0x25 /* Unimplemented Flush Instruction */
77#define SP_TRAP_CPEXP 0x28 /* Co-Processor Exception */
78#define SP_TRAP_DACC 0x29 /* Data Access Error */
79#define SP_TRAP_DIVZ 0x2a /* Divide By Zero */
80#define SP_TRAP_DSTORE 0x2b /* Data Store Error ??? */
81#define SP_TRAP_DMM 0x2c /* Data Access MMU Miss ??? */
82#define SP_TRAP_IMM 0x3c /* Instruction Access MMU Miss ??? */
83
84/* Now the Software Traps... */
85#define SP_TRAP_SUNOS 0x80 /* SunOS System Call */
86#define SP_TRAP_SBPT 0x81 /* Software Breakpoint */
87#define SP_TRAP_SDIVZ 0x82 /* Software Divide-by-Zero trap */
88#define SP_TRAP_FWIN 0x83 /* Flush Windows */
89#define SP_TRAP_CWIN 0x84 /* Clean Windows */
90#define SP_TRAP_RCHK 0x85 /* Range Check */
91#define SP_TRAP_FUNA 0x86 /* Fix Unaligned Access */
92#define SP_TRAP_IOWFL 0x87 /* Integer Overflow */
93#define SP_TRAP_SOLARIS 0x88 /* Solaris System Call */
94#define SP_TRAP_NETBSD 0x89 /* NetBSD System Call */
95#define SP_TRAP_LINUX 0x90 /* Linux System Call */
96
97/* Names used for compatibility with SunOS */
98#define ST_SYSCALL 0x00
99#define ST_BREAKPOINT 0x01
100#define ST_DIV0 0x02
101#define ST_FLUSH_WINDOWS 0x03
102#define ST_CLEAN_WINDOWS 0x04
103#define ST_RANGE_CHECK 0x05
104#define ST_FIX_ALIGN 0x06
105#define ST_INT_OVERFLOW 0x07
106
107/* Special traps... */
108#define SP_TRAP_KBPT1 0xfe /* KADB/PROM Breakpoint one */
109#define SP_TRAP_KBPT2 0xff /* KADB/PROM Breakpoint two */
110
111/* Handy Macros */
112/* Is this a trap we never expect to get? */
113#define BAD_TRAP_P(level) \
114 ((level > SP_TRAP_WDOG && level < SP_TRAP_IRQ1) || \
115 (level > SP_TRAP_IACC && level < SP_TRAP_CPDIS) || \
116 (level > SP_TRAP_BADFL && level < SP_TRAP_CPEXP) || \
117 (level > SP_TRAP_DMM && level < SP_TRAP_IMM) || \
118 (level > SP_TRAP_IMM && level < SP_TRAP_SUNOS) || \
119 (level > SP_TRAP_LINUX && level < SP_TRAP_KBPT1))
120
121/* Is this a Hardware trap? */
122#define HW_TRAP_P(level) ((level > 0) && (level < SP_TRAP_SUNOS))
123
124/* Is this a Software trap? */
125#define SW_TRAP_P(level) ((level >= SP_TRAP_SUNOS) && (level <= SP_TRAP_KBPT2))
126
127/* Is this a system call for some OS we know about? */
128#define SCALL_TRAP_P(level) ((level == SP_TRAP_SUNOS) || \
129 (level == SP_TRAP_SOLARIS) || \
130 (level == SP_TRAP_NETBSD) || \
131 (level == SP_TRAP_LINUX))
132
133#endif /* !(_SPARC_TRAPS_H) */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * traps.h: Format of entries for the Sparc trap table.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7#ifndef _SPARC_TRAPS_H
8#define _SPARC_TRAPS_H
9
10#include <uapi/asm/traps.h>
11
12#ifndef __ASSEMBLY__
13/* This is for V8 compliant Sparc CPUS */
14struct tt_entry {
15 unsigned long inst_one;
16 unsigned long inst_two;
17 unsigned long inst_three;
18 unsigned long inst_four;
19};
20
21/* We set this to _start in system setup. */
22extern struct tt_entry *sparc_ttable;
23
24#endif /* !(__ASSEMBLY__) */
25#endif /* !(_SPARC_TRAPS_H) */