1/*
 2 * timer.h:  Definitions for the timer chips on the Sparc.
 3 *
 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 5 */
 6
 7
 8#ifndef _SPARC_TIMER_H
 9#define _SPARC_TIMER_H
10
11#include <asm/system.h>  /* For SUN4M_NCPUS */
12#include <asm/btfixup.h>
13
14extern __volatile__ unsigned int *master_l10_counter;
15
16/* FIXME: Make do_[gs]ettimeofday btfixup calls */
17BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
18#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
19
20#endif /* !(_SPARC_TIMER_H) */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * timer.h:  Definitions for the timer chips on the Sparc.
 4 *
 5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 6 */
 7
 8
 9#ifndef _SPARC_TIMER_H
10#define _SPARC_TIMER_H
11
12#include <linux/clocksource.h>
13#include <linux/irqreturn.h>
14
15#include <asm-generic/percpu.h>
16
17#include <asm/cpu_type.h>  /* For SUN4M_NCPUS */
18
19#define SBUS_CLOCK_RATE   2000000 /* 2MHz */
20#define TIMER_VALUE_SHIFT 9
21#define TIMER_VALUE_MASK  0x3fffff
22#define TIMER_LIMIT_BIT   (1 << 31)  /* Bit 31 in Counter-Timer register */
23
24/* The counter timer register has the value offset by 9 bits.
25 * From sun4m manual:
26 * When a counter reaches the value in the corresponding limit register,
27 * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200).
28 *
29 * To compensate for this add one to the value.
30 */
31static inline unsigned int timer_value(unsigned int value)
32{
33	return (value + 1) << TIMER_VALUE_SHIFT;
34}
35
36extern volatile u32 __iomem *master_l10_counter;
37
38irqreturn_t notrace timer_interrupt(int dummy, void *dev_id);
39
40#ifdef CONFIG_SMP
41DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent);
42void register_percpu_ce(int cpu);
43#endif
44
45#endif /* !(_SPARC_TIMER_H) */