1/*
 2 * Definitions for CS4271 ASoC codec driver
 3 *
 4 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
 5 *
 6 * This program is free software; you can redistribute it and/or
 7 * modify it under the terms of the GNU General Public License
 8 * as published by the Free Software Foundation; either version 2
 9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __CS4271_H
18#define __CS4271_H
19
20struct cs4271_platform_data {
21	int gpio_nreset;	/* GPIO driving Reset pin, if any */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
22};
23
24#endif /* __CS4271_H */

 1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * Definitions for CS4271 ASoC codec driver
 4 *
 5 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
 
 
 
 
 
 
 
 
 
 
 6 */
 7
 8#ifndef __CS4271_H
 9#define __CS4271_H
10
11struct cs4271_platform_data {
12	int gpio_nreset;	/* GPIO driving Reset pin, if any */
13	bool amutec_eq_bmutec;	/* flag to enable AMUTEC=BMUTEC */
14
15	/*
16	 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET
17	 * line is de-asserted. That also means that clocks cannot be changed
18	 * without putting the chip back into hardware reset, which also requires
19	 * a complete re-initialization of all registers.
20	 *
21	 * One (undocumented) workaround is to assert and de-assert the PDN bit
22	 * in the MODE2 register. This workaround can be enabled with the
23	 * following flag.
24	 *
25	 * Note that this is not needed in case the clocks are stable
26	 * throughout the entire runtime of the codec.
27	 */
28	bool enable_soft_reset;
29};
30
31#endif /* __CS4271_H */