1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2015 MediaTek Inc.
  4 * Author:
  5 *  Zhigang.Wei <zhigang.wei@mediatek.com>
  6 *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
  7 */
  8
  9#ifndef _XHCI_MTK_H_
 10#define _XHCI_MTK_H_
 11
 12#include <linux/clk.h>
 13#include <linux/hashtable.h>
 14
 15#include "xhci.h"
 16
 17#define BULK_CLKS_NUM	5
 18
 19/* support at most 64 ep, use 32 size hash table */
 20#define SCH_EP_HASH_BITS	5
 21
 22/**
 23 * To simplify scheduler algorithm, set a upper limit for ESIT,
 24 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
 25 * round down to the limit value, that means allocating more
 26 * bandwidth to it.
 27 */
 28#define XHCI_MTK_MAX_ESIT	64
 29
 30/**
 31 * @fs_bus_bw: array to keep track of bandwidth already used for FS
 32 * @ep_list: Endpoints using this TT
 33 */
 34struct mu3h_sch_tt {
 35	u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
 36	struct list_head ep_list;
 37};
 38
 39/**
 40 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
 41 *
 42 * @bus_bw: array to keep track of bandwidth already used at each uframes
 43 *
 44 * treat a HS root port as a bandwidth domain, but treat a SS root port as
 45 * two bandwidth domains, one for IN eps and another for OUT eps.
 46 */
 47struct mu3h_sch_bw_info {
 48	u32 bus_bw[XHCI_MTK_MAX_ESIT];
 49};
 50
 51/**
 52 * struct mu3h_sch_ep_info: schedule information for endpoint
 53 *
 54 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
 55 * @num_budget_microframes: number of continuous uframes
 56 *		(@repeat==1) scheduled within the interval
 57 * @bw_cost_per_microframe: bandwidth cost per microframe
 58 * @hentry: hash table entry
 59 * @endpoint: linked into bandwidth domain which it belongs to
 60 * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
 61 * @bw_info: bandwidth domain which this endpoint belongs
 62 * @sch_tt: mu3h_sch_tt linked into
 63 * @ep_type: endpoint type
 64 * @maxpkt: max packet size of endpoint
 65 * @ep: address of usb_host_endpoint struct
 66 * @allocated: the bandwidth is aready allocated from bus_bw
 67 * @offset: which uframe of the interval that transfer should be
 68 *		scheduled first time within the interval
 69 * @repeat: the time gap between two uframes that transfers are
 70 *		scheduled within a interval. in the simple algorithm, only
 71 *		assign 0 or 1 to it; 0 means using only one uframe in a
 72 *		interval, and 1 means using @num_budget_microframes
 73 *		continuous uframes
 74 * @pkts: number of packets to be transferred in the scheduled uframes
 75 * @cs_count: number of CS that host will trigger
 76 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
 77 *		distribute the bMaxBurst+1 packets for a single burst
 78 *		according to @pkts and @repeat, repeate the burst multiple
 79 *		times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
 80 *		according to @pkts and @repeat. normal mode is used by
 81 *		default
 82 * @bw_budget_table: table to record bandwidth budget per microframe
 83 */
 84struct mu3h_sch_ep_info {
 85	u32 esit;
 86	u32 num_budget_microframes;
 87	u32 bw_cost_per_microframe;
 88	struct list_head endpoint;
 89	struct hlist_node hentry;
 90	struct list_head tt_endpoint;
 91	struct mu3h_sch_bw_info *bw_info;
 92	struct mu3h_sch_tt *sch_tt;
 93	u32 ep_type;
 94	u32 maxpkt;
 95	struct usb_host_endpoint *ep;
 96	enum usb_device_speed speed;
 97	bool allocated;
 98	/*
 99	 * mtk xHCI scheduling information put into reserved DWs
100	 * in ep context
101	 */
102	u32 offset;
103	u32 repeat;
104	u32 pkts;
105	u32 cs_count;
106	u32 burst_mode;
107	u32 bw_budget_table[];
108};
109
110#define MU3C_U3_PORT_MAX 4
111#define MU3C_U2_PORT_MAX 5
112
113/**
114 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
115 * @ip_pw_ctr0~3: ip power and clock control registers
116 * @ip_pw_sts1~2: ip power and clock status registers
117 * @ip_xhci_cap: ip xHCI capability register
118 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
119 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
120 * @u2_phy_pll: usb2 phy pll control register
121 */
122struct mu3c_ippc_regs {
123	__le32 ip_pw_ctr0;
124	__le32 ip_pw_ctr1;
125	__le32 ip_pw_ctr2;
126	__le32 ip_pw_ctr3;
127	__le32 ip_pw_sts1;
128	__le32 ip_pw_sts2;
129	__le32 reserved0[3];
130	__le32 ip_xhci_cap;
131	__le32 reserved1[2];
132	__le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
133	__le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
134	__le32 reserved2;
135	__le32 u2_phy_pll;
136	__le32 reserved3[33]; /* 0x80 ~ 0xff */
137};
138
139struct xhci_hcd_mtk {
140	struct device *dev;
141	struct usb_hcd *hcd;
142	struct mu3h_sch_bw_info *sch_array;
143	struct list_head bw_ep_chk_list;
144	DECLARE_HASHTABLE(sch_ep_hash, SCH_EP_HASH_BITS);
145	struct mu3c_ippc_regs __iomem *ippc_regs;
146	int num_u2_ports;
147	int num_u3_ports;
148	int u3p_dis_msk;
149	struct regulator *vusb33;
150	struct regulator *vbus;
151	struct clk_bulk_data clks[BULK_CLKS_NUM];
152	unsigned int has_ippc:1;
153	unsigned int lpm_support:1;
154	unsigned int u2_lpm_disable:1;
155	/* usb remote wakeup */
156	unsigned int uwk_en:1;
157	struct regmap *uwk;
158	u32 uwk_reg_base;
159	u32 uwk_vers;
160};
161
162static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
163{
164	return dev_get_drvdata(hcd->self.controller);
165}
166
167int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
168void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
169int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
170		    struct usb_host_endpoint *ep);
171int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
172		     struct usb_host_endpoint *ep);
173int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
174void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
175
176#endif		/* _XHCI_MTK_H_ */