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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2012-2015 Spreadtrum Communications Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/console.h>
8#include <linux/delay.h>
9#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/dma/sprd-dma.h>
12#include <linux/io.h>
13#include <linux/ioport.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20#include <linux/slab.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23
24/* device name */
25#define UART_NR_MAX 8
26#define SPRD_TTY_NAME "ttyS"
27#define SPRD_FIFO_SIZE 128
28#define SPRD_DEF_RATE 26000000
29#define SPRD_BAUD_IO_LIMIT 3000000
30#define SPRD_TIMEOUT 256000
31
32/* the offset of serial registers and BITs for them */
33/* data registers */
34#define SPRD_TXD 0x0000
35#define SPRD_RXD 0x0004
36
37/* line status register and its BITs */
38#define SPRD_LSR 0x0008
39#define SPRD_LSR_OE BIT(4)
40#define SPRD_LSR_FE BIT(3)
41#define SPRD_LSR_PE BIT(2)
42#define SPRD_LSR_BI BIT(7)
43#define SPRD_LSR_TX_OVER BIT(15)
44
45/* data number in TX and RX fifo */
46#define SPRD_STS1 0x000C
47#define SPRD_RX_FIFO_CNT_MASK GENMASK(7, 0)
48#define SPRD_TX_FIFO_CNT_MASK GENMASK(15, 8)
49
50/* interrupt enable register and its BITs */
51#define SPRD_IEN 0x0010
52#define SPRD_IEN_RX_FULL BIT(0)
53#define SPRD_IEN_TX_EMPTY BIT(1)
54#define SPRD_IEN_BREAK_DETECT BIT(7)
55#define SPRD_IEN_TIMEOUT BIT(13)
56
57/* interrupt clear register */
58#define SPRD_ICLR 0x0014
59#define SPRD_ICLR_TIMEOUT BIT(13)
60
61/* line control register */
62#define SPRD_LCR 0x0018
63#define SPRD_LCR_STOP_1BIT 0x10
64#define SPRD_LCR_STOP_2BIT 0x30
65#define SPRD_LCR_DATA_LEN (BIT(2) | BIT(3))
66#define SPRD_LCR_DATA_LEN5 0x0
67#define SPRD_LCR_DATA_LEN6 0x4
68#define SPRD_LCR_DATA_LEN7 0x8
69#define SPRD_LCR_DATA_LEN8 0xc
70#define SPRD_LCR_PARITY (BIT(0) | BIT(1))
71#define SPRD_LCR_PARITY_EN 0x2
72#define SPRD_LCR_EVEN_PAR 0x0
73#define SPRD_LCR_ODD_PAR 0x1
74
75/* control register 1 */
76#define SPRD_CTL1 0x001C
77#define SPRD_DMA_EN BIT(15)
78#define SPRD_LOOPBACK_EN BIT(14)
79#define RX_HW_FLOW_CTL_THLD BIT(6)
80#define RX_HW_FLOW_CTL_EN BIT(7)
81#define TX_HW_FLOW_CTL_EN BIT(8)
82#define RX_TOUT_THLD_DEF 0x3E00
83#define RX_HFC_THLD_DEF 0x40
84
85/* fifo threshold register */
86#define SPRD_CTL2 0x0020
87#define THLD_TX_EMPTY 0x40
88#define THLD_TX_EMPTY_SHIFT 8
89#define THLD_RX_FULL 0x40
90#define THLD_RX_FULL_MASK GENMASK(6, 0)
91
92/* config baud rate register */
93#define SPRD_CLKD0 0x0024
94#define SPRD_CLKD0_MASK GENMASK(15, 0)
95#define SPRD_CLKD1 0x0028
96#define SPRD_CLKD1_MASK GENMASK(20, 16)
97#define SPRD_CLKD1_SHIFT 16
98
99/* interrupt mask status register */
100#define SPRD_IMSR 0x002C
101#define SPRD_IMSR_RX_FIFO_FULL BIT(0)
102#define SPRD_IMSR_TX_FIFO_EMPTY BIT(1)
103#define SPRD_IMSR_BREAK_DETECT BIT(7)
104#define SPRD_IMSR_TIMEOUT BIT(13)
105#define SPRD_DEFAULT_SOURCE_CLK 26000000
106
107#define SPRD_RX_DMA_STEP 1
108#define SPRD_RX_FIFO_FULL 1
109#define SPRD_TX_FIFO_FULL 0x20
110#define SPRD_UART_RX_SIZE (UART_XMIT_SIZE / 4)
111
112struct sprd_uart_dma {
113 struct dma_chan *chn;
114 unsigned char *virt;
115 dma_addr_t phys_addr;
116 dma_cookie_t cookie;
117 u32 trans_len;
118 bool enable;
119};
120
121struct sprd_uart_port {
122 struct uart_port port;
123 char name[16];
124 struct clk *clk;
125 struct sprd_uart_dma tx_dma;
126 struct sprd_uart_dma rx_dma;
127 dma_addr_t pos;
128 unsigned char *rx_buf_tail;
129};
130
131static struct sprd_uart_port *sprd_port[UART_NR_MAX];
132static int sprd_ports_num;
133
134static int sprd_start_dma_rx(struct uart_port *port);
135static int sprd_tx_dma_config(struct uart_port *port);
136
137static inline unsigned int serial_in(struct uart_port *port,
138 unsigned int offset)
139{
140 return readl_relaxed(port->membase + offset);
141}
142
143static inline void serial_out(struct uart_port *port, unsigned int offset,
144 int value)
145{
146 writel_relaxed(value, port->membase + offset);
147}
148
149static unsigned int sprd_tx_empty(struct uart_port *port)
150{
151 if (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
152 return 0;
153 else
154 return TIOCSER_TEMT;
155}
156
157static unsigned int sprd_get_mctrl(struct uart_port *port)
158{
159 return TIOCM_DSR | TIOCM_CTS;
160}
161
162static void sprd_set_mctrl(struct uart_port *port, unsigned int mctrl)
163{
164 u32 val = serial_in(port, SPRD_CTL1);
165
166 if (mctrl & TIOCM_LOOP)
167 val |= SPRD_LOOPBACK_EN;
168 else
169 val &= ~SPRD_LOOPBACK_EN;
170
171 serial_out(port, SPRD_CTL1, val);
172}
173
174static void sprd_stop_rx(struct uart_port *port)
175{
176 struct sprd_uart_port *sp =
177 container_of(port, struct sprd_uart_port, port);
178 unsigned int ien, iclr;
179
180 if (sp->rx_dma.enable)
181 dmaengine_terminate_all(sp->rx_dma.chn);
182
183 iclr = serial_in(port, SPRD_ICLR);
184 ien = serial_in(port, SPRD_IEN);
185
186 ien &= ~(SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT);
187 iclr |= SPRD_IEN_RX_FULL | SPRD_IEN_BREAK_DETECT;
188
189 serial_out(port, SPRD_IEN, ien);
190 serial_out(port, SPRD_ICLR, iclr);
191}
192
193static void sprd_uart_dma_enable(struct uart_port *port, bool enable)
194{
195 u32 val = serial_in(port, SPRD_CTL1);
196
197 if (enable)
198 val |= SPRD_DMA_EN;
199 else
200 val &= ~SPRD_DMA_EN;
201
202 serial_out(port, SPRD_CTL1, val);
203}
204
205static void sprd_stop_tx_dma(struct uart_port *port)
206{
207 struct sprd_uart_port *sp =
208 container_of(port, struct sprd_uart_port, port);
209 struct circ_buf *xmit = &port->state->xmit;
210 struct dma_tx_state state;
211 u32 trans_len;
212
213 dmaengine_pause(sp->tx_dma.chn);
214
215 dmaengine_tx_status(sp->tx_dma.chn, sp->tx_dma.cookie, &state);
216 if (state.residue) {
217 trans_len = state.residue - sp->tx_dma.phys_addr;
218 xmit->tail = (xmit->tail + trans_len) & (UART_XMIT_SIZE - 1);
219 port->icount.tx += trans_len;
220 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
221 sp->tx_dma.trans_len, DMA_TO_DEVICE);
222 }
223
224 dmaengine_terminate_all(sp->tx_dma.chn);
225 sp->tx_dma.trans_len = 0;
226}
227
228static int sprd_tx_buf_remap(struct uart_port *port)
229{
230 struct sprd_uart_port *sp =
231 container_of(port, struct sprd_uart_port, port);
232 struct circ_buf *xmit = &port->state->xmit;
233
234 sp->tx_dma.trans_len =
235 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
236
237 sp->tx_dma.phys_addr = dma_map_single(port->dev,
238 (void *)&(xmit->buf[xmit->tail]),
239 sp->tx_dma.trans_len,
240 DMA_TO_DEVICE);
241 return dma_mapping_error(port->dev, sp->tx_dma.phys_addr);
242}
243
244static void sprd_complete_tx_dma(void *data)
245{
246 struct uart_port *port = (struct uart_port *)data;
247 struct sprd_uart_port *sp =
248 container_of(port, struct sprd_uart_port, port);
249 struct circ_buf *xmit = &port->state->xmit;
250 unsigned long flags;
251
252 spin_lock_irqsave(&port->lock, flags);
253 dma_unmap_single(port->dev, sp->tx_dma.phys_addr,
254 sp->tx_dma.trans_len, DMA_TO_DEVICE);
255
256 xmit->tail = (xmit->tail + sp->tx_dma.trans_len) & (UART_XMIT_SIZE - 1);
257 port->icount.tx += sp->tx_dma.trans_len;
258
259 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
260 uart_write_wakeup(port);
261
262 if (uart_circ_empty(xmit) || sprd_tx_buf_remap(port) ||
263 sprd_tx_dma_config(port))
264 sp->tx_dma.trans_len = 0;
265
266 spin_unlock_irqrestore(&port->lock, flags);
267}
268
269static int sprd_uart_dma_submit(struct uart_port *port,
270 struct sprd_uart_dma *ud, u32 trans_len,
271 enum dma_transfer_direction direction,
272 dma_async_tx_callback callback)
273{
274 struct dma_async_tx_descriptor *dma_des;
275 unsigned long flags;
276
277 flags = SPRD_DMA_FLAGS(SPRD_DMA_CHN_MODE_NONE,
278 SPRD_DMA_NO_TRG,
279 SPRD_DMA_FRAG_REQ,
280 SPRD_DMA_TRANS_INT);
281
282 dma_des = dmaengine_prep_slave_single(ud->chn, ud->phys_addr, trans_len,
283 direction, flags);
284 if (!dma_des)
285 return -ENODEV;
286
287 dma_des->callback = callback;
288 dma_des->callback_param = port;
289
290 ud->cookie = dmaengine_submit(dma_des);
291 if (dma_submit_error(ud->cookie))
292 return dma_submit_error(ud->cookie);
293
294 dma_async_issue_pending(ud->chn);
295
296 return 0;
297}
298
299static int sprd_tx_dma_config(struct uart_port *port)
300{
301 struct sprd_uart_port *sp =
302 container_of(port, struct sprd_uart_port, port);
303 u32 burst = sp->tx_dma.trans_len > SPRD_TX_FIFO_FULL ?
304 SPRD_TX_FIFO_FULL : sp->tx_dma.trans_len;
305 int ret;
306 struct dma_slave_config cfg = {
307 .dst_addr = port->mapbase + SPRD_TXD,
308 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
309 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
310 .src_maxburst = burst,
311 };
312
313 ret = dmaengine_slave_config(sp->tx_dma.chn, &cfg);
314 if (ret < 0)
315 return ret;
316
317 return sprd_uart_dma_submit(port, &sp->tx_dma, sp->tx_dma.trans_len,
318 DMA_MEM_TO_DEV, sprd_complete_tx_dma);
319}
320
321static void sprd_start_tx_dma(struct uart_port *port)
322{
323 struct sprd_uart_port *sp =
324 container_of(port, struct sprd_uart_port, port);
325 struct circ_buf *xmit = &port->state->xmit;
326
327 if (port->x_char) {
328 serial_out(port, SPRD_TXD, port->x_char);
329 port->icount.tx++;
330 port->x_char = 0;
331 return;
332 }
333
334 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
335 sprd_stop_tx_dma(port);
336 return;
337 }
338
339 if (sp->tx_dma.trans_len)
340 return;
341
342 if (sprd_tx_buf_remap(port) || sprd_tx_dma_config(port))
343 sp->tx_dma.trans_len = 0;
344}
345
346static void sprd_rx_full_thld(struct uart_port *port, u32 thld)
347{
348 u32 val = serial_in(port, SPRD_CTL2);
349
350 val &= ~THLD_RX_FULL_MASK;
351 val |= thld & THLD_RX_FULL_MASK;
352 serial_out(port, SPRD_CTL2, val);
353}
354
355static int sprd_rx_alloc_buf(struct sprd_uart_port *sp)
356{
357 sp->rx_dma.virt = dma_alloc_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
358 &sp->rx_dma.phys_addr, GFP_KERNEL);
359 if (!sp->rx_dma.virt)
360 return -ENOMEM;
361
362 return 0;
363}
364
365static void sprd_rx_free_buf(struct sprd_uart_port *sp)
366{
367 if (sp->rx_dma.virt)
368 dma_free_coherent(sp->port.dev, SPRD_UART_RX_SIZE,
369 sp->rx_dma.virt, sp->rx_dma.phys_addr);
370
371}
372
373static int sprd_rx_dma_config(struct uart_port *port, u32 burst)
374{
375 struct sprd_uart_port *sp =
376 container_of(port, struct sprd_uart_port, port);
377 struct dma_slave_config cfg = {
378 .src_addr = port->mapbase + SPRD_RXD,
379 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
380 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
381 .src_maxburst = burst,
382 };
383
384 return dmaengine_slave_config(sp->rx_dma.chn, &cfg);
385}
386
387static void sprd_uart_dma_rx(struct uart_port *port)
388{
389 struct sprd_uart_port *sp =
390 container_of(port, struct sprd_uart_port, port);
391 struct tty_port *tty = &port->state->port;
392
393 port->icount.rx += sp->rx_dma.trans_len;
394 tty_insert_flip_string(tty, sp->rx_buf_tail, sp->rx_dma.trans_len);
395 tty_flip_buffer_push(tty);
396}
397
398static void sprd_uart_dma_irq(struct uart_port *port)
399{
400 struct sprd_uart_port *sp =
401 container_of(port, struct sprd_uart_port, port);
402 struct dma_tx_state state;
403 enum dma_status status;
404
405 status = dmaengine_tx_status(sp->rx_dma.chn,
406 sp->rx_dma.cookie, &state);
407 if (status == DMA_ERROR)
408 sprd_stop_rx(port);
409
410 if (!state.residue && sp->pos == sp->rx_dma.phys_addr)
411 return;
412
413 if (!state.residue) {
414 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
415 sp->rx_dma.phys_addr - sp->pos;
416 sp->pos = sp->rx_dma.phys_addr;
417 } else {
418 sp->rx_dma.trans_len = state.residue - sp->pos;
419 sp->pos = state.residue;
420 }
421
422 sprd_uart_dma_rx(port);
423 sp->rx_buf_tail += sp->rx_dma.trans_len;
424}
425
426static void sprd_complete_rx_dma(void *data)
427{
428 struct uart_port *port = (struct uart_port *)data;
429 struct sprd_uart_port *sp =
430 container_of(port, struct sprd_uart_port, port);
431 struct dma_tx_state state;
432 enum dma_status status;
433 unsigned long flags;
434
435 spin_lock_irqsave(&port->lock, flags);
436
437 status = dmaengine_tx_status(sp->rx_dma.chn,
438 sp->rx_dma.cookie, &state);
439 if (status != DMA_COMPLETE) {
440 sprd_stop_rx(port);
441 spin_unlock_irqrestore(&port->lock, flags);
442 return;
443 }
444
445 if (sp->pos != sp->rx_dma.phys_addr) {
446 sp->rx_dma.trans_len = SPRD_UART_RX_SIZE +
447 sp->rx_dma.phys_addr - sp->pos;
448 sprd_uart_dma_rx(port);
449 sp->rx_buf_tail += sp->rx_dma.trans_len;
450 }
451
452 if (sprd_start_dma_rx(port))
453 sprd_stop_rx(port);
454
455 spin_unlock_irqrestore(&port->lock, flags);
456}
457
458static int sprd_start_dma_rx(struct uart_port *port)
459{
460 struct sprd_uart_port *sp =
461 container_of(port, struct sprd_uart_port, port);
462 int ret;
463
464 if (!sp->rx_dma.enable)
465 return 0;
466
467 sp->pos = sp->rx_dma.phys_addr;
468 sp->rx_buf_tail = sp->rx_dma.virt;
469 sprd_rx_full_thld(port, SPRD_RX_FIFO_FULL);
470 ret = sprd_rx_dma_config(port, SPRD_RX_DMA_STEP);
471 if (ret)
472 return ret;
473
474 return sprd_uart_dma_submit(port, &sp->rx_dma, SPRD_UART_RX_SIZE,
475 DMA_DEV_TO_MEM, sprd_complete_rx_dma);
476}
477
478static void sprd_release_dma(struct uart_port *port)
479{
480 struct sprd_uart_port *sp =
481 container_of(port, struct sprd_uart_port, port);
482
483 sprd_uart_dma_enable(port, false);
484
485 if (sp->rx_dma.enable)
486 dma_release_channel(sp->rx_dma.chn);
487
488 if (sp->tx_dma.enable)
489 dma_release_channel(sp->tx_dma.chn);
490
491 sp->tx_dma.enable = false;
492 sp->rx_dma.enable = false;
493}
494
495static void sprd_request_dma(struct uart_port *port)
496{
497 struct sprd_uart_port *sp =
498 container_of(port, struct sprd_uart_port, port);
499
500 sp->tx_dma.enable = true;
501 sp->rx_dma.enable = true;
502
503 sp->tx_dma.chn = dma_request_chan(port->dev, "tx");
504 if (IS_ERR(sp->tx_dma.chn)) {
505 dev_err(port->dev, "request TX DMA channel failed, ret = %ld\n",
506 PTR_ERR(sp->tx_dma.chn));
507 sp->tx_dma.enable = false;
508 }
509
510 sp->rx_dma.chn = dma_request_chan(port->dev, "rx");
511 if (IS_ERR(sp->rx_dma.chn)) {
512 dev_err(port->dev, "request RX DMA channel failed, ret = %ld\n",
513 PTR_ERR(sp->rx_dma.chn));
514 sp->rx_dma.enable = false;
515 }
516}
517
518static void sprd_stop_tx(struct uart_port *port)
519{
520 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
521 port);
522 unsigned int ien, iclr;
523
524 if (sp->tx_dma.enable) {
525 sprd_stop_tx_dma(port);
526 return;
527 }
528
529 iclr = serial_in(port, SPRD_ICLR);
530 ien = serial_in(port, SPRD_IEN);
531
532 iclr |= SPRD_IEN_TX_EMPTY;
533 ien &= ~SPRD_IEN_TX_EMPTY;
534
535 serial_out(port, SPRD_IEN, ien);
536 serial_out(port, SPRD_ICLR, iclr);
537}
538
539static void sprd_start_tx(struct uart_port *port)
540{
541 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
542 port);
543 unsigned int ien;
544
545 if (sp->tx_dma.enable) {
546 sprd_start_tx_dma(port);
547 return;
548 }
549
550 ien = serial_in(port, SPRD_IEN);
551 if (!(ien & SPRD_IEN_TX_EMPTY)) {
552 ien |= SPRD_IEN_TX_EMPTY;
553 serial_out(port, SPRD_IEN, ien);
554 }
555}
556
557/* The Sprd serial does not support this function. */
558static void sprd_break_ctl(struct uart_port *port, int break_state)
559{
560 /* nothing to do */
561}
562
563static int handle_lsr_errors(struct uart_port *port,
564 unsigned int *flag,
565 unsigned int *lsr)
566{
567 int ret = 0;
568
569 /* statistics */
570 if (*lsr & SPRD_LSR_BI) {
571 *lsr &= ~(SPRD_LSR_FE | SPRD_LSR_PE);
572 port->icount.brk++;
573 ret = uart_handle_break(port);
574 if (ret)
575 return ret;
576 } else if (*lsr & SPRD_LSR_PE)
577 port->icount.parity++;
578 else if (*lsr & SPRD_LSR_FE)
579 port->icount.frame++;
580 if (*lsr & SPRD_LSR_OE)
581 port->icount.overrun++;
582
583 /* mask off conditions which should be ignored */
584 *lsr &= port->read_status_mask;
585 if (*lsr & SPRD_LSR_BI)
586 *flag = TTY_BREAK;
587 else if (*lsr & SPRD_LSR_PE)
588 *flag = TTY_PARITY;
589 else if (*lsr & SPRD_LSR_FE)
590 *flag = TTY_FRAME;
591
592 return ret;
593}
594
595static inline void sprd_rx(struct uart_port *port)
596{
597 struct sprd_uart_port *sp = container_of(port, struct sprd_uart_port,
598 port);
599 struct tty_port *tty = &port->state->port;
600 unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT;
601
602 if (sp->rx_dma.enable) {
603 sprd_uart_dma_irq(port);
604 return;
605 }
606
607 while ((serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK) &&
608 max_count--) {
609 lsr = serial_in(port, SPRD_LSR);
610 ch = serial_in(port, SPRD_RXD);
611 flag = TTY_NORMAL;
612 port->icount.rx++;
613
614 if (lsr & (SPRD_LSR_BI | SPRD_LSR_PE |
615 SPRD_LSR_FE | SPRD_LSR_OE))
616 if (handle_lsr_errors(port, &flag, &lsr))
617 continue;
618 if (uart_handle_sysrq_char(port, ch))
619 continue;
620
621 uart_insert_char(port, lsr, SPRD_LSR_OE, ch, flag);
622 }
623
624 tty_flip_buffer_push(tty);
625}
626
627static inline void sprd_tx(struct uart_port *port)
628{
629 struct circ_buf *xmit = &port->state->xmit;
630 int count;
631
632 if (port->x_char) {
633 serial_out(port, SPRD_TXD, port->x_char);
634 port->icount.tx++;
635 port->x_char = 0;
636 return;
637 }
638
639 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
640 sprd_stop_tx(port);
641 return;
642 }
643
644 count = THLD_TX_EMPTY;
645 do {
646 serial_out(port, SPRD_TXD, xmit->buf[xmit->tail]);
647 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
648 port->icount.tx++;
649 if (uart_circ_empty(xmit))
650 break;
651 } while (--count > 0);
652
653 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
654 uart_write_wakeup(port);
655
656 if (uart_circ_empty(xmit))
657 sprd_stop_tx(port);
658}
659
660/* this handles the interrupt from one port */
661static irqreturn_t sprd_handle_irq(int irq, void *dev_id)
662{
663 struct uart_port *port = dev_id;
664 unsigned int ims;
665
666 spin_lock(&port->lock);
667
668 ims = serial_in(port, SPRD_IMSR);
669
670 if (!ims) {
671 spin_unlock(&port->lock);
672 return IRQ_NONE;
673 }
674
675 if (ims & SPRD_IMSR_TIMEOUT)
676 serial_out(port, SPRD_ICLR, SPRD_ICLR_TIMEOUT);
677
678 if (ims & SPRD_IMSR_BREAK_DETECT)
679 serial_out(port, SPRD_ICLR, SPRD_IMSR_BREAK_DETECT);
680
681 if (ims & (SPRD_IMSR_RX_FIFO_FULL | SPRD_IMSR_BREAK_DETECT |
682 SPRD_IMSR_TIMEOUT))
683 sprd_rx(port);
684
685 if (ims & SPRD_IMSR_TX_FIFO_EMPTY)
686 sprd_tx(port);
687
688 spin_unlock(&port->lock);
689
690 return IRQ_HANDLED;
691}
692
693static void sprd_uart_dma_startup(struct uart_port *port,
694 struct sprd_uart_port *sp)
695{
696 int ret;
697
698 sprd_request_dma(port);
699 if (!(sp->rx_dma.enable || sp->tx_dma.enable))
700 return;
701
702 ret = sprd_start_dma_rx(port);
703 if (ret) {
704 sp->rx_dma.enable = false;
705 dma_release_channel(sp->rx_dma.chn);
706 dev_warn(port->dev, "fail to start RX dma mode\n");
707 }
708
709 sprd_uart_dma_enable(port, true);
710}
711
712static int sprd_startup(struct uart_port *port)
713{
714 int ret = 0;
715 unsigned int ien, fc;
716 unsigned int timeout;
717 struct sprd_uart_port *sp;
718 unsigned long flags;
719
720 serial_out(port, SPRD_CTL2,
721 THLD_TX_EMPTY << THLD_TX_EMPTY_SHIFT | THLD_RX_FULL);
722
723 /* clear rx fifo */
724 timeout = SPRD_TIMEOUT;
725 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK)
726 serial_in(port, SPRD_RXD);
727
728 /* clear tx fifo */
729 timeout = SPRD_TIMEOUT;
730 while (timeout-- && serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
731 cpu_relax();
732
733 /* clear interrupt */
734 serial_out(port, SPRD_IEN, 0);
735 serial_out(port, SPRD_ICLR, ~0);
736
737 /* allocate irq */
738 sp = container_of(port, struct sprd_uart_port, port);
739 snprintf(sp->name, sizeof(sp->name), "sprd_serial%d", port->line);
740
741 sprd_uart_dma_startup(port, sp);
742
743 ret = devm_request_irq(port->dev, port->irq, sprd_handle_irq,
744 IRQF_SHARED, sp->name, port);
745 if (ret) {
746 dev_err(port->dev, "fail to request serial irq %d, ret=%d\n",
747 port->irq, ret);
748 return ret;
749 }
750 fc = serial_in(port, SPRD_CTL1);
751 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
752 serial_out(port, SPRD_CTL1, fc);
753
754 /* enable interrupt */
755 spin_lock_irqsave(&port->lock, flags);
756 ien = serial_in(port, SPRD_IEN);
757 ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT;
758 if (!sp->rx_dma.enable)
759 ien |= SPRD_IEN_RX_FULL;
760 serial_out(port, SPRD_IEN, ien);
761 spin_unlock_irqrestore(&port->lock, flags);
762
763 return 0;
764}
765
766static void sprd_shutdown(struct uart_port *port)
767{
768 sprd_release_dma(port);
769 serial_out(port, SPRD_IEN, 0);
770 serial_out(port, SPRD_ICLR, ~0);
771 devm_free_irq(port->dev, port->irq, port);
772}
773
774static void sprd_set_termios(struct uart_port *port,
775 struct ktermios *termios,
776 struct ktermios *old)
777{
778 unsigned int baud, quot;
779 unsigned int lcr = 0, fc;
780 unsigned long flags;
781
782 /* ask the core to calculate the divisor for us */
783 baud = uart_get_baud_rate(port, termios, old, 0, SPRD_BAUD_IO_LIMIT);
784
785 quot = port->uartclk / baud;
786
787 /* set data length */
788 switch (termios->c_cflag & CSIZE) {
789 case CS5:
790 lcr |= SPRD_LCR_DATA_LEN5;
791 break;
792 case CS6:
793 lcr |= SPRD_LCR_DATA_LEN6;
794 break;
795 case CS7:
796 lcr |= SPRD_LCR_DATA_LEN7;
797 break;
798 case CS8:
799 default:
800 lcr |= SPRD_LCR_DATA_LEN8;
801 break;
802 }
803
804 /* calculate stop bits */
805 lcr &= ~(SPRD_LCR_STOP_1BIT | SPRD_LCR_STOP_2BIT);
806 if (termios->c_cflag & CSTOPB)
807 lcr |= SPRD_LCR_STOP_2BIT;
808 else
809 lcr |= SPRD_LCR_STOP_1BIT;
810
811 /* calculate parity */
812 lcr &= ~SPRD_LCR_PARITY;
813 termios->c_cflag &= ~CMSPAR; /* no support mark/space */
814 if (termios->c_cflag & PARENB) {
815 lcr |= SPRD_LCR_PARITY_EN;
816 if (termios->c_cflag & PARODD)
817 lcr |= SPRD_LCR_ODD_PAR;
818 else
819 lcr |= SPRD_LCR_EVEN_PAR;
820 }
821
822 spin_lock_irqsave(&port->lock, flags);
823
824 /* update the per-port timeout */
825 uart_update_timeout(port, termios->c_cflag, baud);
826
827 port->read_status_mask = SPRD_LSR_OE;
828 if (termios->c_iflag & INPCK)
829 port->read_status_mask |= SPRD_LSR_FE | SPRD_LSR_PE;
830 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
831 port->read_status_mask |= SPRD_LSR_BI;
832
833 /* characters to ignore */
834 port->ignore_status_mask = 0;
835 if (termios->c_iflag & IGNPAR)
836 port->ignore_status_mask |= SPRD_LSR_PE | SPRD_LSR_FE;
837 if (termios->c_iflag & IGNBRK) {
838 port->ignore_status_mask |= SPRD_LSR_BI;
839 /*
840 * If we're ignoring parity and break indicators,
841 * ignore overruns too (for real raw support).
842 */
843 if (termios->c_iflag & IGNPAR)
844 port->ignore_status_mask |= SPRD_LSR_OE;
845 }
846
847 /* flow control */
848 fc = serial_in(port, SPRD_CTL1);
849 fc &= ~(RX_HW_FLOW_CTL_THLD | RX_HW_FLOW_CTL_EN | TX_HW_FLOW_CTL_EN);
850 if (termios->c_cflag & CRTSCTS) {
851 fc |= RX_HW_FLOW_CTL_THLD;
852 fc |= RX_HW_FLOW_CTL_EN;
853 fc |= TX_HW_FLOW_CTL_EN;
854 }
855
856 /* clock divider bit0~bit15 */
857 serial_out(port, SPRD_CLKD0, quot & SPRD_CLKD0_MASK);
858
859 /* clock divider bit16~bit20 */
860 serial_out(port, SPRD_CLKD1,
861 (quot & SPRD_CLKD1_MASK) >> SPRD_CLKD1_SHIFT);
862 serial_out(port, SPRD_LCR, lcr);
863 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF;
864 serial_out(port, SPRD_CTL1, fc);
865
866 spin_unlock_irqrestore(&port->lock, flags);
867
868 /* Don't rewrite B0 */
869 if (tty_termios_baud_rate(termios))
870 tty_termios_encode_baud_rate(termios, baud, baud);
871}
872
873static const char *sprd_type(struct uart_port *port)
874{
875 return "SPX";
876}
877
878static void sprd_release_port(struct uart_port *port)
879{
880 /* nothing to do */
881}
882
883static int sprd_request_port(struct uart_port *port)
884{
885 return 0;
886}
887
888static void sprd_config_port(struct uart_port *port, int flags)
889{
890 if (flags & UART_CONFIG_TYPE)
891 port->type = PORT_SPRD;
892}
893
894static int sprd_verify_port(struct uart_port *port, struct serial_struct *ser)
895{
896 if (ser->type != PORT_SPRD)
897 return -EINVAL;
898 if (port->irq != ser->irq)
899 return -EINVAL;
900 if (port->iotype != ser->io_type)
901 return -EINVAL;
902 return 0;
903}
904
905static void sprd_pm(struct uart_port *port, unsigned int state,
906 unsigned int oldstate)
907{
908 struct sprd_uart_port *sup =
909 container_of(port, struct sprd_uart_port, port);
910
911 switch (state) {
912 case UART_PM_STATE_ON:
913 clk_prepare_enable(sup->clk);
914 break;
915 case UART_PM_STATE_OFF:
916 clk_disable_unprepare(sup->clk);
917 break;
918 }
919}
920
921#ifdef CONFIG_CONSOLE_POLL
922static int sprd_poll_init(struct uart_port *port)
923{
924 if (port->state->pm_state != UART_PM_STATE_ON) {
925 sprd_pm(port, UART_PM_STATE_ON, 0);
926 port->state->pm_state = UART_PM_STATE_ON;
927 }
928
929 return 0;
930}
931
932static int sprd_poll_get_char(struct uart_port *port)
933{
934 while (!(serial_in(port, SPRD_STS1) & SPRD_RX_FIFO_CNT_MASK))
935 cpu_relax();
936
937 return serial_in(port, SPRD_RXD);
938}
939
940static void sprd_poll_put_char(struct uart_port *port, unsigned char ch)
941{
942 while (serial_in(port, SPRD_STS1) & SPRD_TX_FIFO_CNT_MASK)
943 cpu_relax();
944
945 serial_out(port, SPRD_TXD, ch);
946}
947#endif
948
949static const struct uart_ops serial_sprd_ops = {
950 .tx_empty = sprd_tx_empty,
951 .get_mctrl = sprd_get_mctrl,
952 .set_mctrl = sprd_set_mctrl,
953 .stop_tx = sprd_stop_tx,
954 .start_tx = sprd_start_tx,
955 .stop_rx = sprd_stop_rx,
956 .break_ctl = sprd_break_ctl,
957 .startup = sprd_startup,
958 .shutdown = sprd_shutdown,
959 .set_termios = sprd_set_termios,
960 .type = sprd_type,
961 .release_port = sprd_release_port,
962 .request_port = sprd_request_port,
963 .config_port = sprd_config_port,
964 .verify_port = sprd_verify_port,
965 .pm = sprd_pm,
966#ifdef CONFIG_CONSOLE_POLL
967 .poll_init = sprd_poll_init,
968 .poll_get_char = sprd_poll_get_char,
969 .poll_put_char = sprd_poll_put_char,
970#endif
971};
972
973#ifdef CONFIG_SERIAL_SPRD_CONSOLE
974static void wait_for_xmitr(struct uart_port *port)
975{
976 unsigned int status, tmout = 10000;
977
978 /* wait up to 10ms for the character(s) to be sent */
979 do {
980 status = serial_in(port, SPRD_STS1);
981 if (--tmout == 0)
982 break;
983 udelay(1);
984 } while (status & SPRD_TX_FIFO_CNT_MASK);
985}
986
987static void sprd_console_putchar(struct uart_port *port, int ch)
988{
989 wait_for_xmitr(port);
990 serial_out(port, SPRD_TXD, ch);
991}
992
993static void sprd_console_write(struct console *co, const char *s,
994 unsigned int count)
995{
996 struct uart_port *port = &sprd_port[co->index]->port;
997 int locked = 1;
998 unsigned long flags;
999
1000 if (port->sysrq)
1001 locked = 0;
1002 else if (oops_in_progress)
1003 locked = spin_trylock_irqsave(&port->lock, flags);
1004 else
1005 spin_lock_irqsave(&port->lock, flags);
1006
1007 uart_console_write(port, s, count, sprd_console_putchar);
1008
1009 /* wait for transmitter to become empty */
1010 wait_for_xmitr(port);
1011
1012 if (locked)
1013 spin_unlock_irqrestore(&port->lock, flags);
1014}
1015
1016static int sprd_console_setup(struct console *co, char *options)
1017{
1018 struct sprd_uart_port *sprd_uart_port;
1019 int baud = 115200;
1020 int bits = 8;
1021 int parity = 'n';
1022 int flow = 'n';
1023
1024 if (co->index >= UART_NR_MAX || co->index < 0)
1025 co->index = 0;
1026
1027 sprd_uart_port = sprd_port[co->index];
1028 if (!sprd_uart_port || !sprd_uart_port->port.membase) {
1029 pr_info("serial port %d not yet initialized\n", co->index);
1030 return -ENODEV;
1031 }
1032
1033 if (options)
1034 uart_parse_options(options, &baud, &parity, &bits, &flow);
1035
1036 return uart_set_options(&sprd_uart_port->port, co, baud,
1037 parity, bits, flow);
1038}
1039
1040static struct uart_driver sprd_uart_driver;
1041static struct console sprd_console = {
1042 .name = SPRD_TTY_NAME,
1043 .write = sprd_console_write,
1044 .device = uart_console_device,
1045 .setup = sprd_console_setup,
1046 .flags = CON_PRINTBUFFER,
1047 .index = -1,
1048 .data = &sprd_uart_driver,
1049};
1050
1051static int __init sprd_serial_console_init(void)
1052{
1053 register_console(&sprd_console);
1054 return 0;
1055}
1056console_initcall(sprd_serial_console_init);
1057
1058#define SPRD_CONSOLE (&sprd_console)
1059
1060/* Support for earlycon */
1061static void sprd_putc(struct uart_port *port, int c)
1062{
1063 unsigned int timeout = SPRD_TIMEOUT;
1064
1065 while (timeout-- &&
1066 !(readl(port->membase + SPRD_LSR) & SPRD_LSR_TX_OVER))
1067 cpu_relax();
1068
1069 writeb(c, port->membase + SPRD_TXD);
1070}
1071
1072static void sprd_early_write(struct console *con, const char *s, unsigned int n)
1073{
1074 struct earlycon_device *dev = con->data;
1075
1076 uart_console_write(&dev->port, s, n, sprd_putc);
1077}
1078
1079static int __init sprd_early_console_setup(struct earlycon_device *device,
1080 const char *opt)
1081{
1082 if (!device->port.membase)
1083 return -ENODEV;
1084
1085 device->con->write = sprd_early_write;
1086 return 0;
1087}
1088OF_EARLYCON_DECLARE(sprd_serial, "sprd,sc9836-uart",
1089 sprd_early_console_setup);
1090
1091#else /* !CONFIG_SERIAL_SPRD_CONSOLE */
1092#define SPRD_CONSOLE NULL
1093#endif
1094
1095static struct uart_driver sprd_uart_driver = {
1096 .owner = THIS_MODULE,
1097 .driver_name = "sprd_serial",
1098 .dev_name = SPRD_TTY_NAME,
1099 .major = 0,
1100 .minor = 0,
1101 .nr = UART_NR_MAX,
1102 .cons = SPRD_CONSOLE,
1103};
1104
1105static int sprd_remove(struct platform_device *dev)
1106{
1107 struct sprd_uart_port *sup = platform_get_drvdata(dev);
1108
1109 if (sup) {
1110 uart_remove_one_port(&sprd_uart_driver, &sup->port);
1111 sprd_port[sup->port.line] = NULL;
1112 sprd_rx_free_buf(sup);
1113 sprd_ports_num--;
1114 }
1115
1116 if (!sprd_ports_num)
1117 uart_unregister_driver(&sprd_uart_driver);
1118
1119 return 0;
1120}
1121
1122static bool sprd_uart_is_console(struct uart_port *uport)
1123{
1124 struct console *cons = sprd_uart_driver.cons;
1125
1126 if ((cons && cons->index >= 0 && cons->index == uport->line) ||
1127 of_console_check(uport->dev->of_node, SPRD_TTY_NAME, uport->line))
1128 return true;
1129
1130 return false;
1131}
1132
1133static int sprd_clk_init(struct uart_port *uport)
1134{
1135 struct clk *clk_uart, *clk_parent;
1136 struct sprd_uart_port *u = sprd_port[uport->line];
1137
1138 clk_uart = devm_clk_get(uport->dev, "uart");
1139 if (IS_ERR(clk_uart)) {
1140 dev_warn(uport->dev, "uart%d can't get uart clock\n",
1141 uport->line);
1142 clk_uart = NULL;
1143 }
1144
1145 clk_parent = devm_clk_get(uport->dev, "source");
1146 if (IS_ERR(clk_parent)) {
1147 dev_warn(uport->dev, "uart%d can't get source clock\n",
1148 uport->line);
1149 clk_parent = NULL;
1150 }
1151
1152 if (!clk_uart || clk_set_parent(clk_uart, clk_parent))
1153 uport->uartclk = SPRD_DEFAULT_SOURCE_CLK;
1154 else
1155 uport->uartclk = clk_get_rate(clk_uart);
1156
1157 u->clk = devm_clk_get(uport->dev, "enable");
1158 if (IS_ERR(u->clk)) {
1159 if (PTR_ERR(u->clk) == -EPROBE_DEFER)
1160 return -EPROBE_DEFER;
1161
1162 dev_warn(uport->dev, "uart%d can't get enable clock\n",
1163 uport->line);
1164
1165 /* To keep console alive even if the error occurred */
1166 if (!sprd_uart_is_console(uport))
1167 return PTR_ERR(u->clk);
1168
1169 u->clk = NULL;
1170 }
1171
1172 return 0;
1173}
1174
1175static int sprd_probe(struct platform_device *pdev)
1176{
1177 struct resource *res;
1178 struct uart_port *up;
1179 int irq;
1180 int index;
1181 int ret;
1182
1183 index = of_alias_get_id(pdev->dev.of_node, "serial");
1184 if (index < 0 || index >= ARRAY_SIZE(sprd_port)) {
1185 dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index);
1186 return -EINVAL;
1187 }
1188
1189 sprd_port[index] = devm_kzalloc(&pdev->dev, sizeof(*sprd_port[index]),
1190 GFP_KERNEL);
1191 if (!sprd_port[index])
1192 return -ENOMEM;
1193
1194 up = &sprd_port[index]->port;
1195 up->dev = &pdev->dev;
1196 up->line = index;
1197 up->type = PORT_SPRD;
1198 up->iotype = UPIO_MEM;
1199 up->uartclk = SPRD_DEF_RATE;
1200 up->fifosize = SPRD_FIFO_SIZE;
1201 up->ops = &serial_sprd_ops;
1202 up->flags = UPF_BOOT_AUTOCONF;
1203 up->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SPRD_CONSOLE);
1204
1205 ret = sprd_clk_init(up);
1206 if (ret)
1207 return ret;
1208
1209 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1210 up->membase = devm_ioremap_resource(&pdev->dev, res);
1211 if (IS_ERR(up->membase))
1212 return PTR_ERR(up->membase);
1213
1214 up->mapbase = res->start;
1215
1216 irq = platform_get_irq(pdev, 0);
1217 if (irq < 0)
1218 return irq;
1219 up->irq = irq;
1220
1221 /*
1222 * Allocate one dma buffer to prepare for receive transfer, in case
1223 * memory allocation failure at runtime.
1224 */
1225 ret = sprd_rx_alloc_buf(sprd_port[index]);
1226 if (ret)
1227 return ret;
1228
1229 if (!sprd_ports_num) {
1230 ret = uart_register_driver(&sprd_uart_driver);
1231 if (ret < 0) {
1232 pr_err("Failed to register SPRD-UART driver\n");
1233 return ret;
1234 }
1235 }
1236 sprd_ports_num++;
1237
1238 ret = uart_add_one_port(&sprd_uart_driver, up);
1239 if (ret)
1240 sprd_remove(pdev);
1241
1242 platform_set_drvdata(pdev, up);
1243
1244 return ret;
1245}
1246
1247#ifdef CONFIG_PM_SLEEP
1248static int sprd_suspend(struct device *dev)
1249{
1250 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1251
1252 uart_suspend_port(&sprd_uart_driver, &sup->port);
1253
1254 return 0;
1255}
1256
1257static int sprd_resume(struct device *dev)
1258{
1259 struct sprd_uart_port *sup = dev_get_drvdata(dev);
1260
1261 uart_resume_port(&sprd_uart_driver, &sup->port);
1262
1263 return 0;
1264}
1265#endif
1266
1267static SIMPLE_DEV_PM_OPS(sprd_pm_ops, sprd_suspend, sprd_resume);
1268
1269static const struct of_device_id serial_ids[] = {
1270 {.compatible = "sprd,sc9836-uart",},
1271 {}
1272};
1273MODULE_DEVICE_TABLE(of, serial_ids);
1274
1275static struct platform_driver sprd_platform_driver = {
1276 .probe = sprd_probe,
1277 .remove = sprd_remove,
1278 .driver = {
1279 .name = "sprd_serial",
1280 .of_match_table = of_match_ptr(serial_ids),
1281 .pm = &sprd_pm_ops,
1282 },
1283};
1284
1285module_platform_driver(sprd_platform_driver);
1286
1287MODULE_LICENSE("GPL v2");
1288MODULE_DESCRIPTION("Spreadtrum SoC serial driver series");