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1/*
2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
3 *
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
12 *
13 *
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
15 *
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
18 *
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
26 *
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
30 */
31
32#undef DEBUG
33
34#include <linux/device.h>
35#include <linux/module.h>
36#include <linux/tty.h>
37#include <linux/serial.h>
38#include <linux/sysrq.h>
39#include <linux/console.h>
40#include <linux/delay.h>
41#include <linux/io.h>
42#include <linux/of.h>
43#include <linux/of_platform.h>
44#include <linux/clk.h>
45
46#include <asm/mpc52xx.h>
47#include <asm/mpc52xx_psc.h>
48
49#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50#define SUPPORT_SYSRQ
51#endif
52
53#include <linux/serial_core.h>
54
55
56/* We've been assigned a range on the "Low-density serial ports" major */
57#define SERIAL_PSC_MAJOR 204
58#define SERIAL_PSC_MINOR 148
59
60
61#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
62
63
64static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
65 /* Rem: - We use the read_status_mask as a shadow of
66 * psc->mpc52xx_psc_imr
67 * - It's important that is array is all zero on start as we
68 * use it to know if it's initialized or not ! If it's not sure
69 * it's cleared, then a memset(...,0,...) should be added to
70 * the console_init
71 */
72
73/* lookup table for matching device nodes to index numbers */
74static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
75
76static void mpc52xx_uart_of_enumerate(void);
77
78
79#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
80
81
82/* Forward declaration of the interruption handling routine */
83static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
84static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
85
86
87/* Simple macro to test if a port is console or not. This one is taken
88 * for serial_core.c and maybe should be moved to serial_core.h ? */
89#ifdef CONFIG_SERIAL_CORE_CONSOLE
90#define uart_console(port) \
91 ((port)->cons && (port)->cons->index == (port)->line)
92#else
93#define uart_console(port) (0)
94#endif
95
96/* ======================================================================== */
97/* PSC fifo operations for isolating differences between 52xx and 512x */
98/* ======================================================================== */
99
100struct psc_ops {
101 void (*fifo_init)(struct uart_port *port);
102 int (*raw_rx_rdy)(struct uart_port *port);
103 int (*raw_tx_rdy)(struct uart_port *port);
104 int (*rx_rdy)(struct uart_port *port);
105 int (*tx_rdy)(struct uart_port *port);
106 int (*tx_empty)(struct uart_port *port);
107 void (*stop_rx)(struct uart_port *port);
108 void (*start_tx)(struct uart_port *port);
109 void (*stop_tx)(struct uart_port *port);
110 void (*rx_clr_irq)(struct uart_port *port);
111 void (*tx_clr_irq)(struct uart_port *port);
112 void (*write_char)(struct uart_port *port, unsigned char c);
113 unsigned char (*read_char)(struct uart_port *port);
114 void (*cw_disable_ints)(struct uart_port *port);
115 void (*cw_restore_ints)(struct uart_port *port);
116 unsigned int (*set_baudrate)(struct uart_port *port,
117 struct ktermios *new,
118 struct ktermios *old);
119 int (*clock)(struct uart_port *port, int enable);
120 int (*fifoc_init)(void);
121 void (*fifoc_uninit)(void);
122 void (*get_irq)(struct uart_port *, struct device_node *);
123 irqreturn_t (*handle_irq)(struct uart_port *port);
124};
125
126/* setting the prescaler and divisor reg is common for all chips */
127static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
128 u16 prescaler, unsigned int divisor)
129{
130 /* select prescaler */
131 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
132 out_8(&psc->ctur, divisor >> 8);
133 out_8(&psc->ctlr, divisor & 0xff);
134}
135
136#ifdef CONFIG_PPC_MPC52xx
137#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
138static void mpc52xx_psc_fifo_init(struct uart_port *port)
139{
140 struct mpc52xx_psc __iomem *psc = PSC(port);
141 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
142
143 out_8(&fifo->rfcntl, 0x00);
144 out_be16(&fifo->rfalarm, 0x1ff);
145 out_8(&fifo->tfcntl, 0x07);
146 out_be16(&fifo->tfalarm, 0x80);
147
148 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
149 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
150}
151
152static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
153{
154 return in_be16(&PSC(port)->mpc52xx_psc_status)
155 & MPC52xx_PSC_SR_RXRDY;
156}
157
158static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
159{
160 return in_be16(&PSC(port)->mpc52xx_psc_status)
161 & MPC52xx_PSC_SR_TXRDY;
162}
163
164
165static int mpc52xx_psc_rx_rdy(struct uart_port *port)
166{
167 return in_be16(&PSC(port)->mpc52xx_psc_isr)
168 & port->read_status_mask
169 & MPC52xx_PSC_IMR_RXRDY;
170}
171
172static int mpc52xx_psc_tx_rdy(struct uart_port *port)
173{
174 return in_be16(&PSC(port)->mpc52xx_psc_isr)
175 & port->read_status_mask
176 & MPC52xx_PSC_IMR_TXRDY;
177}
178
179static int mpc52xx_psc_tx_empty(struct uart_port *port)
180{
181 return in_be16(&PSC(port)->mpc52xx_psc_status)
182 & MPC52xx_PSC_SR_TXEMP;
183}
184
185static void mpc52xx_psc_start_tx(struct uart_port *port)
186{
187 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
188 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
189}
190
191static void mpc52xx_psc_stop_tx(struct uart_port *port)
192{
193 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
194 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
195}
196
197static void mpc52xx_psc_stop_rx(struct uart_port *port)
198{
199 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
200 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
201}
202
203static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
204{
205}
206
207static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
208{
209}
210
211static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
212{
213 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
214}
215
216static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
217{
218 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
219}
220
221static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
222{
223 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
224}
225
226static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
227{
228 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
229}
230
231static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
232 struct ktermios *new,
233 struct ktermios *old)
234{
235 unsigned int baud;
236 unsigned int divisor;
237
238 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
239 baud = uart_get_baud_rate(port, new, old,
240 port->uartclk / (32 * 0xffff) + 1,
241 port->uartclk / 32);
242 divisor = (port->uartclk + 16 * baud) / (32 * baud);
243
244 /* enable the /32 prescaler and set the divisor */
245 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
246 return baud;
247}
248
249static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
250 struct ktermios *new,
251 struct ktermios *old)
252{
253 unsigned int baud;
254 unsigned int divisor;
255 u16 prescaler;
256
257 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
258 * ipb freq */
259 baud = uart_get_baud_rate(port, new, old,
260 port->uartclk / (32 * 0xffff) + 1,
261 port->uartclk / 4);
262 divisor = (port->uartclk + 2 * baud) / (4 * baud);
263
264 /* select the proper prescaler and set the divisor */
265 if (divisor > 0xffff) {
266 divisor = (divisor + 4) / 8;
267 prescaler = 0xdd00; /* /32 */
268 } else
269 prescaler = 0xff00; /* /4 */
270 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
271 return baud;
272}
273
274static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
275{
276 port->irqflags = IRQF_DISABLED;
277 port->irq = irq_of_parse_and_map(np, 0);
278}
279
280/* 52xx specific interrupt handler. The caller holds the port lock */
281static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
282{
283 return mpc5xxx_uart_process_int(port);
284}
285
286static struct psc_ops mpc52xx_psc_ops = {
287 .fifo_init = mpc52xx_psc_fifo_init,
288 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
289 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
290 .rx_rdy = mpc52xx_psc_rx_rdy,
291 .tx_rdy = mpc52xx_psc_tx_rdy,
292 .tx_empty = mpc52xx_psc_tx_empty,
293 .stop_rx = mpc52xx_psc_stop_rx,
294 .start_tx = mpc52xx_psc_start_tx,
295 .stop_tx = mpc52xx_psc_stop_tx,
296 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
297 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
298 .write_char = mpc52xx_psc_write_char,
299 .read_char = mpc52xx_psc_read_char,
300 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
301 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
302 .set_baudrate = mpc5200_psc_set_baudrate,
303 .get_irq = mpc52xx_psc_get_irq,
304 .handle_irq = mpc52xx_psc_handle_irq,
305};
306
307static struct psc_ops mpc5200b_psc_ops = {
308 .fifo_init = mpc52xx_psc_fifo_init,
309 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
310 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
311 .rx_rdy = mpc52xx_psc_rx_rdy,
312 .tx_rdy = mpc52xx_psc_tx_rdy,
313 .tx_empty = mpc52xx_psc_tx_empty,
314 .stop_rx = mpc52xx_psc_stop_rx,
315 .start_tx = mpc52xx_psc_start_tx,
316 .stop_tx = mpc52xx_psc_stop_tx,
317 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
318 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
319 .write_char = mpc52xx_psc_write_char,
320 .read_char = mpc52xx_psc_read_char,
321 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
322 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
323 .set_baudrate = mpc5200b_psc_set_baudrate,
324 .get_irq = mpc52xx_psc_get_irq,
325 .handle_irq = mpc52xx_psc_handle_irq,
326};
327
328#endif /* CONFIG_MPC52xx */
329
330#ifdef CONFIG_PPC_MPC512x
331#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
332
333/* PSC FIFO Controller for mpc512x */
334struct psc_fifoc {
335 u32 fifoc_cmd;
336 u32 fifoc_int;
337 u32 fifoc_dma;
338 u32 fifoc_axe;
339 u32 fifoc_debug;
340};
341
342static struct psc_fifoc __iomem *psc_fifoc;
343static unsigned int psc_fifoc_irq;
344
345static void mpc512x_psc_fifo_init(struct uart_port *port)
346{
347 /* /32 prescaler */
348 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
349
350 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
351 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
352 out_be32(&FIFO_512x(port)->txalarm, 1);
353 out_be32(&FIFO_512x(port)->tximr, 0);
354
355 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
356 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
357 out_be32(&FIFO_512x(port)->rxalarm, 1);
358 out_be32(&FIFO_512x(port)->rximr, 0);
359
360 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
361 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
362}
363
364static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
365{
366 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
367}
368
369static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
370{
371 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
372}
373
374static int mpc512x_psc_rx_rdy(struct uart_port *port)
375{
376 return in_be32(&FIFO_512x(port)->rxsr)
377 & in_be32(&FIFO_512x(port)->rximr)
378 & MPC512x_PSC_FIFO_ALARM;
379}
380
381static int mpc512x_psc_tx_rdy(struct uart_port *port)
382{
383 return in_be32(&FIFO_512x(port)->txsr)
384 & in_be32(&FIFO_512x(port)->tximr)
385 & MPC512x_PSC_FIFO_ALARM;
386}
387
388static int mpc512x_psc_tx_empty(struct uart_port *port)
389{
390 return in_be32(&FIFO_512x(port)->txsr)
391 & MPC512x_PSC_FIFO_EMPTY;
392}
393
394static void mpc512x_psc_stop_rx(struct uart_port *port)
395{
396 unsigned long rx_fifo_imr;
397
398 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
399 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
400 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
401}
402
403static void mpc512x_psc_start_tx(struct uart_port *port)
404{
405 unsigned long tx_fifo_imr;
406
407 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
408 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
409 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
410}
411
412static void mpc512x_psc_stop_tx(struct uart_port *port)
413{
414 unsigned long tx_fifo_imr;
415
416 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
417 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
418 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
419}
420
421static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
422{
423 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
424}
425
426static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
427{
428 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
429}
430
431static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
432{
433 out_8(&FIFO_512x(port)->txdata_8, c);
434}
435
436static unsigned char mpc512x_psc_read_char(struct uart_port *port)
437{
438 return in_8(&FIFO_512x(port)->rxdata_8);
439}
440
441static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
442{
443 port->read_status_mask =
444 in_be32(&FIFO_512x(port)->tximr) << 16 |
445 in_be32(&FIFO_512x(port)->rximr);
446 out_be32(&FIFO_512x(port)->tximr, 0);
447 out_be32(&FIFO_512x(port)->rximr, 0);
448}
449
450static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
451{
452 out_be32(&FIFO_512x(port)->tximr,
453 (port->read_status_mask >> 16) & 0x7f);
454 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
455}
456
457static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
458 struct ktermios *new,
459 struct ktermios *old)
460{
461 unsigned int baud;
462 unsigned int divisor;
463
464 /*
465 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
466 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
467 * Furthermore, it states that "After reset, the prescaler by 10
468 * for the UART mode is selected", but the reset register value is
469 * 0x0000 which means a /32 prescaler. This is wrong.
470 *
471 * In reality using /32 prescaler doesn't work, as it is not supported!
472 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
473 * Chapter 4.1 PSC in UART Mode.
474 * Calculate with a /16 prescaler here.
475 */
476
477 /* uartclk contains the ips freq */
478 baud = uart_get_baud_rate(port, new, old,
479 port->uartclk / (16 * 0xffff) + 1,
480 port->uartclk / 16);
481 divisor = (port->uartclk + 8 * baud) / (16 * baud);
482
483 /* enable the /16 prescaler and set the divisor */
484 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
485 return baud;
486}
487
488/* Init PSC FIFO Controller */
489static int __init mpc512x_psc_fifoc_init(void)
490{
491 struct device_node *np;
492
493 np = of_find_compatible_node(NULL, NULL,
494 "fsl,mpc5121-psc-fifo");
495 if (!np) {
496 pr_err("%s: Can't find FIFOC node\n", __func__);
497 return -ENODEV;
498 }
499
500 psc_fifoc = of_iomap(np, 0);
501 if (!psc_fifoc) {
502 pr_err("%s: Can't map FIFOC\n", __func__);
503 of_node_put(np);
504 return -ENODEV;
505 }
506
507 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
508 of_node_put(np);
509 if (psc_fifoc_irq == NO_IRQ) {
510 pr_err("%s: Can't get FIFOC irq\n", __func__);
511 iounmap(psc_fifoc);
512 return -ENODEV;
513 }
514
515 return 0;
516}
517
518static void __exit mpc512x_psc_fifoc_uninit(void)
519{
520 iounmap(psc_fifoc);
521}
522
523/* 512x specific interrupt handler. The caller holds the port lock */
524static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
525{
526 unsigned long fifoc_int;
527 int psc_num;
528
529 /* Read pending PSC FIFOC interrupts */
530 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
531
532 /* Check if it is an interrupt for this port */
533 psc_num = (port->mapbase & 0xf00) >> 8;
534 if (test_bit(psc_num, &fifoc_int) ||
535 test_bit(psc_num + 16, &fifoc_int))
536 return mpc5xxx_uart_process_int(port);
537
538 return IRQ_NONE;
539}
540
541static int mpc512x_psc_clock(struct uart_port *port, int enable)
542{
543 struct clk *psc_clk;
544 int psc_num;
545 char clk_name[10];
546
547 if (uart_console(port))
548 return 0;
549
550 psc_num = (port->mapbase & 0xf00) >> 8;
551 snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
552 psc_clk = clk_get(port->dev, clk_name);
553 if (IS_ERR(psc_clk)) {
554 dev_err(port->dev, "Failed to get PSC clock entry!\n");
555 return -ENODEV;
556 }
557
558 dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis");
559
560 if (enable)
561 clk_enable(psc_clk);
562 else
563 clk_disable(psc_clk);
564
565 return 0;
566}
567
568static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
569{
570 port->irqflags = IRQF_SHARED;
571 port->irq = psc_fifoc_irq;
572}
573
574static struct psc_ops mpc512x_psc_ops = {
575 .fifo_init = mpc512x_psc_fifo_init,
576 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
577 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
578 .rx_rdy = mpc512x_psc_rx_rdy,
579 .tx_rdy = mpc512x_psc_tx_rdy,
580 .tx_empty = mpc512x_psc_tx_empty,
581 .stop_rx = mpc512x_psc_stop_rx,
582 .start_tx = mpc512x_psc_start_tx,
583 .stop_tx = mpc512x_psc_stop_tx,
584 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
585 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
586 .write_char = mpc512x_psc_write_char,
587 .read_char = mpc512x_psc_read_char,
588 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
589 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
590 .set_baudrate = mpc512x_psc_set_baudrate,
591 .clock = mpc512x_psc_clock,
592 .fifoc_init = mpc512x_psc_fifoc_init,
593 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
594 .get_irq = mpc512x_psc_get_irq,
595 .handle_irq = mpc512x_psc_handle_irq,
596};
597#endif
598
599static struct psc_ops *psc_ops;
600
601/* ======================================================================== */
602/* UART operations */
603/* ======================================================================== */
604
605static unsigned int
606mpc52xx_uart_tx_empty(struct uart_port *port)
607{
608 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
609}
610
611static void
612mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
613{
614 if (mctrl & TIOCM_RTS)
615 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
616 else
617 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
618}
619
620static unsigned int
621mpc52xx_uart_get_mctrl(struct uart_port *port)
622{
623 unsigned int ret = TIOCM_DSR;
624 u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
625
626 if (!(status & MPC52xx_PSC_CTS))
627 ret |= TIOCM_CTS;
628 if (!(status & MPC52xx_PSC_DCD))
629 ret |= TIOCM_CAR;
630
631 return ret;
632}
633
634static void
635mpc52xx_uart_stop_tx(struct uart_port *port)
636{
637 /* port->lock taken by caller */
638 psc_ops->stop_tx(port);
639}
640
641static void
642mpc52xx_uart_start_tx(struct uart_port *port)
643{
644 /* port->lock taken by caller */
645 psc_ops->start_tx(port);
646}
647
648static void
649mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
650{
651 unsigned long flags;
652 spin_lock_irqsave(&port->lock, flags);
653
654 port->x_char = ch;
655 if (ch) {
656 /* Make sure tx interrupts are on */
657 /* Truly necessary ??? They should be anyway */
658 psc_ops->start_tx(port);
659 }
660
661 spin_unlock_irqrestore(&port->lock, flags);
662}
663
664static void
665mpc52xx_uart_stop_rx(struct uart_port *port)
666{
667 /* port->lock taken by caller */
668 psc_ops->stop_rx(port);
669}
670
671static void
672mpc52xx_uart_enable_ms(struct uart_port *port)
673{
674 struct mpc52xx_psc __iomem *psc = PSC(port);
675
676 /* clear D_*-bits by reading them */
677 in_8(&psc->mpc52xx_psc_ipcr);
678 /* enable CTS and DCD as IPC interrupts */
679 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
680
681 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
682 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
683}
684
685static void
686mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
687{
688 unsigned long flags;
689 spin_lock_irqsave(&port->lock, flags);
690
691 if (ctl == -1)
692 out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK);
693 else
694 out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK);
695
696 spin_unlock_irqrestore(&port->lock, flags);
697}
698
699static int
700mpc52xx_uart_startup(struct uart_port *port)
701{
702 struct mpc52xx_psc __iomem *psc = PSC(port);
703 int ret;
704
705 if (psc_ops->clock) {
706 ret = psc_ops->clock(port, 1);
707 if (ret)
708 return ret;
709 }
710
711 /* Request IRQ */
712 ret = request_irq(port->irq, mpc52xx_uart_int,
713 port->irqflags, "mpc52xx_psc_uart", port);
714 if (ret)
715 return ret;
716
717 /* Reset/activate the port, clear and enable interrupts */
718 out_8(&psc->command, MPC52xx_PSC_RST_RX);
719 out_8(&psc->command, MPC52xx_PSC_RST_TX);
720
721 out_be32(&psc->sicr, 0); /* UART mode DCD ignored */
722
723 psc_ops->fifo_init(port);
724
725 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
726 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
727
728 return 0;
729}
730
731static void
732mpc52xx_uart_shutdown(struct uart_port *port)
733{
734 struct mpc52xx_psc __iomem *psc = PSC(port);
735
736 /* Shut down the port. Leave TX active if on a console port */
737 out_8(&psc->command, MPC52xx_PSC_RST_RX);
738 if (!uart_console(port))
739 out_8(&psc->command, MPC52xx_PSC_RST_TX);
740
741 port->read_status_mask = 0;
742 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
743
744 if (psc_ops->clock)
745 psc_ops->clock(port, 0);
746
747 /* Release interrupt */
748 free_irq(port->irq, port);
749}
750
751static void
752mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
753 struct ktermios *old)
754{
755 struct mpc52xx_psc __iomem *psc = PSC(port);
756 unsigned long flags;
757 unsigned char mr1, mr2;
758 unsigned int j;
759 unsigned int baud;
760
761 /* Prepare what we're gonna write */
762 mr1 = 0;
763
764 switch (new->c_cflag & CSIZE) {
765 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
766 break;
767 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
768 break;
769 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
770 break;
771 case CS8:
772 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
773 }
774
775 if (new->c_cflag & PARENB) {
776 mr1 |= (new->c_cflag & PARODD) ?
777 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
778 } else
779 mr1 |= MPC52xx_PSC_MODE_PARNONE;
780
781
782 mr2 = 0;
783
784 if (new->c_cflag & CSTOPB)
785 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
786 else
787 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
788 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
789 MPC52xx_PSC_MODE_ONE_STOP;
790
791 if (new->c_cflag & CRTSCTS) {
792 mr1 |= MPC52xx_PSC_MODE_RXRTS;
793 mr2 |= MPC52xx_PSC_MODE_TXCTS;
794 }
795
796 /* Get the lock */
797 spin_lock_irqsave(&port->lock, flags);
798
799 /* Do our best to flush TX & RX, so we don't lose anything */
800 /* But we don't wait indefinitely ! */
801 j = 5000000; /* Maximum wait */
802 /* FIXME Can't receive chars since set_termios might be called at early
803 * boot for the console, all stuff is not yet ready to receive at that
804 * time and that just makes the kernel oops */
805 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
806 while (!mpc52xx_uart_tx_empty(port) && --j)
807 udelay(1);
808
809 if (!j)
810 printk(KERN_ERR "mpc52xx_uart.c: "
811 "Unable to flush RX & TX fifos in-time in set_termios."
812 "Some chars may have been lost.\n");
813
814 /* Reset the TX & RX */
815 out_8(&psc->command, MPC52xx_PSC_RST_RX);
816 out_8(&psc->command, MPC52xx_PSC_RST_TX);
817
818 /* Send new mode settings */
819 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
820 out_8(&psc->mode, mr1);
821 out_8(&psc->mode, mr2);
822 baud = psc_ops->set_baudrate(port, new, old);
823
824 /* Update the per-port timeout */
825 uart_update_timeout(port, new->c_cflag, baud);
826
827 if (UART_ENABLE_MS(port, new->c_cflag))
828 mpc52xx_uart_enable_ms(port);
829
830 /* Reenable TX & RX */
831 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE);
832 out_8(&psc->command, MPC52xx_PSC_RX_ENABLE);
833
834 /* We're all set, release the lock */
835 spin_unlock_irqrestore(&port->lock, flags);
836}
837
838static const char *
839mpc52xx_uart_type(struct uart_port *port)
840{
841 /*
842 * We keep using PORT_MPC52xx for historic reasons although it applies
843 * for MPC512x, too, but print "MPC5xxx" to not irritate users
844 */
845 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
846}
847
848static void
849mpc52xx_uart_release_port(struct uart_port *port)
850{
851 /* remapped by us ? */
852 if (port->flags & UPF_IOREMAP) {
853 iounmap(port->membase);
854 port->membase = NULL;
855 }
856
857 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
858}
859
860static int
861mpc52xx_uart_request_port(struct uart_port *port)
862{
863 int err;
864
865 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
866 port->membase = ioremap(port->mapbase,
867 sizeof(struct mpc52xx_psc));
868
869 if (!port->membase)
870 return -EINVAL;
871
872 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
873 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
874
875 if (err && (port->flags & UPF_IOREMAP)) {
876 iounmap(port->membase);
877 port->membase = NULL;
878 }
879
880 return err;
881}
882
883static void
884mpc52xx_uart_config_port(struct uart_port *port, int flags)
885{
886 if ((flags & UART_CONFIG_TYPE)
887 && (mpc52xx_uart_request_port(port) == 0))
888 port->type = PORT_MPC52xx;
889}
890
891static int
892mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
893{
894 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
895 return -EINVAL;
896
897 if ((ser->irq != port->irq) ||
898 (ser->io_type != UPIO_MEM) ||
899 (ser->baud_base != port->uartclk) ||
900 (ser->iomem_base != (void *)port->mapbase) ||
901 (ser->hub6 != 0))
902 return -EINVAL;
903
904 return 0;
905}
906
907
908static struct uart_ops mpc52xx_uart_ops = {
909 .tx_empty = mpc52xx_uart_tx_empty,
910 .set_mctrl = mpc52xx_uart_set_mctrl,
911 .get_mctrl = mpc52xx_uart_get_mctrl,
912 .stop_tx = mpc52xx_uart_stop_tx,
913 .start_tx = mpc52xx_uart_start_tx,
914 .send_xchar = mpc52xx_uart_send_xchar,
915 .stop_rx = mpc52xx_uart_stop_rx,
916 .enable_ms = mpc52xx_uart_enable_ms,
917 .break_ctl = mpc52xx_uart_break_ctl,
918 .startup = mpc52xx_uart_startup,
919 .shutdown = mpc52xx_uart_shutdown,
920 .set_termios = mpc52xx_uart_set_termios,
921/* .pm = mpc52xx_uart_pm, Not supported yet */
922/* .set_wake = mpc52xx_uart_set_wake, Not supported yet */
923 .type = mpc52xx_uart_type,
924 .release_port = mpc52xx_uart_release_port,
925 .request_port = mpc52xx_uart_request_port,
926 .config_port = mpc52xx_uart_config_port,
927 .verify_port = mpc52xx_uart_verify_port
928};
929
930
931/* ======================================================================== */
932/* Interrupt handling */
933/* ======================================================================== */
934
935static inline int
936mpc52xx_uart_int_rx_chars(struct uart_port *port)
937{
938 struct tty_struct *tty = port->state->port.tty;
939 unsigned char ch, flag;
940 unsigned short status;
941
942 /* While we can read, do so ! */
943 while (psc_ops->raw_rx_rdy(port)) {
944 /* Get the char */
945 ch = psc_ops->read_char(port);
946
947 /* Handle sysreq char */
948#ifdef SUPPORT_SYSRQ
949 if (uart_handle_sysrq_char(port, ch)) {
950 port->sysrq = 0;
951 continue;
952 }
953#endif
954
955 /* Store it */
956
957 flag = TTY_NORMAL;
958 port->icount.rx++;
959
960 status = in_be16(&PSC(port)->mpc52xx_psc_status);
961
962 if (status & (MPC52xx_PSC_SR_PE |
963 MPC52xx_PSC_SR_FE |
964 MPC52xx_PSC_SR_RB)) {
965
966 if (status & MPC52xx_PSC_SR_RB) {
967 flag = TTY_BREAK;
968 uart_handle_break(port);
969 port->icount.brk++;
970 } else if (status & MPC52xx_PSC_SR_PE) {
971 flag = TTY_PARITY;
972 port->icount.parity++;
973 }
974 else if (status & MPC52xx_PSC_SR_FE) {
975 flag = TTY_FRAME;
976 port->icount.frame++;
977 }
978
979 /* Clear error condition */
980 out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT);
981
982 }
983 tty_insert_flip_char(tty, ch, flag);
984 if (status & MPC52xx_PSC_SR_OE) {
985 /*
986 * Overrun is special, since it's
987 * reported immediately, and doesn't
988 * affect the current character
989 */
990 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
991 port->icount.overrun++;
992 }
993 }
994
995 spin_unlock(&port->lock);
996 tty_flip_buffer_push(tty);
997 spin_lock(&port->lock);
998
999 return psc_ops->raw_rx_rdy(port);
1000}
1001
1002static inline int
1003mpc52xx_uart_int_tx_chars(struct uart_port *port)
1004{
1005 struct circ_buf *xmit = &port->state->xmit;
1006
1007 /* Process out of band chars */
1008 if (port->x_char) {
1009 psc_ops->write_char(port, port->x_char);
1010 port->icount.tx++;
1011 port->x_char = 0;
1012 return 1;
1013 }
1014
1015 /* Nothing to do ? */
1016 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1017 mpc52xx_uart_stop_tx(port);
1018 return 0;
1019 }
1020
1021 /* Send chars */
1022 while (psc_ops->raw_tx_rdy(port)) {
1023 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1024 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1025 port->icount.tx++;
1026 if (uart_circ_empty(xmit))
1027 break;
1028 }
1029
1030 /* Wake up */
1031 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1032 uart_write_wakeup(port);
1033
1034 /* Maybe we're done after all */
1035 if (uart_circ_empty(xmit)) {
1036 mpc52xx_uart_stop_tx(port);
1037 return 0;
1038 }
1039
1040 return 1;
1041}
1042
1043static irqreturn_t
1044mpc5xxx_uart_process_int(struct uart_port *port)
1045{
1046 unsigned long pass = ISR_PASS_LIMIT;
1047 unsigned int keepgoing;
1048 u8 status;
1049
1050 /* While we have stuff to do, we continue */
1051 do {
1052 /* If we don't find anything to do, we stop */
1053 keepgoing = 0;
1054
1055 psc_ops->rx_clr_irq(port);
1056 if (psc_ops->rx_rdy(port))
1057 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1058
1059 psc_ops->tx_clr_irq(port);
1060 if (psc_ops->tx_rdy(port))
1061 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1062
1063 status = in_8(&PSC(port)->mpc52xx_psc_ipcr);
1064 if (status & MPC52xx_PSC_D_DCD)
1065 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1066
1067 if (status & MPC52xx_PSC_D_CTS)
1068 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1069
1070 /* Limit number of iteration */
1071 if (!(--pass))
1072 keepgoing = 0;
1073
1074 } while (keepgoing);
1075
1076 return IRQ_HANDLED;
1077}
1078
1079static irqreturn_t
1080mpc52xx_uart_int(int irq, void *dev_id)
1081{
1082 struct uart_port *port = dev_id;
1083 irqreturn_t ret;
1084
1085 spin_lock(&port->lock);
1086
1087 ret = psc_ops->handle_irq(port);
1088
1089 spin_unlock(&port->lock);
1090
1091 return ret;
1092}
1093
1094/* ======================================================================== */
1095/* Console ( if applicable ) */
1096/* ======================================================================== */
1097
1098#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1099
1100static void __init
1101mpc52xx_console_get_options(struct uart_port *port,
1102 int *baud, int *parity, int *bits, int *flow)
1103{
1104 struct mpc52xx_psc __iomem *psc = PSC(port);
1105 unsigned char mr1;
1106
1107 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1108
1109 /* Read the mode registers */
1110 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
1111 mr1 = in_8(&psc->mode);
1112
1113 /* CT{U,L}R are write-only ! */
1114 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1115
1116 /* Parse them */
1117 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1118 case MPC52xx_PSC_MODE_5_BITS:
1119 *bits = 5;
1120 break;
1121 case MPC52xx_PSC_MODE_6_BITS:
1122 *bits = 6;
1123 break;
1124 case MPC52xx_PSC_MODE_7_BITS:
1125 *bits = 7;
1126 break;
1127 case MPC52xx_PSC_MODE_8_BITS:
1128 default:
1129 *bits = 8;
1130 }
1131
1132 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1133 *parity = 'n';
1134 else
1135 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1136}
1137
1138static void
1139mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1140{
1141 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1142 unsigned int i, j;
1143
1144 /* Disable interrupts */
1145 psc_ops->cw_disable_ints(port);
1146
1147 /* Wait the TX buffer to be empty */
1148 j = 5000000; /* Maximum wait */
1149 while (!mpc52xx_uart_tx_empty(port) && --j)
1150 udelay(1);
1151
1152 /* Write all the chars */
1153 for (i = 0; i < count; i++, s++) {
1154 /* Line return handling */
1155 if (*s == '\n')
1156 psc_ops->write_char(port, '\r');
1157
1158 /* Send the char */
1159 psc_ops->write_char(port, *s);
1160
1161 /* Wait the TX buffer to be empty */
1162 j = 20000; /* Maximum wait */
1163 while (!mpc52xx_uart_tx_empty(port) && --j)
1164 udelay(1);
1165 }
1166
1167 /* Restore interrupt state */
1168 psc_ops->cw_restore_ints(port);
1169}
1170
1171
1172static int __init
1173mpc52xx_console_setup(struct console *co, char *options)
1174{
1175 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1176 struct device_node *np = mpc52xx_uart_nodes[co->index];
1177 unsigned int uartclk;
1178 struct resource res;
1179 int ret;
1180
1181 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1182 int bits = 8;
1183 int parity = 'n';
1184 int flow = 'n';
1185
1186 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1187 co, co->index, options);
1188
1189 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1190 pr_debug("PSC%x out of range\n", co->index);
1191 return -EINVAL;
1192 }
1193
1194 if (!np) {
1195 pr_debug("PSC%x not found in device tree\n", co->index);
1196 return -EINVAL;
1197 }
1198
1199 pr_debug("Console on ttyPSC%x is %s\n",
1200 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1201
1202 /* Fetch register locations */
1203 ret = of_address_to_resource(np, 0, &res);
1204 if (ret) {
1205 pr_debug("Could not get resources for PSC%x\n", co->index);
1206 return ret;
1207 }
1208
1209 uartclk = mpc5xxx_get_bus_frequency(np);
1210 if (uartclk == 0) {
1211 pr_debug("Could not find uart clock frequency!\n");
1212 return -EINVAL;
1213 }
1214
1215 /* Basic port init. Needed since we use some uart_??? func before
1216 * real init for early access */
1217 spin_lock_init(&port->lock);
1218 port->uartclk = uartclk;
1219 port->ops = &mpc52xx_uart_ops;
1220 port->mapbase = res.start;
1221 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1222 port->irq = irq_of_parse_and_map(np, 0);
1223
1224 if (port->membase == NULL)
1225 return -EINVAL;
1226
1227 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1228 (void *)port->mapbase, port->membase,
1229 port->irq, port->uartclk);
1230
1231 /* Setup the port parameters accoding to options */
1232 if (options)
1233 uart_parse_options(options, &baud, &parity, &bits, &flow);
1234 else
1235 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1236
1237 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1238 baud, bits, parity, flow);
1239
1240 return uart_set_options(port, co, baud, parity, bits, flow);
1241}
1242
1243
1244static struct uart_driver mpc52xx_uart_driver;
1245
1246static struct console mpc52xx_console = {
1247 .name = "ttyPSC",
1248 .write = mpc52xx_console_write,
1249 .device = uart_console_device,
1250 .setup = mpc52xx_console_setup,
1251 .flags = CON_PRINTBUFFER,
1252 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1253 .data = &mpc52xx_uart_driver,
1254};
1255
1256
1257static int __init
1258mpc52xx_console_init(void)
1259{
1260 mpc52xx_uart_of_enumerate();
1261 register_console(&mpc52xx_console);
1262 return 0;
1263}
1264
1265console_initcall(mpc52xx_console_init);
1266
1267#define MPC52xx_PSC_CONSOLE &mpc52xx_console
1268#else
1269#define MPC52xx_PSC_CONSOLE NULL
1270#endif
1271
1272
1273/* ======================================================================== */
1274/* UART Driver */
1275/* ======================================================================== */
1276
1277static struct uart_driver mpc52xx_uart_driver = {
1278 .driver_name = "mpc52xx_psc_uart",
1279 .dev_name = "ttyPSC",
1280 .major = SERIAL_PSC_MAJOR,
1281 .minor = SERIAL_PSC_MINOR,
1282 .nr = MPC52xx_PSC_MAXNUM,
1283 .cons = MPC52xx_PSC_CONSOLE,
1284};
1285
1286/* ======================================================================== */
1287/* OF Platform Driver */
1288/* ======================================================================== */
1289
1290static struct of_device_id mpc52xx_uart_of_match[] = {
1291#ifdef CONFIG_PPC_MPC52xx
1292 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1293 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1294 /* binding used by old lite5200 device trees: */
1295 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1296 /* binding used by efika: */
1297 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1298#endif
1299#ifdef CONFIG_PPC_MPC512x
1300 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1301#endif
1302 {},
1303};
1304
1305static int __devinit mpc52xx_uart_of_probe(struct platform_device *op)
1306{
1307 int idx = -1;
1308 unsigned int uartclk;
1309 struct uart_port *port = NULL;
1310 struct resource res;
1311 int ret;
1312
1313 /* Check validity & presence */
1314 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1315 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1316 break;
1317 if (idx >= MPC52xx_PSC_MAXNUM)
1318 return -EINVAL;
1319 pr_debug("Found %s assigned to ttyPSC%x\n",
1320 mpc52xx_uart_nodes[idx]->full_name, idx);
1321
1322 /* set the uart clock to the input clock of the psc, the different
1323 * prescalers are taken into account in the set_baudrate() methods
1324 * of the respective chip */
1325 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1326 if (uartclk == 0) {
1327 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1328 return -EINVAL;
1329 }
1330
1331 /* Init the port structure */
1332 port = &mpc52xx_uart_ports[idx];
1333
1334 spin_lock_init(&port->lock);
1335 port->uartclk = uartclk;
1336 port->fifosize = 512;
1337 port->iotype = UPIO_MEM;
1338 port->flags = UPF_BOOT_AUTOCONF |
1339 (uart_console(port) ? 0 : UPF_IOREMAP);
1340 port->line = idx;
1341 port->ops = &mpc52xx_uart_ops;
1342 port->dev = &op->dev;
1343
1344 /* Search for IRQ and mapbase */
1345 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1346 if (ret)
1347 return ret;
1348
1349 port->mapbase = res.start;
1350 if (!port->mapbase) {
1351 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1352 return -EINVAL;
1353 }
1354
1355 psc_ops->get_irq(port, op->dev.of_node);
1356 if (port->irq == NO_IRQ) {
1357 dev_dbg(&op->dev, "Could not get irq\n");
1358 return -EINVAL;
1359 }
1360
1361 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1362 (void *)port->mapbase, port->irq, port->uartclk);
1363
1364 /* Add the port to the uart sub-system */
1365 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1366 if (ret)
1367 return ret;
1368
1369 dev_set_drvdata(&op->dev, (void *)port);
1370 return 0;
1371}
1372
1373static int
1374mpc52xx_uart_of_remove(struct platform_device *op)
1375{
1376 struct uart_port *port = dev_get_drvdata(&op->dev);
1377 dev_set_drvdata(&op->dev, NULL);
1378
1379 if (port)
1380 uart_remove_one_port(&mpc52xx_uart_driver, port);
1381
1382 return 0;
1383}
1384
1385#ifdef CONFIG_PM
1386static int
1387mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1388{
1389 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1390
1391 if (port)
1392 uart_suspend_port(&mpc52xx_uart_driver, port);
1393
1394 return 0;
1395}
1396
1397static int
1398mpc52xx_uart_of_resume(struct platform_device *op)
1399{
1400 struct uart_port *port = (struct uart_port *) dev_get_drvdata(&op->dev);
1401
1402 if (port)
1403 uart_resume_port(&mpc52xx_uart_driver, port);
1404
1405 return 0;
1406}
1407#endif
1408
1409static void
1410mpc52xx_uart_of_assign(struct device_node *np)
1411{
1412 int i;
1413
1414 /* Find the first free PSC number */
1415 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1416 if (mpc52xx_uart_nodes[i] == NULL) {
1417 of_node_get(np);
1418 mpc52xx_uart_nodes[i] = np;
1419 return;
1420 }
1421 }
1422}
1423
1424static void
1425mpc52xx_uart_of_enumerate(void)
1426{
1427 static int enum_done;
1428 struct device_node *np;
1429 const struct of_device_id *match;
1430 int i;
1431
1432 if (enum_done)
1433 return;
1434
1435 /* Assign index to each PSC in device tree */
1436 for_each_matching_node(np, mpc52xx_uart_of_match) {
1437 match = of_match_node(mpc52xx_uart_of_match, np);
1438 psc_ops = match->data;
1439 mpc52xx_uart_of_assign(np);
1440 }
1441
1442 enum_done = 1;
1443
1444 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1445 if (mpc52xx_uart_nodes[i])
1446 pr_debug("%s assigned to ttyPSC%x\n",
1447 mpc52xx_uart_nodes[i]->full_name, i);
1448 }
1449}
1450
1451MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1452
1453static struct platform_driver mpc52xx_uart_of_driver = {
1454 .probe = mpc52xx_uart_of_probe,
1455 .remove = mpc52xx_uart_of_remove,
1456#ifdef CONFIG_PM
1457 .suspend = mpc52xx_uart_of_suspend,
1458 .resume = mpc52xx_uart_of_resume,
1459#endif
1460 .driver = {
1461 .name = "mpc52xx-psc-uart",
1462 .owner = THIS_MODULE,
1463 .of_match_table = mpc52xx_uart_of_match,
1464 },
1465};
1466
1467
1468/* ======================================================================== */
1469/* Module */
1470/* ======================================================================== */
1471
1472static int __init
1473mpc52xx_uart_init(void)
1474{
1475 int ret;
1476
1477 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1478
1479 ret = uart_register_driver(&mpc52xx_uart_driver);
1480 if (ret) {
1481 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1482 __FILE__, ret);
1483 return ret;
1484 }
1485
1486 mpc52xx_uart_of_enumerate();
1487
1488 /*
1489 * Map the PSC FIFO Controller and init if on MPC512x.
1490 */
1491 if (psc_ops && psc_ops->fifoc_init) {
1492 ret = psc_ops->fifoc_init();
1493 if (ret)
1494 return ret;
1495 }
1496
1497 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1498 if (ret) {
1499 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1500 __FILE__, ret);
1501 uart_unregister_driver(&mpc52xx_uart_driver);
1502 return ret;
1503 }
1504
1505 return 0;
1506}
1507
1508static void __exit
1509mpc52xx_uart_exit(void)
1510{
1511 if (psc_ops->fifoc_uninit)
1512 psc_ops->fifoc_uninit();
1513
1514 platform_driver_unregister(&mpc52xx_uart_of_driver);
1515 uart_unregister_driver(&mpc52xx_uart_driver);
1516}
1517
1518
1519module_init(mpc52xx_uart_init);
1520module_exit(mpc52xx_uart_exit);
1521
1522MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1523MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1524MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4 *
5 * FIXME According to the usermanual the status bits in the status register
6 * are only updated when the peripherals access the FIFO and not when the
7 * CPU access them. So since we use this bits to know when we stop writing
8 * and reading, they may not be updated in-time and a race condition may
9 * exists. But I haven't be able to prove this and I don't care. But if
10 * any problem arises, it might worth checking. The TX/RX FIFO Stats
11 * registers should be used in addition.
12 * Update: Actually, they seem updated ... At least the bits we use.
13 *
14 *
15 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
16 *
17 * Some of the code has been inspired/copied from the 2.4 code written
18 * by Dale Farnsworth <dfarnsworth@mvista.com>.
19 *
20 * Copyright (C) 2008 Freescale Semiconductor Inc.
21 * John Rigby <jrigby@gmail.com>
22 * Added support for MPC5121
23 * Copyright (C) 2006 Secret Lab Technologies Ltd.
24 * Grant Likely <grant.likely@secretlab.ca>
25 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
26 * Copyright (C) 2003 MontaVista, Software, Inc.
27 */
28
29#undef DEBUG
30
31#include <linux/device.h>
32#include <linux/module.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/delay.h>
39#include <linux/io.h>
40#include <linux/of.h>
41#include <linux/of_platform.h>
42#include <linux/clk.h>
43
44#include <asm/mpc52xx.h>
45#include <asm/mpc52xx_psc.h>
46
47#include <linux/serial_core.h>
48
49
50/* We've been assigned a range on the "Low-density serial ports" major */
51#define SERIAL_PSC_MAJOR 204
52#define SERIAL_PSC_MINOR 148
53
54
55#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
56
57
58static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
59 /* Rem: - We use the read_status_mask as a shadow of
60 * psc->mpc52xx_psc_imr
61 * - It's important that is array is all zero on start as we
62 * use it to know if it's initialized or not ! If it's not sure
63 * it's cleared, then a memset(...,0,...) should be added to
64 * the console_init
65 */
66
67/* lookup table for matching device nodes to index numbers */
68static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
69
70static void mpc52xx_uart_of_enumerate(void);
71
72
73#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
74
75
76/* Forward declaration of the interruption handling routine */
77static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
78static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
79
80/* ======================================================================== */
81/* PSC fifo operations for isolating differences between 52xx and 512x */
82/* ======================================================================== */
83
84struct psc_ops {
85 void (*fifo_init)(struct uart_port *port);
86 int (*raw_rx_rdy)(struct uart_port *port);
87 int (*raw_tx_rdy)(struct uart_port *port);
88 int (*rx_rdy)(struct uart_port *port);
89 int (*tx_rdy)(struct uart_port *port);
90 int (*tx_empty)(struct uart_port *port);
91 void (*stop_rx)(struct uart_port *port);
92 void (*start_tx)(struct uart_port *port);
93 void (*stop_tx)(struct uart_port *port);
94 void (*rx_clr_irq)(struct uart_port *port);
95 void (*tx_clr_irq)(struct uart_port *port);
96 void (*write_char)(struct uart_port *port, unsigned char c);
97 unsigned char (*read_char)(struct uart_port *port);
98 void (*cw_disable_ints)(struct uart_port *port);
99 void (*cw_restore_ints)(struct uart_port *port);
100 unsigned int (*set_baudrate)(struct uart_port *port,
101 struct ktermios *new,
102 struct ktermios *old);
103 int (*clock_alloc)(struct uart_port *port);
104 void (*clock_relse)(struct uart_port *port);
105 int (*clock)(struct uart_port *port, int enable);
106 int (*fifoc_init)(void);
107 void (*fifoc_uninit)(void);
108 void (*get_irq)(struct uart_port *, struct device_node *);
109 irqreturn_t (*handle_irq)(struct uart_port *port);
110 u16 (*get_status)(struct uart_port *port);
111 u8 (*get_ipcr)(struct uart_port *port);
112 void (*command)(struct uart_port *port, u8 cmd);
113 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
114 void (*set_rts)(struct uart_port *port, int state);
115 void (*enable_ms)(struct uart_port *port);
116 void (*set_sicr)(struct uart_port *port, u32 val);
117 void (*set_imr)(struct uart_port *port, u16 val);
118 u8 (*get_mr1)(struct uart_port *port);
119};
120
121/* setting the prescaler and divisor reg is common for all chips */
122static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
123 u16 prescaler, unsigned int divisor)
124{
125 /* select prescaler */
126 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
127 out_8(&psc->ctur, divisor >> 8);
128 out_8(&psc->ctlr, divisor & 0xff);
129}
130
131static u16 mpc52xx_psc_get_status(struct uart_port *port)
132{
133 return in_be16(&PSC(port)->mpc52xx_psc_status);
134}
135
136static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
137{
138 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
139}
140
141static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
142{
143 out_8(&PSC(port)->command, cmd);
144}
145
146static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
147{
148 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
149 out_8(&PSC(port)->mode, mr1);
150 out_8(&PSC(port)->mode, mr2);
151}
152
153static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
154{
155 if (state)
156 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
157 else
158 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
159}
160
161static void mpc52xx_psc_enable_ms(struct uart_port *port)
162{
163 struct mpc52xx_psc __iomem *psc = PSC(port);
164
165 /* clear D_*-bits by reading them */
166 in_8(&psc->mpc52xx_psc_ipcr);
167 /* enable CTS and DCD as IPC interrupts */
168 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
169
170 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
171 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
172}
173
174static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
175{
176 out_be32(&PSC(port)->sicr, val);
177}
178
179static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
180{
181 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
182}
183
184static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
185{
186 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
187 return in_8(&PSC(port)->mode);
188}
189
190#ifdef CONFIG_PPC_MPC52xx
191#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
192static void mpc52xx_psc_fifo_init(struct uart_port *port)
193{
194 struct mpc52xx_psc __iomem *psc = PSC(port);
195 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
196
197 out_8(&fifo->rfcntl, 0x00);
198 out_be16(&fifo->rfalarm, 0x1ff);
199 out_8(&fifo->tfcntl, 0x07);
200 out_be16(&fifo->tfalarm, 0x80);
201
202 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
203 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
204}
205
206static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
207{
208 return in_be16(&PSC(port)->mpc52xx_psc_status)
209 & MPC52xx_PSC_SR_RXRDY;
210}
211
212static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
213{
214 return in_be16(&PSC(port)->mpc52xx_psc_status)
215 & MPC52xx_PSC_SR_TXRDY;
216}
217
218
219static int mpc52xx_psc_rx_rdy(struct uart_port *port)
220{
221 return in_be16(&PSC(port)->mpc52xx_psc_isr)
222 & port->read_status_mask
223 & MPC52xx_PSC_IMR_RXRDY;
224}
225
226static int mpc52xx_psc_tx_rdy(struct uart_port *port)
227{
228 return in_be16(&PSC(port)->mpc52xx_psc_isr)
229 & port->read_status_mask
230 & MPC52xx_PSC_IMR_TXRDY;
231}
232
233static int mpc52xx_psc_tx_empty(struct uart_port *port)
234{
235 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
236
237 return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
238}
239
240static void mpc52xx_psc_start_tx(struct uart_port *port)
241{
242 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
243 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
244}
245
246static void mpc52xx_psc_stop_tx(struct uart_port *port)
247{
248 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
249 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
250}
251
252static void mpc52xx_psc_stop_rx(struct uart_port *port)
253{
254 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
255 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
256}
257
258static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
259{
260}
261
262static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
263{
264}
265
266static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
267{
268 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
269}
270
271static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
272{
273 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
274}
275
276static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
277{
278 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
279}
280
281static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
282{
283 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
284}
285
286static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
287 struct ktermios *new,
288 struct ktermios *old)
289{
290 unsigned int baud;
291 unsigned int divisor;
292
293 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
294 baud = uart_get_baud_rate(port, new, old,
295 port->uartclk / (32 * 0xffff) + 1,
296 port->uartclk / 32);
297 divisor = (port->uartclk + 16 * baud) / (32 * baud);
298
299 /* enable the /32 prescaler and set the divisor */
300 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
301 return baud;
302}
303
304static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
305 struct ktermios *new,
306 struct ktermios *old)
307{
308 unsigned int baud;
309 unsigned int divisor;
310 u16 prescaler;
311
312 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
313 * ipb freq */
314 baud = uart_get_baud_rate(port, new, old,
315 port->uartclk / (32 * 0xffff) + 1,
316 port->uartclk / 4);
317 divisor = (port->uartclk + 2 * baud) / (4 * baud);
318
319 /* select the proper prescaler and set the divisor
320 * prefer high prescaler for more tolerance on low baudrates */
321 if (divisor > 0xffff || baud <= 115200) {
322 divisor = (divisor + 4) / 8;
323 prescaler = 0xdd00; /* /32 */
324 } else
325 prescaler = 0xff00; /* /4 */
326 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
327 return baud;
328}
329
330static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
331{
332 port->irqflags = 0;
333 port->irq = irq_of_parse_and_map(np, 0);
334}
335
336/* 52xx specific interrupt handler. The caller holds the port lock */
337static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
338{
339 return mpc5xxx_uart_process_int(port);
340}
341
342static const struct psc_ops mpc52xx_psc_ops = {
343 .fifo_init = mpc52xx_psc_fifo_init,
344 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
345 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
346 .rx_rdy = mpc52xx_psc_rx_rdy,
347 .tx_rdy = mpc52xx_psc_tx_rdy,
348 .tx_empty = mpc52xx_psc_tx_empty,
349 .stop_rx = mpc52xx_psc_stop_rx,
350 .start_tx = mpc52xx_psc_start_tx,
351 .stop_tx = mpc52xx_psc_stop_tx,
352 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
353 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
354 .write_char = mpc52xx_psc_write_char,
355 .read_char = mpc52xx_psc_read_char,
356 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
357 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
358 .set_baudrate = mpc5200_psc_set_baudrate,
359 .get_irq = mpc52xx_psc_get_irq,
360 .handle_irq = mpc52xx_psc_handle_irq,
361 .get_status = mpc52xx_psc_get_status,
362 .get_ipcr = mpc52xx_psc_get_ipcr,
363 .command = mpc52xx_psc_command,
364 .set_mode = mpc52xx_psc_set_mode,
365 .set_rts = mpc52xx_psc_set_rts,
366 .enable_ms = mpc52xx_psc_enable_ms,
367 .set_sicr = mpc52xx_psc_set_sicr,
368 .set_imr = mpc52xx_psc_set_imr,
369 .get_mr1 = mpc52xx_psc_get_mr1,
370};
371
372static const struct psc_ops mpc5200b_psc_ops = {
373 .fifo_init = mpc52xx_psc_fifo_init,
374 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
375 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
376 .rx_rdy = mpc52xx_psc_rx_rdy,
377 .tx_rdy = mpc52xx_psc_tx_rdy,
378 .tx_empty = mpc52xx_psc_tx_empty,
379 .stop_rx = mpc52xx_psc_stop_rx,
380 .start_tx = mpc52xx_psc_start_tx,
381 .stop_tx = mpc52xx_psc_stop_tx,
382 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
383 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
384 .write_char = mpc52xx_psc_write_char,
385 .read_char = mpc52xx_psc_read_char,
386 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
387 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
388 .set_baudrate = mpc5200b_psc_set_baudrate,
389 .get_irq = mpc52xx_psc_get_irq,
390 .handle_irq = mpc52xx_psc_handle_irq,
391 .get_status = mpc52xx_psc_get_status,
392 .get_ipcr = mpc52xx_psc_get_ipcr,
393 .command = mpc52xx_psc_command,
394 .set_mode = mpc52xx_psc_set_mode,
395 .set_rts = mpc52xx_psc_set_rts,
396 .enable_ms = mpc52xx_psc_enable_ms,
397 .set_sicr = mpc52xx_psc_set_sicr,
398 .set_imr = mpc52xx_psc_set_imr,
399 .get_mr1 = mpc52xx_psc_get_mr1,
400};
401
402#endif /* CONFIG_PPC_MPC52xx */
403
404#ifdef CONFIG_PPC_MPC512x
405#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
406
407/* PSC FIFO Controller for mpc512x */
408struct psc_fifoc {
409 u32 fifoc_cmd;
410 u32 fifoc_int;
411 u32 fifoc_dma;
412 u32 fifoc_axe;
413 u32 fifoc_debug;
414};
415
416static struct psc_fifoc __iomem *psc_fifoc;
417static unsigned int psc_fifoc_irq;
418static struct clk *psc_fifoc_clk;
419
420static void mpc512x_psc_fifo_init(struct uart_port *port)
421{
422 /* /32 prescaler */
423 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
424
425 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
426 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
427 out_be32(&FIFO_512x(port)->txalarm, 1);
428 out_be32(&FIFO_512x(port)->tximr, 0);
429
430 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
431 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
432 out_be32(&FIFO_512x(port)->rxalarm, 1);
433 out_be32(&FIFO_512x(port)->rximr, 0);
434
435 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
436 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
437}
438
439static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
440{
441 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
442}
443
444static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
445{
446 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
447}
448
449static int mpc512x_psc_rx_rdy(struct uart_port *port)
450{
451 return in_be32(&FIFO_512x(port)->rxsr)
452 & in_be32(&FIFO_512x(port)->rximr)
453 & MPC512x_PSC_FIFO_ALARM;
454}
455
456static int mpc512x_psc_tx_rdy(struct uart_port *port)
457{
458 return in_be32(&FIFO_512x(port)->txsr)
459 & in_be32(&FIFO_512x(port)->tximr)
460 & MPC512x_PSC_FIFO_ALARM;
461}
462
463static int mpc512x_psc_tx_empty(struct uart_port *port)
464{
465 return in_be32(&FIFO_512x(port)->txsr)
466 & MPC512x_PSC_FIFO_EMPTY;
467}
468
469static void mpc512x_psc_stop_rx(struct uart_port *port)
470{
471 unsigned long rx_fifo_imr;
472
473 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
474 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
475 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
476}
477
478static void mpc512x_psc_start_tx(struct uart_port *port)
479{
480 unsigned long tx_fifo_imr;
481
482 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
483 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
484 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
485}
486
487static void mpc512x_psc_stop_tx(struct uart_port *port)
488{
489 unsigned long tx_fifo_imr;
490
491 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
492 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
493 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
494}
495
496static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
497{
498 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
499}
500
501static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
502{
503 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
504}
505
506static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
507{
508 out_8(&FIFO_512x(port)->txdata_8, c);
509}
510
511static unsigned char mpc512x_psc_read_char(struct uart_port *port)
512{
513 return in_8(&FIFO_512x(port)->rxdata_8);
514}
515
516static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
517{
518 port->read_status_mask =
519 in_be32(&FIFO_512x(port)->tximr) << 16 |
520 in_be32(&FIFO_512x(port)->rximr);
521 out_be32(&FIFO_512x(port)->tximr, 0);
522 out_be32(&FIFO_512x(port)->rximr, 0);
523}
524
525static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
526{
527 out_be32(&FIFO_512x(port)->tximr,
528 (port->read_status_mask >> 16) & 0x7f);
529 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
530}
531
532static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
533 struct ktermios *new,
534 struct ktermios *old)
535{
536 unsigned int baud;
537 unsigned int divisor;
538
539 /*
540 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
541 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
542 * Furthermore, it states that "After reset, the prescaler by 10
543 * for the UART mode is selected", but the reset register value is
544 * 0x0000 which means a /32 prescaler. This is wrong.
545 *
546 * In reality using /32 prescaler doesn't work, as it is not supported!
547 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
548 * Chapter 4.1 PSC in UART Mode.
549 * Calculate with a /16 prescaler here.
550 */
551
552 /* uartclk contains the ips freq */
553 baud = uart_get_baud_rate(port, new, old,
554 port->uartclk / (16 * 0xffff) + 1,
555 port->uartclk / 16);
556 divisor = (port->uartclk + 8 * baud) / (16 * baud);
557
558 /* enable the /16 prescaler and set the divisor */
559 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
560 return baud;
561}
562
563/* Init PSC FIFO Controller */
564static int __init mpc512x_psc_fifoc_init(void)
565{
566 int err;
567 struct device_node *np;
568 struct clk *clk;
569
570 /* default error code, potentially overwritten by clock calls */
571 err = -ENODEV;
572
573 np = of_find_compatible_node(NULL, NULL,
574 "fsl,mpc5121-psc-fifo");
575 if (!np) {
576 pr_err("%s: Can't find FIFOC node\n", __func__);
577 goto out_err;
578 }
579
580 clk = of_clk_get(np, 0);
581 if (IS_ERR(clk)) {
582 /* backwards compat with device trees that lack clock specs */
583 clk = clk_get_sys(np->name, "ipg");
584 }
585 if (IS_ERR(clk)) {
586 pr_err("%s: Can't lookup FIFO clock\n", __func__);
587 err = PTR_ERR(clk);
588 goto out_ofnode_put;
589 }
590 if (clk_prepare_enable(clk)) {
591 pr_err("%s: Can't enable FIFO clock\n", __func__);
592 clk_put(clk);
593 goto out_ofnode_put;
594 }
595 psc_fifoc_clk = clk;
596
597 psc_fifoc = of_iomap(np, 0);
598 if (!psc_fifoc) {
599 pr_err("%s: Can't map FIFOC\n", __func__);
600 goto out_clk_disable;
601 }
602
603 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
604 if (psc_fifoc_irq == 0) {
605 pr_err("%s: Can't get FIFOC irq\n", __func__);
606 goto out_unmap;
607 }
608
609 of_node_put(np);
610 return 0;
611
612out_unmap:
613 iounmap(psc_fifoc);
614out_clk_disable:
615 clk_disable_unprepare(psc_fifoc_clk);
616 clk_put(psc_fifoc_clk);
617out_ofnode_put:
618 of_node_put(np);
619out_err:
620 return err;
621}
622
623static void __exit mpc512x_psc_fifoc_uninit(void)
624{
625 iounmap(psc_fifoc);
626
627 /* disable the clock, errors are not fatal */
628 if (psc_fifoc_clk) {
629 clk_disable_unprepare(psc_fifoc_clk);
630 clk_put(psc_fifoc_clk);
631 psc_fifoc_clk = NULL;
632 }
633}
634
635/* 512x specific interrupt handler. The caller holds the port lock */
636static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
637{
638 unsigned long fifoc_int;
639 int psc_num;
640
641 /* Read pending PSC FIFOC interrupts */
642 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
643
644 /* Check if it is an interrupt for this port */
645 psc_num = (port->mapbase & 0xf00) >> 8;
646 if (test_bit(psc_num, &fifoc_int) ||
647 test_bit(psc_num + 16, &fifoc_int))
648 return mpc5xxx_uart_process_int(port);
649
650 return IRQ_NONE;
651}
652
653static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
654static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
655
656/* called from within the .request_port() callback (allocation) */
657static int mpc512x_psc_alloc_clock(struct uart_port *port)
658{
659 int psc_num;
660 struct clk *clk;
661 int err;
662
663 psc_num = (port->mapbase & 0xf00) >> 8;
664
665 clk = devm_clk_get(port->dev, "mclk");
666 if (IS_ERR(clk)) {
667 dev_err(port->dev, "Failed to get MCLK!\n");
668 err = PTR_ERR(clk);
669 goto out_err;
670 }
671 err = clk_prepare_enable(clk);
672 if (err) {
673 dev_err(port->dev, "Failed to enable MCLK!\n");
674 goto out_err;
675 }
676 psc_mclk_clk[psc_num] = clk;
677
678 clk = devm_clk_get(port->dev, "ipg");
679 if (IS_ERR(clk)) {
680 dev_err(port->dev, "Failed to get IPG clock!\n");
681 err = PTR_ERR(clk);
682 goto out_err;
683 }
684 err = clk_prepare_enable(clk);
685 if (err) {
686 dev_err(port->dev, "Failed to enable IPG clock!\n");
687 goto out_err;
688 }
689 psc_ipg_clk[psc_num] = clk;
690
691 return 0;
692
693out_err:
694 if (psc_mclk_clk[psc_num]) {
695 clk_disable_unprepare(psc_mclk_clk[psc_num]);
696 psc_mclk_clk[psc_num] = NULL;
697 }
698 if (psc_ipg_clk[psc_num]) {
699 clk_disable_unprepare(psc_ipg_clk[psc_num]);
700 psc_ipg_clk[psc_num] = NULL;
701 }
702 return err;
703}
704
705/* called from within the .release_port() callback (release) */
706static void mpc512x_psc_relse_clock(struct uart_port *port)
707{
708 int psc_num;
709 struct clk *clk;
710
711 psc_num = (port->mapbase & 0xf00) >> 8;
712 clk = psc_mclk_clk[psc_num];
713 if (clk) {
714 clk_disable_unprepare(clk);
715 psc_mclk_clk[psc_num] = NULL;
716 }
717 if (psc_ipg_clk[psc_num]) {
718 clk_disable_unprepare(psc_ipg_clk[psc_num]);
719 psc_ipg_clk[psc_num] = NULL;
720 }
721}
722
723/* implementation of the .clock() callback (enable/disable) */
724static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
725{
726 int psc_num;
727 struct clk *psc_clk;
728 int ret;
729
730 if (uart_console(port))
731 return 0;
732
733 psc_num = (port->mapbase & 0xf00) >> 8;
734 psc_clk = psc_mclk_clk[psc_num];
735 if (!psc_clk) {
736 dev_err(port->dev, "Failed to get PSC clock entry!\n");
737 return -ENODEV;
738 }
739
740 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
741 if (enable) {
742 ret = clk_enable(psc_clk);
743 if (ret)
744 dev_err(port->dev, "Failed to enable MCLK!\n");
745 return ret;
746 } else {
747 clk_disable(psc_clk);
748 return 0;
749 }
750}
751
752static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
753{
754 port->irqflags = IRQF_SHARED;
755 port->irq = psc_fifoc_irq;
756}
757#endif
758
759#ifdef CONFIG_PPC_MPC512x
760
761#define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
762#define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
763
764static void mpc5125_psc_fifo_init(struct uart_port *port)
765{
766 /* /32 prescaler */
767 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
768
769 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
770 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
771 out_be32(&FIFO_5125(port)->txalarm, 1);
772 out_be32(&FIFO_5125(port)->tximr, 0);
773
774 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
775 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
776 out_be32(&FIFO_5125(port)->rxalarm, 1);
777 out_be32(&FIFO_5125(port)->rximr, 0);
778
779 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
780 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
781}
782
783static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
784{
785 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
786}
787
788static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
789{
790 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
791}
792
793static int mpc5125_psc_rx_rdy(struct uart_port *port)
794{
795 return in_be32(&FIFO_5125(port)->rxsr) &
796 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
797}
798
799static int mpc5125_psc_tx_rdy(struct uart_port *port)
800{
801 return in_be32(&FIFO_5125(port)->txsr) &
802 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
803}
804
805static int mpc5125_psc_tx_empty(struct uart_port *port)
806{
807 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
808}
809
810static void mpc5125_psc_stop_rx(struct uart_port *port)
811{
812 unsigned long rx_fifo_imr;
813
814 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
815 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
816 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
817}
818
819static void mpc5125_psc_start_tx(struct uart_port *port)
820{
821 unsigned long tx_fifo_imr;
822
823 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
824 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
825 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
826}
827
828static void mpc5125_psc_stop_tx(struct uart_port *port)
829{
830 unsigned long tx_fifo_imr;
831
832 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
833 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
834 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
835}
836
837static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
838{
839 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
840}
841
842static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
843{
844 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
845}
846
847static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
848{
849 out_8(&FIFO_5125(port)->txdata_8, c);
850}
851
852static unsigned char mpc5125_psc_read_char(struct uart_port *port)
853{
854 return in_8(&FIFO_5125(port)->rxdata_8);
855}
856
857static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
858{
859 port->read_status_mask =
860 in_be32(&FIFO_5125(port)->tximr) << 16 |
861 in_be32(&FIFO_5125(port)->rximr);
862 out_be32(&FIFO_5125(port)->tximr, 0);
863 out_be32(&FIFO_5125(port)->rximr, 0);
864}
865
866static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
867{
868 out_be32(&FIFO_5125(port)->tximr,
869 (port->read_status_mask >> 16) & 0x7f);
870 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
871}
872
873static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
874 u8 prescaler, unsigned int divisor)
875{
876 /* select prescaler */
877 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
878 out_8(&psc->ctur, divisor >> 8);
879 out_8(&psc->ctlr, divisor & 0xff);
880}
881
882static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
883 struct ktermios *new,
884 struct ktermios *old)
885{
886 unsigned int baud;
887 unsigned int divisor;
888
889 /*
890 * Calculate with a /16 prescaler here.
891 */
892
893 /* uartclk contains the ips freq */
894 baud = uart_get_baud_rate(port, new, old,
895 port->uartclk / (16 * 0xffff) + 1,
896 port->uartclk / 16);
897 divisor = (port->uartclk + 8 * baud) / (16 * baud);
898
899 /* enable the /16 prescaler and set the divisor */
900 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
901 return baud;
902}
903
904/*
905 * MPC5125 have compatible PSC FIFO Controller.
906 * Special init not needed.
907 */
908static u16 mpc5125_psc_get_status(struct uart_port *port)
909{
910 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
911}
912
913static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
914{
915 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
916}
917
918static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
919{
920 out_8(&PSC_5125(port)->command, cmd);
921}
922
923static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
924{
925 out_8(&PSC_5125(port)->mr1, mr1);
926 out_8(&PSC_5125(port)->mr2, mr2);
927}
928
929static void mpc5125_psc_set_rts(struct uart_port *port, int state)
930{
931 if (state & TIOCM_RTS)
932 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
933 else
934 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
935}
936
937static void mpc5125_psc_enable_ms(struct uart_port *port)
938{
939 struct mpc5125_psc __iomem *psc = PSC_5125(port);
940
941 /* clear D_*-bits by reading them */
942 in_8(&psc->mpc52xx_psc_ipcr);
943 /* enable CTS and DCD as IPC interrupts */
944 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
945
946 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
947 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
948}
949
950static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
951{
952 out_be32(&PSC_5125(port)->sicr, val);
953}
954
955static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
956{
957 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
958}
959
960static u8 mpc5125_psc_get_mr1(struct uart_port *port)
961{
962 return in_8(&PSC_5125(port)->mr1);
963}
964
965static const struct psc_ops mpc5125_psc_ops = {
966 .fifo_init = mpc5125_psc_fifo_init,
967 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
968 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
969 .rx_rdy = mpc5125_psc_rx_rdy,
970 .tx_rdy = mpc5125_psc_tx_rdy,
971 .tx_empty = mpc5125_psc_tx_empty,
972 .stop_rx = mpc5125_psc_stop_rx,
973 .start_tx = mpc5125_psc_start_tx,
974 .stop_tx = mpc5125_psc_stop_tx,
975 .rx_clr_irq = mpc5125_psc_rx_clr_irq,
976 .tx_clr_irq = mpc5125_psc_tx_clr_irq,
977 .write_char = mpc5125_psc_write_char,
978 .read_char = mpc5125_psc_read_char,
979 .cw_disable_ints = mpc5125_psc_cw_disable_ints,
980 .cw_restore_ints = mpc5125_psc_cw_restore_ints,
981 .set_baudrate = mpc5125_psc_set_baudrate,
982 .clock_alloc = mpc512x_psc_alloc_clock,
983 .clock_relse = mpc512x_psc_relse_clock,
984 .clock = mpc512x_psc_endis_clock,
985 .fifoc_init = mpc512x_psc_fifoc_init,
986 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
987 .get_irq = mpc512x_psc_get_irq,
988 .handle_irq = mpc512x_psc_handle_irq,
989 .get_status = mpc5125_psc_get_status,
990 .get_ipcr = mpc5125_psc_get_ipcr,
991 .command = mpc5125_psc_command,
992 .set_mode = mpc5125_psc_set_mode,
993 .set_rts = mpc5125_psc_set_rts,
994 .enable_ms = mpc5125_psc_enable_ms,
995 .set_sicr = mpc5125_psc_set_sicr,
996 .set_imr = mpc5125_psc_set_imr,
997 .get_mr1 = mpc5125_psc_get_mr1,
998};
999
1000static const struct psc_ops mpc512x_psc_ops = {
1001 .fifo_init = mpc512x_psc_fifo_init,
1002 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1003 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1004 .rx_rdy = mpc512x_psc_rx_rdy,
1005 .tx_rdy = mpc512x_psc_tx_rdy,
1006 .tx_empty = mpc512x_psc_tx_empty,
1007 .stop_rx = mpc512x_psc_stop_rx,
1008 .start_tx = mpc512x_psc_start_tx,
1009 .stop_tx = mpc512x_psc_stop_tx,
1010 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
1011 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
1012 .write_char = mpc512x_psc_write_char,
1013 .read_char = mpc512x_psc_read_char,
1014 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
1015 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
1016 .set_baudrate = mpc512x_psc_set_baudrate,
1017 .clock_alloc = mpc512x_psc_alloc_clock,
1018 .clock_relse = mpc512x_psc_relse_clock,
1019 .clock = mpc512x_psc_endis_clock,
1020 .fifoc_init = mpc512x_psc_fifoc_init,
1021 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
1022 .get_irq = mpc512x_psc_get_irq,
1023 .handle_irq = mpc512x_psc_handle_irq,
1024 .get_status = mpc52xx_psc_get_status,
1025 .get_ipcr = mpc52xx_psc_get_ipcr,
1026 .command = mpc52xx_psc_command,
1027 .set_mode = mpc52xx_psc_set_mode,
1028 .set_rts = mpc52xx_psc_set_rts,
1029 .enable_ms = mpc52xx_psc_enable_ms,
1030 .set_sicr = mpc52xx_psc_set_sicr,
1031 .set_imr = mpc52xx_psc_set_imr,
1032 .get_mr1 = mpc52xx_psc_get_mr1,
1033};
1034#endif /* CONFIG_PPC_MPC512x */
1035
1036
1037static const struct psc_ops *psc_ops;
1038
1039/* ======================================================================== */
1040/* UART operations */
1041/* ======================================================================== */
1042
1043static unsigned int
1044mpc52xx_uart_tx_empty(struct uart_port *port)
1045{
1046 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1047}
1048
1049static void
1050mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1051{
1052 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1053}
1054
1055static unsigned int
1056mpc52xx_uart_get_mctrl(struct uart_port *port)
1057{
1058 unsigned int ret = TIOCM_DSR;
1059 u8 status = psc_ops->get_ipcr(port);
1060
1061 if (!(status & MPC52xx_PSC_CTS))
1062 ret |= TIOCM_CTS;
1063 if (!(status & MPC52xx_PSC_DCD))
1064 ret |= TIOCM_CAR;
1065
1066 return ret;
1067}
1068
1069static void
1070mpc52xx_uart_stop_tx(struct uart_port *port)
1071{
1072 /* port->lock taken by caller */
1073 psc_ops->stop_tx(port);
1074}
1075
1076static void
1077mpc52xx_uart_start_tx(struct uart_port *port)
1078{
1079 /* port->lock taken by caller */
1080 psc_ops->start_tx(port);
1081}
1082
1083static void
1084mpc52xx_uart_stop_rx(struct uart_port *port)
1085{
1086 /* port->lock taken by caller */
1087 psc_ops->stop_rx(port);
1088}
1089
1090static void
1091mpc52xx_uart_enable_ms(struct uart_port *port)
1092{
1093 psc_ops->enable_ms(port);
1094}
1095
1096static void
1097mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1098{
1099 unsigned long flags;
1100 spin_lock_irqsave(&port->lock, flags);
1101
1102 if (ctl == -1)
1103 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1104 else
1105 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1106
1107 spin_unlock_irqrestore(&port->lock, flags);
1108}
1109
1110static int
1111mpc52xx_uart_startup(struct uart_port *port)
1112{
1113 int ret;
1114
1115 if (psc_ops->clock) {
1116 ret = psc_ops->clock(port, 1);
1117 if (ret)
1118 return ret;
1119 }
1120
1121 /* Request IRQ */
1122 ret = request_irq(port->irq, mpc52xx_uart_int,
1123 port->irqflags, "mpc52xx_psc_uart", port);
1124 if (ret)
1125 return ret;
1126
1127 /* Reset/activate the port, clear and enable interrupts */
1128 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1129 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1130
1131 /*
1132 * According to Freescale's support the RST_TX command can produce a
1133 * spike on the TX pin. So they recommend to delay "for one character".
1134 * One millisecond should be enough for everyone.
1135 */
1136 msleep(1);
1137
1138 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1139
1140 psc_ops->fifo_init(port);
1141
1142 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1143 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1144
1145 return 0;
1146}
1147
1148static void
1149mpc52xx_uart_shutdown(struct uart_port *port)
1150{
1151 /* Shut down the port. Leave TX active if on a console port */
1152 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1153 if (!uart_console(port))
1154 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1155
1156 port->read_status_mask = 0;
1157 psc_ops->set_imr(port, port->read_status_mask);
1158
1159 if (psc_ops->clock)
1160 psc_ops->clock(port, 0);
1161
1162 /* Disable interrupt */
1163 psc_ops->cw_disable_ints(port);
1164
1165 /* Release interrupt */
1166 free_irq(port->irq, port);
1167}
1168
1169static void
1170mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1171 struct ktermios *old)
1172{
1173 unsigned long flags;
1174 unsigned char mr1, mr2;
1175 unsigned int j;
1176 unsigned int baud;
1177
1178 /* Prepare what we're gonna write */
1179 mr1 = 0;
1180
1181 switch (new->c_cflag & CSIZE) {
1182 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
1183 break;
1184 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
1185 break;
1186 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
1187 break;
1188 case CS8:
1189 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
1190 }
1191
1192 if (new->c_cflag & PARENB) {
1193 if (new->c_cflag & CMSPAR)
1194 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1195
1196 /* With CMSPAR, PARODD also means high parity (same as termios) */
1197 mr1 |= (new->c_cflag & PARODD) ?
1198 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1199 } else {
1200 mr1 |= MPC52xx_PSC_MODE_PARNONE;
1201 }
1202
1203 mr2 = 0;
1204
1205 if (new->c_cflag & CSTOPB)
1206 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1207 else
1208 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1209 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1210 MPC52xx_PSC_MODE_ONE_STOP;
1211
1212 if (new->c_cflag & CRTSCTS) {
1213 mr1 |= MPC52xx_PSC_MODE_RXRTS;
1214 mr2 |= MPC52xx_PSC_MODE_TXCTS;
1215 }
1216
1217 /* Get the lock */
1218 spin_lock_irqsave(&port->lock, flags);
1219
1220 /* Do our best to flush TX & RX, so we don't lose anything */
1221 /* But we don't wait indefinitely ! */
1222 j = 5000000; /* Maximum wait */
1223 /* FIXME Can't receive chars since set_termios might be called at early
1224 * boot for the console, all stuff is not yet ready to receive at that
1225 * time and that just makes the kernel oops */
1226 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1227 while (!mpc52xx_uart_tx_empty(port) && --j)
1228 udelay(1);
1229
1230 if (!j)
1231 printk(KERN_ERR "mpc52xx_uart.c: "
1232 "Unable to flush RX & TX fifos in-time in set_termios."
1233 "Some chars may have been lost.\n");
1234
1235 /* Reset the TX & RX */
1236 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1237 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1238
1239 /* Send new mode settings */
1240 psc_ops->set_mode(port, mr1, mr2);
1241 baud = psc_ops->set_baudrate(port, new, old);
1242
1243 /* Update the per-port timeout */
1244 uart_update_timeout(port, new->c_cflag, baud);
1245
1246 if (UART_ENABLE_MS(port, new->c_cflag))
1247 mpc52xx_uart_enable_ms(port);
1248
1249 /* Reenable TX & RX */
1250 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1251 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1252
1253 /* We're all set, release the lock */
1254 spin_unlock_irqrestore(&port->lock, flags);
1255}
1256
1257static const char *
1258mpc52xx_uart_type(struct uart_port *port)
1259{
1260 /*
1261 * We keep using PORT_MPC52xx for historic reasons although it applies
1262 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1263 */
1264 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1265}
1266
1267static void
1268mpc52xx_uart_release_port(struct uart_port *port)
1269{
1270 if (psc_ops->clock_relse)
1271 psc_ops->clock_relse(port);
1272
1273 /* remapped by us ? */
1274 if (port->flags & UPF_IOREMAP) {
1275 iounmap(port->membase);
1276 port->membase = NULL;
1277 }
1278
1279 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1280}
1281
1282static int
1283mpc52xx_uart_request_port(struct uart_port *port)
1284{
1285 int err;
1286
1287 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1288 port->membase = ioremap(port->mapbase,
1289 sizeof(struct mpc52xx_psc));
1290
1291 if (!port->membase)
1292 return -EINVAL;
1293
1294 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1295 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1296
1297 if (err)
1298 goto out_membase;
1299
1300 if (psc_ops->clock_alloc) {
1301 err = psc_ops->clock_alloc(port);
1302 if (err)
1303 goto out_mapregion;
1304 }
1305
1306 return 0;
1307
1308out_mapregion:
1309 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1310out_membase:
1311 if (port->flags & UPF_IOREMAP) {
1312 iounmap(port->membase);
1313 port->membase = NULL;
1314 }
1315 return err;
1316}
1317
1318static void
1319mpc52xx_uart_config_port(struct uart_port *port, int flags)
1320{
1321 if ((flags & UART_CONFIG_TYPE)
1322 && (mpc52xx_uart_request_port(port) == 0))
1323 port->type = PORT_MPC52xx;
1324}
1325
1326static int
1327mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1328{
1329 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1330 return -EINVAL;
1331
1332 if ((ser->irq != port->irq) ||
1333 (ser->io_type != UPIO_MEM) ||
1334 (ser->baud_base != port->uartclk) ||
1335 (ser->iomem_base != (void *)port->mapbase) ||
1336 (ser->hub6 != 0))
1337 return -EINVAL;
1338
1339 return 0;
1340}
1341
1342
1343static const struct uart_ops mpc52xx_uart_ops = {
1344 .tx_empty = mpc52xx_uart_tx_empty,
1345 .set_mctrl = mpc52xx_uart_set_mctrl,
1346 .get_mctrl = mpc52xx_uart_get_mctrl,
1347 .stop_tx = mpc52xx_uart_stop_tx,
1348 .start_tx = mpc52xx_uart_start_tx,
1349 .stop_rx = mpc52xx_uart_stop_rx,
1350 .enable_ms = mpc52xx_uart_enable_ms,
1351 .break_ctl = mpc52xx_uart_break_ctl,
1352 .startup = mpc52xx_uart_startup,
1353 .shutdown = mpc52xx_uart_shutdown,
1354 .set_termios = mpc52xx_uart_set_termios,
1355/* .pm = mpc52xx_uart_pm, Not supported yet */
1356 .type = mpc52xx_uart_type,
1357 .release_port = mpc52xx_uart_release_port,
1358 .request_port = mpc52xx_uart_request_port,
1359 .config_port = mpc52xx_uart_config_port,
1360 .verify_port = mpc52xx_uart_verify_port
1361};
1362
1363
1364/* ======================================================================== */
1365/* Interrupt handling */
1366/* ======================================================================== */
1367
1368static inline int
1369mpc52xx_uart_int_rx_chars(struct uart_port *port)
1370{
1371 struct tty_port *tport = &port->state->port;
1372 unsigned char ch, flag;
1373 unsigned short status;
1374
1375 /* While we can read, do so ! */
1376 while (psc_ops->raw_rx_rdy(port)) {
1377 /* Get the char */
1378 ch = psc_ops->read_char(port);
1379
1380 /* Handle sysreq char */
1381 if (uart_handle_sysrq_char(port, ch))
1382 continue;
1383
1384 /* Store it */
1385
1386 flag = TTY_NORMAL;
1387 port->icount.rx++;
1388
1389 status = psc_ops->get_status(port);
1390
1391 if (status & (MPC52xx_PSC_SR_PE |
1392 MPC52xx_PSC_SR_FE |
1393 MPC52xx_PSC_SR_RB)) {
1394
1395 if (status & MPC52xx_PSC_SR_RB) {
1396 flag = TTY_BREAK;
1397 uart_handle_break(port);
1398 port->icount.brk++;
1399 } else if (status & MPC52xx_PSC_SR_PE) {
1400 flag = TTY_PARITY;
1401 port->icount.parity++;
1402 }
1403 else if (status & MPC52xx_PSC_SR_FE) {
1404 flag = TTY_FRAME;
1405 port->icount.frame++;
1406 }
1407
1408 /* Clear error condition */
1409 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1410
1411 }
1412 tty_insert_flip_char(tport, ch, flag);
1413 if (status & MPC52xx_PSC_SR_OE) {
1414 /*
1415 * Overrun is special, since it's
1416 * reported immediately, and doesn't
1417 * affect the current character
1418 */
1419 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1420 port->icount.overrun++;
1421 }
1422 }
1423
1424 tty_flip_buffer_push(tport);
1425
1426 return psc_ops->raw_rx_rdy(port);
1427}
1428
1429static inline int
1430mpc52xx_uart_int_tx_chars(struct uart_port *port)
1431{
1432 struct circ_buf *xmit = &port->state->xmit;
1433
1434 /* Process out of band chars */
1435 if (port->x_char) {
1436 psc_ops->write_char(port, port->x_char);
1437 port->icount.tx++;
1438 port->x_char = 0;
1439 return 1;
1440 }
1441
1442 /* Nothing to do ? */
1443 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1444 mpc52xx_uart_stop_tx(port);
1445 return 0;
1446 }
1447
1448 /* Send chars */
1449 while (psc_ops->raw_tx_rdy(port)) {
1450 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1451 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1452 port->icount.tx++;
1453 if (uart_circ_empty(xmit))
1454 break;
1455 }
1456
1457 /* Wake up */
1458 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1459 uart_write_wakeup(port);
1460
1461 /* Maybe we're done after all */
1462 if (uart_circ_empty(xmit)) {
1463 mpc52xx_uart_stop_tx(port);
1464 return 0;
1465 }
1466
1467 return 1;
1468}
1469
1470static irqreturn_t
1471mpc5xxx_uart_process_int(struct uart_port *port)
1472{
1473 unsigned long pass = ISR_PASS_LIMIT;
1474 unsigned int keepgoing;
1475 u8 status;
1476
1477 /* While we have stuff to do, we continue */
1478 do {
1479 /* If we don't find anything to do, we stop */
1480 keepgoing = 0;
1481
1482 psc_ops->rx_clr_irq(port);
1483 if (psc_ops->rx_rdy(port))
1484 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1485
1486 psc_ops->tx_clr_irq(port);
1487 if (psc_ops->tx_rdy(port))
1488 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1489
1490 status = psc_ops->get_ipcr(port);
1491 if (status & MPC52xx_PSC_D_DCD)
1492 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1493
1494 if (status & MPC52xx_PSC_D_CTS)
1495 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1496
1497 /* Limit number of iteration */
1498 if (!(--pass))
1499 keepgoing = 0;
1500
1501 } while (keepgoing);
1502
1503 return IRQ_HANDLED;
1504}
1505
1506static irqreturn_t
1507mpc52xx_uart_int(int irq, void *dev_id)
1508{
1509 struct uart_port *port = dev_id;
1510 irqreturn_t ret;
1511
1512 spin_lock(&port->lock);
1513
1514 ret = psc_ops->handle_irq(port);
1515
1516 spin_unlock(&port->lock);
1517
1518 return ret;
1519}
1520
1521/* ======================================================================== */
1522/* Console ( if applicable ) */
1523/* ======================================================================== */
1524
1525#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1526
1527static void __init
1528mpc52xx_console_get_options(struct uart_port *port,
1529 int *baud, int *parity, int *bits, int *flow)
1530{
1531 unsigned char mr1;
1532
1533 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1534
1535 /* Read the mode registers */
1536 mr1 = psc_ops->get_mr1(port);
1537
1538 /* CT{U,L}R are write-only ! */
1539 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1540
1541 /* Parse them */
1542 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1543 case MPC52xx_PSC_MODE_5_BITS:
1544 *bits = 5;
1545 break;
1546 case MPC52xx_PSC_MODE_6_BITS:
1547 *bits = 6;
1548 break;
1549 case MPC52xx_PSC_MODE_7_BITS:
1550 *bits = 7;
1551 break;
1552 case MPC52xx_PSC_MODE_8_BITS:
1553 default:
1554 *bits = 8;
1555 }
1556
1557 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1558 *parity = 'n';
1559 else
1560 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1561}
1562
1563static void
1564mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1565{
1566 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1567 unsigned int i, j;
1568
1569 /* Disable interrupts */
1570 psc_ops->cw_disable_ints(port);
1571
1572 /* Wait the TX buffer to be empty */
1573 j = 5000000; /* Maximum wait */
1574 while (!mpc52xx_uart_tx_empty(port) && --j)
1575 udelay(1);
1576
1577 /* Write all the chars */
1578 for (i = 0; i < count; i++, s++) {
1579 /* Line return handling */
1580 if (*s == '\n')
1581 psc_ops->write_char(port, '\r');
1582
1583 /* Send the char */
1584 psc_ops->write_char(port, *s);
1585
1586 /* Wait the TX buffer to be empty */
1587 j = 20000; /* Maximum wait */
1588 while (!mpc52xx_uart_tx_empty(port) && --j)
1589 udelay(1);
1590 }
1591
1592 /* Restore interrupt state */
1593 psc_ops->cw_restore_ints(port);
1594}
1595
1596
1597static int __init
1598mpc52xx_console_setup(struct console *co, char *options)
1599{
1600 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1601 struct device_node *np = mpc52xx_uart_nodes[co->index];
1602 unsigned int uartclk;
1603 struct resource res;
1604 int ret;
1605
1606 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1607 int bits = 8;
1608 int parity = 'n';
1609 int flow = 'n';
1610
1611 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1612 co, co->index, options);
1613
1614 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1615 pr_debug("PSC%x out of range\n", co->index);
1616 return -EINVAL;
1617 }
1618
1619 if (!np) {
1620 pr_debug("PSC%x not found in device tree\n", co->index);
1621 return -EINVAL;
1622 }
1623
1624 pr_debug("Console on ttyPSC%x is %pOF\n",
1625 co->index, mpc52xx_uart_nodes[co->index]);
1626
1627 /* Fetch register locations */
1628 ret = of_address_to_resource(np, 0, &res);
1629 if (ret) {
1630 pr_debug("Could not get resources for PSC%x\n", co->index);
1631 return ret;
1632 }
1633
1634 uartclk = mpc5xxx_get_bus_frequency(np);
1635 if (uartclk == 0) {
1636 pr_debug("Could not find uart clock frequency!\n");
1637 return -EINVAL;
1638 }
1639
1640 /* Basic port init. Needed since we use some uart_??? func before
1641 * real init for early access */
1642 spin_lock_init(&port->lock);
1643 port->uartclk = uartclk;
1644 port->ops = &mpc52xx_uart_ops;
1645 port->mapbase = res.start;
1646 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1647 port->irq = irq_of_parse_and_map(np, 0);
1648
1649 if (port->membase == NULL)
1650 return -EINVAL;
1651
1652 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1653 (void *)port->mapbase, port->membase,
1654 port->irq, port->uartclk);
1655
1656 /* Setup the port parameters accoding to options */
1657 if (options)
1658 uart_parse_options(options, &baud, &parity, &bits, &flow);
1659 else
1660 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1661
1662 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1663 baud, bits, parity, flow);
1664
1665 return uart_set_options(port, co, baud, parity, bits, flow);
1666}
1667
1668
1669static struct uart_driver mpc52xx_uart_driver;
1670
1671static struct console mpc52xx_console = {
1672 .name = "ttyPSC",
1673 .write = mpc52xx_console_write,
1674 .device = uart_console_device,
1675 .setup = mpc52xx_console_setup,
1676 .flags = CON_PRINTBUFFER,
1677 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1678 .data = &mpc52xx_uart_driver,
1679};
1680
1681
1682static int __init
1683mpc52xx_console_init(void)
1684{
1685 mpc52xx_uart_of_enumerate();
1686 register_console(&mpc52xx_console);
1687 return 0;
1688}
1689
1690console_initcall(mpc52xx_console_init);
1691
1692#define MPC52xx_PSC_CONSOLE &mpc52xx_console
1693#else
1694#define MPC52xx_PSC_CONSOLE NULL
1695#endif
1696
1697
1698/* ======================================================================== */
1699/* UART Driver */
1700/* ======================================================================== */
1701
1702static struct uart_driver mpc52xx_uart_driver = {
1703 .driver_name = "mpc52xx_psc_uart",
1704 .dev_name = "ttyPSC",
1705 .major = SERIAL_PSC_MAJOR,
1706 .minor = SERIAL_PSC_MINOR,
1707 .nr = MPC52xx_PSC_MAXNUM,
1708 .cons = MPC52xx_PSC_CONSOLE,
1709};
1710
1711/* ======================================================================== */
1712/* OF Platform Driver */
1713/* ======================================================================== */
1714
1715static const struct of_device_id mpc52xx_uart_of_match[] = {
1716#ifdef CONFIG_PPC_MPC52xx
1717 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1718 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1719 /* binding used by old lite5200 device trees: */
1720 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1721 /* binding used by efika: */
1722 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1723#endif
1724#ifdef CONFIG_PPC_MPC512x
1725 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1726 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1727#endif
1728 {},
1729};
1730
1731static int mpc52xx_uart_of_probe(struct platform_device *op)
1732{
1733 int idx = -1;
1734 unsigned int uartclk;
1735 struct uart_port *port = NULL;
1736 struct resource res;
1737 int ret;
1738
1739 /* Check validity & presence */
1740 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1741 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1742 break;
1743 if (idx >= MPC52xx_PSC_MAXNUM)
1744 return -EINVAL;
1745 pr_debug("Found %pOF assigned to ttyPSC%x\n",
1746 mpc52xx_uart_nodes[idx], idx);
1747
1748 /* set the uart clock to the input clock of the psc, the different
1749 * prescalers are taken into account in the set_baudrate() methods
1750 * of the respective chip */
1751 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1752 if (uartclk == 0) {
1753 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1754 return -EINVAL;
1755 }
1756
1757 /* Init the port structure */
1758 port = &mpc52xx_uart_ports[idx];
1759
1760 spin_lock_init(&port->lock);
1761 port->uartclk = uartclk;
1762 port->fifosize = 512;
1763 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE);
1764 port->iotype = UPIO_MEM;
1765 port->flags = UPF_BOOT_AUTOCONF |
1766 (uart_console(port) ? 0 : UPF_IOREMAP);
1767 port->line = idx;
1768 port->ops = &mpc52xx_uart_ops;
1769 port->dev = &op->dev;
1770
1771 /* Search for IRQ and mapbase */
1772 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1773 if (ret)
1774 return ret;
1775
1776 port->mapbase = res.start;
1777 if (!port->mapbase) {
1778 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1779 return -EINVAL;
1780 }
1781
1782 psc_ops->get_irq(port, op->dev.of_node);
1783 if (port->irq == 0) {
1784 dev_dbg(&op->dev, "Could not get irq\n");
1785 return -EINVAL;
1786 }
1787
1788 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1789 (void *)port->mapbase, port->irq, port->uartclk);
1790
1791 /* Add the port to the uart sub-system */
1792 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1793 if (ret)
1794 return ret;
1795
1796 platform_set_drvdata(op, (void *)port);
1797 return 0;
1798}
1799
1800static int
1801mpc52xx_uart_of_remove(struct platform_device *op)
1802{
1803 struct uart_port *port = platform_get_drvdata(op);
1804
1805 if (port)
1806 uart_remove_one_port(&mpc52xx_uart_driver, port);
1807
1808 return 0;
1809}
1810
1811#ifdef CONFIG_PM
1812static int
1813mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1814{
1815 struct uart_port *port = platform_get_drvdata(op);
1816
1817 if (port)
1818 uart_suspend_port(&mpc52xx_uart_driver, port);
1819
1820 return 0;
1821}
1822
1823static int
1824mpc52xx_uart_of_resume(struct platform_device *op)
1825{
1826 struct uart_port *port = platform_get_drvdata(op);
1827
1828 if (port)
1829 uart_resume_port(&mpc52xx_uart_driver, port);
1830
1831 return 0;
1832}
1833#endif
1834
1835static void
1836mpc52xx_uart_of_assign(struct device_node *np)
1837{
1838 int i;
1839
1840 /* Find the first free PSC number */
1841 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1842 if (mpc52xx_uart_nodes[i] == NULL) {
1843 of_node_get(np);
1844 mpc52xx_uart_nodes[i] = np;
1845 return;
1846 }
1847 }
1848}
1849
1850static void
1851mpc52xx_uart_of_enumerate(void)
1852{
1853 static int enum_done;
1854 struct device_node *np;
1855 const struct of_device_id *match;
1856 int i;
1857
1858 if (enum_done)
1859 return;
1860
1861 /* Assign index to each PSC in device tree */
1862 for_each_matching_node(np, mpc52xx_uart_of_match) {
1863 match = of_match_node(mpc52xx_uart_of_match, np);
1864 psc_ops = match->data;
1865 mpc52xx_uart_of_assign(np);
1866 }
1867
1868 enum_done = 1;
1869
1870 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1871 if (mpc52xx_uart_nodes[i])
1872 pr_debug("%pOF assigned to ttyPSC%x\n",
1873 mpc52xx_uart_nodes[i], i);
1874 }
1875}
1876
1877MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1878
1879static struct platform_driver mpc52xx_uart_of_driver = {
1880 .probe = mpc52xx_uart_of_probe,
1881 .remove = mpc52xx_uart_of_remove,
1882#ifdef CONFIG_PM
1883 .suspend = mpc52xx_uart_of_suspend,
1884 .resume = mpc52xx_uart_of_resume,
1885#endif
1886 .driver = {
1887 .name = "mpc52xx-psc-uart",
1888 .of_match_table = mpc52xx_uart_of_match,
1889 },
1890};
1891
1892
1893/* ======================================================================== */
1894/* Module */
1895/* ======================================================================== */
1896
1897static int __init
1898mpc52xx_uart_init(void)
1899{
1900 int ret;
1901
1902 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1903
1904 ret = uart_register_driver(&mpc52xx_uart_driver);
1905 if (ret) {
1906 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1907 __FILE__, ret);
1908 return ret;
1909 }
1910
1911 mpc52xx_uart_of_enumerate();
1912
1913 /*
1914 * Map the PSC FIFO Controller and init if on MPC512x.
1915 */
1916 if (psc_ops && psc_ops->fifoc_init) {
1917 ret = psc_ops->fifoc_init();
1918 if (ret)
1919 goto err_init;
1920 }
1921
1922 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1923 if (ret) {
1924 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1925 __FILE__, ret);
1926 goto err_reg;
1927 }
1928
1929 return 0;
1930err_reg:
1931 if (psc_ops && psc_ops->fifoc_uninit)
1932 psc_ops->fifoc_uninit();
1933err_init:
1934 uart_unregister_driver(&mpc52xx_uart_driver);
1935 return ret;
1936}
1937
1938static void __exit
1939mpc52xx_uart_exit(void)
1940{
1941 if (psc_ops->fifoc_uninit)
1942 psc_ops->fifoc_uninit();
1943
1944 platform_driver_unregister(&mpc52xx_uart_of_driver);
1945 uart_unregister_driver(&mpc52xx_uart_driver);
1946}
1947
1948
1949module_init(mpc52xx_uart_init);
1950module_exit(mpc52xx_uart_exit);
1951
1952MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1953MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1954MODULE_LICENSE("GPL");