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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2021 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10#ifndef MPI3MR_H_INCLUDED
11#define MPI3MR_H_INCLUDED
12
13#include <linux/blkdev.h>
14#include <linux/blk-mq.h>
15#include <linux/blk-mq-pci.h>
16#include <linux/delay.h>
17#include <linux/dmapool.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/miscdevice.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/poll.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/types.h>
30#include <linux/uaccess.h>
31#include <linux/utsname.h>
32#include <linux/version.h>
33#include <linux/workqueue.h>
34#include <asm/unaligned.h>
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37#include <scsi/scsi_dbg.h>
38#include <scsi/scsi_device.h>
39#include <scsi/scsi_host.h>
40#include <scsi/scsi_tcq.h>
41
42#include "mpi/mpi30_transport.h"
43#include "mpi/mpi30_cnfg.h"
44#include "mpi/mpi30_image.h"
45#include "mpi/mpi30_init.h"
46#include "mpi/mpi30_ioc.h"
47#include "mpi/mpi30_sas.h"
48#include "mpi3mr_debug.h"
49
50/* Global list and lock for storing multiple adapters managed by the driver */
51extern spinlock_t mrioc_list_lock;
52extern struct list_head mrioc_list;
53extern int prot_mask;
54
55#define MPI3MR_DRIVER_VERSION "00.255.45.01"
56#define MPI3MR_DRIVER_RELDATE "12-December-2020"
57
58#define MPI3MR_DRIVER_NAME "mpi3mr"
59#define MPI3MR_DRIVER_LICENSE "GPL"
60#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
61#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
62
63#define MPI3MR_NAME_LENGTH 32
64#define IOCNAME "%s: "
65
66/* Definitions for internal SGL and Chain SGL buffers */
67#define MPI3MR_PAGE_SIZE_4K 4096
68#define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
69
70/* Definitions for MAX values for shost */
71#define MPI3MR_MAX_CMDS_LUN 7
72#define MPI3MR_MAX_CDB_LENGTH 32
73
74/* Admin queue management definitions */
75#define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
76#define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K)
77#define MPI3MR_ADMIN_REQ_FRAME_SZ 128
78#define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
79
80/* Operational queue management definitions */
81#define MPI3MR_OP_REQ_Q_QD 512
82#define MPI3MR_OP_REP_Q_QD 4096
83#define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
84#define MPI3MR_OP_REP_Q_SEG_SIZE 4096
85#define MPI3MR_MAX_SEG_LIST_SIZE 4096
86
87/* Reserved Host Tag definitions */
88#define MPI3MR_HOSTTAG_INVALID 0xFFFF
89#define MPI3MR_HOSTTAG_INITCMDS 1
90#define MPI3MR_HOSTTAG_IOCTLCMDS 2
91#define MPI3MR_HOSTTAG_BLK_TMS 5
92
93#define MPI3MR_NUM_DEVRMCMD 1
94#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1)
95#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
96 MPI3MR_NUM_DEVRMCMD - 1)
97
98#define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
99
100/* Reduced resource count definition for crash kernel */
101#define MPI3MR_HOST_IOS_KDUMP 128
102
103/* command/controller interaction timeout definitions in seconds */
104#define MPI3MR_INTADMCMD_TIMEOUT 10
105#define MPI3MR_PORTENABLE_TIMEOUT 300
106#define MPI3MR_ABORTTM_TIMEOUT 30
107#define MPI3MR_RESETTM_TIMEOUT 30
108#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
109#define MPI3MR_TSUPDATE_INTERVAL 900
110#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
111#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
112
113#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
114
115/* Internal admin command state definitions*/
116#define MPI3MR_CMD_NOTUSED 0x8000
117#define MPI3MR_CMD_COMPLETE 0x0001
118#define MPI3MR_CMD_PENDING 0x0002
119#define MPI3MR_CMD_REPLY_VALID 0x0004
120#define MPI3MR_CMD_RESET 0x0008
121
122/* Definitions for Event replies and sense buffer allocated per controller */
123#define MPI3MR_NUM_EVT_REPLIES 64
124#define MPI3MR_SENSEBUF_SZ 256
125#define MPI3MR_SENSEBUF_FACTOR 3
126#define MPI3MR_CHAINBUF_FACTOR 3
127#define MPI3MR_CHAINBUFDIX_FACTOR 2
128
129/* Invalid target device handle */
130#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
131
132/* Controller Reset related definitions */
133#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
134#define MPI3MR_MAX_RESET_RETRY_COUNT 3
135
136/* ResponseCode definitions */
137#define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
138#define MPI3MR_RSP_TM_COMPLETE 0x00
139#define MPI3MR_RSP_INVALID_FRAME 0x02
140#define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04
141#define MPI3MR_RSP_TM_FAILED 0x05
142#define MPI3MR_RSP_TM_SUCCEEDED 0x08
143#define MPI3MR_RSP_TM_INVALID_LUN 0x09
144#define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A
145#define MPI3MR_RSP_IO_QUEUED_ON_IOC \
146 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
147
148#define MPI3MR_DEFAULT_MDTS (128 * 1024)
149/* Command retry count definitions */
150#define MPI3MR_DEV_RMHS_RETRY_COUNT 3
151
152/* Default target device queue depth */
153#define MPI3MR_DEFAULT_SDEV_QD 32
154
155/* Definitions for Threaded IRQ poll*/
156#define MPI3MR_IRQ_POLL_SLEEP 2
157#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
158
159/* Definitions for the controller security status*/
160#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
161#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
162
163#define MPI3MR_INVALID_DEVICE 0x00
164#define MPI3MR_CONFIG_SECURE_DEVICE 0x04
165#define MPI3MR_HARD_SECURE_DEVICE 0x08
166#define MPI3MR_TAMPERED_DEVICE 0x0C
167
168/* SGE Flag definition */
169#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
170 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
171 MPI3_SGE_FLAGS_END_OF_LIST)
172
173/* MSI Index from Reply Queue Index */
174#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
175
176/* IOC State definitions */
177enum mpi3mr_iocstate {
178 MRIOC_STATE_READY = 1,
179 MRIOC_STATE_RESET,
180 MRIOC_STATE_FAULT,
181 MRIOC_STATE_BECOMING_READY,
182 MRIOC_STATE_RESET_REQUESTED,
183 MRIOC_STATE_UNRECOVERABLE,
184};
185
186/* Reset reason code definitions*/
187enum mpi3mr_reset_reason {
188 MPI3MR_RESET_FROM_BRINGUP = 1,
189 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
190 MPI3MR_RESET_FROM_IOCTL = 3,
191 MPI3MR_RESET_FROM_EH_HOS = 4,
192 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
193 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6,
194 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
195 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
196 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
197 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
198 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
199 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
200 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
201 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
202 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
203 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
204 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
205 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
206 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
207 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
208 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
209 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
210 MPI3MR_RESET_FROM_SYSFS = 23,
211 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24
212};
213
214/**
215 * struct mpi3mr_compimg_ver - replica of component image
216 * version defined in mpi30_image.h in host endianness
217 *
218 */
219struct mpi3mr_compimg_ver {
220 u16 build_num;
221 u16 cust_id;
222 u8 ph_minor;
223 u8 ph_major;
224 u8 gen_minor;
225 u8 gen_major;
226};
227
228/**
229 * struct mpi3mr_ioc_facs - replica of component image version
230 * defined in mpi30_ioc.h in host endianness
231 *
232 */
233struct mpi3mr_ioc_facts {
234 u32 ioc_capabilities;
235 struct mpi3mr_compimg_ver fw_ver;
236 u32 mpi_version;
237 u16 max_reqs;
238 u16 product_id;
239 u16 op_req_sz;
240 u16 reply_sz;
241 u16 exceptions;
242 u16 max_perids;
243 u16 max_pds;
244 u16 max_sasexpanders;
245 u16 max_sasinitiators;
246 u16 max_enclosures;
247 u16 max_pcie_switches;
248 u16 max_nvme;
249 u16 max_vds;
250 u16 max_hpds;
251 u16 max_advhpds;
252 u16 max_raidpds;
253 u16 min_devhandle;
254 u16 max_devhandle;
255 u16 max_op_req_q;
256 u16 max_op_reply_q;
257 u16 shutdown_timeout;
258 u8 ioc_num;
259 u8 who_init;
260 u16 max_msix_vectors;
261 u8 personality;
262 u8 dma_mask;
263 u8 protocol_flags;
264 u8 sge_mod_mask;
265 u8 sge_mod_value;
266 u8 sge_mod_shift;
267};
268
269/**
270 * struct segments - memory descriptor structure to store
271 * virtual and dma addresses for operational queue segments.
272 *
273 * @segment: virtual address
274 * @segment_dma: dma address
275 */
276struct segments {
277 void *segment;
278 dma_addr_t segment_dma;
279};
280
281/**
282 * struct op_req_qinfo - Operational Request Queue Information
283 *
284 * @ci: consumer index
285 * @pi: producer index
286 * @num_request: Maximum number of entries in the queue
287 * @qid: Queue Id starting from 1
288 * @reply_qid: Associated reply queue Id
289 * @num_segments: Number of discontiguous memory segments
290 * @segment_qd: Depth of each segments
291 * @q_lock: Concurrent queue access lock
292 * @q_segments: Segment descriptor pointer
293 * @q_segment_list: Segment list base virtual address
294 * @q_segment_list_dma: Segment list base DMA address
295 */
296struct op_req_qinfo {
297 u16 ci;
298 u16 pi;
299 u16 num_requests;
300 u16 qid;
301 u16 reply_qid;
302 u16 num_segments;
303 u16 segment_qd;
304 spinlock_t q_lock;
305 struct segments *q_segments;
306 void *q_segment_list;
307 dma_addr_t q_segment_list_dma;
308};
309
310/**
311 * struct op_reply_qinfo - Operational Reply Queue Information
312 *
313 * @ci: consumer index
314 * @qid: Queue Id starting from 1
315 * @num_replies: Maximum number of entries in the queue
316 * @num_segments: Number of discontiguous memory segments
317 * @segment_qd: Depth of each segments
318 * @q_segments: Segment descriptor pointer
319 * @q_segment_list: Segment list base virtual address
320 * @q_segment_list_dma: Segment list base DMA address
321 * @ephase: Expected phased identifier for the reply queue
322 * @pend_ios: Number of IOs pending in HW for this queue
323 * @enable_irq_poll: Flag to indicate polling is enabled
324 * @in_use: Queue is handled by poll/ISR
325 */
326struct op_reply_qinfo {
327 u16 ci;
328 u16 qid;
329 u16 num_replies;
330 u16 num_segments;
331 u16 segment_qd;
332 struct segments *q_segments;
333 void *q_segment_list;
334 dma_addr_t q_segment_list_dma;
335 u8 ephase;
336 atomic_t pend_ios;
337 bool enable_irq_poll;
338 atomic_t in_use;
339};
340
341/**
342 * struct mpi3mr_intr_info - Interrupt cookie information
343 *
344 * @mrioc: Adapter instance reference
345 * @msix_index: MSIx index
346 * @op_reply_q: Associated operational reply queue
347 * @name: Dev name for the irq claiming device
348 */
349struct mpi3mr_intr_info {
350 struct mpi3mr_ioc *mrioc;
351 u16 msix_index;
352 struct op_reply_qinfo *op_reply_q;
353 char name[MPI3MR_NAME_LENGTH];
354};
355
356/**
357 * struct tgt_dev_sas_sata - SAS/SATA device specific
358 * information cached from firmware given data
359 *
360 * @sas_address: World wide unique SAS address
361 * @dev_info: Device information bits
362 */
363struct tgt_dev_sas_sata {
364 u64 sas_address;
365 u16 dev_info;
366};
367
368/**
369 * struct tgt_dev_pcie - PCIe device specific information cached
370 * from firmware given data
371 *
372 * @mdts: Maximum data transfer size
373 * @capb: Device capabilities
374 * @pgsz: Device page size
375 * @abort_to: Timeout for abort TM
376 * @reset_to: Timeout for Target/LUN reset TM
377 */
378struct tgt_dev_pcie {
379 u32 mdts;
380 u16 capb;
381 u8 pgsz;
382 u8 abort_to;
383 u8 reset_to;
384};
385
386/**
387 * struct tgt_dev_volume - virtual device specific information
388 * cached from firmware given data
389 *
390 * @state: State of the VD
391 */
392struct tgt_dev_volume {
393 u8 state;
394};
395
396/**
397 * union _form_spec_inf - union of device specific information
398 */
399union _form_spec_inf {
400 struct tgt_dev_sas_sata sas_sata_inf;
401 struct tgt_dev_pcie pcie_inf;
402 struct tgt_dev_volume vol_inf;
403};
404
405
406
407/**
408 * struct mpi3mr_tgt_dev - target device data structure
409 *
410 * @list: List pointer
411 * @starget: Scsi_target pointer
412 * @dev_handle: FW device handle
413 * @parent_handle: FW parent device handle
414 * @slot: Slot number
415 * @encl_handle: FW enclosure handle
416 * @perst_id: FW assigned Persistent ID
417 * @dev_type: SAS/SATA/PCIE device type
418 * @is_hidden: Should be exposed to upper layers or not
419 * @host_exposed: Already exposed to host or not
420 * @q_depth: Device specific Queue Depth
421 * @wwid: World wide ID
422 * @dev_spec: Device type specific information
423 * @ref_count: Reference count
424 */
425struct mpi3mr_tgt_dev {
426 struct list_head list;
427 struct scsi_target *starget;
428 u16 dev_handle;
429 u16 parent_handle;
430 u16 slot;
431 u16 encl_handle;
432 u16 perst_id;
433 u8 dev_type;
434 u8 is_hidden;
435 u8 host_exposed;
436 u16 q_depth;
437 u64 wwid;
438 union _form_spec_inf dev_spec;
439 struct kref ref_count;
440};
441
442/**
443 * mpi3mr_tgtdev_get - k reference incrementor
444 * @s: Target device reference
445 *
446 * Increment target device reference count.
447 */
448static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
449{
450 kref_get(&s->ref_count);
451}
452
453/**
454 * mpi3mr_free_tgtdev - target device memory dealloctor
455 * @r: k reference pointer of the target device
456 *
457 * Free target device memory when no reference.
458 */
459static inline void mpi3mr_free_tgtdev(struct kref *r)
460{
461 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
462}
463
464/**
465 * mpi3mr_tgtdev_put - k reference decrementor
466 * @s: Target device reference
467 *
468 * Decrement target device reference count.
469 */
470static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
471{
472 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
473}
474
475
476/**
477 * struct mpi3mr_stgt_priv_data - SCSI target private structure
478 *
479 * @starget: Scsi_target pointer
480 * @dev_handle: FW device handle
481 * @perst_id: FW assigned Persistent ID
482 * @num_luns: Number of Logical Units
483 * @block_io: I/O blocked to the device or not
484 * @dev_removed: Device removed in the Firmware
485 * @dev_removedelay: Device is waiting to be removed in FW
486 * @dev_type: Device type
487 * @tgt_dev: Internal target device pointer
488 */
489struct mpi3mr_stgt_priv_data {
490 struct scsi_target *starget;
491 u16 dev_handle;
492 u16 perst_id;
493 u32 num_luns;
494 atomic_t block_io;
495 u8 dev_removed;
496 u8 dev_removedelay;
497 u8 dev_type;
498 struct mpi3mr_tgt_dev *tgt_dev;
499};
500
501/**
502 * struct mpi3mr_stgt_priv_data - SCSI device private structure
503 *
504 * @tgt_priv_data: Scsi_target private data pointer
505 * @lun_id: LUN ID of the device
506 * @ncq_prio_enable: NCQ priority enable for SATA device
507 */
508struct mpi3mr_sdev_priv_data {
509 struct mpi3mr_stgt_priv_data *tgt_priv_data;
510 u32 lun_id;
511 u8 ncq_prio_enable;
512};
513
514/**
515 * struct mpi3mr_drv_cmd - Internal command tracker
516 *
517 * @mutex: Command mutex
518 * @done: Completeor for wakeup
519 * @reply: Firmware reply for internal commands
520 * @sensebuf: Sensebuf for SCSI IO commands
521 * @iou_rc: IO Unit control reason code
522 * @state: Command State
523 * @dev_handle: Firmware handle for device specific commands
524 * @ioc_status: IOC status from the firmware
525 * @ioc_loginfo:IOC log info from the firmware
526 * @is_waiting: Is the command issued in block mode
527 * @retry_count: Retry count for retriable commands
528 * @host_tag: Host tag used by the command
529 * @callback: Callback for non blocking commands
530 */
531struct mpi3mr_drv_cmd {
532 struct mutex mutex;
533 struct completion done;
534 void *reply;
535 u8 *sensebuf;
536 u8 iou_rc;
537 u16 state;
538 u16 dev_handle;
539 u16 ioc_status;
540 u32 ioc_loginfo;
541 u8 is_waiting;
542 u8 retry_count;
543 u16 host_tag;
544
545 void (*callback)(struct mpi3mr_ioc *mrioc,
546 struct mpi3mr_drv_cmd *drv_cmd);
547};
548
549
550/**
551 * struct chain_element - memory descriptor structure to store
552 * virtual and dma addresses for chain elements.
553 *
554 * @addr: virtual address
555 * @dma_addr: dma address
556 */
557struct chain_element {
558 void *addr;
559 dma_addr_t dma_addr;
560};
561
562/**
563 * struct scmd_priv - SCSI command private data
564 *
565 * @host_tag: Host tag specific to operational queue
566 * @in_lld_scope: Command in LLD scope or not
567 * @meta_sg_valid: DIX command with meta data SGL or not
568 * @scmd: SCSI Command pointer
569 * @req_q_idx: Operational request queue index
570 * @chain_idx: Chain frame index
571 * @meta_chain_idx: Chain frame index of meta data SGL
572 * @mpi3mr_scsiio_req: MPI SCSI IO request
573 */
574struct scmd_priv {
575 u16 host_tag;
576 u8 in_lld_scope;
577 u8 meta_sg_valid;
578 struct scsi_cmnd *scmd;
579 u16 req_q_idx;
580 int chain_idx;
581 int meta_chain_idx;
582 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
583};
584
585/**
586 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
587 * private data
588 *
589 * @list: List pointer
590 * @pdev: PCI device pointer
591 * @shost: Scsi_Host pointer
592 * @id: Controller ID
593 * @cpu_count: Number of online CPUs
594 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
595 * @name: Controller ASCII name
596 * @driver_name: Driver ASCII name
597 * @sysif_regs: System interface registers virtual address
598 * @sysif_regs_phys: System interface registers physical address
599 * @bars: PCI BARS
600 * @dma_mask: DMA mask
601 * @msix_count: Number of MSIX vectors used
602 * @intr_enabled: Is interrupts enabled
603 * @num_admin_req: Number of admin requests
604 * @admin_req_q_sz: Admin request queue size
605 * @admin_req_pi: Admin request queue producer index
606 * @admin_req_ci: Admin request queue consumer index
607 * @admin_req_base: Admin request queue base virtual address
608 * @admin_req_dma: Admin request queue base dma address
609 * @admin_req_lock: Admin queue access lock
610 * @num_admin_replies: Number of admin replies
611 * @admin_reply_q_sz: Admin reply queue size
612 * @admin_reply_ci: Admin reply queue consumer index
613 * @admin_reply_ephase:Admin reply queue expected phase
614 * @admin_reply_base: Admin reply queue base virtual address
615 * @admin_reply_dma: Admin reply queue base dma address
616 * @ready_timeout: Controller ready timeout
617 * @intr_info: Interrupt cookie pointer
618 * @intr_info_count: Number of interrupt cookies
619 * @num_queues: Number of operational queues
620 * @num_op_req_q: Number of operational request queues
621 * @req_qinfo: Operational request queue info pointer
622 * @num_op_reply_q: Number of operational reply queues
623 * @op_reply_qinfo: Operational reply queue info pointer
624 * @init_cmds: Command tracker for initialization commands
625 * @facts: Cached IOC facts data
626 * @op_reply_desc_sz: Operational reply descriptor size
627 * @num_reply_bufs: Number of reply buffers allocated
628 * @reply_buf_pool: Reply buffer pool
629 * @reply_buf: Reply buffer base virtual address
630 * @reply_buf_dma: Reply buffer DMA address
631 * @reply_buf_dma_max_address: Reply DMA address max limit
632 * @reply_free_qsz: Reply free queue size
633 * @reply_free_q_pool: Reply free queue pool
634 * @reply_free_q: Reply free queue base virtual address
635 * @reply_free_q_dma: Reply free queue base DMA address
636 * @reply_free_queue_lock: Reply free queue lock
637 * @reply_free_queue_host_index: Reply free queue host index
638 * @num_sense_bufs: Number of sense buffers
639 * @sense_buf_pool: Sense buffer pool
640 * @sense_buf: Sense buffer base virtual address
641 * @sense_buf_dma: Sense buffer base DMA address
642 * @sense_buf_q_sz: Sense buffer queue size
643 * @sense_buf_q_pool: Sense buffer queue pool
644 * @sense_buf_q: Sense buffer queue virtual address
645 * @sense_buf_q_dma: Sense buffer queue DMA address
646 * @sbq_lock: Sense buffer queue lock
647 * @sbq_host_index: Sense buffer queuehost index
648 * @event_masks: Event mask bitmap
649 * @fwevt_worker_name: Firmware event worker thread name
650 * @fwevt_worker_thread: Firmware event worker thread
651 * @fwevt_lock: Firmware event lock
652 * @fwevt_list: Firmware event list
653 * @watchdog_work_q_name: Fault watchdog worker thread name
654 * @watchdog_work_q: Fault watchdog worker thread
655 * @watchdog_work: Fault watchdog work
656 * @watchdog_lock: Fault watchdog lock
657 * @is_driver_loading: Is driver still loading
658 * @scan_started: Async scan started
659 * @scan_failed: Asycn scan failed
660 * @stop_drv_processing: Stop all command processing
661 * @max_host_ios: Maximum host I/O count
662 * @chain_buf_count: Chain buffer count
663 * @chain_buf_pool: Chain buffer pool
664 * @chain_sgl_list: Chain SGL list
665 * @chain_bitmap_sz: Chain buffer allocator bitmap size
666 * @chain_bitmap: Chain buffer allocator bitmap
667 * @chain_buf_lock: Chain buffer list lock
668 * @host_tm_cmds: Command tracker for task management commands
669 * @dev_rmhs_cmds: Command tracker for device removal commands
670 * @devrem_bitmap_sz: Device removal bitmap size
671 * @devrem_bitmap: Device removal bitmap
672 * @dev_handle_bitmap_sz: Device handle bitmap size
673 * @removepend_bitmap: Remove pending bitmap
674 * @delayed_rmhs_list: Delayed device removal list
675 * @ts_update_counter: Timestamp update counter
676 * @fault_dbg: Fault debug flag
677 * @reset_in_progress: Reset in progress flag
678 * @unrecoverable: Controller unrecoverable flag
679 * @reset_mutex: Controller reset mutex
680 * @reset_waitq: Controller reset wait queue
681 * @diagsave_timeout: Diagnostic information save timeout
682 * @logging_level: Controller debug logging level
683 * @flush_io_count: I/O count to flush after reset
684 * @current_event: Firmware event currently in process
685 * @driver_info: Driver, Kernel, OS information to firmware
686 * @change_count: Topology change count
687 * @op_reply_q_offset: Operational reply queue offset with MSIx
688 */
689struct mpi3mr_ioc {
690 struct list_head list;
691 struct pci_dev *pdev;
692 struct Scsi_Host *shost;
693 u8 id;
694 int cpu_count;
695 bool enable_segqueue;
696 u32 irqpoll_sleep;
697
698 char name[MPI3MR_NAME_LENGTH];
699 char driver_name[MPI3MR_NAME_LENGTH];
700
701 volatile struct mpi3_sysif_registers __iomem *sysif_regs;
702 resource_size_t sysif_regs_phys;
703 int bars;
704 u64 dma_mask;
705
706 u16 msix_count;
707 u8 intr_enabled;
708
709 u16 num_admin_req;
710 u32 admin_req_q_sz;
711 u16 admin_req_pi;
712 u16 admin_req_ci;
713 void *admin_req_base;
714 dma_addr_t admin_req_dma;
715 spinlock_t admin_req_lock;
716
717 u16 num_admin_replies;
718 u32 admin_reply_q_sz;
719 u16 admin_reply_ci;
720 u8 admin_reply_ephase;
721 void *admin_reply_base;
722 dma_addr_t admin_reply_dma;
723
724 u32 ready_timeout;
725
726 struct mpi3mr_intr_info *intr_info;
727 u16 intr_info_count;
728
729 u16 num_queues;
730 u16 num_op_req_q;
731 struct op_req_qinfo *req_qinfo;
732
733 u16 num_op_reply_q;
734 struct op_reply_qinfo *op_reply_qinfo;
735
736 struct mpi3mr_drv_cmd init_cmds;
737 struct mpi3mr_ioc_facts facts;
738 u16 op_reply_desc_sz;
739
740 u32 num_reply_bufs;
741 struct dma_pool *reply_buf_pool;
742 u8 *reply_buf;
743 dma_addr_t reply_buf_dma;
744 dma_addr_t reply_buf_dma_max_address;
745
746 u16 reply_free_qsz;
747 struct dma_pool *reply_free_q_pool;
748 __le64 *reply_free_q;
749 dma_addr_t reply_free_q_dma;
750 spinlock_t reply_free_queue_lock;
751 u32 reply_free_queue_host_index;
752
753 u32 num_sense_bufs;
754 struct dma_pool *sense_buf_pool;
755 u8 *sense_buf;
756 dma_addr_t sense_buf_dma;
757
758 u16 sense_buf_q_sz;
759 struct dma_pool *sense_buf_q_pool;
760 __le64 *sense_buf_q;
761 dma_addr_t sense_buf_q_dma;
762 spinlock_t sbq_lock;
763 u32 sbq_host_index;
764 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
765
766 char fwevt_worker_name[MPI3MR_NAME_LENGTH];
767 struct workqueue_struct *fwevt_worker_thread;
768 spinlock_t fwevt_lock;
769 struct list_head fwevt_list;
770
771 char watchdog_work_q_name[20];
772 struct workqueue_struct *watchdog_work_q;
773 struct delayed_work watchdog_work;
774 spinlock_t watchdog_lock;
775
776 u8 is_driver_loading;
777 u8 scan_started;
778 u16 scan_failed;
779 u8 stop_drv_processing;
780
781 u16 max_host_ios;
782 spinlock_t tgtdev_lock;
783 struct list_head tgtdev_list;
784
785 u32 chain_buf_count;
786 struct dma_pool *chain_buf_pool;
787 struct chain_element *chain_sgl_list;
788 u16 chain_bitmap_sz;
789 void *chain_bitmap;
790 spinlock_t chain_buf_lock;
791
792 struct mpi3mr_drv_cmd host_tm_cmds;
793 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
794 u16 devrem_bitmap_sz;
795 void *devrem_bitmap;
796 u16 dev_handle_bitmap_sz;
797 void *removepend_bitmap;
798 struct list_head delayed_rmhs_list;
799
800 u32 ts_update_counter;
801 u8 fault_dbg;
802 u8 reset_in_progress;
803 u8 unrecoverable;
804 struct mutex reset_mutex;
805 wait_queue_head_t reset_waitq;
806
807 u16 diagsave_timeout;
808 int logging_level;
809 u16 flush_io_count;
810
811 struct mpi3mr_fwevt *current_event;
812 struct mpi3_driver_info_layout driver_info;
813 u16 change_count;
814 u16 op_reply_q_offset;
815};
816
817/**
818 * struct mpi3mr_fwevt - Firmware event structure.
819 *
820 * @list: list head
821 * @work: Work structure
822 * @mrioc: Adapter instance reference
823 * @event_id: MPI3 firmware event ID
824 * @send_ack: Event acknowledgment required or not
825 * @process_evt: Bottomhalf processing required or not
826 * @evt_ctx: Event context to send in Ack
827 * @ref_count: kref count
828 * @event_data: Actual MPI3 event data
829 */
830struct mpi3mr_fwevt {
831 struct list_head list;
832 struct work_struct work;
833 struct mpi3mr_ioc *mrioc;
834 u16 event_id;
835 bool send_ack;
836 bool process_evt;
837 u32 evt_ctx;
838 struct kref ref_count;
839 char event_data[0] __aligned(4);
840};
841
842
843/**
844 * struct delayed_dev_rmhs_node - Delayed device removal node
845 *
846 * @list: list head
847 * @handle: Device handle
848 * @iou_rc: IO Unit Control Reason Code
849 */
850struct delayed_dev_rmhs_node {
851 struct list_head list;
852 u16 handle;
853 u8 iou_rc;
854};
855
856int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
857void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
858int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc, u8 re_init);
859void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc, u8 re_init);
860int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
861int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
862u16 admin_req_sz, u8 ignore_reset);
863int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
864 struct op_req_qinfo *opreqq, u8 *req);
865void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
866 dma_addr_t dma_addr);
867void mpi3mr_build_zero_len_sge(void *paddr);
868void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
869 dma_addr_t phys_addr);
870void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
871 dma_addr_t phys_addr);
872void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
873 u64 sense_buf_dma);
874
875void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
876 struct mpi3_event_notification_reply *event_reply);
877void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
878 struct mpi3_default_reply_descriptor *reply_desc,
879 u64 *reply_dma, u16 qidx);
880void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
881void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
882
883int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
884 u32 reset_reason, u8 snapdump);
885int mpi3mr_diagfault_reset_handler(struct mpi3mr_ioc *mrioc,
886 u32 reset_reason);
887void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
888void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
889
890enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
891int mpi3mr_send_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
892 u32 event_ctx);
893
894void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
895void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
896void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
897void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
898void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
899void mpi3mr_flush_delayed_rmhs_list(struct mpi3mr_ioc *mrioc);
900
901#endif /*MPI3MR_H_INCLUDED*/