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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Expose a PWM controlled by the ChromeOS EC to the host processor.
4 *
5 * Copyright (C) 2016 Google, Inc.
6 */
7
8#include <linux/module.h>
9#include <linux/platform_data/cros_ec_commands.h>
10#include <linux/platform_data/cros_ec_proto.h>
11#include <linux/platform_device.h>
12#include <linux/pwm.h>
13#include <linux/slab.h>
14
15/**
16 * struct cros_ec_pwm_device - Driver data for EC PWM
17 *
18 * @dev: Device node
19 * @ec: Pointer to EC device
20 * @chip: PWM controller chip
21 */
22struct cros_ec_pwm_device {
23 struct device *dev;
24 struct cros_ec_device *ec;
25 struct pwm_chip chip;
26};
27
28/**
29 * struct cros_ec_pwm - per-PWM driver data
30 * @duty_cycle: cached duty cycle
31 */
32struct cros_ec_pwm {
33 u16 duty_cycle;
34};
35
36static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *c)
37{
38 return container_of(c, struct cros_ec_pwm_device, chip);
39}
40
41static int cros_ec_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
42{
43 struct cros_ec_pwm *channel;
44
45 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
46 if (!channel)
47 return -ENOMEM;
48
49 pwm_set_chip_data(pwm, channel);
50
51 return 0;
52}
53
54static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
55{
56 struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
57
58 kfree(channel);
59}
60
61static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty)
62{
63 struct {
64 struct cros_ec_command msg;
65 struct ec_params_pwm_set_duty params;
66 } __packed buf;
67 struct ec_params_pwm_set_duty *params = &buf.params;
68 struct cros_ec_command *msg = &buf.msg;
69
70 memset(&buf, 0, sizeof(buf));
71
72 msg->version = 0;
73 msg->command = EC_CMD_PWM_SET_DUTY;
74 msg->insize = 0;
75 msg->outsize = sizeof(*params);
76
77 params->duty = duty;
78 params->pwm_type = EC_PWM_TYPE_GENERIC;
79 params->index = index;
80
81 return cros_ec_cmd_xfer_status(ec, msg);
82}
83
84static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index)
85{
86 struct {
87 struct cros_ec_command msg;
88 union {
89 struct ec_params_pwm_get_duty params;
90 struct ec_response_pwm_get_duty resp;
91 };
92 } __packed buf;
93 struct ec_params_pwm_get_duty *params = &buf.params;
94 struct ec_response_pwm_get_duty *resp = &buf.resp;
95 struct cros_ec_command *msg = &buf.msg;
96 int ret;
97
98 memset(&buf, 0, sizeof(buf));
99
100 msg->version = 0;
101 msg->command = EC_CMD_PWM_GET_DUTY;
102 msg->insize = sizeof(*resp);
103 msg->outsize = sizeof(*params);
104
105 params->pwm_type = EC_PWM_TYPE_GENERIC;
106 params->index = index;
107
108 ret = cros_ec_cmd_xfer_status(ec, msg);
109 if (ret < 0)
110 return ret;
111
112 return resp->duty;
113}
114
115static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
116 const struct pwm_state *state)
117{
118 struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
119 struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
120 u16 duty_cycle;
121 int ret;
122
123 /* The EC won't let us change the period */
124 if (state->period != EC_PWM_MAX_DUTY)
125 return -EINVAL;
126
127 if (state->polarity != PWM_POLARITY_NORMAL)
128 return -EINVAL;
129
130 /*
131 * EC doesn't separate the concept of duty cycle and enabled, but
132 * kernel does. Translate.
133 */
134 duty_cycle = state->enabled ? state->duty_cycle : 0;
135
136 ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle);
137 if (ret < 0)
138 return ret;
139
140 channel->duty_cycle = state->duty_cycle;
141
142 return 0;
143}
144
145static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
146 struct pwm_state *state)
147{
148 struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
149 struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
150 int ret;
151
152 ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm);
153 if (ret < 0) {
154 dev_err(chip->dev, "error getting initial duty: %d\n", ret);
155 return;
156 }
157
158 state->enabled = (ret > 0);
159 state->period = EC_PWM_MAX_DUTY;
160
161 /*
162 * Note that "disabled" and "duty cycle == 0" are treated the same. If
163 * the cached duty cycle is not zero, used the cached duty cycle. This
164 * ensures that the configured duty cycle is kept across a disable and
165 * enable operation and avoids potentially confusing consumers.
166 *
167 * For the case of the initial hardware readout, channel->duty_cycle
168 * will be 0 and the actual duty cycle read from the EC is used.
169 */
170 if (ret == 0 && channel->duty_cycle > 0)
171 state->duty_cycle = channel->duty_cycle;
172 else
173 state->duty_cycle = ret;
174}
175
176static struct pwm_device *
177cros_ec_pwm_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
178{
179 struct pwm_device *pwm;
180
181 if (args->args[0] >= pc->npwm)
182 return ERR_PTR(-EINVAL);
183
184 pwm = pwm_request_from_chip(pc, args->args[0], NULL);
185 if (IS_ERR(pwm))
186 return pwm;
187
188 /* The EC won't let us change the period */
189 pwm->args.period = EC_PWM_MAX_DUTY;
190
191 return pwm;
192}
193
194static const struct pwm_ops cros_ec_pwm_ops = {
195 .request = cros_ec_pwm_request,
196 .free = cros_ec_pwm_free,
197 .get_state = cros_ec_pwm_get_state,
198 .apply = cros_ec_pwm_apply,
199 .owner = THIS_MODULE,
200};
201
202/*
203 * Determine the number of supported PWMs. The EC does not return the number
204 * of PWMs it supports directly, so we have to read the pwm duty cycle for
205 * subsequent channels until we get an error.
206 */
207static int cros_ec_num_pwms(struct cros_ec_device *ec)
208{
209 int i, ret;
210
211 /* The index field is only 8 bits */
212 for (i = 0; i <= U8_MAX; i++) {
213 ret = cros_ec_pwm_get_duty(ec, i);
214 /*
215 * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
216 * responses; everything else is treated as an error.
217 * The EC error codes map to -EOPNOTSUPP and -EINVAL,
218 * so check for those.
219 */
220 switch (ret) {
221 case -EOPNOTSUPP: /* invalid command */
222 return -ENODEV;
223 case -EINVAL: /* invalid parameter */
224 return i;
225 default:
226 if (ret < 0)
227 return ret;
228 break;
229 }
230 }
231
232 return U8_MAX;
233}
234
235static int cros_ec_pwm_probe(struct platform_device *pdev)
236{
237 struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
238 struct device *dev = &pdev->dev;
239 struct cros_ec_pwm_device *ec_pwm;
240 struct pwm_chip *chip;
241 int ret;
242
243 if (!ec) {
244 dev_err(dev, "no parent EC device\n");
245 return -EINVAL;
246 }
247
248 ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
249 if (!ec_pwm)
250 return -ENOMEM;
251 chip = &ec_pwm->chip;
252 ec_pwm->ec = ec;
253
254 /* PWM chip */
255 chip->dev = dev;
256 chip->ops = &cros_ec_pwm_ops;
257 chip->of_xlate = cros_ec_pwm_xlate;
258 chip->of_pwm_n_cells = 1;
259 ret = cros_ec_num_pwms(ec);
260 if (ret < 0) {
261 dev_err(dev, "Couldn't find PWMs: %d\n", ret);
262 return ret;
263 }
264 chip->npwm = ret;
265 dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);
266
267 ret = pwmchip_add(chip);
268 if (ret < 0) {
269 dev_err(dev, "cannot register PWM: %d\n", ret);
270 return ret;
271 }
272
273 platform_set_drvdata(pdev, ec_pwm);
274
275 return ret;
276}
277
278static int cros_ec_pwm_remove(struct platform_device *dev)
279{
280 struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
281 struct pwm_chip *chip = &ec_pwm->chip;
282
283 return pwmchip_remove(chip);
284}
285
286#ifdef CONFIG_OF
287static const struct of_device_id cros_ec_pwm_of_match[] = {
288 { .compatible = "google,cros-ec-pwm" },
289 {},
290};
291MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
292#endif
293
294static struct platform_driver cros_ec_pwm_driver = {
295 .probe = cros_ec_pwm_probe,
296 .remove = cros_ec_pwm_remove,
297 .driver = {
298 .name = "cros-ec-pwm",
299 .of_match_table = of_match_ptr(cros_ec_pwm_of_match),
300 },
301};
302module_platform_driver(cros_ec_pwm_driver);
303
304MODULE_ALIAS("platform:cros-ec-pwm");
305MODULE_DESCRIPTION("ChromeOS EC PWM driver");
306MODULE_LICENSE("GPL v2");