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1/*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/interrupt.h>
35
36#include "shpchp.h"
37
38/* Slot Available Register I field definition */
39#define SLOT_33MHZ 0x0000001f
40#define SLOT_66MHZ_PCIX 0x00001f00
41#define SLOT_100MHZ_PCIX 0x001f0000
42#define SLOT_133MHZ_PCIX 0x1f000000
43
44/* Slot Available Register II field definition */
45#define SLOT_66MHZ 0x0000001f
46#define SLOT_66MHZ_PCIX_266 0x00000f00
47#define SLOT_100MHZ_PCIX_266 0x0000f000
48#define SLOT_133MHZ_PCIX_266 0x000f0000
49#define SLOT_66MHZ_PCIX_533 0x00f00000
50#define SLOT_100MHZ_PCIX_533 0x0f000000
51#define SLOT_133MHZ_PCIX_533 0xf0000000
52
53/* Slot Configuration */
54#define SLOT_NUM 0x0000001F
55#define FIRST_DEV_NUM 0x00001F00
56#define PSN 0x07FF0000
57#define UPDOWN 0x20000000
58#define MRLSENSOR 0x40000000
59#define ATTN_BUTTON 0x80000000
60
61/*
62 * Interrupt Locator Register definitions
63 */
64#define CMD_INTR_PENDING (1 << 0)
65#define SLOT_INTR_PENDING(i) (1 << (i + 1))
66
67/*
68 * Controller SERR-INT Register
69 */
70#define GLOBAL_INTR_MASK (1 << 0)
71#define GLOBAL_SERR_MASK (1 << 1)
72#define COMMAND_INTR_MASK (1 << 2)
73#define ARBITER_SERR_MASK (1 << 3)
74#define COMMAND_DETECTED (1 << 16)
75#define ARBITER_DETECTED (1 << 17)
76#define SERR_INTR_RSVDZ_MASK 0xfffc0000
77
78/*
79 * Logical Slot Register definitions
80 */
81#define SLOT_REG(i) (SLOT1 + (4 * i))
82
83#define SLOT_STATE_SHIFT (0)
84#define SLOT_STATE_MASK (3 << 0)
85#define SLOT_STATE_PWRONLY (1)
86#define SLOT_STATE_ENABLED (2)
87#define SLOT_STATE_DISABLED (3)
88#define PWR_LED_STATE_SHIFT (2)
89#define PWR_LED_STATE_MASK (3 << 2)
90#define ATN_LED_STATE_SHIFT (4)
91#define ATN_LED_STATE_MASK (3 << 4)
92#define ATN_LED_STATE_ON (1)
93#define ATN_LED_STATE_BLINK (2)
94#define ATN_LED_STATE_OFF (3)
95#define POWER_FAULT (1 << 6)
96#define ATN_BUTTON (1 << 7)
97#define MRL_SENSOR (1 << 8)
98#define MHZ66_CAP (1 << 9)
99#define PRSNT_SHIFT (10)
100#define PRSNT_MASK (3 << 10)
101#define PCIX_CAP_SHIFT (12)
102#define PCIX_CAP_MASK_PI1 (3 << 12)
103#define PCIX_CAP_MASK_PI2 (7 << 12)
104#define PRSNT_CHANGE_DETECTED (1 << 16)
105#define ISO_PFAULT_DETECTED (1 << 17)
106#define BUTTON_PRESS_DETECTED (1 << 18)
107#define MRL_CHANGE_DETECTED (1 << 19)
108#define CON_PFAULT_DETECTED (1 << 20)
109#define PRSNT_CHANGE_INTR_MASK (1 << 24)
110#define ISO_PFAULT_INTR_MASK (1 << 25)
111#define BUTTON_PRESS_INTR_MASK (1 << 26)
112#define MRL_CHANGE_INTR_MASK (1 << 27)
113#define CON_PFAULT_INTR_MASK (1 << 28)
114#define MRL_CHANGE_SERR_MASK (1 << 29)
115#define CON_PFAULT_SERR_MASK (1 << 30)
116#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
117
118/*
119 * SHPC Command Code definitnions
120 *
121 * Slot Operation 00h - 3Fh
122 * Set Bus Segment Speed/Mode A 40h - 47h
123 * Power-Only All Slots 48h
124 * Enable All Slots 49h
125 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
126 * Reserved Command Codes 60h - BFh
127 * Vendor Specific Commands C0h - FFh
128 */
129#define SET_SLOT_PWR 0x01 /* Slot Operation */
130#define SET_SLOT_ENABLE 0x02
131#define SET_SLOT_DISABLE 0x03
132#define SET_PWR_ON 0x04
133#define SET_PWR_BLINK 0x08
134#define SET_PWR_OFF 0x0c
135#define SET_ATTN_ON 0x10
136#define SET_ATTN_BLINK 0x20
137#define SET_ATTN_OFF 0x30
138#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
139#define SETA_PCI_66MHZ 0x41
140#define SETA_PCIX_66MHZ 0x42
141#define SETA_PCIX_100MHZ 0x43
142#define SETA_PCIX_133MHZ 0x44
143#define SETA_RESERVED1 0x45
144#define SETA_RESERVED2 0x46
145#define SETA_RESERVED3 0x47
146#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
147#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
148#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
149#define SETB_PCI_66MHZ 0x51
150#define SETB_PCIX_66MHZ_PM 0x52
151#define SETB_PCIX_100MHZ_PM 0x53
152#define SETB_PCIX_133MHZ_PM 0x54
153#define SETB_PCIX_66MHZ_EM 0x55
154#define SETB_PCIX_100MHZ_EM 0x56
155#define SETB_PCIX_133MHZ_EM 0x57
156#define SETB_PCIX_66MHZ_266 0x58
157#define SETB_PCIX_100MHZ_266 0x59
158#define SETB_PCIX_133MHZ_266 0x5a
159#define SETB_PCIX_66MHZ_533 0x5b
160#define SETB_PCIX_100MHZ_533 0x5c
161#define SETB_PCIX_133MHZ_533 0x5d
162#define SETB_RESERVED1 0x5e
163#define SETB_RESERVED2 0x5f
164
165/*
166 * SHPC controller command error code
167 */
168#define SWITCH_OPEN 0x1
169#define INVALID_CMD 0x2
170#define INVALID_SPEED_MODE 0x4
171
172/*
173 * For accessing SHPC Working Register Set via PCI Configuration Space
174 */
175#define DWORD_SELECT 0x2
176#define DWORD_DATA 0x4
177
178/* Field Offset in Logical Slot Register - byte boundary */
179#define SLOT_EVENT_LATCH 0x2
180#define SLOT_SERR_INT_MASK 0x3
181
182static irqreturn_t shpc_isr(int irq, void *dev_id);
183static void start_int_poll_timer(struct controller *ctrl, int sec);
184static int hpc_check_cmd_status(struct controller *ctrl);
185
186static inline u8 shpc_readb(struct controller *ctrl, int reg)
187{
188 return readb(ctrl->creg + reg);
189}
190
191static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
192{
193 writeb(val, ctrl->creg + reg);
194}
195
196static inline u16 shpc_readw(struct controller *ctrl, int reg)
197{
198 return readw(ctrl->creg + reg);
199}
200
201static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
202{
203 writew(val, ctrl->creg + reg);
204}
205
206static inline u32 shpc_readl(struct controller *ctrl, int reg)
207{
208 return readl(ctrl->creg + reg);
209}
210
211static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
212{
213 writel(val, ctrl->creg + reg);
214}
215
216static inline int shpc_indirect_read(struct controller *ctrl, int index,
217 u32 *value)
218{
219 int rc;
220 u32 cap_offset = ctrl->cap_offset;
221 struct pci_dev *pdev = ctrl->pci_dev;
222
223 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
224 if (rc)
225 return rc;
226 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
227}
228
229/*
230 * This is the interrupt polling timeout function.
231 */
232static void int_poll_timeout(unsigned long data)
233{
234 struct controller *ctrl = (struct controller *)data;
235
236 /* Poll for interrupt events. regs == NULL => polling */
237 shpc_isr(0, ctrl);
238
239 init_timer(&ctrl->poll_timer);
240 if (!shpchp_poll_time)
241 shpchp_poll_time = 2; /* default polling interval is 2 sec */
242
243 start_int_poll_timer(ctrl, shpchp_poll_time);
244}
245
246/*
247 * This function starts the interrupt polling timer.
248 */
249static void start_int_poll_timer(struct controller *ctrl, int sec)
250{
251 /* Clamp to sane value */
252 if ((sec <= 0) || (sec > 60))
253 sec = 2;
254
255 ctrl->poll_timer.function = &int_poll_timeout;
256 ctrl->poll_timer.data = (unsigned long)ctrl;
257 ctrl->poll_timer.expires = jiffies + sec * HZ;
258 add_timer(&ctrl->poll_timer);
259}
260
261static inline int is_ctrl_busy(struct controller *ctrl)
262{
263 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
264 return cmd_status & 0x1;
265}
266
267/*
268 * Returns 1 if SHPC finishes executing a command within 1 sec,
269 * otherwise returns 0.
270 */
271static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
272{
273 int i;
274
275 if (!is_ctrl_busy(ctrl))
276 return 1;
277
278 /* Check every 0.1 sec for a total of 1 sec */
279 for (i = 0; i < 10; i++) {
280 msleep(100);
281 if (!is_ctrl_busy(ctrl))
282 return 1;
283 }
284
285 return 0;
286}
287
288static inline int shpc_wait_cmd(struct controller *ctrl)
289{
290 int retval = 0;
291 unsigned long timeout = msecs_to_jiffies(1000);
292 int rc;
293
294 if (shpchp_poll_mode)
295 rc = shpc_poll_ctrl_busy(ctrl);
296 else
297 rc = wait_event_interruptible_timeout(ctrl->queue,
298 !is_ctrl_busy(ctrl), timeout);
299 if (!rc && is_ctrl_busy(ctrl)) {
300 retval = -EIO;
301 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
302 } else if (rc < 0) {
303 retval = -EINTR;
304 ctrl_info(ctrl, "Command was interrupted by a signal\n");
305 }
306
307 return retval;
308}
309
310static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
311{
312 struct controller *ctrl = slot->ctrl;
313 u16 cmd_status;
314 int retval = 0;
315 u16 temp_word;
316
317 mutex_lock(&slot->ctrl->cmd_lock);
318
319 if (!shpc_poll_ctrl_busy(ctrl)) {
320 /* After 1 sec and and the controller is still busy */
321 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
322 retval = -EBUSY;
323 goto out;
324 }
325
326 ++t_slot;
327 temp_word = (t_slot << 8) | (cmd & 0xFF);
328 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
329
330 /* To make sure the Controller Busy bit is 0 before we send out the
331 * command.
332 */
333 shpc_writew(ctrl, CMD, temp_word);
334
335 /*
336 * Wait for command completion.
337 */
338 retval = shpc_wait_cmd(slot->ctrl);
339 if (retval)
340 goto out;
341
342 cmd_status = hpc_check_cmd_status(slot->ctrl);
343 if (cmd_status) {
344 ctrl_err(ctrl,
345 "Failed to issued command 0x%x (error code = %d)\n",
346 cmd, cmd_status);
347 retval = -EIO;
348 }
349 out:
350 mutex_unlock(&slot->ctrl->cmd_lock);
351 return retval;
352}
353
354static int hpc_check_cmd_status(struct controller *ctrl)
355{
356 int retval = 0;
357 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
358
359 switch (cmd_status >> 1) {
360 case 0:
361 retval = 0;
362 break;
363 case 1:
364 retval = SWITCH_OPEN;
365 ctrl_err(ctrl, "Switch opened!\n");
366 break;
367 case 2:
368 retval = INVALID_CMD;
369 ctrl_err(ctrl, "Invalid HPC command!\n");
370 break;
371 case 4:
372 retval = INVALID_SPEED_MODE;
373 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
374 break;
375 default:
376 retval = cmd_status;
377 }
378
379 return retval;
380}
381
382
383static int hpc_get_attention_status(struct slot *slot, u8 *status)
384{
385 struct controller *ctrl = slot->ctrl;
386 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
387 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
388
389 switch (state) {
390 case ATN_LED_STATE_ON:
391 *status = 1; /* On */
392 break;
393 case ATN_LED_STATE_BLINK:
394 *status = 2; /* Blink */
395 break;
396 case ATN_LED_STATE_OFF:
397 *status = 0; /* Off */
398 break;
399 default:
400 *status = 0xFF; /* Reserved */
401 break;
402 }
403
404 return 0;
405}
406
407static int hpc_get_power_status(struct slot * slot, u8 *status)
408{
409 struct controller *ctrl = slot->ctrl;
410 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
411 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
412
413 switch (state) {
414 case SLOT_STATE_PWRONLY:
415 *status = 2; /* Powered only */
416 break;
417 case SLOT_STATE_ENABLED:
418 *status = 1; /* Enabled */
419 break;
420 case SLOT_STATE_DISABLED:
421 *status = 0; /* Disabled */
422 break;
423 default:
424 *status = 0xFF; /* Reserved */
425 break;
426 }
427
428 return 0;
429}
430
431
432static int hpc_get_latch_status(struct slot *slot, u8 *status)
433{
434 struct controller *ctrl = slot->ctrl;
435 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
436
437 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
438
439 return 0;
440}
441
442static int hpc_get_adapter_status(struct slot *slot, u8 *status)
443{
444 struct controller *ctrl = slot->ctrl;
445 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
446 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
447
448 *status = (state != 0x3) ? 1 : 0;
449
450 return 0;
451}
452
453static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
454{
455 struct controller *ctrl = slot->ctrl;
456
457 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
458
459 return 0;
460}
461
462static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
463{
464 int retval = 0;
465 struct controller *ctrl = slot->ctrl;
466 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
467 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
468 u8 pi, pcix_cap;
469
470 if ((retval = hpc_get_prog_int(slot, &pi)))
471 return retval;
472
473 switch (pi) {
474 case 1:
475 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
476 break;
477 case 2:
478 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
479 break;
480 default:
481 return -ENODEV;
482 }
483
484 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
485 __func__, slot_reg, pcix_cap, m66_cap);
486
487 switch (pcix_cap) {
488 case 0x0:
489 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
490 break;
491 case 0x1:
492 *value = PCI_SPEED_66MHz_PCIX;
493 break;
494 case 0x3:
495 *value = PCI_SPEED_133MHz_PCIX;
496 break;
497 case 0x4:
498 *value = PCI_SPEED_133MHz_PCIX_266;
499 break;
500 case 0x5:
501 *value = PCI_SPEED_133MHz_PCIX_533;
502 break;
503 case 0x2:
504 default:
505 *value = PCI_SPEED_UNKNOWN;
506 retval = -ENODEV;
507 break;
508 }
509
510 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
511 return retval;
512}
513
514static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
515{
516 int retval = 0;
517 struct controller *ctrl = slot->ctrl;
518 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
519 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
520
521 if (pi == 2) {
522 *mode = (sec_bus_status & 0x0100) >> 8;
523 } else {
524 retval = -1;
525 }
526
527 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
528 return retval;
529}
530
531static int hpc_query_power_fault(struct slot * slot)
532{
533 struct controller *ctrl = slot->ctrl;
534 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
535
536 /* Note: Logic 0 => fault */
537 return !(slot_reg & POWER_FAULT);
538}
539
540static int hpc_set_attention_status(struct slot *slot, u8 value)
541{
542 u8 slot_cmd = 0;
543
544 switch (value) {
545 case 0 :
546 slot_cmd = SET_ATTN_OFF; /* OFF */
547 break;
548 case 1:
549 slot_cmd = SET_ATTN_ON; /* ON */
550 break;
551 case 2:
552 slot_cmd = SET_ATTN_BLINK; /* BLINK */
553 break;
554 default:
555 return -1;
556 }
557
558 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
559}
560
561
562static void hpc_set_green_led_on(struct slot *slot)
563{
564 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
565}
566
567static void hpc_set_green_led_off(struct slot *slot)
568{
569 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
570}
571
572static void hpc_set_green_led_blink(struct slot *slot)
573{
574 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
575}
576
577static void hpc_release_ctlr(struct controller *ctrl)
578{
579 int i;
580 u32 slot_reg, serr_int;
581
582 /*
583 * Mask event interrupts and SERRs of all slots
584 */
585 for (i = 0; i < ctrl->num_slots; i++) {
586 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
587 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
588 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
589 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
590 CON_PFAULT_SERR_MASK);
591 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
592 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
593 }
594
595 cleanup_slots(ctrl);
596
597 /*
598 * Mask SERR and System Interrupt generation
599 */
600 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
601 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
602 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
603 serr_int &= ~SERR_INTR_RSVDZ_MASK;
604 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
605
606 if (shpchp_poll_mode)
607 del_timer(&ctrl->poll_timer);
608 else {
609 free_irq(ctrl->pci_dev->irq, ctrl);
610 pci_disable_msi(ctrl->pci_dev);
611 }
612
613 iounmap(ctrl->creg);
614 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
615}
616
617static int hpc_power_on_slot(struct slot * slot)
618{
619 int retval;
620
621 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
622 if (retval)
623 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
624
625 return retval;
626}
627
628static int hpc_slot_enable(struct slot * slot)
629{
630 int retval;
631
632 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
633 retval = shpc_write_cmd(slot, slot->hp_slot,
634 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
635 if (retval)
636 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
637
638 return retval;
639}
640
641static int hpc_slot_disable(struct slot * slot)
642{
643 int retval;
644
645 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
646 retval = shpc_write_cmd(slot, slot->hp_slot,
647 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
648 if (retval)
649 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
650
651 return retval;
652}
653
654static int shpc_get_cur_bus_speed(struct controller *ctrl)
655{
656 int retval = 0;
657 struct pci_bus *bus = ctrl->pci_dev->subordinate;
658 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
659 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
660 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
661 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
662
663 if ((pi == 1) && (speed_mode > 4)) {
664 retval = -ENODEV;
665 goto out;
666 }
667
668 switch (speed_mode) {
669 case 0x0:
670 bus_speed = PCI_SPEED_33MHz;
671 break;
672 case 0x1:
673 bus_speed = PCI_SPEED_66MHz;
674 break;
675 case 0x2:
676 bus_speed = PCI_SPEED_66MHz_PCIX;
677 break;
678 case 0x3:
679 bus_speed = PCI_SPEED_100MHz_PCIX;
680 break;
681 case 0x4:
682 bus_speed = PCI_SPEED_133MHz_PCIX;
683 break;
684 case 0x5:
685 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
686 break;
687 case 0x6:
688 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
689 break;
690 case 0x7:
691 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
692 break;
693 case 0x8:
694 bus_speed = PCI_SPEED_66MHz_PCIX_266;
695 break;
696 case 0x9:
697 bus_speed = PCI_SPEED_100MHz_PCIX_266;
698 break;
699 case 0xa:
700 bus_speed = PCI_SPEED_133MHz_PCIX_266;
701 break;
702 case 0xb:
703 bus_speed = PCI_SPEED_66MHz_PCIX_533;
704 break;
705 case 0xc:
706 bus_speed = PCI_SPEED_100MHz_PCIX_533;
707 break;
708 case 0xd:
709 bus_speed = PCI_SPEED_133MHz_PCIX_533;
710 break;
711 default:
712 retval = -ENODEV;
713 break;
714 }
715
716 out:
717 bus->cur_bus_speed = bus_speed;
718 dbg("Current bus speed = %d\n", bus_speed);
719 return retval;
720}
721
722
723static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
724{
725 int retval;
726 struct controller *ctrl = slot->ctrl;
727 u8 pi, cmd;
728
729 pi = shpc_readb(ctrl, PROG_INTERFACE);
730 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
731 return -EINVAL;
732
733 switch (value) {
734 case PCI_SPEED_33MHz:
735 cmd = SETA_PCI_33MHZ;
736 break;
737 case PCI_SPEED_66MHz:
738 cmd = SETA_PCI_66MHZ;
739 break;
740 case PCI_SPEED_66MHz_PCIX:
741 cmd = SETA_PCIX_66MHZ;
742 break;
743 case PCI_SPEED_100MHz_PCIX:
744 cmd = SETA_PCIX_100MHZ;
745 break;
746 case PCI_SPEED_133MHz_PCIX:
747 cmd = SETA_PCIX_133MHZ;
748 break;
749 case PCI_SPEED_66MHz_PCIX_ECC:
750 cmd = SETB_PCIX_66MHZ_EM;
751 break;
752 case PCI_SPEED_100MHz_PCIX_ECC:
753 cmd = SETB_PCIX_100MHZ_EM;
754 break;
755 case PCI_SPEED_133MHz_PCIX_ECC:
756 cmd = SETB_PCIX_133MHZ_EM;
757 break;
758 case PCI_SPEED_66MHz_PCIX_266:
759 cmd = SETB_PCIX_66MHZ_266;
760 break;
761 case PCI_SPEED_100MHz_PCIX_266:
762 cmd = SETB_PCIX_100MHZ_266;
763 break;
764 case PCI_SPEED_133MHz_PCIX_266:
765 cmd = SETB_PCIX_133MHZ_266;
766 break;
767 case PCI_SPEED_66MHz_PCIX_533:
768 cmd = SETB_PCIX_66MHZ_533;
769 break;
770 case PCI_SPEED_100MHz_PCIX_533:
771 cmd = SETB_PCIX_100MHZ_533;
772 break;
773 case PCI_SPEED_133MHz_PCIX_533:
774 cmd = SETB_PCIX_133MHZ_533;
775 break;
776 default:
777 return -EINVAL;
778 }
779
780 retval = shpc_write_cmd(slot, 0, cmd);
781 if (retval)
782 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
783 else
784 shpc_get_cur_bus_speed(ctrl);
785
786 return retval;
787}
788
789static irqreturn_t shpc_isr(int irq, void *dev_id)
790{
791 struct controller *ctrl = (struct controller *)dev_id;
792 u32 serr_int, slot_reg, intr_loc, intr_loc2;
793 int hp_slot;
794
795 /* Check to see if it was our interrupt */
796 intr_loc = shpc_readl(ctrl, INTR_LOC);
797 if (!intr_loc)
798 return IRQ_NONE;
799
800 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
801
802 if(!shpchp_poll_mode) {
803 /*
804 * Mask Global Interrupt Mask - see implementation
805 * note on p. 139 of SHPC spec rev 1.0
806 */
807 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
808 serr_int |= GLOBAL_INTR_MASK;
809 serr_int &= ~SERR_INTR_RSVDZ_MASK;
810 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
811
812 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
813 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
814 }
815
816 if (intr_loc & CMD_INTR_PENDING) {
817 /*
818 * Command Complete Interrupt Pending
819 * RO only - clear by writing 1 to the Command Completion
820 * Detect bit in Controller SERR-INT register
821 */
822 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
823 serr_int &= ~SERR_INTR_RSVDZ_MASK;
824 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
825
826 wake_up_interruptible(&ctrl->queue);
827 }
828
829 if (!(intr_loc & ~CMD_INTR_PENDING))
830 goto out;
831
832 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
833 /* To find out which slot has interrupt pending */
834 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
835 continue;
836
837 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
838 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
839 hp_slot, slot_reg);
840
841 if (slot_reg & MRL_CHANGE_DETECTED)
842 shpchp_handle_switch_change(hp_slot, ctrl);
843
844 if (slot_reg & BUTTON_PRESS_DETECTED)
845 shpchp_handle_attention_button(hp_slot, ctrl);
846
847 if (slot_reg & PRSNT_CHANGE_DETECTED)
848 shpchp_handle_presence_change(hp_slot, ctrl);
849
850 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
851 shpchp_handle_power_fault(hp_slot, ctrl);
852
853 /* Clear all slot events */
854 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
855 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
856 }
857 out:
858 if (!shpchp_poll_mode) {
859 /* Unmask Global Interrupt Mask */
860 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
861 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
862 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
863 }
864
865 return IRQ_HANDLED;
866}
867
868static int shpc_get_max_bus_speed(struct controller *ctrl)
869{
870 int retval = 0;
871 struct pci_bus *bus = ctrl->pci_dev->subordinate;
872 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
873 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
874 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
875 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
876
877 if (pi == 2) {
878 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
879 bus_speed = PCI_SPEED_133MHz_PCIX_533;
880 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
881 bus_speed = PCI_SPEED_100MHz_PCIX_533;
882 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
883 bus_speed = PCI_SPEED_66MHz_PCIX_533;
884 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
885 bus_speed = PCI_SPEED_133MHz_PCIX_266;
886 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
887 bus_speed = PCI_SPEED_100MHz_PCIX_266;
888 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
889 bus_speed = PCI_SPEED_66MHz_PCIX_266;
890 }
891
892 if (bus_speed == PCI_SPEED_UNKNOWN) {
893 if (slot_avail1 & SLOT_133MHZ_PCIX)
894 bus_speed = PCI_SPEED_133MHz_PCIX;
895 else if (slot_avail1 & SLOT_100MHZ_PCIX)
896 bus_speed = PCI_SPEED_100MHz_PCIX;
897 else if (slot_avail1 & SLOT_66MHZ_PCIX)
898 bus_speed = PCI_SPEED_66MHz_PCIX;
899 else if (slot_avail2 & SLOT_66MHZ)
900 bus_speed = PCI_SPEED_66MHz;
901 else if (slot_avail1 & SLOT_33MHZ)
902 bus_speed = PCI_SPEED_33MHz;
903 else
904 retval = -ENODEV;
905 }
906
907 bus->max_bus_speed = bus_speed;
908 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
909
910 return retval;
911}
912
913static struct hpc_ops shpchp_hpc_ops = {
914 .power_on_slot = hpc_power_on_slot,
915 .slot_enable = hpc_slot_enable,
916 .slot_disable = hpc_slot_disable,
917 .set_bus_speed_mode = hpc_set_bus_speed_mode,
918 .set_attention_status = hpc_set_attention_status,
919 .get_power_status = hpc_get_power_status,
920 .get_attention_status = hpc_get_attention_status,
921 .get_latch_status = hpc_get_latch_status,
922 .get_adapter_status = hpc_get_adapter_status,
923
924 .get_adapter_speed = hpc_get_adapter_speed,
925 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
926 .get_prog_int = hpc_get_prog_int,
927
928 .query_power_fault = hpc_query_power_fault,
929 .green_led_on = hpc_set_green_led_on,
930 .green_led_off = hpc_set_green_led_off,
931 .green_led_blink = hpc_set_green_led_blink,
932
933 .release_ctlr = hpc_release_ctlr,
934};
935
936int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
937{
938 int rc = -1, num_slots = 0;
939 u8 hp_slot;
940 u32 shpc_base_offset;
941 u32 tempdword, slot_reg, slot_config;
942 u8 i;
943
944 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
945 ctrl_dbg(ctrl, "Hotplug Controller:\n");
946
947 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
948 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
949 /* amd shpc driver doesn't use Base Offset; assume 0 */
950 ctrl->mmio_base = pci_resource_start(pdev, 0);
951 ctrl->mmio_size = pci_resource_len(pdev, 0);
952 } else {
953 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
954 if (!ctrl->cap_offset) {
955 ctrl_err(ctrl, "Cannot find PCI capability\n");
956 goto abort;
957 }
958 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
959
960 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
961 if (rc) {
962 ctrl_err(ctrl, "Cannot read base_offset\n");
963 goto abort;
964 }
965
966 rc = shpc_indirect_read(ctrl, 3, &tempdword);
967 if (rc) {
968 ctrl_err(ctrl, "Cannot read slot config\n");
969 goto abort;
970 }
971 num_slots = tempdword & SLOT_NUM;
972 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
973
974 for (i = 0; i < 9 + num_slots; i++) {
975 rc = shpc_indirect_read(ctrl, i, &tempdword);
976 if (rc) {
977 ctrl_err(ctrl,
978 "Cannot read creg (index = %d)\n", i);
979 goto abort;
980 }
981 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
982 }
983
984 ctrl->mmio_base =
985 pci_resource_start(pdev, 0) + shpc_base_offset;
986 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
987 }
988
989 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
990 pdev->vendor, pdev->device, pdev->subsystem_vendor,
991 pdev->subsystem_device);
992
993 rc = pci_enable_device(pdev);
994 if (rc) {
995 ctrl_err(ctrl, "pci_enable_device failed\n");
996 goto abort;
997 }
998
999 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1000 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
1001 rc = -1;
1002 goto abort;
1003 }
1004
1005 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1006 if (!ctrl->creg) {
1007 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
1008 ctrl->mmio_size, ctrl->mmio_base);
1009 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1010 rc = -1;
1011 goto abort;
1012 }
1013 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
1014
1015 mutex_init(&ctrl->crit_sect);
1016 mutex_init(&ctrl->cmd_lock);
1017
1018 /* Setup wait queue */
1019 init_waitqueue_head(&ctrl->queue);
1020
1021 ctrl->hpc_ops = &shpchp_hpc_ops;
1022
1023 /* Return PCI Controller Info */
1024 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1025 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1026 ctrl->num_slots = slot_config & SLOT_NUM;
1027 ctrl->first_slot = (slot_config & PSN) >> 16;
1028 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1029
1030 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1031 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1032 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1033 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1034 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1035 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1036 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1038 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1039
1040 /* Mask the MRL sensor SERR Mask of individual slot in
1041 * Slot SERR-INT Mask & clear all the existing event if any
1042 */
1043 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1044 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1045 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1046 hp_slot, slot_reg);
1047 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1048 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1049 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1050 CON_PFAULT_SERR_MASK);
1051 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1052 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1053 }
1054
1055 if (shpchp_poll_mode) {
1056 /* Install interrupt polling timer. Start with 10 sec delay */
1057 init_timer(&ctrl->poll_timer);
1058 start_int_poll_timer(ctrl, 10);
1059 } else {
1060 /* Installs the interrupt handler */
1061 rc = pci_enable_msi(pdev);
1062 if (rc) {
1063 ctrl_info(ctrl,
1064 "Can't get msi for the hotplug controller\n");
1065 ctrl_info(ctrl,
1066 "Use INTx for the hotplug controller\n");
1067 }
1068
1069 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1070 MY_NAME, (void *)ctrl);
1071 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1072 ctrl->pci_dev->irq, rc);
1073 if (rc) {
1074 ctrl_err(ctrl, "Can't get irq %d for the hotplug "
1075 "controller\n", ctrl->pci_dev->irq);
1076 goto abort_iounmap;
1077 }
1078 }
1079 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1080
1081 shpc_get_max_bus_speed(ctrl);
1082 shpc_get_cur_bus_speed(ctrl);
1083
1084 /*
1085 * Unmask all event interrupts of all slots
1086 */
1087 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1088 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1089 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1090 hp_slot, slot_reg);
1091 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1092 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1093 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1094 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1095 }
1096 if (!shpchp_poll_mode) {
1097 /* Unmask all general input interrupts and SERR */
1098 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1099 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1100 SERR_INTR_RSVDZ_MASK);
1101 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1102 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1103 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1104 }
1105
1106 return 0;
1107
1108 /* We end up here for the many possible ways to fail this API. */
1109abort_iounmap:
1110 iounmap(ctrl->creg);
1111abort:
1112 return rc;
1113}
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Standard PCI Hot Plug Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/types.h>
19#include <linux/pci.h>
20#include <linux/interrupt.h>
21
22#include "shpchp.h"
23
24/* Slot Available Register I field definition */
25#define SLOT_33MHZ 0x0000001f
26#define SLOT_66MHZ_PCIX 0x00001f00
27#define SLOT_100MHZ_PCIX 0x001f0000
28#define SLOT_133MHZ_PCIX 0x1f000000
29
30/* Slot Available Register II field definition */
31#define SLOT_66MHZ 0x0000001f
32#define SLOT_66MHZ_PCIX_266 0x00000f00
33#define SLOT_100MHZ_PCIX_266 0x0000f000
34#define SLOT_133MHZ_PCIX_266 0x000f0000
35#define SLOT_66MHZ_PCIX_533 0x00f00000
36#define SLOT_100MHZ_PCIX_533 0x0f000000
37#define SLOT_133MHZ_PCIX_533 0xf0000000
38
39/* Slot Configuration */
40#define SLOT_NUM 0x0000001F
41#define FIRST_DEV_NUM 0x00001F00
42#define PSN 0x07FF0000
43#define UPDOWN 0x20000000
44#define MRLSENSOR 0x40000000
45#define ATTN_BUTTON 0x80000000
46
47/*
48 * Interrupt Locator Register definitions
49 */
50#define CMD_INTR_PENDING (1 << 0)
51#define SLOT_INTR_PENDING(i) (1 << (i + 1))
52
53/*
54 * Controller SERR-INT Register
55 */
56#define GLOBAL_INTR_MASK (1 << 0)
57#define GLOBAL_SERR_MASK (1 << 1)
58#define COMMAND_INTR_MASK (1 << 2)
59#define ARBITER_SERR_MASK (1 << 3)
60#define COMMAND_DETECTED (1 << 16)
61#define ARBITER_DETECTED (1 << 17)
62#define SERR_INTR_RSVDZ_MASK 0xfffc0000
63
64/*
65 * Logical Slot Register definitions
66 */
67#define SLOT_REG(i) (SLOT1 + (4 * i))
68
69#define SLOT_STATE_SHIFT (0)
70#define SLOT_STATE_MASK (3 << 0)
71#define SLOT_STATE_PWRONLY (1)
72#define SLOT_STATE_ENABLED (2)
73#define SLOT_STATE_DISABLED (3)
74#define PWR_LED_STATE_SHIFT (2)
75#define PWR_LED_STATE_MASK (3 << 2)
76#define ATN_LED_STATE_SHIFT (4)
77#define ATN_LED_STATE_MASK (3 << 4)
78#define ATN_LED_STATE_ON (1)
79#define ATN_LED_STATE_BLINK (2)
80#define ATN_LED_STATE_OFF (3)
81#define POWER_FAULT (1 << 6)
82#define ATN_BUTTON (1 << 7)
83#define MRL_SENSOR (1 << 8)
84#define MHZ66_CAP (1 << 9)
85#define PRSNT_SHIFT (10)
86#define PRSNT_MASK (3 << 10)
87#define PCIX_CAP_SHIFT (12)
88#define PCIX_CAP_MASK_PI1 (3 << 12)
89#define PCIX_CAP_MASK_PI2 (7 << 12)
90#define PRSNT_CHANGE_DETECTED (1 << 16)
91#define ISO_PFAULT_DETECTED (1 << 17)
92#define BUTTON_PRESS_DETECTED (1 << 18)
93#define MRL_CHANGE_DETECTED (1 << 19)
94#define CON_PFAULT_DETECTED (1 << 20)
95#define PRSNT_CHANGE_INTR_MASK (1 << 24)
96#define ISO_PFAULT_INTR_MASK (1 << 25)
97#define BUTTON_PRESS_INTR_MASK (1 << 26)
98#define MRL_CHANGE_INTR_MASK (1 << 27)
99#define CON_PFAULT_INTR_MASK (1 << 28)
100#define MRL_CHANGE_SERR_MASK (1 << 29)
101#define CON_PFAULT_SERR_MASK (1 << 30)
102#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
103
104/*
105 * SHPC Command Code definitions
106 *
107 * Slot Operation 00h - 3Fh
108 * Set Bus Segment Speed/Mode A 40h - 47h
109 * Power-Only All Slots 48h
110 * Enable All Slots 49h
111 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
112 * Reserved Command Codes 60h - BFh
113 * Vendor Specific Commands C0h - FFh
114 */
115#define SET_SLOT_PWR 0x01 /* Slot Operation */
116#define SET_SLOT_ENABLE 0x02
117#define SET_SLOT_DISABLE 0x03
118#define SET_PWR_ON 0x04
119#define SET_PWR_BLINK 0x08
120#define SET_PWR_OFF 0x0c
121#define SET_ATTN_ON 0x10
122#define SET_ATTN_BLINK 0x20
123#define SET_ATTN_OFF 0x30
124#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
125#define SETA_PCI_66MHZ 0x41
126#define SETA_PCIX_66MHZ 0x42
127#define SETA_PCIX_100MHZ 0x43
128#define SETA_PCIX_133MHZ 0x44
129#define SETA_RESERVED1 0x45
130#define SETA_RESERVED2 0x46
131#define SETA_RESERVED3 0x47
132#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
133#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
134#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
135#define SETB_PCI_66MHZ 0x51
136#define SETB_PCIX_66MHZ_PM 0x52
137#define SETB_PCIX_100MHZ_PM 0x53
138#define SETB_PCIX_133MHZ_PM 0x54
139#define SETB_PCIX_66MHZ_EM 0x55
140#define SETB_PCIX_100MHZ_EM 0x56
141#define SETB_PCIX_133MHZ_EM 0x57
142#define SETB_PCIX_66MHZ_266 0x58
143#define SETB_PCIX_100MHZ_266 0x59
144#define SETB_PCIX_133MHZ_266 0x5a
145#define SETB_PCIX_66MHZ_533 0x5b
146#define SETB_PCIX_100MHZ_533 0x5c
147#define SETB_PCIX_133MHZ_533 0x5d
148#define SETB_RESERVED1 0x5e
149#define SETB_RESERVED2 0x5f
150
151/*
152 * SHPC controller command error code
153 */
154#define SWITCH_OPEN 0x1
155#define INVALID_CMD 0x2
156#define INVALID_SPEED_MODE 0x4
157
158/*
159 * For accessing SHPC Working Register Set via PCI Configuration Space
160 */
161#define DWORD_SELECT 0x2
162#define DWORD_DATA 0x4
163
164/* Field Offset in Logical Slot Register - byte boundary */
165#define SLOT_EVENT_LATCH 0x2
166#define SLOT_SERR_INT_MASK 0x3
167
168static irqreturn_t shpc_isr(int irq, void *dev_id);
169static void start_int_poll_timer(struct controller *ctrl, int sec);
170static int hpc_check_cmd_status(struct controller *ctrl);
171
172static inline u8 shpc_readb(struct controller *ctrl, int reg)
173{
174 return readb(ctrl->creg + reg);
175}
176
177static inline u16 shpc_readw(struct controller *ctrl, int reg)
178{
179 return readw(ctrl->creg + reg);
180}
181
182static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
183{
184 writew(val, ctrl->creg + reg);
185}
186
187static inline u32 shpc_readl(struct controller *ctrl, int reg)
188{
189 return readl(ctrl->creg + reg);
190}
191
192static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
193{
194 writel(val, ctrl->creg + reg);
195}
196
197static inline int shpc_indirect_read(struct controller *ctrl, int index,
198 u32 *value)
199{
200 int rc;
201 u32 cap_offset = ctrl->cap_offset;
202 struct pci_dev *pdev = ctrl->pci_dev;
203
204 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
205 if (rc)
206 return rc;
207 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
208}
209
210/*
211 * This is the interrupt polling timeout function.
212 */
213static void int_poll_timeout(struct timer_list *t)
214{
215 struct controller *ctrl = from_timer(ctrl, t, poll_timer);
216
217 /* Poll for interrupt events. regs == NULL => polling */
218 shpc_isr(0, ctrl);
219
220 if (!shpchp_poll_time)
221 shpchp_poll_time = 2; /* default polling interval is 2 sec */
222
223 start_int_poll_timer(ctrl, shpchp_poll_time);
224}
225
226/*
227 * This function starts the interrupt polling timer.
228 */
229static void start_int_poll_timer(struct controller *ctrl, int sec)
230{
231 /* Clamp to sane value */
232 if ((sec <= 0) || (sec > 60))
233 sec = 2;
234
235 ctrl->poll_timer.expires = jiffies + sec * HZ;
236 add_timer(&ctrl->poll_timer);
237}
238
239static inline int is_ctrl_busy(struct controller *ctrl)
240{
241 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
242 return cmd_status & 0x1;
243}
244
245/*
246 * Returns 1 if SHPC finishes executing a command within 1 sec,
247 * otherwise returns 0.
248 */
249static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
250{
251 int i;
252
253 if (!is_ctrl_busy(ctrl))
254 return 1;
255
256 /* Check every 0.1 sec for a total of 1 sec */
257 for (i = 0; i < 10; i++) {
258 msleep(100);
259 if (!is_ctrl_busy(ctrl))
260 return 1;
261 }
262
263 return 0;
264}
265
266static inline int shpc_wait_cmd(struct controller *ctrl)
267{
268 int retval = 0;
269 unsigned long timeout = msecs_to_jiffies(1000);
270 int rc;
271
272 if (shpchp_poll_mode)
273 rc = shpc_poll_ctrl_busy(ctrl);
274 else
275 rc = wait_event_interruptible_timeout(ctrl->queue,
276 !is_ctrl_busy(ctrl), timeout);
277 if (!rc && is_ctrl_busy(ctrl)) {
278 retval = -EIO;
279 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
280 } else if (rc < 0) {
281 retval = -EINTR;
282 ctrl_info(ctrl, "Command was interrupted by a signal\n");
283 }
284
285 return retval;
286}
287
288static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
289{
290 struct controller *ctrl = slot->ctrl;
291 u16 cmd_status;
292 int retval = 0;
293 u16 temp_word;
294
295 mutex_lock(&slot->ctrl->cmd_lock);
296
297 if (!shpc_poll_ctrl_busy(ctrl)) {
298 /* After 1 sec and and the controller is still busy */
299 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
300 retval = -EBUSY;
301 goto out;
302 }
303
304 ++t_slot;
305 temp_word = (t_slot << 8) | (cmd & 0xFF);
306 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
307
308 /* To make sure the Controller Busy bit is 0 before we send out the
309 * command.
310 */
311 shpc_writew(ctrl, CMD, temp_word);
312
313 /*
314 * Wait for command completion.
315 */
316 retval = shpc_wait_cmd(slot->ctrl);
317 if (retval)
318 goto out;
319
320 cmd_status = hpc_check_cmd_status(slot->ctrl);
321 if (cmd_status) {
322 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",
323 cmd, cmd_status);
324 retval = -EIO;
325 }
326 out:
327 mutex_unlock(&slot->ctrl->cmd_lock);
328 return retval;
329}
330
331static int hpc_check_cmd_status(struct controller *ctrl)
332{
333 int retval = 0;
334 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
335
336 switch (cmd_status >> 1) {
337 case 0:
338 retval = 0;
339 break;
340 case 1:
341 retval = SWITCH_OPEN;
342 ctrl_err(ctrl, "Switch opened!\n");
343 break;
344 case 2:
345 retval = INVALID_CMD;
346 ctrl_err(ctrl, "Invalid HPC command!\n");
347 break;
348 case 4:
349 retval = INVALID_SPEED_MODE;
350 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
351 break;
352 default:
353 retval = cmd_status;
354 }
355
356 return retval;
357}
358
359
360static int hpc_get_attention_status(struct slot *slot, u8 *status)
361{
362 struct controller *ctrl = slot->ctrl;
363 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
364 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
365
366 switch (state) {
367 case ATN_LED_STATE_ON:
368 *status = 1; /* On */
369 break;
370 case ATN_LED_STATE_BLINK:
371 *status = 2; /* Blink */
372 break;
373 case ATN_LED_STATE_OFF:
374 *status = 0; /* Off */
375 break;
376 default:
377 *status = 0xFF; /* Reserved */
378 break;
379 }
380
381 return 0;
382}
383
384static int hpc_get_power_status(struct slot *slot, u8 *status)
385{
386 struct controller *ctrl = slot->ctrl;
387 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
388 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
389
390 switch (state) {
391 case SLOT_STATE_PWRONLY:
392 *status = 2; /* Powered only */
393 break;
394 case SLOT_STATE_ENABLED:
395 *status = 1; /* Enabled */
396 break;
397 case SLOT_STATE_DISABLED:
398 *status = 0; /* Disabled */
399 break;
400 default:
401 *status = 0xFF; /* Reserved */
402 break;
403 }
404
405 return 0;
406}
407
408
409static int hpc_get_latch_status(struct slot *slot, u8 *status)
410{
411 struct controller *ctrl = slot->ctrl;
412 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
413
414 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
415
416 return 0;
417}
418
419static int hpc_get_adapter_status(struct slot *slot, u8 *status)
420{
421 struct controller *ctrl = slot->ctrl;
422 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
423 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
424
425 *status = (state != 0x3) ? 1 : 0;
426
427 return 0;
428}
429
430static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
431{
432 struct controller *ctrl = slot->ctrl;
433
434 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
435
436 return 0;
437}
438
439static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
440{
441 int retval = 0;
442 struct controller *ctrl = slot->ctrl;
443 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
444 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
445 u8 pi, pcix_cap;
446
447 retval = hpc_get_prog_int(slot, &pi);
448 if (retval)
449 return retval;
450
451 switch (pi) {
452 case 1:
453 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
454 break;
455 case 2:
456 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
457 break;
458 default:
459 return -ENODEV;
460 }
461
462 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
463 __func__, slot_reg, pcix_cap, m66_cap);
464
465 switch (pcix_cap) {
466 case 0x0:
467 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
468 break;
469 case 0x1:
470 *value = PCI_SPEED_66MHz_PCIX;
471 break;
472 case 0x3:
473 *value = PCI_SPEED_133MHz_PCIX;
474 break;
475 case 0x4:
476 *value = PCI_SPEED_133MHz_PCIX_266;
477 break;
478 case 0x5:
479 *value = PCI_SPEED_133MHz_PCIX_533;
480 break;
481 case 0x2:
482 default:
483 *value = PCI_SPEED_UNKNOWN;
484 retval = -ENODEV;
485 break;
486 }
487
488 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
489 return retval;
490}
491
492static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
493{
494 int retval = 0;
495 struct controller *ctrl = slot->ctrl;
496 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
497 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
498
499 if (pi == 2) {
500 *mode = (sec_bus_status & 0x0100) >> 8;
501 } else {
502 retval = -1;
503 }
504
505 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
506 return retval;
507}
508
509static int hpc_query_power_fault(struct slot *slot)
510{
511 struct controller *ctrl = slot->ctrl;
512 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
513
514 /* Note: Logic 0 => fault */
515 return !(slot_reg & POWER_FAULT);
516}
517
518static int hpc_set_attention_status(struct slot *slot, u8 value)
519{
520 u8 slot_cmd = 0;
521
522 switch (value) {
523 case 0:
524 slot_cmd = SET_ATTN_OFF; /* OFF */
525 break;
526 case 1:
527 slot_cmd = SET_ATTN_ON; /* ON */
528 break;
529 case 2:
530 slot_cmd = SET_ATTN_BLINK; /* BLINK */
531 break;
532 default:
533 return -1;
534 }
535
536 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
537}
538
539
540static void hpc_set_green_led_on(struct slot *slot)
541{
542 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
543}
544
545static void hpc_set_green_led_off(struct slot *slot)
546{
547 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
548}
549
550static void hpc_set_green_led_blink(struct slot *slot)
551{
552 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
553}
554
555static void hpc_release_ctlr(struct controller *ctrl)
556{
557 int i;
558 u32 slot_reg, serr_int;
559
560 /*
561 * Mask event interrupts and SERRs of all slots
562 */
563 for (i = 0; i < ctrl->num_slots; i++) {
564 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
565 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
566 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
567 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
568 CON_PFAULT_SERR_MASK);
569 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
570 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
571 }
572
573 cleanup_slots(ctrl);
574
575 /*
576 * Mask SERR and System Interrupt generation
577 */
578 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
579 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
580 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
581 serr_int &= ~SERR_INTR_RSVDZ_MASK;
582 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
583
584 if (shpchp_poll_mode)
585 del_timer(&ctrl->poll_timer);
586 else {
587 free_irq(ctrl->pci_dev->irq, ctrl);
588 pci_disable_msi(ctrl->pci_dev);
589 }
590
591 iounmap(ctrl->creg);
592 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
593}
594
595static int hpc_power_on_slot(struct slot *slot)
596{
597 int retval;
598
599 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
600 if (retval)
601 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
602
603 return retval;
604}
605
606static int hpc_slot_enable(struct slot *slot)
607{
608 int retval;
609
610 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
611 retval = shpc_write_cmd(slot, slot->hp_slot,
612 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
613 if (retval)
614 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
615
616 return retval;
617}
618
619static int hpc_slot_disable(struct slot *slot)
620{
621 int retval;
622
623 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
624 retval = shpc_write_cmd(slot, slot->hp_slot,
625 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
626 if (retval)
627 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
628
629 return retval;
630}
631
632static int shpc_get_cur_bus_speed(struct controller *ctrl)
633{
634 int retval = 0;
635 struct pci_bus *bus = ctrl->pci_dev->subordinate;
636 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
637 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
638 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
639 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
640
641 if ((pi == 1) && (speed_mode > 4)) {
642 retval = -ENODEV;
643 goto out;
644 }
645
646 switch (speed_mode) {
647 case 0x0:
648 bus_speed = PCI_SPEED_33MHz;
649 break;
650 case 0x1:
651 bus_speed = PCI_SPEED_66MHz;
652 break;
653 case 0x2:
654 bus_speed = PCI_SPEED_66MHz_PCIX;
655 break;
656 case 0x3:
657 bus_speed = PCI_SPEED_100MHz_PCIX;
658 break;
659 case 0x4:
660 bus_speed = PCI_SPEED_133MHz_PCIX;
661 break;
662 case 0x5:
663 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
664 break;
665 case 0x6:
666 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
667 break;
668 case 0x7:
669 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
670 break;
671 case 0x8:
672 bus_speed = PCI_SPEED_66MHz_PCIX_266;
673 break;
674 case 0x9:
675 bus_speed = PCI_SPEED_100MHz_PCIX_266;
676 break;
677 case 0xa:
678 bus_speed = PCI_SPEED_133MHz_PCIX_266;
679 break;
680 case 0xb:
681 bus_speed = PCI_SPEED_66MHz_PCIX_533;
682 break;
683 case 0xc:
684 bus_speed = PCI_SPEED_100MHz_PCIX_533;
685 break;
686 case 0xd:
687 bus_speed = PCI_SPEED_133MHz_PCIX_533;
688 break;
689 default:
690 retval = -ENODEV;
691 break;
692 }
693
694 out:
695 bus->cur_bus_speed = bus_speed;
696 dbg("Current bus speed = %d\n", bus_speed);
697 return retval;
698}
699
700
701static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value)
702{
703 int retval;
704 struct controller *ctrl = slot->ctrl;
705 u8 pi, cmd;
706
707 pi = shpc_readb(ctrl, PROG_INTERFACE);
708 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
709 return -EINVAL;
710
711 switch (value) {
712 case PCI_SPEED_33MHz:
713 cmd = SETA_PCI_33MHZ;
714 break;
715 case PCI_SPEED_66MHz:
716 cmd = SETA_PCI_66MHZ;
717 break;
718 case PCI_SPEED_66MHz_PCIX:
719 cmd = SETA_PCIX_66MHZ;
720 break;
721 case PCI_SPEED_100MHz_PCIX:
722 cmd = SETA_PCIX_100MHZ;
723 break;
724 case PCI_SPEED_133MHz_PCIX:
725 cmd = SETA_PCIX_133MHZ;
726 break;
727 case PCI_SPEED_66MHz_PCIX_ECC:
728 cmd = SETB_PCIX_66MHZ_EM;
729 break;
730 case PCI_SPEED_100MHz_PCIX_ECC:
731 cmd = SETB_PCIX_100MHZ_EM;
732 break;
733 case PCI_SPEED_133MHz_PCIX_ECC:
734 cmd = SETB_PCIX_133MHZ_EM;
735 break;
736 case PCI_SPEED_66MHz_PCIX_266:
737 cmd = SETB_PCIX_66MHZ_266;
738 break;
739 case PCI_SPEED_100MHz_PCIX_266:
740 cmd = SETB_PCIX_100MHZ_266;
741 break;
742 case PCI_SPEED_133MHz_PCIX_266:
743 cmd = SETB_PCIX_133MHZ_266;
744 break;
745 case PCI_SPEED_66MHz_PCIX_533:
746 cmd = SETB_PCIX_66MHZ_533;
747 break;
748 case PCI_SPEED_100MHz_PCIX_533:
749 cmd = SETB_PCIX_100MHZ_533;
750 break;
751 case PCI_SPEED_133MHz_PCIX_533:
752 cmd = SETB_PCIX_133MHZ_533;
753 break;
754 default:
755 return -EINVAL;
756 }
757
758 retval = shpc_write_cmd(slot, 0, cmd);
759 if (retval)
760 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
761 else
762 shpc_get_cur_bus_speed(ctrl);
763
764 return retval;
765}
766
767static irqreturn_t shpc_isr(int irq, void *dev_id)
768{
769 struct controller *ctrl = (struct controller *)dev_id;
770 u32 serr_int, slot_reg, intr_loc, intr_loc2;
771 int hp_slot;
772
773 /* Check to see if it was our interrupt */
774 intr_loc = shpc_readl(ctrl, INTR_LOC);
775 if (!intr_loc)
776 return IRQ_NONE;
777
778 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
779
780 if (!shpchp_poll_mode) {
781 /*
782 * Mask Global Interrupt Mask - see implementation
783 * note on p. 139 of SHPC spec rev 1.0
784 */
785 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
786 serr_int |= GLOBAL_INTR_MASK;
787 serr_int &= ~SERR_INTR_RSVDZ_MASK;
788 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
789
790 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
791 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
792 }
793
794 if (intr_loc & CMD_INTR_PENDING) {
795 /*
796 * Command Complete Interrupt Pending
797 * RO only - clear by writing 1 to the Command Completion
798 * Detect bit in Controller SERR-INT register
799 */
800 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
801 serr_int &= ~SERR_INTR_RSVDZ_MASK;
802 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
803
804 wake_up_interruptible(&ctrl->queue);
805 }
806
807 if (!(intr_loc & ~CMD_INTR_PENDING))
808 goto out;
809
810 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
811 /* To find out which slot has interrupt pending */
812 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
813 continue;
814
815 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
816 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
817 hp_slot, slot_reg);
818
819 if (slot_reg & MRL_CHANGE_DETECTED)
820 shpchp_handle_switch_change(hp_slot, ctrl);
821
822 if (slot_reg & BUTTON_PRESS_DETECTED)
823 shpchp_handle_attention_button(hp_slot, ctrl);
824
825 if (slot_reg & PRSNT_CHANGE_DETECTED)
826 shpchp_handle_presence_change(hp_slot, ctrl);
827
828 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
829 shpchp_handle_power_fault(hp_slot, ctrl);
830
831 /* Clear all slot events */
832 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
833 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
834 }
835 out:
836 if (!shpchp_poll_mode) {
837 /* Unmask Global Interrupt Mask */
838 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
839 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
840 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
841 }
842
843 return IRQ_HANDLED;
844}
845
846static int shpc_get_max_bus_speed(struct controller *ctrl)
847{
848 int retval = 0;
849 struct pci_bus *bus = ctrl->pci_dev->subordinate;
850 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
851 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
852 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
853 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
854
855 if (pi == 2) {
856 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
857 bus_speed = PCI_SPEED_133MHz_PCIX_533;
858 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
859 bus_speed = PCI_SPEED_100MHz_PCIX_533;
860 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
861 bus_speed = PCI_SPEED_66MHz_PCIX_533;
862 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
863 bus_speed = PCI_SPEED_133MHz_PCIX_266;
864 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
865 bus_speed = PCI_SPEED_100MHz_PCIX_266;
866 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
867 bus_speed = PCI_SPEED_66MHz_PCIX_266;
868 }
869
870 if (bus_speed == PCI_SPEED_UNKNOWN) {
871 if (slot_avail1 & SLOT_133MHZ_PCIX)
872 bus_speed = PCI_SPEED_133MHz_PCIX;
873 else if (slot_avail1 & SLOT_100MHZ_PCIX)
874 bus_speed = PCI_SPEED_100MHz_PCIX;
875 else if (slot_avail1 & SLOT_66MHZ_PCIX)
876 bus_speed = PCI_SPEED_66MHz_PCIX;
877 else if (slot_avail2 & SLOT_66MHZ)
878 bus_speed = PCI_SPEED_66MHz;
879 else if (slot_avail1 & SLOT_33MHZ)
880 bus_speed = PCI_SPEED_33MHz;
881 else
882 retval = -ENODEV;
883 }
884
885 bus->max_bus_speed = bus_speed;
886 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
887
888 return retval;
889}
890
891static const struct hpc_ops shpchp_hpc_ops = {
892 .power_on_slot = hpc_power_on_slot,
893 .slot_enable = hpc_slot_enable,
894 .slot_disable = hpc_slot_disable,
895 .set_bus_speed_mode = hpc_set_bus_speed_mode,
896 .set_attention_status = hpc_set_attention_status,
897 .get_power_status = hpc_get_power_status,
898 .get_attention_status = hpc_get_attention_status,
899 .get_latch_status = hpc_get_latch_status,
900 .get_adapter_status = hpc_get_adapter_status,
901
902 .get_adapter_speed = hpc_get_adapter_speed,
903 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
904 .get_prog_int = hpc_get_prog_int,
905
906 .query_power_fault = hpc_query_power_fault,
907 .green_led_on = hpc_set_green_led_on,
908 .green_led_off = hpc_set_green_led_off,
909 .green_led_blink = hpc_set_green_led_blink,
910
911 .release_ctlr = hpc_release_ctlr,
912};
913
914int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
915{
916 int rc = -1, num_slots = 0;
917 u8 hp_slot;
918 u32 shpc_base_offset;
919 u32 tempdword, slot_reg, slot_config;
920 u8 i;
921
922 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
923 ctrl_dbg(ctrl, "Hotplug Controller:\n");
924
925 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
926 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) {
927 /* amd shpc driver doesn't use Base Offset; assume 0 */
928 ctrl->mmio_base = pci_resource_start(pdev, 0);
929 ctrl->mmio_size = pci_resource_len(pdev, 0);
930 } else {
931 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
932 if (!ctrl->cap_offset) {
933 ctrl_err(ctrl, "Cannot find PCI capability\n");
934 goto abort;
935 }
936 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
937
938 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
939 if (rc) {
940 ctrl_err(ctrl, "Cannot read base_offset\n");
941 goto abort;
942 }
943
944 rc = shpc_indirect_read(ctrl, 3, &tempdword);
945 if (rc) {
946 ctrl_err(ctrl, "Cannot read slot config\n");
947 goto abort;
948 }
949 num_slots = tempdword & SLOT_NUM;
950 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
951
952 for (i = 0; i < 9 + num_slots; i++) {
953 rc = shpc_indirect_read(ctrl, i, &tempdword);
954 if (rc) {
955 ctrl_err(ctrl, "Cannot read creg (index = %d)\n",
956 i);
957 goto abort;
958 }
959 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
960 }
961
962 ctrl->mmio_base =
963 pci_resource_start(pdev, 0) + shpc_base_offset;
964 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
965 }
966
967 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
968 pdev->vendor, pdev->device, pdev->subsystem_vendor,
969 pdev->subsystem_device);
970
971 rc = pci_enable_device(pdev);
972 if (rc) {
973 ctrl_err(ctrl, "pci_enable_device failed\n");
974 goto abort;
975 }
976
977 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
978 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
979 rc = -1;
980 goto abort;
981 }
982
983 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
984 if (!ctrl->creg) {
985 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
986 ctrl->mmio_size, ctrl->mmio_base);
987 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
988 rc = -1;
989 goto abort;
990 }
991 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
992
993 mutex_init(&ctrl->crit_sect);
994 mutex_init(&ctrl->cmd_lock);
995
996 /* Setup wait queue */
997 init_waitqueue_head(&ctrl->queue);
998
999 ctrl->hpc_ops = &shpchp_hpc_ops;
1000
1001 /* Return PCI Controller Info */
1002 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1003 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1004 ctrl->num_slots = slot_config & SLOT_NUM;
1005 ctrl->first_slot = (slot_config & PSN) >> 16;
1006 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1007
1008 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1009 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1010 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1011 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1012 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1013 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1014 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1015 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1016 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1017
1018 /* Mask the MRL sensor SERR Mask of individual slot in
1019 * Slot SERR-INT Mask & clear all the existing event if any
1020 */
1021 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1022 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1023 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1024 hp_slot, slot_reg);
1025 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1026 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1027 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1028 CON_PFAULT_SERR_MASK);
1029 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1030 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1031 }
1032
1033 if (shpchp_poll_mode) {
1034 /* Install interrupt polling timer. Start with 10 sec delay */
1035 timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
1036 start_int_poll_timer(ctrl, 10);
1037 } else {
1038 /* Installs the interrupt handler */
1039 rc = pci_enable_msi(pdev);
1040 if (rc) {
1041 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");
1042 ctrl_info(ctrl, "Use INTx for the hotplug controller\n");
1043 } else {
1044 pci_set_master(pdev);
1045 }
1046
1047 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1048 MY_NAME, (void *)ctrl);
1049 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1050 ctrl->pci_dev->irq, rc);
1051 if (rc) {
1052 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",
1053 ctrl->pci_dev->irq);
1054 goto abort_iounmap;
1055 }
1056 }
1057 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1058
1059 shpc_get_max_bus_speed(ctrl);
1060 shpc_get_cur_bus_speed(ctrl);
1061
1062 /*
1063 * Unmask all event interrupts of all slots
1064 */
1065 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1066 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1067 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1068 hp_slot, slot_reg);
1069 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1070 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1071 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1072 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1073 }
1074 if (!shpchp_poll_mode) {
1075 /* Unmask all general input interrupts and SERR */
1076 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1077 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1078 SERR_INTR_RSVDZ_MASK);
1079 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1080 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1081 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1082 }
1083
1084 return 0;
1085
1086 /* We end up here for the many possible ways to fail this API. */
1087abort_iounmap:
1088 iounmap(ctrl->creg);
1089abort:
1090 return rc;
1091}