Loading...
Note: File does not exist in v3.1.
1/*
2 * Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
3 *
4 * Copyright 2004 IDT Inc. (rischelp@idt.com)
5 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright 2008 Florian Fainelli <florian@openwrt.org>
7 * Copyright 2017 Roman Yeryomin <roman@advem.lv>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Writing to a DMA status register:
30 *
31 * When writing to the status register, you should mask the bit you have
32 * been testing the status register with. Both Tx and Rx DMA registers
33 * should stick to this procedure.
34 */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/moduleparam.h>
39#include <linux/sched.h>
40#include <linux/ctype.h>
41#include <linux/types.h>
42#include <linux/interrupt.h>
43#include <linux/ioport.h>
44#include <linux/iopoll.h>
45#include <linux/in.h>
46#include <linux/of_device.h>
47#include <linux/of_net.h>
48#include <linux/slab.h>
49#include <linux/string.h>
50#include <linux/delay.h>
51#include <linux/netdevice.h>
52#include <linux/etherdevice.h>
53#include <linux/skbuff.h>
54#include <linux/errno.h>
55#include <linux/platform_device.h>
56#include <linux/mii.h>
57#include <linux/ethtool.h>
58#include <linux/crc32.h>
59#include <linux/pgtable.h>
60#include <linux/clk.h>
61
62#define DRV_NAME "korina"
63#define DRV_VERSION "0.20"
64#define DRV_RELDATE "15Sep2017"
65
66struct eth_regs {
67 u32 ethintfc;
68 u32 ethfifott;
69 u32 etharc;
70 u32 ethhash0;
71 u32 ethhash1;
72 u32 ethu0[4]; /* Reserved. */
73 u32 ethpfs;
74 u32 ethmcp;
75 u32 eth_u1[10]; /* Reserved. */
76 u32 ethspare;
77 u32 eth_u2[42]; /* Reserved. */
78 u32 ethsal0;
79 u32 ethsah0;
80 u32 ethsal1;
81 u32 ethsah1;
82 u32 ethsal2;
83 u32 ethsah2;
84 u32 ethsal3;
85 u32 ethsah3;
86 u32 ethrbc;
87 u32 ethrpc;
88 u32 ethrupc;
89 u32 ethrfc;
90 u32 ethtbc;
91 u32 ethgpf;
92 u32 eth_u9[50]; /* Reserved. */
93 u32 ethmac1;
94 u32 ethmac2;
95 u32 ethipgt;
96 u32 ethipgr;
97 u32 ethclrt;
98 u32 ethmaxf;
99 u32 eth_u10; /* Reserved. */
100 u32 ethmtest;
101 u32 miimcfg;
102 u32 miimcmd;
103 u32 miimaddr;
104 u32 miimwtd;
105 u32 miimrdd;
106 u32 miimind;
107 u32 eth_u11; /* Reserved. */
108 u32 eth_u12; /* Reserved. */
109 u32 ethcfsa0;
110 u32 ethcfsa1;
111 u32 ethcfsa2;
112};
113
114/* Ethernet interrupt registers */
115#define ETH_INT_FC_EN BIT(0)
116#define ETH_INT_FC_ITS BIT(1)
117#define ETH_INT_FC_RIP BIT(2)
118#define ETH_INT_FC_JAM BIT(3)
119#define ETH_INT_FC_OVR BIT(4)
120#define ETH_INT_FC_UND BIT(5)
121#define ETH_INT_FC_IOC 0x000000c0
122
123/* Ethernet FIFO registers */
124#define ETH_FIFI_TT_TTH_BIT 0
125#define ETH_FIFO_TT_TTH 0x0000007f
126
127/* Ethernet ARC/multicast registers */
128#define ETH_ARC_PRO BIT(0)
129#define ETH_ARC_AM BIT(1)
130#define ETH_ARC_AFM BIT(2)
131#define ETH_ARC_AB BIT(3)
132
133/* Ethernet SAL registers */
134#define ETH_SAL_BYTE_5 0x000000ff
135#define ETH_SAL_BYTE_4 0x0000ff00
136#define ETH_SAL_BYTE_3 0x00ff0000
137#define ETH_SAL_BYTE_2 0xff000000
138
139/* Ethernet SAH registers */
140#define ETH_SAH_BYTE1 0x000000ff
141#define ETH_SAH_BYTE0 0x0000ff00
142
143/* Ethernet GPF register */
144#define ETH_GPF_PTV 0x0000ffff
145
146/* Ethernet PFG register */
147#define ETH_PFS_PFD BIT(0)
148
149/* Ethernet CFSA[0-3] registers */
150#define ETH_CFSA0_CFSA4 0x000000ff
151#define ETH_CFSA0_CFSA5 0x0000ff00
152#define ETH_CFSA1_CFSA2 0x000000ff
153#define ETH_CFSA1_CFSA3 0x0000ff00
154#define ETH_CFSA1_CFSA0 0x000000ff
155#define ETH_CFSA1_CFSA1 0x0000ff00
156
157/* Ethernet MAC1 registers */
158#define ETH_MAC1_RE BIT(0)
159#define ETH_MAC1_PAF BIT(1)
160#define ETH_MAC1_RFC BIT(2)
161#define ETH_MAC1_TFC BIT(3)
162#define ETH_MAC1_LB BIT(4)
163#define ETH_MAC1_MR BIT(31)
164
165/* Ethernet MAC2 registers */
166#define ETH_MAC2_FD BIT(0)
167#define ETH_MAC2_FLC BIT(1)
168#define ETH_MAC2_HFE BIT(2)
169#define ETH_MAC2_DC BIT(3)
170#define ETH_MAC2_CEN BIT(4)
171#define ETH_MAC2_PE BIT(5)
172#define ETH_MAC2_VPE BIT(6)
173#define ETH_MAC2_APE BIT(7)
174#define ETH_MAC2_PPE BIT(8)
175#define ETH_MAC2_LPE BIT(9)
176#define ETH_MAC2_NB BIT(12)
177#define ETH_MAC2_BP BIT(13)
178#define ETH_MAC2_ED BIT(14)
179
180/* Ethernet IPGT register */
181#define ETH_IPGT 0x0000007f
182
183/* Ethernet IPGR registers */
184#define ETH_IPGR_IPGR2 0x0000007f
185#define ETH_IPGR_IPGR1 0x00007f00
186
187/* Ethernet CLRT registers */
188#define ETH_CLRT_MAX_RET 0x0000000f
189#define ETH_CLRT_COL_WIN 0x00003f00
190
191/* Ethernet MAXF register */
192#define ETH_MAXF 0x0000ffff
193
194/* Ethernet test registers */
195#define ETH_TEST_REG BIT(2)
196#define ETH_MCP_DIV 0x000000ff
197
198/* MII registers */
199#define ETH_MII_CFG_RSVD 0x0000000c
200#define ETH_MII_CMD_RD BIT(0)
201#define ETH_MII_CMD_SCN BIT(1)
202#define ETH_MII_REG_ADDR 0x0000001f
203#define ETH_MII_PHY_ADDR 0x00001f00
204#define ETH_MII_WTD_DATA 0x0000ffff
205#define ETH_MII_RDD_DATA 0x0000ffff
206#define ETH_MII_IND_BSY BIT(0)
207#define ETH_MII_IND_SCN BIT(1)
208#define ETH_MII_IND_NV BIT(2)
209
210/* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors. */
211#define ETH_RX_FD BIT(0)
212#define ETH_RX_LD BIT(1)
213#define ETH_RX_ROK BIT(2)
214#define ETH_RX_FM BIT(3)
215#define ETH_RX_MP BIT(4)
216#define ETH_RX_BP BIT(5)
217#define ETH_RX_VLT BIT(6)
218#define ETH_RX_CF BIT(7)
219#define ETH_RX_OVR BIT(8)
220#define ETH_RX_CRC BIT(9)
221#define ETH_RX_CV BIT(10)
222#define ETH_RX_DB BIT(11)
223#define ETH_RX_LE BIT(12)
224#define ETH_RX_LOR BIT(13)
225#define ETH_RX_CES BIT(14)
226#define ETH_RX_LEN_BIT 16
227#define ETH_RX_LEN 0xffff0000
228
229#define ETH_TX_FD BIT(0)
230#define ETH_TX_LD BIT(1)
231#define ETH_TX_OEN BIT(2)
232#define ETH_TX_PEN BIT(3)
233#define ETH_TX_CEN BIT(4)
234#define ETH_TX_HEN BIT(5)
235#define ETH_TX_TOK BIT(6)
236#define ETH_TX_MP BIT(7)
237#define ETH_TX_BP BIT(8)
238#define ETH_TX_UND BIT(9)
239#define ETH_TX_OF BIT(10)
240#define ETH_TX_ED BIT(11)
241#define ETH_TX_EC BIT(12)
242#define ETH_TX_LC BIT(13)
243#define ETH_TX_TD BIT(14)
244#define ETH_TX_CRC BIT(15)
245#define ETH_TX_LE BIT(16)
246#define ETH_TX_CC 0x001E0000
247
248/* DMA descriptor (in physical memory). */
249struct dma_desc {
250 u32 control; /* Control. use DMAD_* */
251 u32 ca; /* Current Address. */
252 u32 devcs; /* Device control and status. */
253 u32 link; /* Next descriptor in chain. */
254};
255
256#define DMA_DESC_COUNT_BIT 0
257#define DMA_DESC_COUNT_MSK 0x0003ffff
258#define DMA_DESC_DS_BIT 20
259#define DMA_DESC_DS_MSK 0x00300000
260
261#define DMA_DESC_DEV_CMD_BIT 22
262#define DMA_DESC_DEV_CMD_MSK 0x01c00000
263
264/* DMA descriptors interrupts */
265#define DMA_DESC_COF BIT(25) /* Chain on finished */
266#define DMA_DESC_COD BIT(26) /* Chain on done */
267#define DMA_DESC_IOF BIT(27) /* Interrupt on finished */
268#define DMA_DESC_IOD BIT(28) /* Interrupt on done */
269#define DMA_DESC_TERM BIT(29) /* Terminated */
270#define DMA_DESC_DONE BIT(30) /* Done */
271#define DMA_DESC_FINI BIT(31) /* Finished */
272
273/* DMA register (within Internal Register Map). */
274struct dma_reg {
275 u32 dmac; /* Control. */
276 u32 dmas; /* Status. */
277 u32 dmasm; /* Mask. */
278 u32 dmadptr; /* Descriptor pointer. */
279 u32 dmandptr; /* Next descriptor pointer. */
280};
281
282/* DMA channels specific registers */
283#define DMA_CHAN_RUN_BIT BIT(0)
284#define DMA_CHAN_DONE_BIT BIT(1)
285#define DMA_CHAN_MODE_BIT BIT(2)
286#define DMA_CHAN_MODE_MSK 0x0000000c
287#define DMA_CHAN_MODE_AUTO 0
288#define DMA_CHAN_MODE_BURST 1
289#define DMA_CHAN_MODE_XFRT 2
290#define DMA_CHAN_MODE_RSVD 3
291#define DMA_CHAN_ACT_BIT BIT(4)
292
293/* DMA status registers */
294#define DMA_STAT_FINI BIT(0)
295#define DMA_STAT_DONE BIT(1)
296#define DMA_STAT_CHAIN BIT(2)
297#define DMA_STAT_ERR BIT(3)
298#define DMA_STAT_HALT BIT(4)
299
300#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
301 ((dev)->dev_addr[1]))
302#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
303 ((dev)->dev_addr[3] << 16) | \
304 ((dev)->dev_addr[4] << 8) | \
305 ((dev)->dev_addr[5]))
306
307#define MII_CLOCK 1250000 /* no more than 2.5MHz */
308
309/* the following must be powers of two */
310#define KORINA_NUM_RDS 64 /* number of receive descriptors */
311#define KORINA_NUM_TDS 64 /* number of transmit descriptors */
312
313/* KORINA_RBSIZE is the hardware's default maximum receive
314 * frame size in bytes. Having this hardcoded means that there
315 * is no support for MTU sizes greater than 1500. */
316#define KORINA_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
317#define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
318#define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
319#define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc))
320#define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc))
321
322#define TX_TIMEOUT (6000 * HZ / 1000)
323
324enum chain_status {
325 desc_filled,
326 desc_is_empty
327};
328
329#define DMA_COUNT(count) ((count) & DMA_DESC_COUNT_MSK)
330#define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0)
331#define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0)
332#define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
333
334/* Information that need to be kept for each board. */
335struct korina_private {
336 struct eth_regs __iomem *eth_regs;
337 struct dma_reg __iomem *rx_dma_regs;
338 struct dma_reg __iomem *tx_dma_regs;
339 struct dma_desc *td_ring; /* transmit descriptor ring */
340 struct dma_desc *rd_ring; /* receive descriptor ring */
341 dma_addr_t td_dma;
342 dma_addr_t rd_dma;
343
344 struct sk_buff *tx_skb[KORINA_NUM_TDS];
345 struct sk_buff *rx_skb[KORINA_NUM_RDS];
346
347 dma_addr_t rx_skb_dma[KORINA_NUM_RDS];
348 dma_addr_t tx_skb_dma[KORINA_NUM_TDS];
349
350 int rx_next_done;
351 int rx_chain_head;
352 int rx_chain_tail;
353 enum chain_status rx_chain_status;
354
355 int tx_next_done;
356 int tx_chain_head;
357 int tx_chain_tail;
358 enum chain_status tx_chain_status;
359 int tx_count;
360 int tx_full;
361
362 int rx_irq;
363 int tx_irq;
364
365 spinlock_t lock; /* NIC xmit lock */
366
367 int dma_halt_cnt;
368 int dma_run_cnt;
369 struct napi_struct napi;
370 struct timer_list media_check_timer;
371 struct mii_if_info mii_if;
372 struct work_struct restart_task;
373 struct net_device *dev;
374 struct device *dmadev;
375 int mii_clock_freq;
376};
377
378static dma_addr_t korina_tx_dma(struct korina_private *lp, int idx)
379{
380 return lp->td_dma + (idx * sizeof(struct dma_desc));
381}
382
383static dma_addr_t korina_rx_dma(struct korina_private *lp, int idx)
384{
385 return lp->rd_dma + (idx * sizeof(struct dma_desc));
386}
387
388static inline void korina_abort_dma(struct net_device *dev,
389 struct dma_reg *ch)
390{
391 if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
392 writel(0x10, &ch->dmac);
393
394 while (!(readl(&ch->dmas) & DMA_STAT_HALT))
395 netif_trans_update(dev);
396
397 writel(0, &ch->dmas);
398 }
399
400 writel(0, &ch->dmadptr);
401 writel(0, &ch->dmandptr);
402}
403
404static void korina_abort_tx(struct net_device *dev)
405{
406 struct korina_private *lp = netdev_priv(dev);
407
408 korina_abort_dma(dev, lp->tx_dma_regs);
409}
410
411static void korina_abort_rx(struct net_device *dev)
412{
413 struct korina_private *lp = netdev_priv(dev);
414
415 korina_abort_dma(dev, lp->rx_dma_regs);
416}
417
418/* transmit packet */
419static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
420{
421 struct korina_private *lp = netdev_priv(dev);
422 u32 chain_prev, chain_next;
423 unsigned long flags;
424 struct dma_desc *td;
425 dma_addr_t ca;
426 u32 length;
427 int idx;
428
429 spin_lock_irqsave(&lp->lock, flags);
430
431 idx = lp->tx_chain_tail;
432 td = &lp->td_ring[idx];
433
434 /* stop queue when full, drop pkts if queue already full */
435 if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
436 lp->tx_full = 1;
437
438 if (lp->tx_count == (KORINA_NUM_TDS - 2))
439 netif_stop_queue(dev);
440 else
441 goto drop_packet;
442 }
443
444 lp->tx_count++;
445
446 lp->tx_skb[idx] = skb;
447
448 length = skb->len;
449
450 /* Setup the transmit descriptor. */
451 ca = dma_map_single(lp->dmadev, skb->data, length, DMA_TO_DEVICE);
452 if (dma_mapping_error(lp->dmadev, ca))
453 goto drop_packet;
454
455 lp->tx_skb_dma[idx] = ca;
456 td->ca = ca;
457
458 chain_prev = (idx - 1) & KORINA_TDS_MASK;
459 chain_next = (idx + 1) & KORINA_TDS_MASK;
460
461 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
462 if (lp->tx_chain_status == desc_is_empty) {
463 /* Update tail */
464 td->control = DMA_COUNT(length) |
465 DMA_DESC_COF | DMA_DESC_IOF;
466 /* Move tail */
467 lp->tx_chain_tail = chain_next;
468 /* Write to NDPTR */
469 writel(korina_tx_dma(lp, lp->tx_chain_head),
470 &lp->tx_dma_regs->dmandptr);
471 /* Move head to tail */
472 lp->tx_chain_head = lp->tx_chain_tail;
473 } else {
474 /* Update tail */
475 td->control = DMA_COUNT(length) |
476 DMA_DESC_COF | DMA_DESC_IOF;
477 /* Link to prev */
478 lp->td_ring[chain_prev].control &=
479 ~DMA_DESC_COF;
480 /* Link to prev */
481 lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
482 /* Move tail */
483 lp->tx_chain_tail = chain_next;
484 /* Write to NDPTR */
485 writel(korina_tx_dma(lp, lp->tx_chain_head),
486 &lp->tx_dma_regs->dmandptr);
487 /* Move head to tail */
488 lp->tx_chain_head = lp->tx_chain_tail;
489 lp->tx_chain_status = desc_is_empty;
490 }
491 } else {
492 if (lp->tx_chain_status == desc_is_empty) {
493 /* Update tail */
494 td->control = DMA_COUNT(length) |
495 DMA_DESC_COF | DMA_DESC_IOF;
496 /* Move tail */
497 lp->tx_chain_tail = chain_next;
498 lp->tx_chain_status = desc_filled;
499 } else {
500 /* Update tail */
501 td->control = DMA_COUNT(length) |
502 DMA_DESC_COF | DMA_DESC_IOF;
503 lp->td_ring[chain_prev].control &=
504 ~DMA_DESC_COF;
505 lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
506 lp->tx_chain_tail = chain_next;
507 }
508 }
509
510 netif_trans_update(dev);
511 spin_unlock_irqrestore(&lp->lock, flags);
512
513 return NETDEV_TX_OK;
514
515drop_packet:
516 dev->stats.tx_dropped++;
517 dev_kfree_skb_any(skb);
518 spin_unlock_irqrestore(&lp->lock, flags);
519
520 return NETDEV_TX_OK;
521}
522
523static int korina_mdio_wait(struct korina_private *lp)
524{
525 u32 value;
526
527 return readl_poll_timeout_atomic(&lp->eth_regs->miimind,
528 value, value & ETH_MII_IND_BSY,
529 1, 1000);
530}
531
532static int korina_mdio_read(struct net_device *dev, int phy, int reg)
533{
534 struct korina_private *lp = netdev_priv(dev);
535 int ret;
536
537 ret = korina_mdio_wait(lp);
538 if (ret < 0)
539 return ret;
540
541 writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
542 writel(1, &lp->eth_regs->miimcmd);
543
544 ret = korina_mdio_wait(lp);
545 if (ret < 0)
546 return ret;
547
548 if (readl(&lp->eth_regs->miimind) & ETH_MII_IND_NV)
549 return -EINVAL;
550
551 ret = readl(&lp->eth_regs->miimrdd);
552 writel(0, &lp->eth_regs->miimcmd);
553 return ret;
554}
555
556static void korina_mdio_write(struct net_device *dev, int phy, int reg, int val)
557{
558 struct korina_private *lp = netdev_priv(dev);
559
560 if (korina_mdio_wait(lp))
561 return;
562
563 writel(0, &lp->eth_regs->miimcmd);
564 writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
565 writel(val, &lp->eth_regs->miimwtd);
566}
567
568/* Ethernet Rx DMA interrupt */
569static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
570{
571 struct net_device *dev = dev_id;
572 struct korina_private *lp = netdev_priv(dev);
573 u32 dmas, dmasm;
574 irqreturn_t retval;
575
576 dmas = readl(&lp->rx_dma_regs->dmas);
577 if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
578 dmasm = readl(&lp->rx_dma_regs->dmasm);
579 writel(dmasm | (DMA_STAT_DONE |
580 DMA_STAT_HALT | DMA_STAT_ERR),
581 &lp->rx_dma_regs->dmasm);
582
583 napi_schedule(&lp->napi);
584
585 if (dmas & DMA_STAT_ERR)
586 printk(KERN_ERR "%s: DMA error\n", dev->name);
587
588 retval = IRQ_HANDLED;
589 } else
590 retval = IRQ_NONE;
591
592 return retval;
593}
594
595static int korina_rx(struct net_device *dev, int limit)
596{
597 struct korina_private *lp = netdev_priv(dev);
598 struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
599 struct sk_buff *skb, *skb_new;
600 u32 devcs, pkt_len, dmas;
601 dma_addr_t ca;
602 int count;
603
604 for (count = 0; count < limit; count++) {
605 skb = lp->rx_skb[lp->rx_next_done];
606 skb_new = NULL;
607
608 devcs = rd->devcs;
609
610 if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0)
611 break;
612
613 /* check that this is a whole packet
614 * WARNING: DMA_FD bit incorrectly set
615 * in Rc32434 (errata ref #077) */
616 if (!(devcs & ETH_RX_LD))
617 goto next;
618
619 if (!(devcs & ETH_RX_ROK)) {
620 /* Update statistics counters */
621 dev->stats.rx_errors++;
622 dev->stats.rx_dropped++;
623 if (devcs & ETH_RX_CRC)
624 dev->stats.rx_crc_errors++;
625 if (devcs & ETH_RX_LE)
626 dev->stats.rx_length_errors++;
627 if (devcs & ETH_RX_OVR)
628 dev->stats.rx_fifo_errors++;
629 if (devcs & ETH_RX_CV)
630 dev->stats.rx_frame_errors++;
631 if (devcs & ETH_RX_CES)
632 dev->stats.rx_frame_errors++;
633
634 goto next;
635 }
636
637 /* Malloc up new buffer. */
638 skb_new = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
639 if (!skb_new)
640 break;
641
642 ca = dma_map_single(lp->dmadev, skb_new->data, KORINA_RBSIZE,
643 DMA_FROM_DEVICE);
644 if (dma_mapping_error(lp->dmadev, ca)) {
645 dev_kfree_skb_any(skb_new);
646 break;
647 }
648
649 pkt_len = RCVPKT_LENGTH(devcs);
650 dma_unmap_single(lp->dmadev, lp->rx_skb_dma[lp->rx_next_done],
651 pkt_len, DMA_FROM_DEVICE);
652
653 /* Do not count the CRC */
654 skb_put(skb, pkt_len - 4);
655 skb->protocol = eth_type_trans(skb, dev);
656
657 /* Pass the packet to upper layers */
658 napi_gro_receive(&lp->napi, skb);
659 dev->stats.rx_packets++;
660 dev->stats.rx_bytes += pkt_len;
661
662 /* Update the mcast stats */
663 if (devcs & ETH_RX_MP)
664 dev->stats.multicast++;
665
666 lp->rx_skb[lp->rx_next_done] = skb_new;
667 lp->rx_skb_dma[lp->rx_next_done] = ca;
668
669next:
670 rd->devcs = 0;
671
672 /* Restore descriptor's curr_addr */
673 rd->ca = lp->rx_skb_dma[lp->rx_next_done];
674
675 rd->control = DMA_COUNT(KORINA_RBSIZE) |
676 DMA_DESC_COD | DMA_DESC_IOD;
677 lp->rd_ring[(lp->rx_next_done - 1) &
678 KORINA_RDS_MASK].control &=
679 ~DMA_DESC_COD;
680
681 lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
682 rd = &lp->rd_ring[lp->rx_next_done];
683 writel((u32)~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
684 }
685
686 dmas = readl(&lp->rx_dma_regs->dmas);
687
688 if (dmas & DMA_STAT_HALT) {
689 writel((u32)~(DMA_STAT_HALT | DMA_STAT_ERR),
690 &lp->rx_dma_regs->dmas);
691
692 lp->dma_halt_cnt++;
693 rd->devcs = 0;
694 rd->ca = lp->rx_skb_dma[lp->rx_next_done];
695 writel(korina_rx_dma(lp, rd - lp->rd_ring),
696 &lp->rx_dma_regs->dmandptr);
697 }
698
699 return count;
700}
701
702static int korina_poll(struct napi_struct *napi, int budget)
703{
704 struct korina_private *lp =
705 container_of(napi, struct korina_private, napi);
706 struct net_device *dev = lp->dev;
707 int work_done;
708
709 work_done = korina_rx(dev, budget);
710 if (work_done < budget) {
711 napi_complete_done(napi, work_done);
712
713 writel(readl(&lp->rx_dma_regs->dmasm) &
714 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
715 &lp->rx_dma_regs->dmasm);
716 }
717 return work_done;
718}
719
720/*
721 * Set or clear the multicast filter for this adaptor.
722 */
723static void korina_multicast_list(struct net_device *dev)
724{
725 struct korina_private *lp = netdev_priv(dev);
726 unsigned long flags;
727 struct netdev_hw_addr *ha;
728 u32 recognise = ETH_ARC_AB; /* always accept broadcasts */
729
730 /* Set promiscuous mode */
731 if (dev->flags & IFF_PROMISC)
732 recognise |= ETH_ARC_PRO;
733
734 else if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 4))
735 /* All multicast and broadcast */
736 recognise |= ETH_ARC_AM;
737
738 /* Build the hash table */
739 if (netdev_mc_count(dev) > 4) {
740 u16 hash_table[4] = { 0 };
741 u32 crc;
742
743 netdev_for_each_mc_addr(ha, dev) {
744 crc = ether_crc_le(6, ha->addr);
745 crc >>= 26;
746 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
747 }
748 /* Accept filtered multicast */
749 recognise |= ETH_ARC_AFM;
750
751 /* Fill the MAC hash tables with their values */
752 writel((u32)(hash_table[1] << 16 | hash_table[0]),
753 &lp->eth_regs->ethhash0);
754 writel((u32)(hash_table[3] << 16 | hash_table[2]),
755 &lp->eth_regs->ethhash1);
756 }
757
758 spin_lock_irqsave(&lp->lock, flags);
759 writel(recognise, &lp->eth_regs->etharc);
760 spin_unlock_irqrestore(&lp->lock, flags);
761}
762
763static void korina_tx(struct net_device *dev)
764{
765 struct korina_private *lp = netdev_priv(dev);
766 struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
767 u32 devcs;
768 u32 dmas;
769
770 spin_lock(&lp->lock);
771
772 /* Process all desc that are done */
773 while (IS_DMA_FINISHED(td->control)) {
774 if (lp->tx_full == 1) {
775 netif_wake_queue(dev);
776 lp->tx_full = 0;
777 }
778
779 devcs = lp->td_ring[lp->tx_next_done].devcs;
780 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
781 (ETH_TX_FD | ETH_TX_LD)) {
782 dev->stats.tx_errors++;
783 dev->stats.tx_dropped++;
784
785 /* Should never happen */
786 printk(KERN_ERR "%s: split tx ignored\n",
787 dev->name);
788 } else if (devcs & ETH_TX_TOK) {
789 dev->stats.tx_packets++;
790 dev->stats.tx_bytes +=
791 lp->tx_skb[lp->tx_next_done]->len;
792 } else {
793 dev->stats.tx_errors++;
794 dev->stats.tx_dropped++;
795
796 /* Underflow */
797 if (devcs & ETH_TX_UND)
798 dev->stats.tx_fifo_errors++;
799
800 /* Oversized frame */
801 if (devcs & ETH_TX_OF)
802 dev->stats.tx_aborted_errors++;
803
804 /* Excessive deferrals */
805 if (devcs & ETH_TX_ED)
806 dev->stats.tx_carrier_errors++;
807
808 /* Collisions: medium busy */
809 if (devcs & ETH_TX_EC)
810 dev->stats.collisions++;
811
812 /* Late collision */
813 if (devcs & ETH_TX_LC)
814 dev->stats.tx_window_errors++;
815 }
816
817 /* We must always free the original skb */
818 if (lp->tx_skb[lp->tx_next_done]) {
819 dma_unmap_single(lp->dmadev,
820 lp->tx_skb_dma[lp->tx_next_done],
821 lp->tx_skb[lp->tx_next_done]->len,
822 DMA_TO_DEVICE);
823 dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
824 lp->tx_skb[lp->tx_next_done] = NULL;
825 }
826
827 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
828 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
829 lp->td_ring[lp->tx_next_done].link = 0;
830 lp->td_ring[lp->tx_next_done].ca = 0;
831 lp->tx_count--;
832
833 /* Go on to next transmission */
834 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
835 td = &lp->td_ring[lp->tx_next_done];
836
837 }
838
839 /* Clear the DMA status register */
840 dmas = readl(&lp->tx_dma_regs->dmas);
841 writel(~dmas, &lp->tx_dma_regs->dmas);
842
843 writel(readl(&lp->tx_dma_regs->dmasm) &
844 ~(DMA_STAT_FINI | DMA_STAT_ERR),
845 &lp->tx_dma_regs->dmasm);
846
847 spin_unlock(&lp->lock);
848}
849
850static irqreturn_t
851korina_tx_dma_interrupt(int irq, void *dev_id)
852{
853 struct net_device *dev = dev_id;
854 struct korina_private *lp = netdev_priv(dev);
855 u32 dmas, dmasm;
856 irqreturn_t retval;
857
858 dmas = readl(&lp->tx_dma_regs->dmas);
859
860 if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
861 dmasm = readl(&lp->tx_dma_regs->dmasm);
862 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
863 &lp->tx_dma_regs->dmasm);
864
865 korina_tx(dev);
866
867 if (lp->tx_chain_status == desc_filled &&
868 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
869 writel(korina_tx_dma(lp, lp->tx_chain_head),
870 &lp->tx_dma_regs->dmandptr);
871 lp->tx_chain_status = desc_is_empty;
872 lp->tx_chain_head = lp->tx_chain_tail;
873 netif_trans_update(dev);
874 }
875 if (dmas & DMA_STAT_ERR)
876 printk(KERN_ERR "%s: DMA error\n", dev->name);
877
878 retval = IRQ_HANDLED;
879 } else
880 retval = IRQ_NONE;
881
882 return retval;
883}
884
885
886static void korina_check_media(struct net_device *dev, unsigned int init_media)
887{
888 struct korina_private *lp = netdev_priv(dev);
889
890 mii_check_media(&lp->mii_if, 1, init_media);
891
892 if (lp->mii_if.full_duplex)
893 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
894 &lp->eth_regs->ethmac2);
895 else
896 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
897 &lp->eth_regs->ethmac2);
898}
899
900static void korina_poll_media(struct timer_list *t)
901{
902 struct korina_private *lp = from_timer(lp, t, media_check_timer);
903 struct net_device *dev = lp->dev;
904
905 korina_check_media(dev, 0);
906 mod_timer(&lp->media_check_timer, jiffies + HZ);
907}
908
909static void korina_set_carrier(struct mii_if_info *mii)
910{
911 if (mii->force_media) {
912 /* autoneg is off: Link is always assumed to be up */
913 if (!netif_carrier_ok(mii->dev))
914 netif_carrier_on(mii->dev);
915 } else /* Let MMI library update carrier status */
916 korina_check_media(mii->dev, 0);
917}
918
919static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
920{
921 struct korina_private *lp = netdev_priv(dev);
922 struct mii_ioctl_data *data = if_mii(rq);
923 int rc;
924
925 if (!netif_running(dev))
926 return -EINVAL;
927 spin_lock_irq(&lp->lock);
928 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
929 spin_unlock_irq(&lp->lock);
930 korina_set_carrier(&lp->mii_if);
931
932 return rc;
933}
934
935/* ethtool helpers */
936static void netdev_get_drvinfo(struct net_device *dev,
937 struct ethtool_drvinfo *info)
938{
939 struct korina_private *lp = netdev_priv(dev);
940
941 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
942 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
943 strlcpy(info->bus_info, lp->dev->name, sizeof(info->bus_info));
944}
945
946static int netdev_get_link_ksettings(struct net_device *dev,
947 struct ethtool_link_ksettings *cmd)
948{
949 struct korina_private *lp = netdev_priv(dev);
950
951 spin_lock_irq(&lp->lock);
952 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
953 spin_unlock_irq(&lp->lock);
954
955 return 0;
956}
957
958static int netdev_set_link_ksettings(struct net_device *dev,
959 const struct ethtool_link_ksettings *cmd)
960{
961 struct korina_private *lp = netdev_priv(dev);
962 int rc;
963
964 spin_lock_irq(&lp->lock);
965 rc = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
966 spin_unlock_irq(&lp->lock);
967 korina_set_carrier(&lp->mii_if);
968
969 return rc;
970}
971
972static u32 netdev_get_link(struct net_device *dev)
973{
974 struct korina_private *lp = netdev_priv(dev);
975
976 return mii_link_ok(&lp->mii_if);
977}
978
979static const struct ethtool_ops netdev_ethtool_ops = {
980 .get_drvinfo = netdev_get_drvinfo,
981 .get_link = netdev_get_link,
982 .get_link_ksettings = netdev_get_link_ksettings,
983 .set_link_ksettings = netdev_set_link_ksettings,
984};
985
986static int korina_alloc_ring(struct net_device *dev)
987{
988 struct korina_private *lp = netdev_priv(dev);
989 struct sk_buff *skb;
990 dma_addr_t ca;
991 int i;
992
993 /* Initialize the transmit descriptors */
994 for (i = 0; i < KORINA_NUM_TDS; i++) {
995 lp->td_ring[i].control = DMA_DESC_IOF;
996 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
997 lp->td_ring[i].ca = 0;
998 lp->td_ring[i].link = 0;
999 }
1000 lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
1001 lp->tx_full = lp->tx_count = 0;
1002 lp->tx_chain_status = desc_is_empty;
1003
1004 /* Initialize the receive descriptors */
1005 for (i = 0; i < KORINA_NUM_RDS; i++) {
1006 skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
1007 if (!skb)
1008 return -ENOMEM;
1009 lp->rx_skb[i] = skb;
1010 lp->rd_ring[i].control = DMA_DESC_IOD |
1011 DMA_COUNT(KORINA_RBSIZE);
1012 lp->rd_ring[i].devcs = 0;
1013 ca = dma_map_single(lp->dmadev, skb->data, KORINA_RBSIZE,
1014 DMA_FROM_DEVICE);
1015 if (dma_mapping_error(lp->dmadev, ca))
1016 return -ENOMEM;
1017 lp->rd_ring[i].ca = ca;
1018 lp->rx_skb_dma[i] = ca;
1019 lp->rd_ring[i].link = korina_rx_dma(lp, i + 1);
1020 }
1021
1022 /* loop back receive descriptors, so the last
1023 * descriptor points to the first one */
1024 lp->rd_ring[i - 1].link = lp->rd_dma;
1025 lp->rd_ring[i - 1].control |= DMA_DESC_COD;
1026
1027 lp->rx_next_done = 0;
1028 lp->rx_chain_head = 0;
1029 lp->rx_chain_tail = 0;
1030 lp->rx_chain_status = desc_is_empty;
1031
1032 return 0;
1033}
1034
1035static void korina_free_ring(struct net_device *dev)
1036{
1037 struct korina_private *lp = netdev_priv(dev);
1038 int i;
1039
1040 for (i = 0; i < KORINA_NUM_RDS; i++) {
1041 lp->rd_ring[i].control = 0;
1042 if (lp->rx_skb[i]) {
1043 dma_unmap_single(lp->dmadev, lp->rx_skb_dma[i],
1044 KORINA_RBSIZE, DMA_FROM_DEVICE);
1045 dev_kfree_skb_any(lp->rx_skb[i]);
1046 lp->rx_skb[i] = NULL;
1047 }
1048 }
1049
1050 for (i = 0; i < KORINA_NUM_TDS; i++) {
1051 lp->td_ring[i].control = 0;
1052 if (lp->tx_skb[i]) {
1053 dma_unmap_single(lp->dmadev, lp->tx_skb_dma[i],
1054 lp->tx_skb[i]->len, DMA_TO_DEVICE);
1055 dev_kfree_skb_any(lp->tx_skb[i]);
1056 lp->tx_skb[i] = NULL;
1057 }
1058 }
1059}
1060
1061/*
1062 * Initialize the RC32434 ethernet controller.
1063 */
1064static int korina_init(struct net_device *dev)
1065{
1066 struct korina_private *lp = netdev_priv(dev);
1067
1068 /* Disable DMA */
1069 korina_abort_tx(dev);
1070 korina_abort_rx(dev);
1071
1072 /* reset ethernet logic */
1073 writel(0, &lp->eth_regs->ethintfc);
1074 while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
1075 netif_trans_update(dev);
1076
1077 /* Enable Ethernet Interface */
1078 writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
1079
1080 /* Allocate rings */
1081 if (korina_alloc_ring(dev)) {
1082 printk(KERN_ERR "%s: descriptor allocation failed\n", dev->name);
1083 korina_free_ring(dev);
1084 return -ENOMEM;
1085 }
1086
1087 writel(0, &lp->rx_dma_regs->dmas);
1088 /* Start Rx DMA */
1089 writel(0, &lp->rx_dma_regs->dmandptr);
1090 writel(korina_rx_dma(lp, 0), &lp->rx_dma_regs->dmadptr);
1091
1092 writel(readl(&lp->tx_dma_regs->dmasm) &
1093 ~(DMA_STAT_FINI | DMA_STAT_ERR),
1094 &lp->tx_dma_regs->dmasm);
1095 writel(readl(&lp->rx_dma_regs->dmasm) &
1096 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
1097 &lp->rx_dma_regs->dmasm);
1098
1099 /* Accept only packets destined for this Ethernet device address */
1100 writel(ETH_ARC_AB, &lp->eth_regs->etharc);
1101
1102 /* Set all Ether station address registers to their initial values */
1103 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
1104 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
1105
1106 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
1107 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
1108
1109 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
1110 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
1111
1112 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
1113 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
1114
1115
1116 /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
1117 writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
1118 &lp->eth_regs->ethmac2);
1119
1120 /* Back to back inter-packet-gap */
1121 writel(0x15, &lp->eth_regs->ethipgt);
1122 /* Non - Back to back inter-packet-gap */
1123 writel(0x12, &lp->eth_regs->ethipgr);
1124
1125 /* Management Clock Prescaler Divisor
1126 * Clock independent setting */
1127 writel(((lp->mii_clock_freq) / MII_CLOCK + 1) & ~1,
1128 &lp->eth_regs->ethmcp);
1129 writel(0, &lp->eth_regs->miimcfg);
1130
1131 /* don't transmit until fifo contains 48b */
1132 writel(48, &lp->eth_regs->ethfifott);
1133
1134 writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
1135
1136 korina_check_media(dev, 1);
1137
1138 napi_enable(&lp->napi);
1139 netif_start_queue(dev);
1140
1141 return 0;
1142}
1143
1144/*
1145 * Restart the RC32434 ethernet controller.
1146 */
1147static void korina_restart_task(struct work_struct *work)
1148{
1149 struct korina_private *lp = container_of(work,
1150 struct korina_private, restart_task);
1151 struct net_device *dev = lp->dev;
1152
1153 /*
1154 * Disable interrupts
1155 */
1156 disable_irq(lp->rx_irq);
1157 disable_irq(lp->tx_irq);
1158
1159 writel(readl(&lp->tx_dma_regs->dmasm) |
1160 DMA_STAT_FINI | DMA_STAT_ERR,
1161 &lp->tx_dma_regs->dmasm);
1162 writel(readl(&lp->rx_dma_regs->dmasm) |
1163 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
1164 &lp->rx_dma_regs->dmasm);
1165
1166 napi_disable(&lp->napi);
1167
1168 korina_free_ring(dev);
1169
1170 if (korina_init(dev) < 0) {
1171 printk(KERN_ERR "%s: cannot restart device\n", dev->name);
1172 return;
1173 }
1174 korina_multicast_list(dev);
1175
1176 enable_irq(lp->tx_irq);
1177 enable_irq(lp->rx_irq);
1178}
1179
1180static void korina_tx_timeout(struct net_device *dev, unsigned int txqueue)
1181{
1182 struct korina_private *lp = netdev_priv(dev);
1183
1184 schedule_work(&lp->restart_task);
1185}
1186
1187#ifdef CONFIG_NET_POLL_CONTROLLER
1188static void korina_poll_controller(struct net_device *dev)
1189{
1190 disable_irq(dev->irq);
1191 korina_tx_dma_interrupt(dev->irq, dev);
1192 enable_irq(dev->irq);
1193}
1194#endif
1195
1196static int korina_open(struct net_device *dev)
1197{
1198 struct korina_private *lp = netdev_priv(dev);
1199 int ret;
1200
1201 /* Initialize */
1202 ret = korina_init(dev);
1203 if (ret < 0) {
1204 printk(KERN_ERR "%s: cannot open device\n", dev->name);
1205 goto out;
1206 }
1207
1208 /* Install the interrupt handler
1209 * that handles the Done Finished */
1210 ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt,
1211 0, "Korina ethernet Rx", dev);
1212 if (ret < 0) {
1213 printk(KERN_ERR "%s: unable to get Rx DMA IRQ %d\n",
1214 dev->name, lp->rx_irq);
1215 goto err_release;
1216 }
1217 ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt,
1218 0, "Korina ethernet Tx", dev);
1219 if (ret < 0) {
1220 printk(KERN_ERR "%s: unable to get Tx DMA IRQ %d\n",
1221 dev->name, lp->tx_irq);
1222 goto err_free_rx_irq;
1223 }
1224
1225 mod_timer(&lp->media_check_timer, jiffies + 1);
1226out:
1227 return ret;
1228
1229err_free_rx_irq:
1230 free_irq(lp->rx_irq, dev);
1231err_release:
1232 korina_free_ring(dev);
1233 goto out;
1234}
1235
1236static int korina_close(struct net_device *dev)
1237{
1238 struct korina_private *lp = netdev_priv(dev);
1239 u32 tmp;
1240
1241 del_timer(&lp->media_check_timer);
1242
1243 /* Disable interrupts */
1244 disable_irq(lp->rx_irq);
1245 disable_irq(lp->tx_irq);
1246
1247 korina_abort_tx(dev);
1248 tmp = readl(&lp->tx_dma_regs->dmasm);
1249 tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1250 writel(tmp, &lp->tx_dma_regs->dmasm);
1251
1252 korina_abort_rx(dev);
1253 tmp = readl(&lp->rx_dma_regs->dmasm);
1254 tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1255 writel(tmp, &lp->rx_dma_regs->dmasm);
1256
1257 napi_disable(&lp->napi);
1258
1259 cancel_work_sync(&lp->restart_task);
1260
1261 korina_free_ring(dev);
1262
1263 free_irq(lp->rx_irq, dev);
1264 free_irq(lp->tx_irq, dev);
1265
1266 return 0;
1267}
1268
1269static const struct net_device_ops korina_netdev_ops = {
1270 .ndo_open = korina_open,
1271 .ndo_stop = korina_close,
1272 .ndo_start_xmit = korina_send_packet,
1273 .ndo_set_rx_mode = korina_multicast_list,
1274 .ndo_tx_timeout = korina_tx_timeout,
1275 .ndo_do_ioctl = korina_ioctl,
1276 .ndo_validate_addr = eth_validate_addr,
1277 .ndo_set_mac_address = eth_mac_addr,
1278#ifdef CONFIG_NET_POLL_CONTROLLER
1279 .ndo_poll_controller = korina_poll_controller,
1280#endif
1281};
1282
1283static int korina_probe(struct platform_device *pdev)
1284{
1285 u8 *mac_addr = dev_get_platdata(&pdev->dev);
1286 struct korina_private *lp;
1287 struct net_device *dev;
1288 struct clk *clk;
1289 void __iomem *p;
1290 int rc;
1291
1292 dev = devm_alloc_etherdev(&pdev->dev, sizeof(struct korina_private));
1293 if (!dev)
1294 return -ENOMEM;
1295
1296 SET_NETDEV_DEV(dev, &pdev->dev);
1297 lp = netdev_priv(dev);
1298
1299 if (mac_addr)
1300 ether_addr_copy(dev->dev_addr, mac_addr);
1301 else if (of_get_mac_address(pdev->dev.of_node, dev->dev_addr) < 0)
1302 eth_hw_addr_random(dev);
1303
1304 clk = devm_clk_get_optional(&pdev->dev, "mdioclk");
1305 if (IS_ERR(clk))
1306 return PTR_ERR(clk);
1307 if (clk) {
1308 clk_prepare_enable(clk);
1309 lp->mii_clock_freq = clk_get_rate(clk);
1310 } else {
1311 lp->mii_clock_freq = 200000000; /* max possible input clk */
1312 }
1313
1314 lp->rx_irq = platform_get_irq_byname(pdev, "rx");
1315 lp->tx_irq = platform_get_irq_byname(pdev, "tx");
1316
1317 p = devm_platform_ioremap_resource_byname(pdev, "emac");
1318 if (IS_ERR(p)) {
1319 printk(KERN_ERR DRV_NAME ": cannot remap registers\n");
1320 return PTR_ERR(p);
1321 }
1322 lp->eth_regs = p;
1323
1324 p = devm_platform_ioremap_resource_byname(pdev, "dma_rx");
1325 if (IS_ERR(p)) {
1326 printk(KERN_ERR DRV_NAME ": cannot remap Rx DMA registers\n");
1327 return PTR_ERR(p);
1328 }
1329 lp->rx_dma_regs = p;
1330
1331 p = devm_platform_ioremap_resource_byname(pdev, "dma_tx");
1332 if (IS_ERR(p)) {
1333 printk(KERN_ERR DRV_NAME ": cannot remap Tx DMA registers\n");
1334 return PTR_ERR(p);
1335 }
1336 lp->tx_dma_regs = p;
1337
1338 lp->td_ring = dmam_alloc_coherent(&pdev->dev, TD_RING_SIZE,
1339 &lp->td_dma, GFP_KERNEL);
1340 if (!lp->td_ring)
1341 return -ENOMEM;
1342
1343 lp->rd_ring = dmam_alloc_coherent(&pdev->dev, RD_RING_SIZE,
1344 &lp->rd_dma, GFP_KERNEL);
1345 if (!lp->rd_ring)
1346 return -ENOMEM;
1347
1348 spin_lock_init(&lp->lock);
1349 /* just use the rx dma irq */
1350 dev->irq = lp->rx_irq;
1351 lp->dev = dev;
1352 lp->dmadev = &pdev->dev;
1353
1354 dev->netdev_ops = &korina_netdev_ops;
1355 dev->ethtool_ops = &netdev_ethtool_ops;
1356 dev->watchdog_timeo = TX_TIMEOUT;
1357 netif_napi_add(dev, &lp->napi, korina_poll, NAPI_POLL_WEIGHT);
1358
1359 lp->mii_if.dev = dev;
1360 lp->mii_if.mdio_read = korina_mdio_read;
1361 lp->mii_if.mdio_write = korina_mdio_write;
1362 lp->mii_if.phy_id = 1;
1363 lp->mii_if.phy_id_mask = 0x1f;
1364 lp->mii_if.reg_num_mask = 0x1f;
1365
1366 platform_set_drvdata(pdev, dev);
1367
1368 rc = register_netdev(dev);
1369 if (rc < 0) {
1370 printk(KERN_ERR DRV_NAME
1371 ": cannot register net device: %d\n", rc);
1372 return rc;
1373 }
1374 timer_setup(&lp->media_check_timer, korina_poll_media, 0);
1375
1376 INIT_WORK(&lp->restart_task, korina_restart_task);
1377
1378 printk(KERN_INFO "%s: " DRV_NAME "-" DRV_VERSION " " DRV_RELDATE "\n",
1379 dev->name);
1380 return rc;
1381}
1382
1383static int korina_remove(struct platform_device *pdev)
1384{
1385 struct net_device *dev = platform_get_drvdata(pdev);
1386
1387 unregister_netdev(dev);
1388
1389 return 0;
1390}
1391
1392#ifdef CONFIG_OF
1393static const struct of_device_id korina_match[] = {
1394 {
1395 .compatible = "idt,3243x-emac",
1396 },
1397 { }
1398};
1399MODULE_DEVICE_TABLE(of, korina_match);
1400#endif
1401
1402static struct platform_driver korina_driver = {
1403 .driver = {
1404 .name = "korina",
1405 .of_match_table = of_match_ptr(korina_match),
1406 },
1407 .probe = korina_probe,
1408 .remove = korina_remove,
1409};
1410
1411module_platform_driver(korina_driver);
1412
1413MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1414MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1415MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1416MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1417MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1418MODULE_LICENSE("GPL");