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1/*
2 * Allwinner EMAC Fast Ethernet driver for Linux.
3 *
4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * Based on the Linux driver provided by Allwinner:
8 * Copyright (C) 1997 Sten Wang
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/clk.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/mii.h>
22#include <linux/module.h>
23#include <linux/netdevice.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26#include <linux/of_mdio.h>
27#include <linux/of_net.h>
28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/phy.h>
31#include <linux/soc/sunxi/sunxi_sram.h>
32
33#include "sun4i-emac.h"
34
35#define DRV_NAME "sun4i-emac"
36
37#define EMAC_MAX_FRAME_LEN 0x0600
38
39#define EMAC_DEFAULT_MSG_ENABLE 0x0000
40static int debug = -1; /* defaults above */;
41module_param(debug, int, 0);
42MODULE_PARM_DESC(debug, "debug message flags");
43
44/* Transmit timeout, default 5 seconds. */
45static int watchdog = 5000;
46module_param(watchdog, int, 0400);
47MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
48
49/* EMAC register address locking.
50 *
51 * The EMAC uses an address register to control where data written
52 * to the data register goes. This means that the address register
53 * must be preserved over interrupts or similar calls.
54 *
55 * During interrupt and other critical calls, a spinlock is used to
56 * protect the system, but the calls themselves save the address
57 * in the address register in case they are interrupting another
58 * access to the device.
59 *
60 * For general accesses a lock is provided so that calls which are
61 * allowed to sleep are serialised so that the address register does
62 * not need to be saved. This lock also serves to serialise access
63 * to the EEPROM and PHY access registers which are shared between
64 * these two devices.
65 */
66
67/* The driver supports the original EMACE, and now the two newer
68 * devices, EMACA and EMACB.
69 */
70
71struct emac_board_info {
72 struct clk *clk;
73 struct device *dev;
74 struct platform_device *pdev;
75 spinlock_t lock;
76 void __iomem *membase;
77 u32 msg_enable;
78 struct net_device *ndev;
79 struct sk_buff *skb_last;
80 u16 tx_fifo_stat;
81
82 int emacrx_completed_flag;
83
84 struct device_node *phy_node;
85 unsigned int link;
86 unsigned int speed;
87 unsigned int duplex;
88
89 phy_interface_t phy_interface;
90};
91
92static void emac_update_speed(struct net_device *dev)
93{
94 struct emac_board_info *db = netdev_priv(dev);
95 unsigned int reg_val;
96
97 /* set EMAC SPEED, depend on PHY */
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
99 reg_val &= ~(0x1 << 8);
100 if (db->speed == SPEED_100)
101 reg_val |= 1 << 8;
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
103}
104
105static void emac_update_duplex(struct net_device *dev)
106{
107 struct emac_board_info *db = netdev_priv(dev);
108 unsigned int reg_val;
109
110 /* set duplex depend on phy */
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
112 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
113 if (db->duplex)
114 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
115 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
116}
117
118static void emac_handle_link_change(struct net_device *dev)
119{
120 struct emac_board_info *db = netdev_priv(dev);
121 struct phy_device *phydev = dev->phydev;
122 unsigned long flags;
123 int status_change = 0;
124
125 if (phydev->link) {
126 if (db->speed != phydev->speed) {
127 spin_lock_irqsave(&db->lock, flags);
128 db->speed = phydev->speed;
129 emac_update_speed(dev);
130 spin_unlock_irqrestore(&db->lock, flags);
131 status_change = 1;
132 }
133
134 if (db->duplex != phydev->duplex) {
135 spin_lock_irqsave(&db->lock, flags);
136 db->duplex = phydev->duplex;
137 emac_update_duplex(dev);
138 spin_unlock_irqrestore(&db->lock, flags);
139 status_change = 1;
140 }
141 }
142
143 if (phydev->link != db->link) {
144 if (!phydev->link) {
145 db->speed = 0;
146 db->duplex = -1;
147 }
148 db->link = phydev->link;
149
150 status_change = 1;
151 }
152
153 if (status_change)
154 phy_print_status(phydev);
155}
156
157static int emac_mdio_probe(struct net_device *dev)
158{
159 struct emac_board_info *db = netdev_priv(dev);
160 struct phy_device *phydev;
161
162 /* to-do: PHY interrupts are currently not supported */
163
164 /* attach the mac to the phy */
165 phydev = of_phy_connect(db->ndev, db->phy_node,
166 &emac_handle_link_change, 0,
167 db->phy_interface);
168 if (!phydev) {
169 netdev_err(db->ndev, "could not find the PHY\n");
170 return -ENODEV;
171 }
172
173 /* mask with MAC supported features */
174 phy_set_max_speed(phydev, SPEED_100);
175
176 db->link = 0;
177 db->speed = 0;
178 db->duplex = -1;
179
180 return 0;
181}
182
183static void emac_mdio_remove(struct net_device *dev)
184{
185 phy_disconnect(dev->phydev);
186}
187
188static void emac_reset(struct emac_board_info *db)
189{
190 dev_dbg(db->dev, "resetting device\n");
191
192 /* RESET device */
193 writel(0, db->membase + EMAC_CTL_REG);
194 udelay(200);
195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
196 udelay(200);
197}
198
199static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
200{
201 writesl(reg, data, round_up(count, 4) / 4);
202}
203
204static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
205{
206 readsl(reg, data, round_up(count, 4) / 4);
207}
208
209/* ethtool ops */
210static void emac_get_drvinfo(struct net_device *dev,
211 struct ethtool_drvinfo *info)
212{
213 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
214 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
215}
216
217static u32 emac_get_msglevel(struct net_device *dev)
218{
219 struct emac_board_info *db = netdev_priv(dev);
220
221 return db->msg_enable;
222}
223
224static void emac_set_msglevel(struct net_device *dev, u32 value)
225{
226 struct emac_board_info *db = netdev_priv(dev);
227
228 db->msg_enable = value;
229}
230
231static const struct ethtool_ops emac_ethtool_ops = {
232 .get_drvinfo = emac_get_drvinfo,
233 .get_link = ethtool_op_get_link,
234 .get_link_ksettings = phy_ethtool_get_link_ksettings,
235 .set_link_ksettings = phy_ethtool_set_link_ksettings,
236 .get_msglevel = emac_get_msglevel,
237 .set_msglevel = emac_set_msglevel,
238};
239
240static unsigned int emac_setup(struct net_device *ndev)
241{
242 struct emac_board_info *db = netdev_priv(ndev);
243 unsigned int reg_val;
244
245 /* set up TX */
246 reg_val = readl(db->membase + EMAC_TX_MODE_REG);
247
248 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
249 db->membase + EMAC_TX_MODE_REG);
250
251 /* set MAC */
252 /* set MAC CTL0 */
253 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
254 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
255 EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
256 db->membase + EMAC_MAC_CTL0_REG);
257
258 /* set MAC CTL1 */
259 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
260 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
261 reg_val |= EMAC_MAC_CTL1_CRC_EN;
262 reg_val |= EMAC_MAC_CTL1_PAD_EN;
263 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
264
265 /* set up IPGT */
266 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
267
268 /* set up IPGR */
269 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
270 db->membase + EMAC_MAC_IPGR_REG);
271
272 /* set up Collison window */
273 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
274 db->membase + EMAC_MAC_CLRT_REG);
275
276 /* set up Max Frame Length */
277 writel(EMAC_MAX_FRAME_LEN,
278 db->membase + EMAC_MAC_MAXF_REG);
279
280 return 0;
281}
282
283static void emac_set_rx_mode(struct net_device *ndev)
284{
285 struct emac_board_info *db = netdev_priv(ndev);
286 unsigned int reg_val;
287
288 /* set up RX */
289 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
290
291 if (ndev->flags & IFF_PROMISC)
292 reg_val |= EMAC_RX_CTL_PASS_ALL_EN;
293 else
294 reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN;
295
296 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
297 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
298 EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
299 EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
300 db->membase + EMAC_RX_CTL_REG);
301}
302
303static unsigned int emac_powerup(struct net_device *ndev)
304{
305 struct emac_board_info *db = netdev_priv(ndev);
306 unsigned int reg_val;
307
308 /* initial EMAC */
309 /* flush RX FIFO */
310 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
311 reg_val |= 0x8;
312 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
313 udelay(1);
314
315 /* initial MAC */
316 /* soft reset MAC */
317 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
318 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
319 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
320
321 /* set MII clock */
322 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
323 reg_val &= (~(0xf << 2));
324 reg_val |= (0xD << 2);
325 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
326
327 /* clear RX counter */
328 writel(0x0, db->membase + EMAC_RX_FBC_REG);
329
330 /* disable all interrupt and clear interrupt status */
331 writel(0, db->membase + EMAC_INT_CTL_REG);
332 reg_val = readl(db->membase + EMAC_INT_STA_REG);
333 writel(reg_val, db->membase + EMAC_INT_STA_REG);
334
335 udelay(1);
336
337 /* set up EMAC */
338 emac_setup(ndev);
339
340 /* set mac_address to chip */
341 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
342 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
343 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
344 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
345
346 mdelay(1);
347
348 return 0;
349}
350
351static int emac_set_mac_address(struct net_device *dev, void *p)
352{
353 struct sockaddr *addr = p;
354 struct emac_board_info *db = netdev_priv(dev);
355
356 if (netif_running(dev))
357 return -EBUSY;
358
359 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
360
361 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
362 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
363 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
364 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
365
366 return 0;
367}
368
369/* Initialize emac board */
370static void emac_init_device(struct net_device *dev)
371{
372 struct emac_board_info *db = netdev_priv(dev);
373 unsigned long flags;
374 unsigned int reg_val;
375
376 spin_lock_irqsave(&db->lock, flags);
377
378 emac_update_speed(dev);
379 emac_update_duplex(dev);
380
381 /* enable RX/TX */
382 reg_val = readl(db->membase + EMAC_CTL_REG);
383 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
384 db->membase + EMAC_CTL_REG);
385
386 /* enable RX/TX0/RX Hlevel interrup */
387 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
388 reg_val |= (0xf << 0) | (0x01 << 8);
389 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
390
391 spin_unlock_irqrestore(&db->lock, flags);
392}
393
394/* Our watchdog timed out. Called by the networking layer */
395static void emac_timeout(struct net_device *dev, unsigned int txqueue)
396{
397 struct emac_board_info *db = netdev_priv(dev);
398 unsigned long flags;
399
400 if (netif_msg_timer(db))
401 dev_err(db->dev, "tx time out.\n");
402
403 /* Save previous register address */
404 spin_lock_irqsave(&db->lock, flags);
405
406 netif_stop_queue(dev);
407 emac_reset(db);
408 emac_init_device(dev);
409 /* We can accept TX packets again */
410 netif_trans_update(dev);
411 netif_wake_queue(dev);
412
413 /* Restore previous register address */
414 spin_unlock_irqrestore(&db->lock, flags);
415}
416
417/* Hardware start transmission.
418 * Send a packet to media from the upper layer.
419 */
420static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
421{
422 struct emac_board_info *db = netdev_priv(dev);
423 unsigned long channel;
424 unsigned long flags;
425
426 channel = db->tx_fifo_stat & 3;
427 if (channel == 3)
428 return NETDEV_TX_BUSY;
429
430 channel = (channel == 1 ? 1 : 0);
431
432 spin_lock_irqsave(&db->lock, flags);
433
434 writel(channel, db->membase + EMAC_TX_INS_REG);
435
436 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
437 skb->data, skb->len);
438 dev->stats.tx_bytes += skb->len;
439
440 db->tx_fifo_stat |= 1 << channel;
441 /* TX control: First packet immediately send, second packet queue */
442 if (channel == 0) {
443 /* set TX len */
444 writel(skb->len, db->membase + EMAC_TX_PL0_REG);
445 /* start translate from fifo to phy */
446 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
447 db->membase + EMAC_TX_CTL0_REG);
448
449 /* save the time stamp */
450 netif_trans_update(dev);
451 } else if (channel == 1) {
452 /* set TX len */
453 writel(skb->len, db->membase + EMAC_TX_PL1_REG);
454 /* start translate from fifo to phy */
455 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
456 db->membase + EMAC_TX_CTL1_REG);
457
458 /* save the time stamp */
459 netif_trans_update(dev);
460 }
461
462 if ((db->tx_fifo_stat & 3) == 3) {
463 /* Second packet */
464 netif_stop_queue(dev);
465 }
466
467 spin_unlock_irqrestore(&db->lock, flags);
468
469 /* free this SKB */
470 dev_consume_skb_any(skb);
471
472 return NETDEV_TX_OK;
473}
474
475/* EMAC interrupt handler
476 * receive the packet to upper layer, free the transmitted packet
477 */
478static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
479 unsigned int tx_status)
480{
481 /* One packet sent complete */
482 db->tx_fifo_stat &= ~(tx_status & 3);
483 if (3 == (tx_status & 3))
484 dev->stats.tx_packets += 2;
485 else
486 dev->stats.tx_packets++;
487
488 if (netif_msg_tx_done(db))
489 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
490
491 netif_wake_queue(dev);
492}
493
494/* Received a packet and pass to upper layer
495 */
496static void emac_rx(struct net_device *dev)
497{
498 struct emac_board_info *db = netdev_priv(dev);
499 struct sk_buff *skb;
500 u8 *rdptr;
501 bool good_packet;
502 static int rxlen_last;
503 unsigned int reg_val;
504 u32 rxhdr, rxstatus, rxcount, rxlen;
505
506 /* Check packet ready or not */
507 while (1) {
508 /* race warning: the first packet might arrive with
509 * the interrupts disabled, but the second will fix
510 * it
511 */
512 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
513
514 if (netif_msg_rx_status(db))
515 dev_dbg(db->dev, "RXCount: %x\n", rxcount);
516
517 if ((db->skb_last != NULL) && (rxlen_last > 0)) {
518 dev->stats.rx_bytes += rxlen_last;
519
520 /* Pass to upper layer */
521 db->skb_last->protocol = eth_type_trans(db->skb_last,
522 dev);
523 netif_rx(db->skb_last);
524 dev->stats.rx_packets++;
525 db->skb_last = NULL;
526 rxlen_last = 0;
527
528 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
529 reg_val &= ~EMAC_RX_CTL_DMA_EN;
530 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
531 }
532
533 if (!rxcount) {
534 db->emacrx_completed_flag = 1;
535 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
536 reg_val |= (0xf << 0) | (0x01 << 8);
537 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
538
539 /* had one stuck? */
540 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
541 if (!rxcount)
542 return;
543 }
544
545 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
546 if (netif_msg_rx_status(db))
547 dev_dbg(db->dev, "receive header: %x\n", reg_val);
548 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
549 /* disable RX */
550 reg_val = readl(db->membase + EMAC_CTL_REG);
551 writel(reg_val & ~EMAC_CTL_RX_EN,
552 db->membase + EMAC_CTL_REG);
553
554 /* Flush RX FIFO */
555 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
556 writel(reg_val | (1 << 3),
557 db->membase + EMAC_RX_CTL_REG);
558
559 do {
560 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
561 } while (reg_val & (1 << 3));
562
563 /* enable RX */
564 reg_val = readl(db->membase + EMAC_CTL_REG);
565 writel(reg_val | EMAC_CTL_RX_EN,
566 db->membase + EMAC_CTL_REG);
567 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
568 reg_val |= (0xf << 0) | (0x01 << 8);
569 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
570
571 db->emacrx_completed_flag = 1;
572
573 return;
574 }
575
576 /* A packet ready now & Get status/length */
577 good_packet = true;
578
579 rxhdr = readl(db->membase + EMAC_RX_IO_DATA_REG);
580
581 if (netif_msg_rx_status(db))
582 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
583
584 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
585 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
586
587 if (netif_msg_rx_status(db))
588 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
589 rxstatus, rxlen);
590
591 /* Packet Status check */
592 if (rxlen < 0x40) {
593 good_packet = false;
594 if (netif_msg_rx_err(db))
595 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
596 }
597
598 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
599 good_packet = false;
600
601 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
602 if (netif_msg_rx_err(db))
603 dev_dbg(db->dev, "crc error\n");
604 dev->stats.rx_crc_errors++;
605 }
606
607 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
608 if (netif_msg_rx_err(db))
609 dev_dbg(db->dev, "length error\n");
610 dev->stats.rx_length_errors++;
611 }
612 }
613
614 /* Move data from EMAC */
615 if (good_packet) {
616 skb = netdev_alloc_skb(dev, rxlen + 4);
617 if (!skb)
618 continue;
619 skb_reserve(skb, 2);
620 rdptr = skb_put(skb, rxlen - 4);
621
622 /* Read received packet from RX SRAM */
623 if (netif_msg_rx_status(db))
624 dev_dbg(db->dev, "RxLen %x\n", rxlen);
625
626 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
627 rdptr, rxlen);
628 dev->stats.rx_bytes += rxlen;
629
630 /* Pass to upper layer */
631 skb->protocol = eth_type_trans(skb, dev);
632 netif_rx(skb);
633 dev->stats.rx_packets++;
634 }
635 }
636}
637
638static irqreturn_t emac_interrupt(int irq, void *dev_id)
639{
640 struct net_device *dev = dev_id;
641 struct emac_board_info *db = netdev_priv(dev);
642 int int_status;
643 unsigned int reg_val;
644
645 /* A real interrupt coming */
646
647 spin_lock(&db->lock);
648
649 /* Disable all interrupts */
650 writel(0, db->membase + EMAC_INT_CTL_REG);
651
652 /* Got EMAC interrupt status */
653 /* Got ISR */
654 int_status = readl(db->membase + EMAC_INT_STA_REG);
655 /* Clear ISR status */
656 writel(int_status, db->membase + EMAC_INT_STA_REG);
657
658 if (netif_msg_intr(db))
659 dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
660
661 /* Received the coming packet */
662 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
663 /* carrier lost */
664 db->emacrx_completed_flag = 0;
665 emac_rx(dev);
666 }
667
668 /* Transmit Interrupt check */
669 if (int_status & (0x01 | 0x02))
670 emac_tx_done(dev, db, int_status);
671
672 if (int_status & (0x04 | 0x08))
673 netdev_info(dev, " ab : %x\n", int_status);
674
675 /* Re-enable interrupt mask */
676 if (db->emacrx_completed_flag == 1) {
677 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
678 reg_val |= (0xf << 0) | (0x01 << 8);
679 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
680 }
681 spin_unlock(&db->lock);
682
683 return IRQ_HANDLED;
684}
685
686#ifdef CONFIG_NET_POLL_CONTROLLER
687/*
688 * Used by netconsole
689 */
690static void emac_poll_controller(struct net_device *dev)
691{
692 disable_irq(dev->irq);
693 emac_interrupt(dev->irq, dev);
694 enable_irq(dev->irq);
695}
696#endif
697
698/* Open the interface.
699 * The interface is opened whenever "ifconfig" actives it.
700 */
701static int emac_open(struct net_device *dev)
702{
703 struct emac_board_info *db = netdev_priv(dev);
704 int ret;
705
706 if (netif_msg_ifup(db))
707 dev_dbg(db->dev, "enabling %s\n", dev->name);
708
709 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev))
710 return -EAGAIN;
711
712 /* Initialize EMAC board */
713 emac_reset(db);
714 emac_init_device(dev);
715
716 ret = emac_mdio_probe(dev);
717 if (ret < 0) {
718 free_irq(dev->irq, dev);
719 netdev_err(dev, "cannot probe MDIO bus\n");
720 return ret;
721 }
722
723 phy_start(dev->phydev);
724 netif_start_queue(dev);
725
726 return 0;
727}
728
729static void emac_shutdown(struct net_device *dev)
730{
731 unsigned int reg_val;
732 struct emac_board_info *db = netdev_priv(dev);
733
734 /* Disable all interrupt */
735 writel(0, db->membase + EMAC_INT_CTL_REG);
736
737 /* clear interrupt status */
738 reg_val = readl(db->membase + EMAC_INT_STA_REG);
739 writel(reg_val, db->membase + EMAC_INT_STA_REG);
740
741 /* Disable RX/TX */
742 reg_val = readl(db->membase + EMAC_CTL_REG);
743 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
744 writel(reg_val, db->membase + EMAC_CTL_REG);
745}
746
747/* Stop the interface.
748 * The interface is stopped when it is brought.
749 */
750static int emac_stop(struct net_device *ndev)
751{
752 struct emac_board_info *db = netdev_priv(ndev);
753
754 if (netif_msg_ifdown(db))
755 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
756
757 netif_stop_queue(ndev);
758 netif_carrier_off(ndev);
759
760 phy_stop(ndev->phydev);
761
762 emac_mdio_remove(ndev);
763
764 emac_shutdown(ndev);
765
766 free_irq(ndev->irq, ndev);
767
768 return 0;
769}
770
771static const struct net_device_ops emac_netdev_ops = {
772 .ndo_open = emac_open,
773 .ndo_stop = emac_stop,
774 .ndo_start_xmit = emac_start_xmit,
775 .ndo_tx_timeout = emac_timeout,
776 .ndo_set_rx_mode = emac_set_rx_mode,
777 .ndo_do_ioctl = phy_do_ioctl_running,
778 .ndo_validate_addr = eth_validate_addr,
779 .ndo_set_mac_address = emac_set_mac_address,
780#ifdef CONFIG_NET_POLL_CONTROLLER
781 .ndo_poll_controller = emac_poll_controller,
782#endif
783};
784
785/* Search EMAC board, allocate space and register it
786 */
787static int emac_probe(struct platform_device *pdev)
788{
789 struct device_node *np = pdev->dev.of_node;
790 struct emac_board_info *db;
791 struct net_device *ndev;
792 int ret = 0;
793
794 ndev = alloc_etherdev(sizeof(struct emac_board_info));
795 if (!ndev) {
796 dev_err(&pdev->dev, "could not allocate device.\n");
797 return -ENOMEM;
798 }
799
800 SET_NETDEV_DEV(ndev, &pdev->dev);
801
802 db = netdev_priv(ndev);
803
804 db->dev = &pdev->dev;
805 db->ndev = ndev;
806 db->pdev = pdev;
807 db->msg_enable = netif_msg_init(debug, EMAC_DEFAULT_MSG_ENABLE);
808
809 spin_lock_init(&db->lock);
810
811 db->membase = of_iomap(np, 0);
812 if (!db->membase) {
813 dev_err(&pdev->dev, "failed to remap registers\n");
814 ret = -ENOMEM;
815 goto out;
816 }
817
818 /* fill in parameters for net-dev structure */
819 ndev->base_addr = (unsigned long)db->membase;
820 ndev->irq = irq_of_parse_and_map(np, 0);
821 if (ndev->irq == -ENXIO) {
822 netdev_err(ndev, "No irq resource\n");
823 ret = ndev->irq;
824 goto out_iounmap;
825 }
826
827 db->clk = devm_clk_get(&pdev->dev, NULL);
828 if (IS_ERR(db->clk)) {
829 ret = PTR_ERR(db->clk);
830 goto out_dispose_mapping;
831 }
832
833 ret = clk_prepare_enable(db->clk);
834 if (ret) {
835 dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret);
836 goto out_dispose_mapping;
837 }
838
839 ret = sunxi_sram_claim(&pdev->dev);
840 if (ret) {
841 dev_err(&pdev->dev, "Error couldn't map SRAM to device\n");
842 goto out_clk_disable_unprepare;
843 }
844
845 db->phy_node = of_parse_phandle(np, "phy-handle", 0);
846 if (!db->phy_node)
847 db->phy_node = of_parse_phandle(np, "phy", 0);
848 if (!db->phy_node) {
849 dev_err(&pdev->dev, "no associated PHY\n");
850 ret = -ENODEV;
851 goto out_release_sram;
852 }
853
854 /* Read MAC-address from DT */
855 ret = of_get_mac_address(np, ndev->dev_addr);
856 if (ret) {
857 /* if the MAC address is invalid get a random one */
858 eth_hw_addr_random(ndev);
859 dev_warn(&pdev->dev, "using random MAC address %pM\n",
860 ndev->dev_addr);
861 }
862
863 db->emacrx_completed_flag = 1;
864 emac_powerup(ndev);
865 emac_reset(db);
866
867 ndev->netdev_ops = &emac_netdev_ops;
868 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
869 ndev->ethtool_ops = &emac_ethtool_ops;
870
871 platform_set_drvdata(pdev, ndev);
872
873 /* Carrier starts down, phylib will bring it up */
874 netif_carrier_off(ndev);
875
876 ret = register_netdev(ndev);
877 if (ret) {
878 dev_err(&pdev->dev, "Registering netdev failed!\n");
879 ret = -ENODEV;
880 goto out_release_sram;
881 }
882
883 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
884 ndev->name, db->membase, ndev->irq, ndev->dev_addr);
885
886 return 0;
887
888out_release_sram:
889 sunxi_sram_release(&pdev->dev);
890out_clk_disable_unprepare:
891 clk_disable_unprepare(db->clk);
892out_dispose_mapping:
893 irq_dispose_mapping(ndev->irq);
894out_iounmap:
895 iounmap(db->membase);
896out:
897 dev_err(db->dev, "not found (%d).\n", ret);
898
899 free_netdev(ndev);
900
901 return ret;
902}
903
904static int emac_remove(struct platform_device *pdev)
905{
906 struct net_device *ndev = platform_get_drvdata(pdev);
907 struct emac_board_info *db = netdev_priv(ndev);
908
909 unregister_netdev(ndev);
910 sunxi_sram_release(&pdev->dev);
911 clk_disable_unprepare(db->clk);
912 irq_dispose_mapping(ndev->irq);
913 iounmap(db->membase);
914 free_netdev(ndev);
915
916 dev_dbg(&pdev->dev, "released and freed device\n");
917 return 0;
918}
919
920static int emac_suspend(struct platform_device *dev, pm_message_t state)
921{
922 struct net_device *ndev = platform_get_drvdata(dev);
923
924 netif_carrier_off(ndev);
925 netif_device_detach(ndev);
926 emac_shutdown(ndev);
927
928 return 0;
929}
930
931static int emac_resume(struct platform_device *dev)
932{
933 struct net_device *ndev = platform_get_drvdata(dev);
934 struct emac_board_info *db = netdev_priv(ndev);
935
936 emac_reset(db);
937 emac_init_device(ndev);
938 netif_device_attach(ndev);
939
940 return 0;
941}
942
943static const struct of_device_id emac_of_match[] = {
944 {.compatible = "allwinner,sun4i-a10-emac",},
945
946 /* Deprecated */
947 {.compatible = "allwinner,sun4i-emac",},
948 {},
949};
950
951MODULE_DEVICE_TABLE(of, emac_of_match);
952
953static struct platform_driver emac_driver = {
954 .driver = {
955 .name = "sun4i-emac",
956 .of_match_table = emac_of_match,
957 },
958 .probe = emac_probe,
959 .remove = emac_remove,
960 .suspend = emac_suspend,
961 .resume = emac_resume,
962};
963
964module_platform_driver(emac_driver);
965
966MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
967MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
968MODULE_DESCRIPTION("Allwinner A10 emac network driver");
969MODULE_LICENSE("GPL");